A method for determining the location where a fault exists during the functional verification of sequential logic circuits

Abstract

The present invention discloses a method for determining the location where a fault exists during the functional verification of a sequential logic circuit, belonging to the basic algorithms of EDA. By abstracting the sequential circuit into multiple covering units, establishing a state transition graph, dividing the problem into three mutually exclusive scenarios, and through relevant algorithms, calculating the probability that a specified fault occurs only at a specific location, sorting the probabilities that occur under all possible states, so as to determine the most likely location where the fault appears, thereby supplementing the integrity of dynamic verification.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, belonging to the basic algorithms of EDA, and particularly relates to the field of EDA software used in the functional verification of sequential logic circuits. Background Art

[0002] In recent years, integrated circuits have achieved rapid development and are the core of China's information industry today. China's integrated circuit EDA software has long been restricted by others, and the country strongly supports its development. Verification is a key issue in the development of VLSI and software and hardware systems. Currently, the main method to measure the progress of dynamic verification is based on coverage. Coverage can be divided into code coverage and functional coverage, and among them, functional coverage is an important indicator to measure the design integrity. Summary of the Invention

[0003] The content of the present invention proposes a method for determining the location where a fault exists for sequential circuits based on the prior art, that is, calculating the probability that a specified fault a occurs only in a specific state e. This method is divided into two parts: preliminary modeling and algorithm calculation. Finally, by calculating and sorting the probabilities of the existence of the specified fault in each state, the most likely location where the fault exists can be obtained.

[0004] The technical solution adopted by the present invention is a method for determining the location where a fault exists during the functional verification of sequential logic circuits. In the preliminary modeling part, the logical functions of sequential circuits are comprehensively represented by driving equations, state equations, and output equations, and the state transitions of sequential circuits are described by state transition diagrams. The transition probabilities between states and the initial distribution are obtained through the simulation of sequential circuits. After specifying the faults and states to be concerned about, irrelevant states are merged into a coverage bin to obtain an abstract state transition diagram, completing the preliminary modeling work.

[0005] The algorithm calculation divides the problem of the probability that a specified fault a occurs only in a specific state e into three mutually exclusive scenarios according to the test period, and performs forward algorithm calculation based on the transition probabilities between states, fault detection probabilities, and initial distribution probabilities. For details, see the attached drawings. Among them, p(i,j) is the transition probability, q i is the probability of the occurrence of the fault, T is the test period, is the initial distribution, and the probability of this event in the j-th state in the i-th period is a[i][j]. The three scenarios are respectively:

[0006] 1) The fault a is first detected at the initial time and occurs in the state e; it occurs in the state e in the initial distribution, that is, a[0][e]. The state transition starts from the state e in the T = 1 test, and the probabilities of non-occurrence of the fault are used for calculation in other states during the entire test period. In the T = 1,...t tests, both the occurrence and non-occurrence of the state e are acceptable, that is, ∑ s' [A(T - 1, s')·p(s', s)].

[0007] 2) Fault a was first found to occur in state e during the last test; the fault did not occur in the previous t - 1 cycles, i.e., (1 - q i ), and in the t-th test, considering the state transition from the previous cycle to state e and the occurrence of the fault, i.e., ∑ s' [A(t - 1, s') · p(s', e) · q e .

[0008] 3) Fault a was first found to occur in state e during a certain intermediate test; considering that the fault first occurred in the intermediate T = 1,... t - 1 tests and did not occur initially, and it may occur in the last test. The fault a first occurred in the T-th test cycle. Only the state transition to state e is considered in this test cycle, and the state jumps from state e to other states in the (T + 1)-th test cycle.

[0009] The accuracy of the algorithm can be verified by the Monte Carlo method through a large number of random simulation experiments on the number of states, the fault detection probability, the number of tests, and the observed states respectively.

[0010] After obtaining the probability that the specified fault a occurs only in the specific state e, changing the state in which the fault occurs can obtain the probability that the specified fault a occurs in other states, and sorting all the results. The state with the highest probability is the state in which the fault a is most likely to occur.

[0011] This method helps to determine the location where the faults exist in the functional verification of sequential logic circuits, thereby measuring the integrity of the test and improving the current dynamic verification process. Description of the Drawings

[0012] Figure 1 It is the algorithm flowchart for the specified fault being first found to occur in a specific state initially.

[0013] Figure 2 It is the algorithm flowchart for the specified fault being found to occur in a specific state during the last test.

[0014] Figure 3 It is the algorithm flowchart for the specified fault being first found to occur in a specific state during a certain intermediate test. Detailed Implementation Manner

[0015] In the present invention, the sequential circuit is abstracted into multiple coverage units, a state transition graph is established, the problem is divided into three mutually exclusive scenarios, and through relevant algorithms, the probability that the specified fault occurs only at a certain specific position is calculated, and the probabilities occurring in all possible states are sorted, so as to determine the position where the fault is most likely to appear, thereby supplementing the integrity of the dynamic verification.

[0016] A method for determining the location of a fault during the functional verification of a sequential logic circuit, which studies the problem of the existence of a fault. When the sequential circuit is functionally verified using random excitation, the probability of the event that a specified fault a occurs only in a specific state e is studied. This problem is divided into three mutually exclusive scenarios, and each scenario has a specific algorithm. The state in which the specified fault occurs is transformed, and the results are sorted. This method helps to measure the integrity of the test and improve the current dynamic verification process.

[0017] The problem of studying the probability that a specified fault a occurs only in a specific state e is characterized by transforming the sequential logic circuit into a state transition diagram and performing multi-coverage bin analysis.

[0018] The above-mentioned problem is divided into three mutually exclusive scenarios. The problem of the probability that a specified fault a occurs only in a specific state e is divided into three scenarios according to the position where the fault first appears in the entire test cycle. Scenario 1: The fault a is first detected in the initial state and occurs in state e, and occurs only in state e throughout the test cycle. Scenario 2: The fault a is detected in state e in the last test. Scenario 3: The fault a is first detected in a certain middle test and occurs in state e, and the fault a occurs only in state e in subsequent tests.

[0019] The algorithm considers the transition probability between states, the fault detection probability, the initial distribution, and the test cycle. The fault detection probability is the probability of detecting a certain fault after reaching a certain state, and the transition probability between states is obtained by simulation. In the test cycle where it is first detected, it only transfers to a specific state, and the next transition starts from the specific state. After that, for each test, the specified fault can only be considered to occur in the specific state. The state in which the fault occurs is changed, and finally, the probabilities of the specified fault occurring in different states are sorted.

Claims

1. A method for determining the location of a fault during the functional verification of a sequential logic circuit, characterized in that: The method includes a pre-modeling part and an algorithm calculation part; in the pre-modeling part, the logical function of the sequential circuit is comprehensively represented by a driving equation, a state equation, and an output equation, the state transition of the sequential circuit is described by a state transition diagram, and the transition probability and initial distribution between states are obtained through sequential circuit simulation; after specifying the faults and states to be concerned about, the irrelevant states are merged into a covering bin to obtain an abstract state transition diagram, completing the pre-modeling work; The algorithm calculation part is to calculate the specified fault a only in specific states e The probability problem that occurs is divided into three mutually exclusive scenarios according to the test period, and the forward algorithm is calculated based on the transition probability between states, the fault detection probability, and the initial distribution probability; among them p ( i,j ) is the transition probability, q i is the fault detection probability, T is the test period, φ i is the initial distribution. The probability of the fault in the i th cycle and the j th state is a i j ;​​ The three scenarios for determining the location of a fault during the functional verification of a sequential logic circuit are respectively: Fault a is first detected in the initial state e occurs; occurs in the initial distribution in the state e , that is a [0] e ; T = 1 state transition in the test starts from the state e begins, and the probabilities of no fault occurrence are used for other states during the entire test cycle T = 1,... t times of testing, the state e can either occur or not occur; Fault a First detected in the last test in the state e Occurs; previous t -1 periodic faults do not occur i.e. (1 - q i ), in the t th test, considering the state transition from the previous cycle to the state e and the fault occurs; Fault a was first detected in a certain intermediate test in the state e occurred; Consider the first occurrence of a fault in the middle T = 1,... t - 1 tests, and it does not occur initially and may occur in the last test; the T fault in the a first occurs in the e th test cycle. Only consider the state transition to state T in this test cycle, and e jump to other states in the + 1 test cycle starting from state Obtain the specified fault a Only in a specific state e After the probability of occurrence, change the state of fault occurrence to obtain the specified fault a The probability of occurrence in other states, and sort all the results. The one with the highest probability is the specified fault a The most likely state of occurrence.

2. A method for determining the location of a fault in the functional verification of a sequential logic circuit according to claim 1, characterized in that: Through the Monte Carlo method, data random simulation experiments are respectively carried out on the number of states, the fault detection probability, the number of tests, and the observed states to verify the accuracy of the results.

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