A stable on-chip clock generation circuit

Abstract

The present invention belongs to the technical field of integrated circuits and relates to a stable on-chip clock generation circuit. The present invention includes a charge and discharge circuit, a comparator, and a timing logic circuit. Four switches are used in the charge and discharge circuit to jointly control the charging and discharging of the charging capacitor C1 to generate a linearly rising triangular wave signal. The compensation capacitor C2 in the charge and discharge circuit is used to offset the negative voltage mutation caused by the capacitor flip, effectively stabilizing the waveform and frequency of the triangular wave at the charging node VC. The comparator compares the charging triangular wave signal VC with the reference voltage source VREF, and the output signal is supplied to the timing logic circuit. The timing logic circuit is connected to the output of the comparator and is used to generate the first clock SW and the second clock SW_B, and the two are non-overlapping clock signals. By swapping the charging and discharging of the upper and lower plates of the capacitor C1 and combining with the compensation capacitor C2, the present invention can achieve rapid discharge of the charge on the capacitor, with a stable output clock frequency, a simple circuit structure, and low power consumption.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and particularly relates to a stable on-chip clock generation circuit. Background Art

[0002] The clock source is an important module in many electronic systems. For example, in a switching power supply, the clock signal is used to control the turn-off and turn-on of the power transistor, thereby achieving energy transfer in a chopping form; in an analog-to-digital converter (ADC), the clock signal is used to sample the analog signal, and the clock frequency determines the sampling frequency. Therefore, the quality of the clock source will directly affect the overall performance of the electronic system.

[0003] Refer to Figure 1 , which shows a schematic structural diagram of a conventional on-chip clock generation circuit, specifically including two comparators COMP1 and COMP2, current source I N and current source I P , two switches S1 and S2, a charging capacitor C, and an RS flip-flop. Figure 1 The working mode of the on-chip clock source shown is as follows: The opening and closing of switches S1 and S2 are controlled by the output signals CLK and CLK_B of the RS flip-flop, and the charging capacitor C is repeatedly charged and discharged by current source I N and current source I P .

[0004] Figure 1 The working process of a conventional on-chip clock generation circuit shown is as follows:

[0005] When the output signal CLK of the RS flip-flop is at a low level and the output signal CLK_B is at a high level, switch S1 is turned on, switch S2 is turned off, and current source I P charges capacitor C. When the voltage VC on capacitor C rises above the reference voltage VH at the inverting terminal of comparator COMP1, the output signal of comparator COMP1 is at a high level, the RS flip-flop is in the set state, the output signal CLK becomes high level, and output CLK_B becomes low level. At this time, switch S1 is turned off, switch S2 is turned on, and current source I N discharges capacitor C, and the potential VC on the capacitor starts to decrease. When the VC potential drops to the reference voltage VL connected to the non-inverting terminal of comparator COMP2, comparator COMP2 outputs a high level, the RS flip-flop is in the reset state, the output signal CLK becomes low level, and CLK_B becomes high level. Thereafter, the circuit continuously repeats the above process, and the voltage VC on capacitor C repeatedly oscillates back and forth between VH and VL.

[0006] Figure 1A conventional on-chip clock generation circuit as shown has two main problems: Firstly, the use of a dual comparator in the structure brings a large power consumption loss; Secondly, the mismatch between the two comparators has an adverse effect on the clock frequency stability. Therefore, there is still room for continuous improvement and optimization in terms of power consumption and frequency stability of the conventional on-chip clock generation circuit. Summary of the Invention

[0007] Aiming at the problems existing in the above on-chip clock generation circuit, the purpose of the present invention is to provide a stable on-chip clock generation circuit.

[0008] To achieve the above purpose, the present invention adopts the following technical solutions:

[0009] A stable on-chip clock generation circuit includes a charge and discharge circuit, a comparator, and a timing logic circuit, where:

[0010] The charge and discharge circuit receives the first clock SW and the second clock SW_B from the timing logic circuit, and controls the reference current source Iref to repeatedly charge the left and right plates of the charging capacitor C1 according to the feedback clock signal, generating a stable triangular wave signal VC;

[0011] The comparator compares the triangular wave signal VC generated by the charge and discharge circuit with the reference voltage source VREF, and outputs a comparison signal VO;

[0012] The timing logic circuit receives the output signal VO of the comparator and generates non-overlapping first clock SW and second clock SW_B.

[0013] Specifically, the above charge and discharge circuit includes a reference current source Iref, a charging capacitor C1, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, and a compensation capacitor C2, where,

[0014] One end of the charging current source Iref is connected to the compensation capacitor C2, the first switch S1, and the second switch S2, and the other end is connected to the power supply VDD;

[0015] One end of the compensation capacitor C2 is connected to one end of the first switch S1 and the second switch S2, and the other end is grounded. The other ends of the first switch S1 and the second switch S2 are respectively connected to the left and right two ports of the charging capacitor C1;

[0016] The left end of the charging capacitor C1 is also connected to the third switch S3, and the right end of the charging capacitor C1 is also connected to the fourth switch S4. The other ends of the third switch S3 and the fourth switch S4 are commonly grounded;

[0017] The first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are all composed of an NMOS transistor and two PMOS transistors. Taking the first switch S1 as an example, where,

[0018] The sources and drains of PM1_A and PM1_B are short - circuited. The drain of PM1_A is also connected to the drain of NMOS transistor NM1, and the source of PM1_B is also connected to the source of NMOS transistor NM1. The gates of PM1_A, PM1_B, and NM1 are connected together. PM1_A and PM1_B have the same size and the width - to - length ratio is half of that of NM1.

[0019] The structures of the second switch S2, the third switch S3, and the fourth switch S4 are the same as that of the first switch S1, and will not be elaborated here.

[0020] The first switch S1 and the fourth switch S4 are controlled by the first clock SW, and the second switch S2 and the third switch S3 are controlled by the second clock SW_B.

[0021] The in - phase port of the above comparator is connected to one end of the reference voltage source VREF. The anti - phase port of the comparator is connected to the compensation capacitor C2, the first switch S1, and the second switch S2. The output of the comparator is connected to the input of the first inverter. The other end of the reference voltage source VREF is grounded.

[0022] The above - mentioned timing logic circuit includes a D - flip - flop, two AND gates, and six inverters. The input of the first inverter is connected to the output VO of the comparator. The output of the first inverter is connected to the clock clk port of the D - flip - flop. The D terminal of the D - flip - flop is connected to and the Q terminal is connected to the input of the second inverter and the input of the first AND gate. The other input of the first AND gate is connected to the output of the fourth inverter. One input of the second AND gate is connected to the output of the second inverter, and the other input of the second AND gate is connected to the output of the third inverter. The input of the third inverter is connected to the output of the first AND gate. The input of the fourth inverter is connected to the output of the second AND gate. The input of the fifth inverter is connected to the output of the third inverter, and the output of the fifth inverter is the first clock SW. The input of the sixth inverter is connected to the output of the fourth inverter, and the output of the sixth inverter is the second clock SW_B.

[0023] Compared with the prior art, the present invention has the following advantages:

[0024] The on - chip clock generation circuit of the present invention only uses a single comparator in its structure, effectively reducing power consumption. By using switches, the reference current source realizes the cyclic charging of the left and right plates of the charging capacitor C1 and the instantaneous discharge of the capacitor, and uses the compensation capacitor C2 to offset the negative - voltage mutation caused by the instantaneous discharge of the capacitor, keeping the low potential of the charging - node VC triangular - wave signal stable at 0 all the time, enhancing the frequency stability of the signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a conventional on - chip clock generation circuit

[0026] Figure 2Circuit structure diagram of the on-chip clock generation circuit of the present invention

[0027] Figure 3 Working process diagram of the on-chip clock generation circuit of the present invention

[0028] Figure 4 Simulation result diagram of the on-chip clock generation circuit of the present invention Specific implementation mode

[0029] The present invention will be further described in detail below with reference to the accompanying drawings.

[0030] Embodiment 1

[0031] As Figure 2 shown, a stable on-chip generation circuit of the present invention includes a charge-discharge circuit, a comparator, and a timing logic circuit. Among them,

[0032] The charge-discharge circuit receives the first clock SW and the second clock SW_B from the timing logic circuit, and controls the reference current source Iref to repeatedly charge the charging capacitor C1 according to the clock signal to generate a stable triangular wave signal VC;

[0033] The comparator compares the triangular wave signal VC generated by the charge-discharge circuit with the reference voltage VREF and outputs a comparison signal VO;

[0034] The timing logic circuit receives the output signal VO of the comparator and generates non-overlapping first clock SW and second clock SW_B.

[0035] Specifically, the above-mentioned charge-discharge circuit includes a reference current source Iref, a charging capacitor C1, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, and a compensation capacitor C2. Among them,

[0036] One end of the charging current source Iref is connected to the compensation capacitor C2, the first switch S1, and the second switch S2, and the other end is connected to the power supply VDD;

[0037] One end of the compensation capacitor C2 is connected to one end of the first switch S1 and the second S2, and the other end is grounded. The other ends of the first switch S1 and the second switch S2 are respectively connected to the left and right two ports of the charging capacitor C1;

[0038] The left end of the charging capacitor C1 is also connected to the third switch S3, and the right end of the charging capacitor C1 is also connected to the fourth switch S4. The other ends of the third switch S3 and the fourth switch S4 are commonly grounded;

[0039] The first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are all composed of an NMOS transistor and two PMOS transistors. Taking the first switch S1 as an example, among them:

[0040] The sources and drains of PM1_A and PM1_B are shorted. The drain of PM1_A is also connected to the drain of NMOS transistor NM1, and the source of PM1_B is also connected to the source of NMOS transistor. The gates of PM1_A, PM1_B, and NM1 are connected. PM1_A and PM1_B have the same size and a width-to-length ratio that is half of that of NM1, which can effectively avoid the influence of clock feedthrough and charge injection.

[0041] The structures of the second switch S2, the third switch S3, and the fourth switch S4 are the same as that of the first switch S1, and will not be elaborated here.

[0042] The first switch S1 and the fourth switch S4 are controlled by the first clock SW, and the second switch S2 and the third switch S3 are controlled by the second clock SW_B.

[0043] The in-phase port of the comparator is connected to one end of the reference voltage source VREF. The inverting terminal of the comparator is connected to one end of the compensation capacitor C2, one end of the first switch S1, and one end of the second switch S2. The output VO of the comparator is connected to the input of the first inverter in the timing logic circuit. The other end of the reference voltage source VREF is grounded.

[0044] The above-mentioned timing logic circuit includes a D flip-flop, two AND gates, and six inverters. The input of the first inverter is connected to the output VO of the comparator. The output of the first inverter is connected to the clock clk port of the D flip-flop. The D terminal of the D flip-flop is and connected. The Q terminal is connected to the input of the second inverter and the input of the first AND gate. The other input of the first AND gate is connected to the output of the fourth inverter. One input of the second AND gate is connected to the output of the second inverter. The other input of the second AND gate is connected to the output of the third inverter. The input of the third inverter is connected to the output of the first AND gate. The input of the fourth inverter is connected to the output of the second AND gate. The input of the fifth inverter is connected to the output of the third inverter, and the first clock SW is output. The input of the sixth inverter is connected to the output of the fourth inverter, and the second clock SW_B is output.

[0045] The working principle of the present invention is as follows:

[0046] In the charge and discharge circuit, the first switch S1 and the fourth switch S4 are controlled by the first clock signal SW, and the second switch S2 and the third switch S3 are controlled by the second clock SW_B. The first clock SW and the second clock SW_B are two-phase non-overlapping clocks, that is, they cannot be high at the same time.

[0047] There is no charge on the preset charging capacitor C1 and the compensation capacitor C2, and the voltage of node VC is 0. The comparator output comparison signal VO is at a high level. After being processed by the timing logic circuit, the first clock SW is at a high level, and the second clock SW_B is at a low level. The first switch S1 and the fourth switch S4 are in a conducting state, and the second switch S2 and the third switch S3 are in an off state. The left plate terminal VL of the charging capacitor C1 and the compensation capacitor C2 are commonly connected to the reference current source Iref, and the right plate of the charging capacitor C1 is grounded. The reference current source Iref starts to linearly charge the charging capacitor C1 and the compensation capacitor C2, generating a triangular wave signal VC. The voltage during the charging process satisfies the relationship:

[0048] V = (Iref × t) / (C1 + C2)

[0049] When the charging node voltage VC is greater than the reference voltage source VREF, the comparator output comparison signal VO becomes a low level. After being processed by the timing logic circuit, the first clock SW becomes a low level, and the second clock SW_B becomes a high level. At this time, the first switch S1 and the fourth switch S4 are turned off, and the second switch S2 and the third switch S3 are turned on. The upper plate VL of the charging capacitor C1 is instantaneously switched to ground, and the lower plate VR of the charging capacitor is instantaneously switched to connect to the charging current source Iref.

[0050] The voltage difference across the capacitor cannot change suddenly. Therefore, the difference between VL and VR is still approximately VREF, and since VL = 0, VR = -VREF. Due to the existence of the compensation capacitor C2, the charge on it is Qp = C2 × Vref. By reasonably setting the ratio of the capacitors C1 and C2, the negative charge Qn = –C1 × Vref on the charging capacitor C1 can be neutralized, so that the total charge on the charging capacitor C1 and the compensation capacitor C2 is 0, and the comparator output VO returns to a high level. The charging current source Iref starts to charge the capacitor again, generating a triangular wave signal.

[0051] When the charging node voltage VC is greater than VREF again, the comparator output VO becomes a low level. After being processed by the timing logic signal, the first clock SW becomes a high level, and the second clock SW_B becomes a low level. Finally, this circuit can realize the repeated charging and discharging of the capacitor, generating a clock signal with a stable frequency.

[0052] Embodiment 2

[0053] Referring to Figure 3 , shows Figure 2 a schematic diagram of the working process of the on-chip clock generation circuit shown, and the working process of the on-chip clock generation circuit is as follows:

[0054] After the clock generation circuit is powered on, at time t0, the initial voltage of the charging node VC is 0, the voltage VL of the left plate of the charging capacitor C1 is 0, and the voltage VR of the right plate is 0. Then the output signal VO of the comparator is at a high level, the first clock SW is at a high level, the second clock SW_B is at a low level, the first switch S1 and the fourth switch S4 are turned on, and the second switch S2 and the third switch S3 are turned off. The left plate of the charging capacitor C1 is connected to the reference current source Iref to start charging. The potential VL of the left plate is the same as the potential of the charging node VC and starts to rise at a slope of Iref / (C1 + C2), generating a triangular wave signal. The right plate of the compensation capacitor C2 is grounded, and the VR voltage is always 0.

[0055] At time t1, when the potential VC of the charging node rises to the reference voltage VREF, after the output signal VO passes through the delay time td of the comparator, it becomes low at time t2. The first clock SW also becomes low, the second clock SW_B becomes high, the first switch S1 and the fourth switch S4 are turned off, and the second switch S2 and the third switch S3 are turned on. The charge on the left plate VL of the charging capacitor C1 is discharged instantaneously, and the VL voltage becomes 0. Due to the existence of the compensation capacitor C2, the right plate VR of the charging capacitor C1 is connected to the VC node, and the potential is stabilized at 0. After the comparator passes through the delay time td, the output becomes high again at time t3. The charging current source Iref charges the capacitor again. The right plate VR of the charging capacitor C1 is the same as the charging node VC and continues to charge at a slope of Iref / (C1 + C2). Until time t4, when the VC potential is greater than VREF, the output VO of the comparator becomes low at time t5. The first clock SW then becomes high, the second clock SW_B becomes low, and the charge on the right plate VR of the charging capacitor C1 is discharged instantaneously, and the VR voltage becomes 0. Due to the existence of the compensation capacitor C2, the left plate VL of the charging capacitor C1 is connected to the node VC again, and the potential is stabilized at 0. After the comparator passes through the delay time td of td, the output VO becomes high again at time t6. The reference current source Iref recharges the capacitor, and the voltage of the node VC starts to rise linearly, thus completing one cycle.

[0056] One cycle of the clock signal SW includes the linear charging time T1 for the charging node VC to rise from zero potential to the VREF voltage and the delay time Td of the comparator. According to the principle of charge conservation, the expression for the linear charging time T1 can be obtained as:

[0057]

[0058] Therefore, the output frequency of the clock signal is:

[0059]

[0060] Figure 4This is the actual circuit simulation diagram of the clock generation circuit of the present invention. The frequency of the output first clock signal SW is 800 KHz. In one cycle, the left and right plates VR and VL of the charging capacitor C1 are charged in sequence to generate a triangular wave signal. After VC is greater than VREF, the charge is instantaneously discharged to the ground. Due to the existence of the compensation capacitor C2, there is no transient negative voltage mutation. The simulation shows that the initial voltage on the capacitor is 19 nV each time it is recharged, which meets the theoretical expectation.

[0061] In summary, the on-chip clock generation circuit has the following advantages:

[0062] First, the on-chip clock generation circuit of the present invention uses only a single comparator. Compared with the traditional dual-comparator structure, it not only reduces power consumption but also eliminates the adverse effects of dual-comparator mismatch on frequency stability.

[0063] Second, the on-chip clock generation circuit of the present invention uses the structure of a flip capacitor to charge the left and right plates of the charging capacitor C1 in sequence to generate a triangular wave signal, and suppresses the transient negative voltage caused by the flip of the capacitor plates by adding a compensation capacitor C2, so that in each charging cycle, the charging node linearly rises from the 0 potential, enhancing the frequency stability of the clock signal.

[0064] Furthermore, in the switch structure of the on-chip clock generation circuit of the present invention, by adding two PMOS transistors, the adverse effects of charge injection and clock feedthrough on the signal frequency are effectively suppressed.

[0065] Finally, the first clock SW and the second clock SW_B generated by the on-chip clock generation circuit of the present invention are two-phase non-overlapping clocks, which prevent all four switches from conducting simultaneously when the capacitor discharges, generating a surge current.

[0066] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention, making various non-substantive improvements, or directly applying the above-mentioned concept and technical solution of the present invention to other occasions without improvement, should be included in the protection scope of the present invention.

Claims

1. A stable on-chip clock generation circuit, characterized in that The described stable on-chip clock generation circuit includes a charge and discharge circuit (100), a comparator (200), and a timing logic circuit (300), where: The charge and discharge circuit (100) receives the first clock SW and the second clock SW_B fed back by the timing logic circuit (300), and generates a charging triangular wave signal VC; The inverting input terminal of the comparator (200) is connected to the triangular wave signal VC output by the charge and discharge circuit (100), the non-inverting input terminal is connected to the reference voltage source VREF, and the output comparison signal VO is given to the timing logic circuit (300); The timing logic circuit (300) receives the output signal VO of the comparator (200), outputs the first clock SW and the second clock SW_B, and feeds them back to the charge and discharge circuit (100); The charge and discharge circuit (100) includes a reference current source Iref, a charging capacitor C1, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, and a compensation capacitor C2, where: The left plate of the charging capacitor C1 is connected to the second port of the first switch S1 and the first port of the third switch S3, and the right plate is connected to the second port of the second switch S2 and the first port of the fourth switch S4; The first switch S1 and the fourth switch S4 are controlled by the first clock SW, the second switch S2 and the fourth switch S3 are controlled by the second clock SW_B, and the plates of the charging capacitor C1 are determined to be in a grounded state or a charging state according to the clock signal; The reference current source Iref outputs a stable triangular wave signal VC by linearly charging the capacitor; The first switch S1 includes NM1, PM1_A, and PM1_B, where the aspect ratios of PM1_A and PM1_B are 1 / 2 of NM1, and the source and drain are short-circuited, which can eliminate the adverse effects caused by charge injection and clock feedthrough. The structures of the second switch S2, the third switch S3, and the fourth switch S4 are the same as that of the first switch S1; The upper end of the compensation capacitor C2 is connected to the charging node of the reference current source Iref, and the lower end is grounded, which is used to suppress the negative voltage mutation caused by the flip of the charging capacitor C1 and make the triangular wave signal VC stable.

2. The stable on-chip clock generation circuit according to claim 1, wherein The described timing logic circuit includes a D flip-flop (301), a first inverter (302), a second inverter (303), a first AND gate (304), a second AND gate (305), a third inverter (306), a fourth inverter (307), a fifth inverter (308), a sixth inverter (309), where: The first inverter (302) is connected to the output VO of the comparator (200), and the output is connected to the D flip-flop (301); The D terminal of the D flip-flop (301) and the terminal are connected, and the Q terminal is connected to the second inverter (303) and the first AND gate (304); The output of the second inverter (303) is connected to the input of the second AND gate (305); The first output of the first AND gate (304) is connected to the output Q of the D flip-flop (301), the second input is connected to the output of the fourth inverter (307), and the output of the first AND gate (304) is connected to the input of the third inverter (306); The first input of the second AND gate (305) is connected to the output of the second inverter (303), the second input is connected to the output of the third inverter (306), and the output of the second AND gate (305) is connected to the input of the fourth inverter (307); The input of the fifth inverter (308) is connected to the output of the third inverter (306), and the output, the first clock SW, is connected to the control terminals of the first switch S1 (101) and the fourth switch S4 (104); The input of the sixth inverter (309) is connected to the output of the fourth inverter (307), and the output, the second clock SW_B, is connected to the control terminals of the second switch S2 (102) and the third switch S3 (103).

3. A stable on-chip clock generation circuit according to claim 1, characterized in that, The generated first clock SW and second clock SW_B are two-phase non-overlapping clocks, that is, they cannot be at a high potential simultaneously, so as to avoid the simultaneous conduction of the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 and the generation of surge current.

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