Standard cell pass rate test classification method, device, equipment, program and medium

Abstract

Embodiments of the present disclosure provide a method, apparatus, device, computer program product, and readable storage medium for testing and classifying the pass-through rate of standard cells. The method provided by the embodiments of the present disclosure includes obtaining a layout planning diagram, where the layout planning diagram includes a plurality of pre-arranged layout blocks; obtaining a list of standard cells to be tested, where the list of standard cells to be tested includes a plurality of standard cells to be tested; for each of the standard cells to be tested in the list of standard cells to be tested, determining its pass-through rate in the layout planning diagram; and classifying the plurality of standard cells to be tested according to the determined pass-through rate of each of the standard cells to be tested, so as to quickly screen out the standard cells that best match the chip layout design, facilitate the optimization of the standard cells with poor matching, and improve the utilization rate of the layout space.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a method, apparatus, device, computer program product, and readable storage medium for testing and classifying the passing rate of standard cells. Background Art

[0002] With the improvement of the chip manufacturing process level, manufacturers can implement more and more circuit elements in a smaller surface area of the silicon substrate. An integrated circuit contains millions of transistors on a single chip. Currently, the main method for developing integrated circuits is to use standard cells during the development process. In this standard cell-based design method, multiple standard cells with specified logical functions are prepared in advance. Multiple standard cells are arranged on a semiconductor substrate, and according to the user's needs, these standard cells are connected by wiring, and these standard cells are combined to design an integrated circuit that implements the specified function. Classifying the standard cells can be faster and more accurate when selecting standard cells.

[0003] Currently, there are some methods for classifying standard cells according to the power consumption, performance, area, and manufacturability of the standard cells. However, these classification methods only classify around the properties of the standard cells and cannot measure the matching degree between the standard cells and the chip layout design, and cannot quickly and accurately select the standard cells that are most matched with the chip layout design.

[0004] Therefore, a standard cell classification method is needed, which can quickly screen out the standard cells that are most matched with the chip layout design through this classification method, facilitate the optimization of the standard cells with poor matching, and improve the layout space utilization rate. Summary of the Invention

[0005] To solve the above problems, the present disclosure obtains a layout planning diagram, calculates the passing rate of the standard cells in the layout planning diagram, and classifies the standard cells according to the passing rate, so as to quickly screen out the standard cells that are most matched with the chip layout design, facilitate the optimization of the standard cells with poor matching, and improve the layout space utilization rate.

[0006] Embodiments of the present disclosure provide a method, device, computer program product, and readable storage medium for testing and classifying the passing rate of standard cells.

[0007] Embodiments of the present disclosure provide a method for testing and classifying the pass-through rate of standard cells. The method includes: obtaining a layout planning diagram, which includes a plurality of pre-arranged layout blocks; obtaining a list of standard cells to be tested, which includes a plurality of standard cells to be tested; for each standard cell to be tested in the list of standard cells to be tested, determining its pass-through rate in the layout planning diagram; and classifying the plurality of standard cells to be tested according to the determined pass-through rate of each standard cell to be tested.

[0008] According to an embodiment of the present disclosure, a position in the layout planning diagram where the standard cell can be placed is a standard position. For each standard cell to be tested in the list of standard cells to be tested, determining its pass-through rate in the layout planning diagram includes: placing the standard cell to be tested in the list of standard cells to be tested at each standard position for design rule checking, and when no design rule checking violation occurs, determining the position where the standard cell to be tested is located as a valid position; calculating the pass-through rate of the standard cell to be tested using the following equation: where PassRatio is the pass-through rate of the standard cell to be tested, Count 标准 is the number of standard positions, and Count 有效 is the number of valid positions.

[0009] According to an embodiment of the present disclosure, classifying the standard cells to be tested according to the pass-through rate of the standard cells to be tested includes: generating n threshold ranges, where at least one of the threshold ranges corresponds to a category of the standard cells to be tested, and n > 1; determining the category of the standard cells to be tested according to the threshold range in which the pass-through rate of the standard cells to be tested is located.

[0010] Embodiments of the present disclosure also provide a method for testing the power supply and ground structure score of a layout planning diagram. The method includes: obtaining a layout planning diagram, which includes a plurality of pre-arranged layout blocks, and the plurality of pre-arranged layout blocks include power blocks and the power supply and ground power supply network; obtaining a list of standard cells, which includes a plurality of standard cells; for each standard cell in the list of standard cells, determining its pass-through rate in the layout planning diagram; obtaining the total pass-through rate of the list of standard cells based on the pass-through rate of each standard cell in the list of standard cells; and calculating the power supply and ground structure score of the layout planning diagram according to the total pass-through rate.

[0011] According to an embodiment of the present disclosure, obtaining the total pass ratio of the standard cell list based on the pass ratio of each standard cell in the standard cell list includes: performing a weighted sum of the pass ratios of each standard cell to calculate the total pass ratio of the standard cell list.

[0012] According to an embodiment of the present disclosure, the positions in the layout planning diagram where the standard cells can be placed are standard positions; wherein, for each standard cell in the standard cell list, determining its pass ratio in the layout planning diagram includes: placing the standard cells in the standard cell list at each standard position for design rule checking, and determining the position where the standard cell is located as a valid position when no design rule checking violation occurs; calculating the pass ratio of the standard cell using the following equation: where PassRatio is the pass ratio of the standard cell, and Count 标准 is the number of the standard positions, and Count 有效 is the number of the valid positions.

[0013] According to an embodiment of the present disclosure, it further includes: obtaining another layout planning diagram, determining the total pass ratio of the standard cell list in the another layout planning diagram, and calculating the power supply and grounding structure score of the another layout planning diagram; comparing the power supply and grounding structure score of the layout planning diagram with the power supply and grounding structure score of the another layout planning diagram, and determining the power supply and grounding structure with a higher score as the most suitable structure for the standard cell list.

[0014] According to an embodiment of the present disclosure, it further includes: judging whether the power supply and grounding structure of the layout planning diagram meets the design requirements of the layout planning diagram according to the power supply and grounding structure score of the layout planning diagram; in the case where the power supply and grounding structure of the layout planning diagram does not meet the design requirements of the layout planning diagram, adjusting the layout of the power supply block and the power supply and grounding power supply network.

[0015] According to an embodiment of the present disclosure, judging whether the power supply and grounding structure of the layout planning diagram meets the design requirements of the layout planning diagram includes: generating a design requirement threshold range, and in the case where the power supply and grounding structure score of the layout planning diagram is within the design requirement threshold range, the power supply and grounding structure of the layout planning diagram meets the design requirements.

[0016] Embodiments of the present disclosure also provide a standard cell pass-through rate test and classification device, the device comprising: a layout planning diagram acquisition module configured to acquire a layout planning diagram, the layout planning diagram including a plurality of pre-arranged layout blocks; a list acquisition module configured to acquire a list of standard cells to be tested, the list of standard cells to be tested including a plurality of standard cells to be tested; a pass-through rate test module configured to determine, for each of the standard cells to be tested in the list of standard cells to be tested, its pass-through rate in the layout planning diagram; and a classification module configured to classify the plurality of standard cells to be tested according to the determined pass-through rate of each of the standard cells to be tested.

[0017] Embodiments of the present disclosure also provide a power supply and ground structure score test device for a layout planning diagram, the device comprising: a layout planning diagram acquisition module configured to acquire a layout planning diagram, the layout planning diagram including a plurality of pre-arranged layout blocks, the plurality of pre-arranged layout blocks including a power block and a power supply and ground power supply network; a list acquisition module configured to acquire a list of standard cells, the list of standard cells including a plurality of standard cells; a pass-through rate test module configured to determine, for each of the standard cells in the list of standard cells, its pass-through rate in the layout planning diagram; and a score test module configured to obtain the total pass-through rate of the list of standard cells based on the pass-through rate of each of the standard cells in the list of standard cells, and calculate the power supply and ground structure score of the layout planning diagram according to the total pass-through rate.

[0018] Embodiments of the present disclosure also provide a standard cell pass-through rate test and classification device, the device comprising: one or more processors; and one or more memories storing computer-executable programs, which when executed by the processors, execute the method according to any one of the embodiments of the present disclosure.

[0019] Embodiments of the present disclosure also provide a power supply and ground structure score test device for a layout planning diagram, the device comprising: one or more processors; and one or more memories storing computer-executable programs, which when executed by the processors, execute the method according to any one of the embodiments of the present disclosure.

[0020] Embodiments of the present disclosure also provide a computer program product, the computer program product including computer software code, which is used to implement the method according to any one of the embodiments of the present disclosure when run by a processor.

[0021] Embodiments of the present disclosure also provide a computer-readable storage medium, on which computer-executable instructions are stored, and the instructions are used to implement the method according to any one of the embodiments of the present disclosure when executed by a processor.

[0022] Through the method of the present disclosure, the standard cells that best match the chip layout design can be quickly screened out, facilitating the optimization of the standard cells with poor matching and improving the utilization rate of the layout space. In addition, the method of the present disclosure can be applied to the power supply and ground structure score test of the layout planning diagram, select the power supply and ground structure that best matches the existing standard cell list, and determine whether the power supply and ground structure meet the design requirements. Description of the Drawings

[0023] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some exemplary embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts. The following drawings are not deliberately drawn to scale in actual size, and the focus is on showing the gist of the present invention.

[0024] Figure 1 Shows a schematic diagram of standard cell placement;

[0025] Figure 2 Shows a schematic diagram of the failure situation of standard cell placement;

[0026] Figure 3 Shows a flowchart of the standard cell placement pass rate test classification method 100 according to an embodiment of the present disclosure;

[0027] Figure 4 Shows a flowchart of the power supply and ground structure score test method 200 for a layout planning diagram according to an embodiment of the present disclosure;

[0028] Figure 5 Shows a flowchart of the method 300 for comparing the power supply and ground structure scores of a layout planning diagram;

[0029] Figure 6 Shows a flowchart of the method 400 for determining whether the power supply and ground structure of a layout planning diagram meet the design requirements of the layout planning diagram;

[0030] Figure 7 Shows a schematic diagram of the standard cell placement pass rate test classification device 1000 according to an embodiment of the present disclosure;

[0031] Figure 8 Shows a schematic diagram of the power supply and ground structure score test device 2000 for a layout planning diagram according to an embodiment of the present disclosure;

[0032] Figure 9 FIG. 3000 is a schematic diagram showing the architecture of an exemplary computing device according to an embodiment of the present disclosure;

[0033] Figure 10 FIG. 4000 is a schematic diagram showing a computer-readable storage medium according to an embodiment of the present disclosure;

[0034] Figure 11 FIG. 500 is a schematic block diagram showing a standard cell pass rate test classification device according to an embodiment of the present disclosure;

[0035] Figure 12 FIG. 600 is a schematic block diagram showing a power supply and ground structure score test device for a layout plan according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0036] In order to make the objectives, technical solutions and advantages of the present disclosure more apparent, exemplary embodiments according to the present disclosure will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments of the present disclosure. It should be understood that the present disclosure is not limited by the exemplary embodiments described herein.

[0037] As shown in this application and the claims, unless the context clearly indicates otherwise, words such as "a", "an", "one" and / or "the" are not specifically singular and may also include plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of the steps and elements that have been clearly identified, and these steps and elements do not constitute an exclusive list. A method or device may also include other steps or elements.

[0038] In this specification and the drawings, steps and elements that are substantially the same or similar are denoted by the same or similar reference numerals, and the repeated description of these steps and elements will be omitted. At the same time, in the description of the present disclosure, terms such as "first", "second", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance or order.

[0039] In addition, in this specification and the drawings, if a flowchart is used to illustrate the steps of a method according to an embodiment of the present disclosure, it should be understood that the steps before or after may not necessarily be carried out precisely in sequence. On the contrary, they can be carried out in reverse order or simultaneously, unless explicitly limited by the embodiments of the present disclosure. At the same time, other operations can also be added to these processes, or one or several steps can be removed from these processes.

[0040] In addition, in this specification and the drawings, unless otherwise clearly stated, words such as "connected" or "coupled" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms used herein are for the purpose of describing embodiments of the present invention only and are not intended to limit the present invention.

[0042] To facilitate the description of this disclosure, the following concepts related to this disclosure are introduced.

[0043] In the process of chip development, the physical implementation process of backend design mainly includes three parts: placement planning, placement, and routing. Placement planning is to place the macro cell modules of the chip and determine the placement positions of various functional circuits in general, such as intellectual property (IP) modules, random access memory (RAM), input / output (I / O) pins, etc., which can directly affect the final area of the chip. Placement is to place standard cells, input / output pads (I / O pads), and macro cells (Marco) to implement circuit logic. Routing refers to connecting each unit and I / O pad with interconnecting wires according to the connection relationship of the circuit under the constraints of process rules, routing layer limits, line width, line spacing limits, and reliable insulation electrical performance of each net.

[0044] A standard cell is a group of transistors and interconnect structures that provide Boolean logic functions (such as AND gates, OR gates, XOR gates, XNOR gates, inverters) or storage functions (flip-flops or latches). Each standard cell corresponds to multiple unit circuits of different sizes and different driving capabilities, and different driving strength circuits are integer multiples of the basic size or the minimum size.

[0045] A standard cell library is a collection of low-level electronic logic functions, such as AND gates, OR gates, converters, flip-flops, latches, and buffers. These cells are all rectangular with the same height, or the height is an integer multiple of the basic height, and the widths can be different to ensure that other very regular sizes are not used during the circuit design stage, which enables them to be placed in rows, thus simplifying the process of automated digital layout.

[0046] Standard cell design refers to the technology of calling pre-designed functional cells from the library, arranging them in rows, and leaving a certain wiring area between rows. In order to ensure that the placement of each cell with other cells does not cause design rule check errors, all layouts must be designed using pre-defined templates. Since the classic router uses a grid-based method for wiring connections, grid-based wiring connections can simplify the algorithm of the wiring tool and reduce the memory resources occupied by the computer. The location, size, and shape of all cell input and output ports try to meet the grid spacing requirements, which can improve the efficiency of the router. In addition to the power supply and ground, other lead-out contacts are arranged on both sides of the cell. The power line and ground line are generally located at the upper and lower boundaries of the cell to facilitate connection sharing and reduce chip area.

[0047] In summary, the solutions provided by the embodiments of the present disclosure involve technologies such as standard cells, standard cell libraries, and standard cell designs. The embodiments of the present disclosure will be further described below in conjunction with the accompanying drawings.

[0048] Figure 1 A schematic diagram of standard cell placement is shown.

[0049] like Figure 1 As shown in the figure, the pre-designed standard cells are called from the library and placed based on the grid, arranged in rows, with a certain wiring area between rows. The classic router uses a grid-based method for wiring connections. Therefore, the position, size, and shape of all standard cell input and output ports try to meet the grid spacing requirements.

[0050] Figure 2 A schematic diagram of standard cell placement failure is shown.

[0051] like Figure 2 As shown, the situations where the standard cell placement fails include but are not limited to the following two: as shown in 201, the standard cell placement position conflicts with the pre-placed internal routing such as the power and ground network structure, special signal routing, etc., resulting in the failure of the standard cell placement; as shown in 202, the spacing between macro cells is not enough to place the standard cell, and the standard cell and macro cell placement positions overlap, resulting in the failure of the standard cell placement. In addition, when the standard cell placement position overlaps with the via or pad position, the standard cell placement failure will also occur.

[0052] Figure 3 A flow chart of a standard unit pass rate test classification method 100 according to an embodiment of the present disclosure is shown.

[0053] like Figure 3 As shown, in step S101, a layout planning diagram is obtained, and the layout planning diagram includes a plurality of pre-arranged layout blocks.

[0054] Optionally, the layout planning diagram can be generated using an Electronic Design Automation (EDA) platform.

[0055] Optionally, the layout planning diagram design is grid-based. Layout blocks are pre-arranged on the layout planning diagram, including power blocks, power and ground supply networks, and other pre-arranged special signal routing networks, etc. Standard cells are arranged in rows in the format of cell rows; within the area between adjacent standard cell rows, routing channels are arranged, and routing is carried out within the routing channels; power blocks, power and ground supply networks are designed according to the power and ground design interchange format, which describes the actual design of power and ground, lists the positions and connection relationships of power and ground, and uses the design interchange format to transfer designs between different design systems.

[0056] In step S102, a list of standard cells to be tested is obtained, and the list of standard cells to be tested includes multiple standard cells to be tested.

[0057] Optionally, each list of standard cells to be tested includes multiple standard cells to be tested. Standard cells can be various types of devices such as AND gates, OR gates, XOR gates, XNOR gates, inverters, flip-flops, or latches. Each list of test standard cells can include only one type of cell to be tested, or can include multiple types of cells to be tested. For example, there are 20 standard cells in the list of standard cells to be tested, which can be 20 AND gates, or a combination of 8 AND gates, 3 OR gates, and 9 inverters.

[0058] Optionally, multiple standard cells to be tested can form one list of standard cells to be tested or multiple lists of standard cells to be tested. One list of standard cells to be tested can be obtained, or multiple lists of standard cells to be tested can be obtained. The number of standard cells to be tested and the types of standard cells within each list can be the same or different. For example, if the standard cells to be tested are 10 AND gates and 10 flip-flops, the 10 AND gates and 10 flip-flops can be grouped into 1 list of standard cells to be detected for testing, or 3 AND gates and 2 flip-flops can be grouped into one list to be detected, and 7 AND gates and 8 flip-flops can be grouped into another list of standard cells to be detected, and two lists of standard cells to be detected are obtained for testing the two lists of standard cells to be detected.

[0059] Optionally, in the case of obtaining one or more lists of standard cells to be tested, all the lists of standard cells to be tested can be tested, or some of the lists of standard cells to be tested can be tested. If the test is terminated midway, the test results of the tested standard cells are obtained.

[0060] In step S103, for each of the to-be-tested standard cells in the to-be-tested standard cell list, determine its placement pass rate in the layout planning diagram.

[0061] According to an embodiment of the present disclosure, on the layout planning diagram, the positions where the to-be-tested standard cells can be placed are standard positions. Place the to-be-tested standard cells in the to-be-tested standard cell list one by one at each standard position. After the placement is completed, perform design rule checking. When no design rule checking violations occur, determine the position where the to-be-tested standard cell is located as a valid position. The ratio of the number of valid positions to the number of standard positions is the placement pass rate of the standard cell.

[0062] In step S104, classify the multiple to-be-tested standard cells according to the determined placement pass rate of each of the to-be-tested standard cells.

[0063] According to an embodiment of the present disclosure, one or more thresholds can be set to form multiple threshold intervals. Different threshold intervals correspond to different classifications of the to-be-tested standard cells, and each classification represents a different matching degree between the to-be-tested standard cell and the chip layout design. For example, set two thresholds to form three threshold intervals, corresponding to three classifications of the to-be-tested standard cells, respectively representing high matching degree, medium matching degree, and low matching degree with the chip layout design. When the placement pass rate of the to-be-tested standard cell is within the corresponding threshold interval, the classification of the to-be-tested standard cell and its matching degree with the chip layout design can be determined.

[0064] Optionally, after the classification of the to-be-tested standard cells is completed, output the placement pass rate of each to-be-tested standard cell in the to-be-tested standard cell list obtained by testing and the classification results of the to-be-tested standard cells in tabular form.

[0065] Based on the above, in the present disclosure, by determining the placement pass rate of the standard cell and classifying the standard cell based on the placement pass rate, the standard cell that best matches the chip layout design can be quickly screened out, which is convenient for optimizing the standard cell with poor matching and improving the layout space utilization rate.

[0066] According to an embodiment of the present disclosure, the positions in the layout planning diagram where the standard cells can be placed are standard positions; wherein, for each of the to-be-tested standard cells in the to-be-tested standard cell list, determining its placement pass rate in the layout planning diagram includes: placing the to-be-tested standard cells in the to-be-tested standard cell list at each of the standard positions for design rule checking, and when no design rule checking violations occur, determining the position where the to-be-tested standard cell is located as a valid position; calculating the placement pass rate of the to-be-tested standard cell using the following equation:

[0067]

[0068] where PassRatio is the passing rate of the standard cell to be tested, Count 标准 is the number of the standard positions, Count 有效 is the number of the valid positions.

[0069] Situations causing design rule check violations include that when a standard cell is placed at a standard position, there is a conflict between the pins of the standard cell and the traces, and there is an overlap due to a small distance between the standard cell and the surrounding macro cells, etc.

[0070] For example, there are 10 AND gates in the list of standard cells to be tested, and there are 50 standard positions in the layout planning diagram. After obtaining the list of standard cells to be tested, the first standard cell is placed in each of the 50 standard positions one by one for design rule check. Design rule check violations do not occur in 43 of these positions, so the passing rate of this standard cell is 86%. After the 10 AND gates are each checked for design rules one by one in the 50 standard positions, the design rule check ends.

[0071] Optionally, the design rule check can utilize the original design rule check function of the software, or can be performed by a self-written program, and the design rules can be modified according to the actual design requirements and the adaptation situation with the standard cells.

[0072] Based on the above, in the present disclosure, by determining the valid positions and standard positions of the standard cells, the passing rate of the standard cells is calculated.

[0073] According to an embodiment of the present disclosure, classifying the standard cells to be tested according to the passing rate of the standard cells to be tested includes: generating n threshold ranges, where at least one of the threshold ranges corresponds to a category of the standard cells to be tested, and n > 1; determining the category of the standard cells to be tested according to the threshold range in which the passing rate of the standard cells to be tested is located.

[0074] For example, two thresholds of 50% and 80% can be determined, and then three threshold ranges of greater than 0% and less than or equal to 50%, greater than 50% and less than or equal to 80%, and greater than 80% and less than or equal to 100% are generated, corresponding to three types of standard cells, two types of standard cells, and one type of standard cell respectively. The three types of standard cells have a low matching degree with the chip layout design, the two types of standard cells have a medium matching degree with the chip layout design, and the one type of standard cell has a high matching degree with the chip layout design. Then when the passing rate of the standard cell is 46%, this standard cell is a three-type standard cell and has a low matching degree with the chip layout design; when the passing rate of the standard cell is 85%, this standard cell is a one-type standard cell and has a high matching degree with the chip layout design.

[0075] Optionally, according to different determined threshold quantities, the matching degree differentiation between the standard cells and the chip layout design can be more refined. For example, when determining three thresholds, the standard cells are divided into five categories, and the matching degrees between the corresponding standard cells and the chip layout design are divided into low matching degree, relatively low matching degree, medium matching degree, relatively high matching degree, and high matching degree.

[0076] Optionally, for this type of standard cell with a low passing rate, its matching degree with the current chip layout design is relatively low. When selecting the placement of standard cells, fewer or no such standard cells can be placed; alternatively, according to the requirements of the chip layout design, this type of standard cell can be optimized, such as modifying the shape of the standard cell, the pin positions, etc., so that the standard cell better adapts to the requirements of the chip layout design and improves the space utilization rate.

[0077] Figure 4 FIG. 200 is a flowchart of a method for testing the power supply and ground structure score of a layout planning diagram according to an embodiment of the present disclosure.

[0078] As Figure 4 shown, in step S201, a layout planning diagram is obtained. The layout planning diagram includes a plurality of pre-arranged layout blocks, and the plurality of pre-arranged layout blocks include a power supply block and a power supply and ground power supply network.

[0079] Optionally, the layout planning diagram can be generated using an Electronic Design Automation (EDA) platform.

[0080] According to an embodiment of the present disclosure, the layout planning diagram design is based on a grid. Layout blocks, including a power supply block, a power supply and ground power supply network, and other pre-arranged special signal wiring networks, etc., are pre-arranged on the layout planning diagram. The standard cells are arranged in rows in the format of cell rows; in the area between adjacent standard cell rows, a routing channel is arranged, and the routing is carried out in the routing channel. The power supply block, the power supply and ground power supply network are designed according to the power supply and ground design interchange format, and the power supply and ground design interchange format describes the actual design of the power supply and ground, lists the positions and connection relationships of the power supply and ground, and uses the design interchange format to transfer the design between different design systems.

[0081] In step S202, a standard cell list is obtained, and the standard cell list includes a plurality of standard cells.

[0082] Optionally, each standard cell list includes multiple standard cells. The standard cells in the standard cell list include various types such as AND gates, OR gates, XOR gates, XNOR gates, inverters, flip - flops, or latches. Each test standard cell list can include only one type of cell or multiple types of cells. For example, if there are 20 standard cells in the standard cell list, they can be 20 AND gates, or a combination of 8 AND gates, 3 OR gates, and 9 inverters.

[0083] Optionally, multiple standard cells can form one standard cell list or multiple standard cell lists. One standard cell list or multiple standard cell lists can be obtained. The number and type of standard cells in each list can be the same or different. For example, if the standard cells are 10 AND gates and 10 flip - flops, the 10 AND gates and 10 flip - flops can be grouped into 1 list to be tested, or 3 AND gates and 2 flip - flops can be grouped into one list to be tested, and 7 AND gates and 8 flip - flops can be grouped into another list to be tested, and then two lists to be tested are obtained and tested.

[0084] Optionally, in the case of obtaining multiple standard cell lists, all the standard cell lists can be tested, or some of the standard cell lists can be tested. If the test is ended halfway, the test results of the tested standard cells are obtained.

[0085] In step S203, for each of the standard cells in the standard cell list, determine its passing rate in the layout planning diagram.

[0086] According to the embodiments of the present disclosure, on the layout planning diagram, the positions where standard cells can be placed are standard positions. Place the standard cells in the standard cell list one by one at each standard position. After placement, perform a design rule check. If no design rule check violation occurs, determine the position where the standard cell is located as a valid position. The ratio of the number of valid positions to the number of standard positions is the passing rate of the standard cell.

[0087] In step S204, based on the passing rate of each of the standard cells in the standard cell list, obtain the total passing rate of the standard cell list.

[0088] Optionally, perform one of the calculations of summing, weighted summing, and taking the average of the through - put rates of all the standard cells in a standard cell list to obtain the total through - put rate of the standard cell list. For example, if there are 10 AND gates and 5 OR gates in a standard cell list, the through - put rates of the 15 gate devices can be added together as the total through - put rate of the standard cell list; weights of 1 and 0.5 can be assigned to the AND gates and OR gates respectively, and the through - put rates of the 15 gate devices can be weighted and summed as the total through - put rate of the standard cell list; the average of the through - put rates of the 15 gate devices can be taken as the total through - put rate of the standard cell list.

[0089] Optionally, when calculating the total through - put rate for multiple standard cell lists, perform one of the calculations of summing, weighted summing, and taking the average of the total through - put rates of the multiple standard cell lists respectively to obtain the total through - put rate of all the standard cell lists. For example, if there are 2 standard cell lists, the total through - put rates of the 2 standard cell lists can be added together as the total through - put rate of the 2 standard cell lists; weights of 1 and 0.5 can be assigned to the 2 standard cell lists respectively, and the total through - put rates of the 2 standard cell lists can be weighted and summed as the total through - put rate of the 2 standard cell lists; the average of the total through - put rates of the 2 standard cell lists can be taken as the total through - put rate of the 2 standard cell lists.

[0090] The above - mentioned embodiments of the present disclosure are only used as examples for calculating the total through - put rate and should not be regarded as a limitation on the method for calculating the total through - put rate.

[0091] In step S205, calculate the power supply and grounding structure score of the layout planning diagram according to the total through - put rate.

[0092] Optionally, the total through - put rate of the standard cell list can be directly used as the score of the power supply and grounding structure of the layout planning diagram, or the total through - put rate of the standard cell list can be divided by the shortest distance between the power supply and the ground, and the calculation result is used as the score of the power supply and grounding structure of the layout planning diagram.

[0093] The above - mentioned embodiments of the present disclosure are only used as examples and should not be regarded as a limitation on the method for calculating the power supply and grounding structure score of the layout planning diagram according to the total through - put rate.

[0094] Based on the above, in the present disclosure, by determining the total through - put rate of the standard cell list and calculating the power supply and grounding structure score of the layout planning diagram, the power supply and grounding structure most adapted to the existing standard cell list can be quickly screened.

[0095] Figure 5 Shows a flowchart of method 300 for comparing the power supply and grounding structure scores of the layout planning diagram.

[0096] As Figure 5As shown, in step S301, obtain another layout planning diagram, determine the total routing rate of the standard cell list in the another layout planning diagram, and calculate the power supply and grounding structure score of the another layout planning diagram.

[0097] Optionally, after obtaining another layout planning diagram and calculating the power supply and grounding structure score of the another layout planning diagram, other different layout planning diagrams can be continuously obtained to obtain multiple layout planning diagrams.

[0098] In step S302, compare the power supply and grounding structure score of the layout planning diagram with the power supply and grounding structure score of the another layout planning diagram, and determine the power supply and grounding structure with the higher score as the most suitable structure for the standard cell list.

[0099] Optionally, multiple layout planning diagrams can be obtained, and the power supply and grounding structure scores of the multiple layout planning diagrams are compared. The power supply and grounding structure with the highest score is the most suitable structure for the standard cell list. For example, when the power supply and grounding structure score of the first layout planning diagram is 70 points, the power supply and grounding structure score of the second layout planning diagram is 90 points, and the power supply and grounding structure score of the third layout planning diagram is 50 points, the second layout planning diagram is more suitable for the standard cell list, and the second layout planning diagram can be selected to cooperate with the standard cell list during the chip design process.

[0100] Based on the above, in the present disclosure, by comparing the power supply and grounding structure scores of different layout planning diagrams, a power supply and grounding design that is more suitable for the standard cell list can be selected.

[0101] Figure 6 Shows a flowchart of method 400 for determining whether the power supply and grounding structure of a layout planning diagram meets the design requirements of the layout planning diagram.

[0102] As Figure 6 shown, in step S401, according to the power supply and grounding structure score of the layout planning diagram, determine whether the power supply and grounding structure of the layout planning diagram meets the design requirements of the layout planning diagram.

[0103] According to an embodiment of the present disclosure, determining whether the power supply and grounding structure of the layout planning diagram meets the design requirements of the layout planning diagram includes: generating a design requirement threshold range, and in the case where the power supply and grounding structure score of the layout planning diagram is within the design requirement threshold range, the power supply and grounding structure of the layout planning diagram meets the design requirements.

[0104] For example, if 60 is the passing score for the power supply and grounding structure of the layout planning diagram to meet the design requirements of the layout planning diagram, then when the score of the power supply and grounding structure of the layout planning diagram is greater than or equal to 60, the power supply and grounding structure of the layout planning diagram meets the design requirements, and when the score of the power supply and grounding structure of the layout planning diagram is less than 60, the power supply and grounding structure of the layout planning diagram does not meet the design requirements.

[0105] In step S402, in the case where the power supply and grounding structure of the layout planning diagram does not meet the design requirements of the layout planning diagram, adjust the layout of the power block and the power supply and grounding power network.

[0106] Optionally, adjust the layout of the power block and the power supply and grounding power network, and then determine again whether the power supply and grounding structure of the layout planning diagram meets the design requirements of the layout planning diagram until the design requirements are met.

[0107] According to another aspect of the present disclosure, there is also provided a standard cell throughput rate test and classification device. Figure 11 FIG. shows a schematic block diagram of a standard cell throughput rate test and classification device 500 according to an embodiment of the present disclosure.

[0108] As Figure 11 shown, the standard cell throughput rate test and classification device 500 may include a layout planning diagram acquisition module 501, a list acquisition module 502, a throughput rate test module 503, and a classification module 504.

[0109] Among them, the layout planning diagram acquisition module 501 may be configured to acquire a layout planning diagram, and the layout planning diagram includes a plurality of pre-arranged layout blocks.

[0110] Optionally, the acquired layout planning diagram may be generated using an Electronic Design Automation (EDA) platform.

[0111] The list acquisition module 502 may be configured to acquire a list of standard cells to be tested, and the list of standard cells to be tested includes a plurality of standard cells to be tested.

[0112] Optionally, the acquired plurality of standard cells to be tested may form a list of standard cells to be tested or multiple lists of standard cells to be tested. The list acquisition module 502 may acquire one list of standard cells to be tested or multiple lists of standard cells to be tested. The number of standard cells to be tested and the type of standard cells in each list may be the same or different.

[0113] The throughput rate test module 503 may be configured to determine the throughput rate of each standard cell to be tested in the layout planning diagram for each standard cell to be tested in the list of standard cells to be tested.

[0114] Optionally, on the layout planning diagram, the positions where the standard cells to be tested can be placed are standard positions. The placement pass rate testing module 503 places the standard cells to be tested in the list of standard cells to be tested one by one at each standard position. After the placement is completed, a design rule check is performed. If no design rule check violation occurs, the position where the standard cell to be tested is located is determined as a valid position. The ratio of the number of valid positions to the number of standard positions is the placement pass rate of the standard cell.

[0115] The classification module 504 can be configured to classify the multiple standard cells to be tested according to the placement pass rate of each determined standard cell to be tested.

[0116] Optionally, one or more thresholds can be set to form multiple threshold intervals. Different threshold intervals correspond to different classifications of the standard cells to be tested, and each classification represents a different matching degree between the standard cells to be tested and the chip layout design.

[0117] According to another aspect of the present disclosure, there is also provided a power supply and ground structure score testing device for a layout planning diagram. Figure 12 FIG. shows a schematic block diagram of a power supply and ground structure score testing device 200 for a layout planning diagram according to an embodiment of the present disclosure.

[0118] As Figure 12 shown, the power supply and ground structure score testing device 600 for the layout planning diagram may include a layout planning diagram acquisition module 601, a list acquisition module 602, a placement pass rate testing module 603, and a score testing module 604.

[0119] Among them, the layout planning diagram acquisition module 601 can be configured to acquire a layout planning diagram, and the layout planning diagram includes a plurality of pre-arranged layout blocks, and the plurality of pre-arranged layout blocks include power supply blocks and power supply and ground power supply networks.

[0120] Optionally, the acquired layout planning diagram can be generated using an Electronic Design Automation (EDA) platform.

[0121] The list acquisition module 602 can be configured to acquire a standard cell list, and the standard cell list includes a plurality of standard cells.

[0122] Optionally, each standard cell list acquired by the list acquisition module 602 includes a plurality of standard cells. The standard cells in the standard cell list include various types such as AND gates, OR gates, XOR gates, XNOR gates, inverters, flip-flops, or latches. Each test standard cell list can include only one type of cell or multiple types of cells.

[0123] The via rate test module 603 can be configured to determine the via rate of each of the standard cells in the list of standard cells in the layout planning diagram.

[0124] Optionally, on the layout planning diagram, the positions where standard cells can be placed are standard positions. The via rate test module 603 places the standard cells in the list of standard cells one by one at each standard position. After the placement is completed, a design rule check is performed. If no design rule check violation occurs, the position where the standard cell is located is determined to be a valid position. The ratio of the number of valid positions to the number of standard positions is the via rate of the standard cell.

[0125] The score test module 604 can be configured to obtain the total via rate of the list of standard cells based on the via rate of each of the standard cells in the list of standard cells, and calculate the power supply and ground structure score of the layout planning diagram according to the total via rate.

[0126] Optionally, the total via rate of the list of standard cells can be directly used as the score of the power supply and ground structure of the layout planning diagram, or the total via rate of the list of standard cells can be divided by the shortest distance between the power supply and the ground, and the calculation result is used as the score of the power supply and ground structure of the layout planning diagram.

[0127] According to another aspect of the present disclosure, there is also provided a standard cell via rate test and classification device. Figure 7 FIG. shows a schematic diagram of a standard cell via rate test and classification device 1000 according to an embodiment of the present disclosure.

[0128] As Figure 7 shown, the standard cell via rate test and classification device 1000 may include one or more processors 1001 and one or more memories 1002. Among them, computer-readable code is stored in the memory 1002, and when the computer-readable code is run by the one or more processors 1001, the method described above can be executed.

[0129] According to another aspect of the present disclosure, there is also provided a power supply and ground structure score test device for a layout planning diagram. Figure 8 FIG. shows a schematic diagram of a power supply and ground structure score test device 2000 for a layout planning diagram according to an embodiment of the present disclosure.

[0130] As Figure 8 shown, the power supply and ground structure score test device 2000 for the layout planning diagram may include one or more processors 2001 and one or more memories 2002. Among them, computer-readable code is stored in the memory 2002, and when the computer-readable code is run by the one or more processors 2001, the method described above can be executed.

[0131] The processor in the embodiments of the present disclosure may be an integrated circuit chip with signal processing capabilities. The above-mentioned processor may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. It can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc., and may be of the X86 architecture or the ARM architecture.

[0132] Generally speaking, the various exemplary embodiments of the present disclosure may be implemented in hardware or dedicated circuits, software, firmware, logic, or any combination thereof. Some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software that can be executed by a controller, a microprocessor or other computing devices. When aspects of the embodiments of the present disclosure are illustrated or described as block diagrams, flowcharts or using some other graphical representation, it will be understood that the blocks, devices, systems, technologies or methods described herein may be implemented as non-limiting examples in hardware, software, firmware, dedicated circuits or logic, general-purpose hardware or controllers or other computing devices, or some combination thereof.

[0133] For example, the method or device according to the embodiments of the present disclosure may also be implemented by means of Figure 9 the architecture of the computing device 3000 shown. As Figure 9 shown, the computing device 3000 may include a bus 3010, one or more CPUs 3020, a read-only memory (ROM) 3030, a random access memory (RAM) 3040, a communication port 3050 connected to a network, an input / output component 3060, a hard disk 3070, etc. The storage device in the computing device 3000, such as the ROM 3030 or the hard disk 3070, may store various data or files used for the processing and / or communication of the methods provided by the present disclosure and the program instructions executed by the CPU. The computing device 3000 may also include a user interface 3080. Of course, Figure 9 the architecture shown is only exemplary, and when implementing different devices, one or more components shown in the Figure 9 computing device may be omitted according to actual needs.

[0134] According to yet another aspect of the present disclosure, a computer-readable storage medium is also provided. Figure 10 FIG. 4000 shows a schematic diagram of the storage medium according to the present disclosure.

[0135] As Figure 10As shown, computer-readable instructions 4010 are stored on the computer storage medium 4020. When the computer-readable instructions 4010 are run by a processor, the methods according to the embodiments of the present disclosure described with reference to the above figures can be executed. The computer-readable storage medium in the embodiments of the present disclosure can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. The non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus random access memory (DR RAM). It should be noted that the memory for the methods described herein is intended to include, but is not limited to, these and any other suitable types of memory. It should be noted that the memory for the methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0136] Embodiments of the present disclosure also provide a computer program product or a computer program. The computer program product or the computer program includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the methods according to the embodiments of the present disclosure.

[0137] Embodiments of the present disclosure provide a method, a device, a computer program product, and a readable storage medium for testing and classifying the pass-through rate of standard cells. The method provided by the embodiments of the present disclosure includes obtaining a layout planning diagram, where the layout planning diagram includes a plurality of pre-arranged layout blocks; obtaining a list of standard cells to be tested, where the list of standard cells to be tested includes a plurality of standard cells to be tested; for each standard cell to be tested in the list of standard cells to be tested, determining its pass-through rate in the layout planning diagram; and classifying the plurality of standard cells to be tested according to the determined pass-through rate of each standard cell to be tested, so as to quickly screen out the standard cells that best match the chip layout design.

[0138] Through the method of the present disclosure, standard cells that best match the chip layout design can be quickly screened out, facilitating the optimization of standard cells with poor matching, and improving the utilization rate of the layout space. In addition, the method of the present disclosure can be applied to the power supply and ground structure score test of the layout planning diagram, select the power supply and ground structure that best matches the existing standard cell list, and determine whether the power supply and ground structure meets the design requirements.

[0139] It should be noted that the flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code that contains at least one executable instruction for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than that marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, as well as the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or operations, or by a combination of dedicated hardware and computer instructions.

[0140] Generally speaking, various exemplary embodiments of the present disclosure can be implemented in hardware or dedicated circuits, software, firmware, logic, or any combination thereof. Some aspects can be implemented in hardware, while other aspects can be implemented in firmware or software that can be executed by a controller, a microprocessor, or other computing devices. When aspects of the embodiments of the present disclosure are illustrated or described as block diagrams, flowcharts, or using some other graphical representation, it will be understood that the blocks, devices, systems, technologies, or methods described herein can be implemented as non-limiting examples in hardware, software, firmware, dedicated circuits or logic, general hardware or controllers or other computing devices, or some combination thereof.

[0141] The exemplary embodiments of the present disclosure described in detail above are merely illustrative and not restrictive. Those skilled in the art should understand that various modifications and combinations can be made to these embodiments or their features without departing from the principles and spirit of the present disclosure, and such modifications should fall within the scope of the present disclosure.

Claims

1. A classification method for the pass-through rate test of standard cells, including: Obtaining a layout planning diagram, where the layout planning diagram includes multiple pre-arranged layout blocks; Obtaining a list of standard cells to be tested, where the list of standard cells to be tested includes multiple standard cells to be tested; For each of the standard cells to be tested in the list of standard cells to be tested, determining its pass-through rate in the layout planning diagram; and Classifying the multiple standard cells to be tested according to the pass-through rate of each of the determined standard cells to be tested; wherein, the position in the layout planning diagram where the standard cell can be placed is the standard position; For each of the standard cells to be tested in the list of standard cells to be tested, determining its pass-through rate in the layout planning diagram includes: Placing the standard cells to be tested in the list of standard cells to be tested at each of the standard positions for design rule checking, and when no design rule checking violation occurs, determining the position where the standard cell to be tested is located as a valid position; wherein, the ratio of the number of valid positions to the number of standard positions is the pass-through rate of the standard cell.

2. The classification method according to claim 1, wherein, Classifying the standard cells to be tested according to the pass-through rate of the standard cells to be tested includes: Generating n threshold ranges, where at least one of the threshold ranges corresponds to a category of the standard cells to be tested, and n > 1; Determining the category of the standard cells to be tested according to the threshold range in which the pass-through rate of the standard cells to be tested is located.

3. A method for testing the power supply and grounding structure score of a layout planning diagram, including: Obtaining a layout planning diagram, where the layout planning diagram includes multiple pre-arranged layout blocks, and the multiple pre-arranged layout blocks include power supply blocks and a power supply and grounding power supply network; Obtaining a list of standard cells, where the list of standard cells includes multiple standard cells; For each of the standard cells in the list of standard cells, determining its pass-through rate in the layout planning diagram; Based on the pass-through rate of each of the standard cells in the list of standard cells, obtaining the total pass-through rate of the list of standard cells; and Calculating the power supply and grounding structure score of the layout planning diagram according to the total pass-through rate; wherein, the position in the layout planning diagram where the standard cell can be placed is the standard position; For each of the standard cells to be tested in the list of standard cells to be tested, determining its pass-through rate in the layout planning diagram includes: Placing the standard cells to be tested in the list of standard cells to be tested at each of the standard positions for design rule checking, and when no design rule checking violation occurs, determining the position where the standard cell to be tested is located as a valid position; wherein, the ratio of the number of valid positions to the number of standard positions is the pass-through rate of the standard cell.

4. The testing method according to claim 3, wherein, Obtaining the total pass-through rate of the list of standard cells based on the pass-through rate of each of the standard cells in the list of standard cells includes: Perform one of summation, weighted summation, and averaging on the pass-through rates of all the standard cells to obtain the total pass-through rate of the standard cell list.

5. The test method according to claim 3, further comprises: Obtain another layout plan, determine the total pass-through rate of the standard cell list in the another layout plan, and calculate the power supply and grounding structure score of the another layout plan; Compare the power supply and grounding structure score of the layout plan with the power supply and grounding structure score of the another layout plan, and determine the power supply and grounding structure with a higher score as the most suitable structure for the standard cell list.

6. The test method according to claim 3, further comprises: Judge whether the power supply and grounding structure of the layout plan meets the design requirements of the layout plan according to the power supply and grounding structure score of the layout plan; In the case where the power supply and grounding structure of the layout plan does not meet the design requirements of the layout plan, adjust the layout of the power block and the power supply and grounding power network.

7. The test method according to claim 6, wherein, judging whether the power supply and grounding structure of the layout plan meets the design requirements of the layout plan includes: Generate a design requirement threshold range. When the power supply and grounding structure score of the layout plan is within the design requirement threshold range, the power supply and grounding structure of the layout plan meets the design requirements.

8. A standard cell pass-through rate test classification device, comprises: A layout plan acquisition module configured to acquire a layout plan, the layout plan including a plurality of pre-arranged layout blocks; A list acquisition module configured to acquire a list of standard cells to be tested, the list of standard cells to be tested including a plurality of standard cells to be tested; A pass-through rate test module configured to determine the pass-through rate of each standard cell to be tested in the layout plan for the list of standard cells to be tested; and A classification module configured to classify the plurality of standard cells to be tested according to the determined pass-through rate of each standard cell to be tested; wherein, the position in the layout plan where the standard cell can be placed is a standard position; For each standard cell to be tested in the list of standard cells to be tested, determining its pass-through rate in the layout plan includes: Place the standard cell to be tested in the list of standard cells to be tested at each standard position for design rule checking. When no design rule checking violation occurs, determine the position where the standard cell to be tested is located as a valid position; wherein, the ratio of the number of valid positions to the number of standard positions is the pass-through rate of the standard cell.

9. A power supply and grounding structure score test device for a layout plan, comprises: A layout plan acquisition module configured to acquire a layout plan, the layout plan including a plurality of pre-arranged layout blocks, and the plurality of pre-arranged layout blocks including a power block and a power supply and grounding power network; A list acquisition module, configured to acquire a standard cell list, where the standard cell list includes a plurality of standard cells; A penetration rate test module, configured to determine, for each of the standard cells in the standard cell list, its penetration rate in the layout planning diagram; A score test module, configured to obtain the total penetration rate of the standard cell list based on the penetration rate of each of the standard cells in the standard cell list, and calculate the power supply and ground structure score of the layout planning diagram according to the total penetration rate; Wherein, the positions in the layout planning diagram where the standard cells can be placed are standard positions; Determining, for each of the to-be-tested standard cells in the to-be-tested standard cell list, its penetration rate in the layout planning diagram includes: Placing the to-be-tested standard cells in the to-be-tested standard cell list at each of the standard positions for design rule checking, and determining the position where the to-be-tested standard cell is located as a valid position when no design rule checking violation occurs; wherein, the ratio of the number of the valid positions to the number of the standard positions is the penetration rate of the standard cell.

10. A standard cell penetration rate test and classification device, including: One or more processors; And One or more memories, storing computer-executable programs, which, when executed by the processors, execute the method according to any one of claims 1 or 2.

11. A power supply and ground structure score test device for a layout planning diagram, including: One or more processors; And One or more memories, storing computer-executable programs, which, when executed by the processors, execute the method according to any one of claims 3-7.

12. A computer program product, including computer software code, which is used to implement the method according to any one of claims 1-7 when run by a processor.

13. A computer-readable storage medium, storing computer-executable instructions thereon, which are used to implement the method according to any one of claims 1-7 when executed by a processor.

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