Non-volatile memory, control method thereof, and storage system

Abstract

The present application provides a non-volatile memory, a control method thereof, and a storage system. The non-volatile memory includes a plurality of memory strings, each memory string includes a plurality of memory cell groups, and each memory cell group includes a plurality of memory cells. The method includes: performing an erase and reprogram operation on a partial memory cell group of the memory string, wherein the memory cell group on which the erase and reprogram operation is performed is a first memory cell group, and the memory cell group in the memory string on which the erase and reprogram operation is not performed is a second memory cell group; and applying a conduction voltage to unselected memory cells when performing a read operation on selected memory cells, wherein a first conduction voltage is applied to unselected memory cells in the first memory cell group, and a second conduction voltage is applied to unselected memory cells in the second memory cell group, and the first conduction voltage is greater than the second conduction voltage.

Description

Technical Field

[0001] The present application relates to the field of memories, and more specifically, to a non-volatile memory, a control method thereof, and a non-volatile storage system. Background Art

[0002] Flash memories have widely used 3D NAND flash chips to process data. As the number of 3D NAND stacking layers increases, the storage capacity of a block gradually increases, that is, the amount of data contained in a block filled with data is gradually increasing. Existing 3D NAND flash chips usually adopt an erasure operation in units of blocks. When it is necessary to delete some data in a block and retain some other data, it is necessary to first transfer the data to be retained to another blank block, and then perform a whole-block erasure operation on the current block. In order to reduce the amount of data to be transferred during this operation process, a block partial erasure and rewrite operation has also emerged in the erasure operation of current 3D NAND flash chips. Generally speaking, only the page where the data to be deleted is located is erased, while the pages where the data to be retained are located remain unchanged, and then new data is written on the erased pages. However, due to the problems in the current specific technical implementation, it is difficult to perform an erasure and reprogramming operation on any page. Usually, physically continuous word lines are divided into several groups, and then a block partial erasure and reprogramming operation is performed on one or more word line groups.

[0003] During the programming operation or reading operation of a 3D NAND flash chip, a programming voltage or a reading voltage needs to be applied to the word line of the selected programming or reading memory cell, and a conduction voltage is applied to other memory cells on the same memory string as the selected programming or reading memory cell. There is a voltage difference between the conduction voltage and the above-mentioned programming voltage or reading voltage, which will cause programming interference or read interference in non-programming or non-reading memory cells during the programming or reading process. As the number of programming or reading times increases, the programming interference or read interference becomes larger and larger, which easily leads to a decrease in the data reliability of non-programming or non-reading memory cells. The decrease in data reliability is mainly reflected in that the threshold distribution of the memory cells in the lowest state drifts towards the high threshold direction, resulting in a smaller reading window for the lowest state, and making it easy for the word lines of the memory cells in the lowest state to fail in the reading operation. Summary of the Invention

[0004] In view of the above or at least some other deficiencies in the related art, the present application provides a non-volatile memory and a control method thereof.

[0005] One aspect of the present application provides a control method for a non-volatile memory. The non-volatile memory includes a plurality of memory strings, each memory string includes a plurality of memory cell groups, and each memory cell group includes a plurality of memory cells. The method is characterized in that the method includes: performing an erase and reprogram operation on a partial memory cell group of the memory string, wherein the memory cell group on which the erase and reprogram operation is performed is a first memory cell group, and the memory cell group in the memory string on which the erase and reprogram operation is not performed is a second memory cell group; and when performing a read operation on a selected memory cell, applying a conduction voltage to an unselected memory cell, wherein a first conduction voltage is applied to an unselected memory cell in the first memory cell group, and a second conduction voltage is applied to an unselected memory cell in the second memory cell group, and the first conduction voltage is greater than the second conduction voltage.

[0006] In one embodiment, the memory string further includes a redundant cell group located between the plurality of memory cell groups. The method further includes: when performing a read operation on a selected memory cell, applying a third conduction voltage to the redundant cell group, wherein the third conduction voltage is less than the first conduction voltage and greater than the second conduction voltage.

[0007] In one embodiment, the voltage difference between the first conduction voltage and the third conduction voltage is less than 1V, and the voltage difference between the third conduction voltage and the second conduction voltage is less than 1V.

[0008] In one embodiment, the method further includes: when performing a read operation on a selected memory cell, applying a read voltage to the selected memory cell.

[0009] In one embodiment, the non-volatile memory further includes a memory word line group coupled to the memory cell group. The method further includes: applying the first conduction voltage to the first memory cell group through the memory word line group corresponding to the first memory cell group, and applying the second conduction voltage to the second memory cell group through the memory word line group corresponding to the second memory cell group.

[0010] In one embodiment, the non-volatile memory further includes a redundant word line group coupled to the redundant cell group. The method further includes: applying the third conduction voltage to the redundant cell group through the redundant word line group.

[0011] In one embodiment, the non-volatile memory includes any one of a single-level cell (SLC) flash memory, a multi-level cell (MLC) flash memory, a three-level cell (TLC) flash memory, a four-level cell (QLC) flash memory, and a five-level cell (PLC) flash memory.

[0012] Another aspect of the present application provides a non-volatile memory, comprising: a storage array including a plurality of memory strings, each of the memory strings including a plurality of memory cell groups, and each of the memory cell groups including a plurality of memory cells, wherein the memory cell groups in the memory string that perform an erase and reprogram operation are first memory cell groups, and the memory cell groups that do not perform an erase and reprogram operation are second memory cell groups; and a control circuit configured to, when performing a read operation on a selected memory cell, apply a first conduction voltage to unselected memory cells in the first memory cell groups and apply a second conduction voltage to unselected memory cells in the second memory cell groups, wherein the first conduction voltage is greater than the second conduction voltage.

[0013] In one embodiment, the memory string further includes a redundant cell group located between the plurality of memory cell groups, and the control circuit is further configured to: when performing a read operation on a selected memory cell, apply a third conduction voltage to the redundant cell group, wherein the third conduction voltage is less than the first conduction voltage and greater than the second conduction voltage.

[0014] In one embodiment, the non-volatile memory further includes: a voltage generation circuit coupled to the storage array and configured to generate the first conduction voltage, the second conduction voltage, and the third conduction voltage in response to a command of the control circuit.

[0015] In one embodiment, the voltage difference between the first conduction voltage and the third conduction voltage is less than 1V, and the voltage difference between the third conduction voltage and the second conduction voltage is less than 1V.

[0016] In one embodiment, the non-volatile memory further includes a memory word line group coupled to the memory cell groups and a redundant word line group coupled to the redundant cell group.

[0017] In one embodiment, the control circuit is further configured to: when performing a read operation on a selected memory cell, apply a read voltage to the selected memory cell.

[0018] In one embodiment, the non-volatile memory includes any one of a single-level cell (SLC) flash memory, a multi-level cell (MLC) flash memory, a triple-level cell (TLC) flash memory, a quad-level cell (QLC) flash memory, and a penta-level cell (PLC) flash memory.

[0019] Another aspect of the present application further provides a non-volatile storage system, the storage system including: at least one non-volatile memory as described in any of the above embodiments; and a controller electrically connected to the non-volatile memory and configured to control the non-volatile memory to perform a control method as described in any of the above embodiments.

[0020] An embodiment of the present application provides a non - volatile memory, its control method, and a storage system. For blocks with partial erasure and reprogramming, the configuration of the conduction voltage of non - read storage units during a read operation is changed. Specifically: the conduction voltage of the storage unit group with partial erasure and reprogramming of the block is increased, while the conduction voltage of the storage unit group that retains the original data during the partial erasure and reprogramming operation of the block is decreased, so that the total resistance of the storage string during the read operation can remain unchanged and no additional read noise is caused. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] By reading the detailed description of the non - restrictive embodiments with reference to the following drawings, other features, objects, and advantages of the present application will become more apparent:

[0022] Figure 1 is a schematic diagram of the partial erasure and reprogramming operation of a block in the related art;

[0023] Figure 2 is Figure 1 the timing diagram of the read operation after the partial erasure and reprogramming operation of the block in;

[0024] Figure 3A and Figure 3B is the distribution diagram of the threshold voltage of the storage unit;

[0025] Figure 4 is the distribution diagram of the threshold voltage of the lowest state of the 3D NAND flash memory chip in different situations;

[0026] Figure 5 is a schematic flowchart of a control method for a non - volatile memory according to an embodiment of the present application;

[0027] Figure 6 is according to an embodiment of the present application Figure 1 the timing diagram of the read operation after the partial erasure and reprogramming operation of the block in;

[0028] Figure 7 is a schematic structural diagram of a non - volatile memory according to an embodiment of the present application;

[0029] Figure 8 is a schematic diagram of a storage array according to an exemplary embodiment of the present application; and

[0030] Figure 9A and 9B is a functional block diagram of a non - volatile storage system according to an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] To better understand the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application and do not limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0032] It should be noted that in this specification, the expressions such as first, second, third, etc. are only used to distinguish one feature from another feature and do not represent any limitation on the features. Therefore, without departing from the teachings of the present application, the first storage unit group discussed below may also be referred to as the second storage unit group. Vice versa.

[0033] It should also be understood that the terms "comprise", "comprising", "have", "including" and / or "containing", when used in this specification, indicate the presence of the stated features, elements and / or components, but do not preclude the presence or addition of one or more other features, elements, components and / or combinations thereof. In addition, when an expression such as "at least one of..." appears after a list of listed features, it modifies the entire list of listed features rather than an individual element in the list. In addition, when describing embodiments of the present application, the use of "may" means "one or more embodiments of the present application". And the term "exemplary" is intended to refer to an example or illustration.

[0034] Unless otherwise defined, all terms used herein (including engineering terms and scientific and technical terms) have the same meaning as commonly understood by those of ordinary skill in the art to which the present application pertains. It should also be understood that unless there is a clear statement in the present application, words defined in a commonly used dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense.

[0035] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments may be combined with each other. In addition, unless explicitly defined or in contradiction with the context, the specific steps included in the methods described in the present application do not have to be limited to the recited order and may be executed in any order or executed in parallel. The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0036] Figure 1 is a schematic diagram of the block partial erasure and reprogramming operation of the related art. As Figure 1As shown in the left figure in [context], a storage string 1 includes storage cell groups 101 to 103 and redundant cell groups 201 to 203. The redundant cell groups 201 to 203 are respectively located between the storage cell groups 101 to 103. Exemplarily, the storage cell groups 101 to 103 are electrically connected to corresponding storage word line groups (not shown), and the redundant cell groups 201 to 203 are electrically connected to corresponding redundant word line groups (not shown). The storage cell groups 101 to 103 may respectively include a plurality of storage cells. For example, the storage cell group 101 includes storage cells 1011 to 1012. The redundant cell groups 201 to 203 may respectively include a plurality of redundant cells (not shown). In an exemplary embodiment, the storage cell groups 101 to 103 are all filled with data. For example, if the storage cell group 102 is selected for an erase and reprogram operation, then as Figure 1 shown in the middle figure of [context], first, an erase operation is performed on the storage cell group 102, while the data of other storage cell groups (such as the storage cell group 101 and the storage cell group 103) is retained. Then as Figure 1 shown in the right figure of [context], a reprogram operation is performed on the storage cell group 102, that is, new data is written into the storage cell group 102.

[0037] When performing a read operation on a selected storage cell, a read voltage needs to be applied to the selected storage cell, and a conduction voltage is applied to other storage cells and redundant cells on the same storage string as the storage cell for this read operation, so that these storage cells are all in an on state. Among them, the conduction voltage is also referred to as a transfer voltage or an on voltage.

[0038] Figure 2 is Figure 1 the timing diagram of the read operation after the block partial erase and reprogram operation in [context]. Exemplarily, the storage cell 1011 in the storage cell group 101 is selected for a read operation, and the other storage cells 101a in the storage cell group 101 are not subjected to a read operation. As Figure 2 shown, the horizontal axis represents time t, and the vertical axis represents voltage. For example, when a read operation is performed on the storage cell 1011 of the storage string 1 between t1 and t2, then a read voltage Vread is applied to the storage cell 1011 between t1 and t2. Among them, exemplarily, the read voltage Vread can be stepped. And a conduction voltage Vpass of the same magnitude can be applied to the non-read storage cells 101a of the storage string 1, the storage cell group 102, the storage cell group 103, and the redundant cell groups 201 to 203, so that the entire storage string 1 is conductive.

[0039] The above selection of the storage cell 1011 for a read operation is only an exemplary illustration. Actually, any storage cell in the storage cell groups 101 to 103 can be selected for a read operation. Figure 1The number of storage cell groups and redundant cell groups in [it] can be any number, and this application does not limit it. In addition, those skilled in the art should understand that the voltages applied to the storage cell groups 101 to 103 and the redundant cell groups 201 to 203 are all applied through the corresponding storage word line groups and redundant word line groups that are electrically connected to them.

[0040] Figure 3A and Figure 3B is a distribution diagram of the threshold voltages of the storage cells. Among them, the horizontal axis is the threshold voltage Vt, and the vertical axis is the number of storage cells. Figure 3A and Figure 3B Taking the multi-level cell (MLC) technology as an example, according to this technology, each storage cell stores two bits of information, namely 00, 01, 10, and 11. The threshold voltage of the storage cell can be in four different states, namely, as Figure 3A and Figure 3B shown, the P0 state, the P1 state, the P2 state, and the P3 state. Exemplarily, the P0 state is the lowest state, corresponding to the data format 00, and the P1 state, the P2 state, and the P3 state correspond to the data formats 01, 10, and 11 respectively.

[0041] Figure 3A is the distribution diagram of the threshold voltages of the storage cells without interference. Referring to Figure 3A shown, there is a window distance between each state, and this window distance can be divided into multiple windows, such as the E0 window and the E1 window between the P0 state and the P1 state. Among them, the E0 window is close to the E state, and the E1 window is close to the P1 state. By analogy, the window distances between the P1 state, the P2 state, and the P3 state are divided into the E2 window, the E3 window, the E4 window, and the E5 window.

[0042] When performing a programming operation or a read operation on the storage cells of a 3D NAND flash memory chip, a programming or reading voltage is applied to the word line of the storage cell to be programmed or read, and a conduction voltage is applied to the other storage cells on the same storage string as the storage cell to be programmed or read. The conduction voltage causes interference to the P0 state, the P1 state, the P2 state, and the P3 state, especially to the storage cells in the lowest state (P0 state). Since the threshold voltage of the lowest state (P0 state) is small, the voltage difference between the threshold voltage of the P0 state and the conduction voltage is relatively large, the electric field strength is relatively large, and the tunneling effect is strong. Therefore, the lowest state (P0 state) is most easily affected by the programming effect of the conduction voltage. The conduction voltage causes the threshold distributions of the various states of the non-read storage cells to drift towards the high-threshold direction, especially causing the distribution of the lowest state (P0 state) to drift towards the direction close to the P1 state (as Figure 3BAs shown, the E0 window becomes smaller. Since the E0 window becomes smaller, it may lead to reading errors in the memory cells in the lowest state (P0 state), reducing the reliability of data storage. This is the programming interference and read interference that exist during the programming or reading process of memory cells. Programming interference and read interference will cause the data reliability of the memory cells located on these word lines to decline, which is mainly reflected in the fact that the threshold distribution of the lowest state will shift towards the high threshold direction, resulting in a smaller reading window for the lowest state, and thus the memory cells in the lowest state are prone to read operation failures.

[0043] Figure 4 is the threshold voltage distribution diagram of the lowest state of a 3D NAND flash memory chip under different conditions. Refer to Figure 4 As shown, the solid line 1 is the threshold voltage distribution diagram of the lowest state (P0 state) after performing a full block erase and then reprogramming. Affected by programming interference, the threshold voltage of the lowest state (P0 state) after performing a full block erase and then reprogramming drifts towards the direction close to the P1 state. Assuming the reading window becomes E01, all the following discussions are based on the solid line 1 as a reference.

[0044] Based on the solid line 1, that is, on the basis of performing a full block erase and then reprogramming, continue to perform a partial block erase and then reprogramming operation. The threshold voltage distribution of the lowest state (P0 state) of the memory cells that retain the original data is the dashed line 2. Due to the interference of the partial block erase and then reprogramming, the threshold voltage distribution of the lowest state (P0 state) of the memory cells that retain the original data drifts towards the direction close to the P1 state, and the reading window is E02, and the E02 window becomes smaller compared to E01. Based on the dashed line 2, that is, after performing a full block erase and then reprogramming and then performing a partial block erase and then reprogramming operation, after several (such as 1000 times) read operations, the threshold voltage distribution of the lowest state (P0 state) of the memory cells that retain the original data is the dashed line 3. Due to the influence of several read interferences, the threshold voltage distribution of the lowest state (P0 state) of the memory cells that retain the original data continues to drift towards the direction close to the P1 state, and the reading window E03 of the dashed line 3 further decreases. Since the E0 window becomes smaller, it may lead to reading errors in the memory cells in the lowest state (P0 state), reducing the reliability of data storage. The dashed line 4 is for the memory cells that perform erase and reprogramming during the partial block erase and then reprogramming. Compared with the solid line 1 of performing a full block erase and then reprogramming, since only some memory cells perform the erase and reprogramming operation, the programming interference received is much smaller, so the dashed line 4 is lower than the solid line 1, and the reading window E04 becomes larger.

[0045] In summary, in the related art, applying the same conduction voltage to the memory cells that are not read during the read operation after the partial block erase and then reprogramming will cause relatively serious programming interference and read interference.

[0046] Figure 5Schematic flowchart of a control method for a non-volatile memory according to an embodiment of the present application. The non-volatile memory includes a plurality of memory strings, each memory string includes a plurality of memory cell groups and redundant cell groups located between the plurality of memory cell groups, and the redundant cell groups do not store data. Referring again to Figure 1 , the non-volatile memory includes a plurality of memory strings 1, and each memory string 1 may include memory cell groups 101-103 and redundant cell groups 201-203. The redundant cell groups 201-203 are respectively located between the memory cell groups 101-103. The memory cell groups 101-103 are electrically connected to corresponding memory word line groups (not shown), and the redundant cell groups 201-203 are electrically connected to corresponding redundant word line groups (not shown). Exemplarily, the memory cell groups 101-103 may respectively include a plurality of memory cells. For example, the memory cell group 101 includes memory cells 1011-1012. The redundant cell groups 201-203 may respectively include a plurality of redundant cells (not shown) Figure 1 Only three memory cell groups and three redundant cell groups are schematically shown in

[0047] Refer to Figure 5 As shown, a control method 1000 for a non-volatile memory according to an embodiment of the present application includes the following steps:

[0048] Step S101: Perform an erase and reprogram operation on some of the memory cell groups of the memory string. Among them, the memory cell group on which the erase and reprogram operation is performed is the first memory cell group, and the memory cell groups in the memory string on which the erase and reprogram operation is not performed are the second memory cell groups; and

[0049] Step S102: When performing a read operation on the selected memory cells, apply a conduction voltage to the unselected memory cells. Among them, apply a first conduction voltage to the unselected memory cells in the first memory cell group, and apply a second conduction voltage to the unselected memory cells in the second memory cell group, where the first conduction voltage is greater than the second conduction voltage.

[0050] Refer to again Figure 1 , in an exemplary embodiment, in step S101 of a control method 1000 for a non-volatile memory according to the present application, an erase and reprogram operation is performed on some of the memory cell groups of the memory string 1. Among them, the memory cell group on which the erase and reprogram operation is performed is the first memory cell group, and the memory cell groups in the memory string 1 on which the erase and reprogram operation is not performed are the second memory cell groups. As Figure 1Exemplarily, if the memory cell group 102 is selected for an erase and reprogram operation, then the memory cell group 102 is the first memory cell group, and the other memory cell groups that retain the original data (without performing the erase and reprogram operation), such as the memory cell group 101 and the memory cell group 103, are the second memory cell groups.

[0051] Figure 6 is according to an embodiment of the present application Figure 1 is the timing diagram of the read operation after the block partial erase and reprogram operation in. Refer to Figure 1 , exemplarily, if the memory cell 1011 in the memory cell group 101 is selected for a read operation, the other memory cells 101a in the memory cell group 101 except the memory cell 1011 do not perform the read operation. As Figure 6 shown, the horizontal axis represents time t, and the vertical axis represents voltage. A read operation is performed on the memory cell 1011 of the memory string 1 between t1 and t2. According to step S102 of a control method 1000 of a non-volatile memory of the present application, during the read operation, a first conduction voltage Vpass1 is applied to the unselected memory cells (i.e., the memory cell group 102) in the first memory cell group, a second conduction voltage Vpass2 is applied to the unselected memory cells (i.e., the memory cells 101a and the memory cell group 103) in the second memory cell group, and the first conduction voltage Vpass1 is greater than the second conduction voltage Vpass2.

[0052] In an exemplary embodiment, a third conduction voltage is applied to the redundant cell groups 201 to 203, where the third conduction voltage Vpass (i.e., Figure 2 the Vpass in) is such that the magnitude of the third conduction voltage Vpass is between the first conduction voltage Vpass1 and the second conduction voltage Vpass2.

[0053] For the convenience of comparison with the Figure 2 in the related art, Figure 6 also shows Figure 2 the conduction voltage Vpass in. What is the same between a control method 1000 of a non-volatile memory of the present application and the related art is that when a read operation is performed on the memory cell 1011 of the memory string 1 between t1 and t2, a read voltage Vread is applied to the memory cell 1011, and the same conduction voltage Vpass is applied to the redundant cell groups 201 to 203. What is different between a control method 1000 of a non-volatile memory of the present application and the related art is that a first conduction voltage Vpass1 is applied to the first memory cell group (i.e., the memory cell group 102), while a second conduction voltage Vpass2 is applied to the other second memory cell groups that retain the original data (i.e., the memory cells 101a and the memory cell group 103), where Vpass1 is greater than Vpass, and Vpass is greater than Vpass2.

[0054] In an exemplary embodiment, the voltage difference between the first conduction voltage Vpass1 and the third conduction voltage Vpass is less than 1V. That is, in the read operation, the conduction voltage of the erased and reprogrammed memory cell group 102 is appropriately increased.

[0055] In an exemplary embodiment, the voltage difference between the third conduction voltage Vpass and the second conduction voltage Vpass2 is less than 1V. That is, in the read operation, the conduction voltages of the memory cells 101a that retain the original data and the memory cell group 103 in the block partial erase and reprogram are appropriately reduced.

[0056] In an exemplary embodiment, multiple memory cell groups and redundant cell groups are respectively coupled to corresponding word line groups (not shown), where the memory cell group includes multiple memory cells, the redundant cell group includes multiple redundant cells, and the word line group includes multiple word lines. The word line group coupled to the memory cell group is called a memory word line group (not shown), and the word line group coupled to the redundant cell group is called a redundant word line group (not shown). Those skilled in the art should understand that the voltages applied to the memory cell groups 101-103 and the redundant cell groups 201-203 as described above are all applied through the corresponding word line groups (not shown) electrically connected thereto. For example, the first conduction voltage Vpass1 is applied through the memory word line group corresponding to the first memory cell group (memory cell group 102), the second conduction voltage Vpass2 is applied through the memory word line group corresponding to the second memory cell group (memory cells 101a and memory cell group 103), and the third conduction voltage Vpass is applied to the redundant cell groups 201-203 through the redundant word line group.

[0057] In an exemplary embodiment, when a read operation is performed on a selected memory cell, a read voltage is applied to the word line of the selected memory cell. Additionally, those skilled in the art should understand that the read voltage applied to the word line of the selected memory cell as described above is applied through the word line electrically connected thereto.

[0058] In some embodiments, the non-volatile memory may include any one of a single-level cell (SLC) flash memory, a multi-level cell (MLC) flash memory, a three-level cell (TLC) flash memory, a four-level cell (QLC) flash memory, and a five-level cell (PLC) flash memory.

[0059] A control method for a non-volatile memory according to an embodiment of the present application, during a read operation after a block partial erase and reprogram operation, reduces the on-resistance of the memory string due to an increase in the on-voltage of the word line group that retains the original data in the block partial erase and reprogram operation, while increasing the on-voltage of the word line group in the block partial erase and reprogram reduces the on-resistance of the memory string. In this way, the total resistance of the memory string in the read stage can remain unchanged, without causing additional read noise.

[0060] Figure 7 is a schematic structural diagram of a non-volatile memory according to an embodiment of the present application. As Figure 7 shown, the non-volatile memory 100 may include a memory array 10, a voltage generation circuit 20, and a control circuit 30.

[0061] The memory array 10 may include a plurality of memory strings. Each memory string may include a plurality of memory cell groups and redundant cell groups located between the plurality of memory cell groups. The plurality of memory cell groups of each memory string include a first memory cell group and a second memory cell group. Among them, the memory cell group that performs the erase and reprogram operation in the memory string is the first memory cell group, and the memory cell group that does not perform the erase and reprogram operation is the second memory cell group. According to an embodiment of the present application, referring again to Figure 1 , the memory array 10 includes a plurality of memory strings 1. Each memory string 1 may include memory cell groups 101 to 103 and redundant cell groups 201 to 203. The redundant cell groups 201 to 203 are respectively located between the memory cell groups 101 to 103. In an exemplary embodiment, if the memory cell group 102 is selected for the erase and reprogram operation, then the memory cell group 102 is the first group of memory cell groups, and the other memory cell groups that retain the original data (such as the memory cell group 101 and the memory cell group 103) are the second memory cell groups.

[0062] As Figure 1 shown, the memory array 10 may include a plurality of memory word line groups (not shown) respectively electrically connected to the plurality of memory cell groups 101 to 103 and a redundant word line group (not shown) electrically connected to the redundant cell groups 201 to 203. Each memory cell group 101 to 103 may include a plurality of memory cells, and the redundant cell groups 201 to 203 may include a plurality of redundant cells. Each memory cell can implement multiple memory states, where a lower memory state corresponds to a lower threshold voltage, and a higher memory state corresponds to a higher threshold voltage.

[0063] According to an embodiment of the present application, each storage cell in the storage array 10 is capable of storing one or more bits. For example, a storage cell in a single-level cell (SLC) flash memory can store one bit, a storage cell in a multi-level cell (MLC) flash memory can store two bits, a storage cell in a triple-level cell (TLC) flash memory can store three bits, a storage cell in a quad-level cell (QLC) flash memory can store four bits, a storage cell in a penta-level cell (PLC) flash memory can store five bits, and so on. A multi-level storage cell can implement multiple storage states, and thus data bits can be written to the storage cell by programming the multi-level storage cell to one of the multiple storage states. For example, an MLC has four storage states, which are respectively determined by two bits; a TLC has eight storage states, which are respectively determined by three bits; a QLC has sixteen storage states, which are respectively determined by four bits; a PLC has thirty-two storage states, which are respectively determined by five bits. The embodiment of the present application does not specifically limit the type of the storage array 10, and any suitable memory array without departing from the teachings of the present invention is allowed.

[0064] Reference Figure 7 , according to an embodiment of the present application, the control circuit 30 is coupled to the storage array 10 and the voltage generation circuit 20, and is configured to control the voltage generation circuit 20 to generate different voltages applied to the storage array 10. For example, during a read operation on a selected storage cell, a read voltage is applied to the selected storage cell, and a conduction voltage is applied to a plurality of unselected storage cell groups. Among them, a first conduction voltage is applied to the unselected storage cells in the first storage cell group, a second conduction voltage is applied to the unselected storage cells in the second storage cell group, and a third conduction voltage is applied to the redundant cell group. Among them, the first conduction voltage is greater than the third conduction voltage, and the third conduction voltage is greater than the second conduction voltage.

[0065] In an exemplary embodiment, the voltage difference between the first conduction voltage and the third conduction voltage is less than 1V. That is, during the read operation, the conduction voltage of the storage cell group that has been erased and reprogrammed is appropriately increased.

[0066] In an exemplary embodiment, the voltage difference between the third conduction voltage and the second conduction voltage is less than 1V. That is, during the read operation, the conduction voltage of the storage cell group that retains the original data during the partial block erase and reprogramming is appropriately decreased.

[0067] According to an embodiment of the present application, asFigure 7 As shown, the voltage generation circuit 20 is coupled to the memory array 10 and can generate various voltages for performing operations such as erasing, programming, reading / writing, and verifying on the memory array 10 in response to control signals from the control circuit 30. Specifically, the voltage generation circuit 20 can generate word line voltages, such as programming voltages, programming inhibit voltages, read voltages, and verify voltages, etc.

[0068] Figure 8 FIG. is a schematic diagram of the memory array 10 according to an exemplary embodiment of the present application. As Figure 8 shown, each memory array 10 includes a plurality of memory cells arrayed in a three-dimensional space, forming a plurality of memory strings. The channels of the memory cells located in the same memory string are physically connected. The gates of the plurality of memory cells are controlled by the same word line WL. By applying different programming voltages to the word line WL, the memory cells can be in a conductive state or a programmed state. The memory cells can be connected to the word line WL and the bit line BL. For example, the word line WL can include WL1, WL2, WL3, WL4, as well as WLn, WLn+1, WLn+2, WLn+3, and the bit line BL can include BL1, BL2, BL3, BL4, as well as BLm-2, BLm-1, BLm. At the same time, the memory cells can also be connected to other selection lines, such as the string selection line SSL, the ground selection line GSL, the common source line CSL, etc. The number of memory cells, the number of word lines WL, and the number of bit lines BL are for illustrative purposes, and the present application is not limited thereto. According to an embodiment of the present application, the memory array 10 can be connected to the voltage generation circuit 20 via the word line WL and the bit line BL.

[0069] Since the content and structure involved in describing the control method 1000 of the non-volatile memory in the above text can be fully or partially applied to the non-volatile memory described here, the related or similar content will not be elaborated again.

[0070] Another aspect of the present application also provides a non-volatile storage system, Figure 9A and Figure 9B are functional block diagrams of the non-volatile storage systems 2000a and 2000b according to embodiments of the present application. As Figure 9A and Figure 9B shown, the non-volatile storage system 2000a or 2000b includes at least one non-volatile memory 100 and a controller 200.

[0071] The non-volatile memory 100 can be the same as the non-volatile memory described in any of the above embodiments, and the present application will not elaborate on this again. The present application does not limit the number of non-volatile memories included in the non-volatile storage system.

[0072] The controller 200 can control the non-volatile memory 100 through a channel (not shown), and the non-volatile memory 100 can perform operations based on the control of the controller 200. The non-volatile memory 100 can receive commands and addresses from the controller 200 through the channel and access the area selected from the storage array 10 (refer to Figure 7 ) in response to the address. In other words, the non-volatile memory 100 can perform internal operations corresponding to the commands on the area selected by the address. More specifically, the controller 200 sends a command and an address for executing the control method 1000 of the non-volatile memory described in any of the above embodiments through the channel, causing the non-volatile memory 100 to execute the control method 1000.

[0073] In some examples, the control device 200 and one or more non-volatile storage devices 100 can be integrated into various types of storage systems. In other words, the storage systems 2000a and 2000b can be implemented and packaged into different types of final electronic products.

[0074] In one example as shown in Figure 9A , the control device 200 and a single non-volatile storage device 100 can be integrated into a non-volatile storage system 2000a in the form of a memory card. The memory card can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CompactFlash (CF) card, a SmartMedia (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a Universal Flash Storage card (UFS), etc. The non-volatile storage system 2000a in the form of a memory card can also include a memory card connector 300a for coupling it to a host (not shown).

[0075] In another example as shown in Figure 9B , the control device 200 and multiple non-volatile storage devices 100 can be integrated into a non-volatile storage system 2000b in the form of a solid-state drive (SSD). The solid-state drive (SSD) can also include an SSD connector 300b for coupling it to a host. In some embodiments, the storage capacity and / or operating speed of the solid-state drive (SSD) can be higher than those of the memory card.

[0076] The above description is only a preferred embodiment of the present application and an explanation of the technical principles applied. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by the specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, a technical solution formed by mutually replacing the above features with (but not limited to) technical features with similar functions in the present application.

Claims

1. A control method for a non-volatile memory, the non-volatile memory comprising a plurality of memory strings, each of the memory strings comprising a plurality of memory cell groups, and each of the memory cell groups comprising a plurality of memory cells, characterized in that, The method includes: Performing an erase and reprogram operation on a partial storage cell group of the storage string, wherein the storage cell group on which the erase and reprogram operation is performed is the first storage cell group, and the storage cell group in the storage string on which the erase and reprogram operation is not performed is the second storage cell group; and When performing a read operation on a selected storage cell, applying a conduction voltage to the unselected storage cells, wherein a first conduction voltage is applied to the unselected storage cells in the first storage cell group, and a second conduction voltage is applied to the unselected storage cells in the second storage cell group, wherein the first conduction voltage is greater than the second conduction voltage.

2. The control method according to claim 1, wherein, The storage string further includes a redundant cell group located between the multiple storage cell groups, and the method further includes: When performing a read operation on a selected storage cell, applying a third conduction voltage to the redundant cell group, wherein the third conduction voltage is less than the first conduction voltage and greater than the second conduction voltage.

3. The control method according to claim 2, wherein, The voltage difference between the first conduction voltage and the third conduction voltage is less than 1V, and the voltage difference between the third conduction voltage and the second conduction voltage is less than 1V.

4. The control method according to claim 1, wherein, The method further includes: When performing a read operation on a selected storage cell, applying a read voltage to the selected storage cell.

5. The control method according to claim 1, wherein, The non-volatile memory further includes a storage word line group coupled to the storage cell group, and the method further includes: Applying the first conduction voltage to the unselected storage cells in the first storage cell group through the storage word line group corresponding to the first storage cell group, and applying the second conduction voltage to the unselected storage cells in the second storage cell group through the storage word line group corresponding to the second storage cell group.

6. The control method according to claim 2, wherein, The non-volatile memory further includes a redundant word line group coupled to the redundant cell group, and the method further includes: Applying the third conduction voltage to the redundant cell group through the redundant word line group.

7. The control method according to any one of claims 1-6, wherein, The non-volatile memory includes any one of a single-level cell (SLC) flash memory, a multi-level cell (MLC) flash memory, a triple-level cell (TLC) flash memory, a quad-level cell (QLC) flash memory, and a penta-level cell (PLC) flash memory.

8. A non-volatile memory, characterized in that, Including: A storage array including multiple storage strings, each of the storage strings including multiple storage cell groups, and each of the storage cell groups including multiple storage cells, wherein the storage cell group in the storage string on which the erase and reprogram operation is performed is the first storage cell group, and the storage cell group on which the erase and reprogram operation is not performed is the second storage cell group; and A control circuit configured to apply a first conduction voltage to the unselected storage cells in the first storage cell group and a second conduction voltage to the unselected storage cells in the second storage cell group when performing a read operation on a selected storage cell, wherein the first conduction voltage is greater than the second conduction voltage.

9. The non-volatile memory according to claim 8, wherein, The storage string further includes a redundant cell group located between the multiple storage cell groups, The control circuit is further configured to: when a read operation is performed on a selected memory cell, apply a third conduction voltage to the redundant cell group, wherein the third conduction voltage is less than the first conduction voltage and greater than the second conduction voltage.

10. The non-volatile memory according to claim 9, wherein, The non-volatile memory further includes: a voltage generation circuit, coupled to the memory array, and generating the first conduction voltage, the second conduction voltage, and the third conduction voltage in response to a command of the control circuit.

11. The non-volatile memory according to claim 9, wherein, The voltage difference between the first conduction voltage and the third conduction voltage is less than 1V, and the voltage difference between the third conduction voltage and the second conduction voltage is less than 1V.

12. The non-volatile memory according to claim 9, wherein, The non-volatile memory further includes a memory word line group coupled to the memory cell group and a redundant word line group coupled to the redundant cell group.

13. The non-volatile memory according to claim 8, wherein, The control circuit is further configured to: when a read operation is performed on a selected memory cell, apply a read voltage to the selected memory cell.

14. The non-volatile memory according to any one of claims 8-13, wherein, The non-volatile memory includes any one of a single-level cell (SLC) flash memory, a multi-level cell (MLC) flash memory, a triple-level cell (TLC) flash memory, a quad-level cell (QLC) flash memory, and a penta-level cell (PLC) flash memory.

15. A non-volatile storage system, characterized in that, Comprising: at least one non-volatile memory according to any one of claims 8-14; and a controller, electrically connected to the non-volatile memory, and controlling the non-volatile memory to execute the control method according to any one of claims 1 to 7.

Images