A polysilicon line width control method and device

Abstract

The embodiment of the present invention discloses a polysilicon line width control method and a device thereof; through a multi-level parameter linkage mechanism, the accuracy of line width control is improved with a universal APC (Auto Process Control); after obtaining a linkage parameter set for polysilicon line width control, the parameters are linked or optimized in batches according to the needs of the process technology; an effective solution is provided for the open circuit problem of the active area during the head-to-head development and etching process in a hard mask 28nm and below process, and the method is applicable to silicon nitride or metal mask and dual damascene processes of polysilicon structures; the yield rate can be effectively improved, the line width control accuracy can be improved, and the electrical performance of the device can be improved.

Description

Technical Field

[0001] The invention belongs to the field of microelectronic technology, and in particular relates to a polysilicon line width control method and a device thereof. Background Art

[0002] One-step photolithography and one-step etching of polysilicon are used to form Fig.10 When the feature size reaches certain process or higher precision requirements, such as Fig.11 , there will be polysilicon head to head H2H (Head to Head) development problems and such Fig.12 The active area short circuit problem is shown.

[0003] The inventors found that even if the Fig.13 The hard mask etch shown is used to define the polysilicon line width and the Fig.14 In the LEC (Line Edge Cut) line end etching process shown, the hard mask etching used to define the critical line width often cannot fully control the convergence of the final line width, thereby affecting the electrical properties and yield of the device. Summary of the invention

[0004] The embodiment of the present invention discloses a polysilicon line width control method and a device thereof, which improves the line width control accuracy with a general APC (Auto Process Control) through a multi-level linkage parameter linkage mechanism.

[0005] Specifically, the embodiment of the present invention obtains a linkage parameter set for polysilicon line width control and performs parameter linkage or optimization in batches according to the requirements of the process technology.

[0006] The linkage parameter set includes a first linkage parameter, a second linkage parameter, and up to an Nth linkage parameter, where N is a natural number greater than or equal to 4.

[0007] Further, the first linkage parameter includes a first linkage first parameter and a first linkage second parameter; the second linkage parameter includes a second linkage first parameter and a second linkage second parameter; and so on, until the N-th linkage parameter includes the N-th linkage first parameter and the N-th linkage second parameter, wherein the linkage parameter set is used to integrate the constraint conditions in the etching process; the constraint conditions include the time length of the etching process.

[0008] By associating the first linkage first parameter and the first linkage second parameter, the first linkage difference between the first linkage first parameter and the first linkage second parameter is controlled; the first linkage difference is determined according to the control accuracy of the line width control or adjusted with a preset value as the target value.

[0009] Furthermore, the first linkage first parameter can be collected or measured from the photolithography system, and the first linkage first parameter is a measurable line width value; the first linkage second parameter is collected or measured from the etching system, and the first linkage second parameter is a measurable etching width value.

[0010] Further, the first linkage first parameter may be a line width value of photolithography, which may be measured and obtained; and the first linkage second parameter may be a line width value of the hard mask HM, which may be measured and obtained.

[0011] Furthermore, by associating the second linkage first parameter and the second linkage second parameter, the second linkage difference between the second linkage first parameter and the second linkage second parameter can be controlled; the second linkage difference is determined according to the control accuracy of the line width control or adjusted with a preset value as the target value.

[0012] Furthermore, it may also include collecting or measuring the second linkage first parameter from the photolithography system, where the second linkage first parameter is a measurable line width value; on the other hand, it may also include collecting or measuring the second linkage second parameter from the head-to-head etching system.

[0013] The second linkage first parameter may be a line width value of hard mask HM lithography, and the second linkage second parameter may be a line width value of LEC etching; the LEC etching is a line end cutting etching process.

[0014] Furthermore, automatic adjustment of the corresponding parameters can be achieved by sending the first linkage parameter and / or the second linkage parameter to an APC process control system or other SISO (Single Input Single Output) control system; wherein the APC or other SISO system receives at most one of the first linkage parameter and the second linkage parameter in the same time period and implements adjustment of the corresponding process.

[0015] Furthermore, the characteristic size of the photolithography, LEC etching or HM etching is less than or equal to 28 nm; and the hard mask includes a metal hard mask; and the etching process may include a dual damascene linkage process.

[0016] Furthermore, linkage parameters can be further obtained by associating the third linkage first parameter and the third joint electrical second parameter; by sending the linkage relationship quantity of the third linkage first parameter and the third joint electrical second parameter to the APC process control system or other SISO control system; wherein the linkage relationship quantity includes the relationship between the HM polysilicon groove and the HM etching time.

[0017] Furthermore, the line width can be further adjusted by associating the fourth linkage first parameter and the fourth linkage second parameter; wherein the fourth linkage first parameter can be the line width difference between HM etching and LEC etching; the fourth linkage second parameter can be the LEC endpoint parameter Endpt value.

[0018] Furthermore, the groove preparation process can be improved by associating the fifth linkage first parameter and the fifth linkage second parameter; wherein the fifth linkage first parameter is the LEC end point parameter Endpt value; and the fifth linkage second parameter is the HM polysilicon groove back-etching state.

[0019] Furthermore, the difference in line width between LEC and HM can be controlled by establishing a correlation between the HM polysilicon groove and the HM etching time.

[0020] Furthermore, the line width difference between LEC and HM etching can be controlled by establishing a correlation between the etching back and the etching back time through an APC process control system or other SISO control systems.

[0021] Among them, the OE time of HM etching can be controlled by APC process control system or other SISO control system; the control of OE time is used to adjust the line width difference between HM etching and LEC etching; the line width is adjusted by combining HM etching with APC process control system or other SISO control system.

[0022] The embodiment of the present invention further discloses a line width control device, comprising a first linkage subsystem, a second linkage subsystem, and an Mth linkage subsystem; wherein M is a natural number greater than or equal to 4;

[0023] The device also includes a process control subsystem; wherein the first linkage subsystem to the Mth linkage subsystem receive parameters sent by a linkage parameter set; the linkage parameter set includes a first linkage parameter, a second linkage parameter to an Nth linkage parameter, where N is a natural number greater than or equal to 4.

[0024] The first linkage parameter includes the first linkage first parameter and the first linkage second parameter; the second linkage parameter includes the second linkage first parameter and the second linkage second parameter; until the Nth linkage parameter includes the Nth linkage first parameter and the Nth linkage second parameter; the linkage parameter set is used for the integration of constraint conditions in the etching process; the constraint conditions include the time length of the etching process;

[0025] The process control subsystem associates the first linkage first parameter and the first linkage second parameter, and controls the first linkage difference between the first linkage first parameter and the first linkage second parameter; the first linkage difference is determined according to the control accuracy of the line width control or adjusted with a preset value as the target value.

[0026] Furthermore, the first linkage subsystem establishes a correlation between the line width difference between HM etching and LEC and LEC Endpt; the second linkage subsystem establishes an information correlation between LEC Endpt and HM polysilicon groove back-etching; the third linkage subsystem establishes a correlation between HM polysilicon groove information and HM etching OE time; the fourth linkage subsystem establishes a correlation between the groove and etching time; and the process control subsystem adjusts the line width difference between LEC etching and HM etching.

[0027] Based on this, more precise HM etching time control can be achieved through APC or other SISO systems, thereby more accurately controlling the line width difference between HM and LEC. Combining HM with APC or other SISO systems of lithography can improve the control accuracy of line width.

[0028] It should be noted that the terms "first", "second" and similar terms used in this article are only for describing the various components in the technical solution, and do not constitute a limitation of the technical solution, nor can they be understood as an indication or suggestion of the importance of the corresponding elements; elements with "first", "second" and similar terms indicate that the corresponding technical solution contains at least one of the element. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solution of the present invention and facilitate further understanding of the technical effects, technical features and purposes of the present invention, the present invention is described in detail below in conjunction with the accompanying drawings. The accompanying drawings constitute an essential part of the specification and are used together with the embodiments of the present invention to illustrate the technical solution of the present invention, but do not constitute a limitation to the present invention.

[0030] The same reference numerals in the accompanying drawings represent the same components, specifically:

[0031] Figure 1 This is a schematic diagram of a control flow of an embodiment of the present invention;

[0032] Figure 2 Schematic diagram of the relationship between polysilicon etching depth and line width according to an embodiment of the present invention;

[0033] Figure 3 This is a correlation diagram between HM and LEC line width difference and LEC Endpt in an embodiment of the present invention;

[0034] Figure 4 This is a correlation diagram of LEC Endpt and HM polysilicon recess Recess according to an embodiment of the present invention;

[0035] Figure 5 This is a correlation diagram of the OE time of the HM polysilicon recess and HM etching according to an embodiment of the present invention;

[0036] Figure 6This is a graph showing the correlation between the HM polysilicon recess Recess and the Recess time according to an embodiment of the present invention;

[0037] Figure 7 This is a schematic diagram of a polysilicon recess according to an embodiment of the present invention;

[0038] Figure 8 This is a diagram illustrating the improvement of Recess time control according to an embodiment of the present invention;

[0039] Fig. 9 It is a diagram showing the improvement of the key dimensions of LEC according to an embodiment of the present invention;

[0040] Fig.10 A schematic diagram showing the comparison of polysilicon etching before and after in the prior art;

[0041] Fig.11 It is a schematic diagram of the head-to-head imaging problem;

[0042] Fig.12 This is a comparison diagram of the normal and open circuit states of the active area in the etching process;

[0043] Fig.13 is a schematic diagram of hard mask etching;

[0044] Fig.14 This is a schematic diagram of LEC line end etching;

[0045] Fig.15 This is a structural block diagram of an apparatus according to an embodiment of the present invention;

[0046] Fig.16 This is a schematic diagram of parameters of the first linkage subsystem of the device according to an embodiment of the present invention;

[0047] Fig.17 It is a schematic diagram of parameters of the second linkage subsystem of the device according to an embodiment of the present invention;

[0048] Fig.18 This is a schematic diagram of parameters of the Nth linkage subsystem of the device according to an embodiment of the present invention;

[0049] Fig.19 This is a graph showing the relationship between the hard mask line width and the final line width.

[0050] in:

[0051] 101-initialization process;

[0052] 102-Signal detection process;

[0053] 103-hard mask etching process;

[0054] 104-Association and comparison process;

[0055] 105-LET line end lithography process;

[0056] 106-LET line end etching process;

[0057] 107-LET key dimension acquisition process;

[0058] 200-linkage parameter set;

[0059] 201-first linkage parameter, 211-first linkage first parameter, 212-first linkage second parameter;

[0060] 202-second linkage parameter, 221-second linkage first parameter, 222-second linkage second parameter;

[0061] 203-third linkage parameter;

[0062] 20M-Mth linkage parameter;

[0063] 20N-Nth linkage parameter, 2N1-Nth linkage first parameter, 2N2-Nth linkage second parameter;

[0064] 300-process control subsystem parameters;

[0065] 312-association parameters of the first linkage subsystem and the second linkage subsystem;

[0066] 323-association parameters of the second linkage subsystem and the third linkage subsystem;

[0067] 3MN-the correlation parameters between the Mth linkage subsystem and the Nth linkage subsystem;

[0068] 400- small line width acquisition status;

[0069] 500-Large line width acquisition status;

[0070] 401, 501-substrate;

[0071] 402, 502-polysilicon layer;

[0072] 403, 503-silicon nitride layer;

[0073] 404, 504- oxide layer;

[0074] 610-state before one-step photolithography process;

[0075] 620-state after one-step photolithography process;

[0076] 615, 625 - silicon substrate;

[0077] 614, 624-polysilicon layer;

[0078] 613, 623-silicon nitride HM layer;

[0079] 612-Bottom anti-reflective coating;

[0080] 611- photoresist layer;

[0081] 710- Schematic diagram of the state before hard mask etching;

[0082] 720- Schematic diagram of the state after hard mask etching;

[0083] Schematic diagram of the 810-LEC line end before etching;

[0084] Schematic diagram of the 820-LEC line end after etching.

[0085] In addition, the reference units of each horizontal and vertical axis include:

[0086] Figure 3 Seconds (s) - nanometers (nm),

[0087] Figure 4 Angstrom (Å)-second (s),

[0088] Figure 5 Seconds (s) - Angstroms (Å),

[0089] Figure 6 Angstroms (Å) - nanometers (nm),

[0090] Figure 7 Seconds (s) - (analog signal strength);

[0091] Among them, the above-mentioned figure is a scatter plot of the parameters corresponding to the horizontal and vertical coordinates. DETAILED DESCRIPTION

[0092] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. Of course, the specific embodiments described below are only for explaining the technical solutions of the present invention, rather than for limiting the present invention. In addition, the parts described in the embodiments or the accompanying drawings are only examples of the relevant parts of the present invention, rather than the whole of the present invention.

[0093] like Fig.15 As shown, the line width control method according to the embodiment of the present invention improves the control accuracy of the line width by acquiring a linkage parameter set 200 .

[0094] Specifically, the linkage parameter set 200 includes a first linkage parameter 201 , a second linkage parameter 202 , and up to an Nth linkage parameter 20N; wherein N is a natural number greater than or equal to 4.

[0095] The first linkage parameter 201 includes the first linkage first parameter 211 and the first linkage second parameter 212; the second linkage parameter 202 includes the second linkage first parameter 221 and the second linkage second parameter 222; and so on, until the Nth linkage parameter 20N includes the Nth linkage first parameter 2N1 and the Nth linkage second parameter 2N2; the linkage parameter set 200 is used to integrate the constraint conditions in the etching process; its constraint conditions include the time length of the etching process.

[0096] By associating the first linkage first parameter 211 and the first linkage second parameter 212, the first linkage difference between the first linkage first parameter 211 and the first linkage second parameter 212 is controlled; the first linkage difference is determined according to the control accuracy of the line width control or adjusted with a preset value as the target value.

[0097] Furthermore, by collecting or measuring the first linkage first parameter 211 in the photolithography system and collecting or measuring the second parameter 212 in the etching system, the corresponding control system can be parameterized.

[0098] Further, the first linkage first parameter 211 may be a line width value of lithography, which may be measured and obtained; in addition, the first linkage second parameter 212 may be a line width value of the hard mask HM, which may be measured and obtained.

[0099] Furthermore, by associating the second linkage first parameter 221 and the second linkage second parameter 222, the second linkage difference between the second linkage first parameter 221 and the second linkage second parameter 222 is controlled; the second linkage difference is determined according to the control accuracy of the line width control or adjusted with a preset value as the target value.

[0100] Similarly, the second-linkage first parameter 221 is collected or measured from the photolithography system, and the second-linkage first parameter 221 is a measurable line width value; the second-linkage second parameter 222 is collected or measured from the head-to-head etching system.

[0101] Further, the second linkage first parameter 221 may be a line width value of hard mask HM lithography, and the second linkage second parameter 222 may be a line width value of LEC etching; wherein LEC etching is a line end cutting etching process.

[0102] Furthermore, by sending the first linkage parameter 201 and / or the second linkage parameter 202 to the APC process control system or other SISO control system; the APC or other SISO system receives at most one of the first linkage parameter 201 and the second linkage parameter 202 in the same period and implements the adjustment of the corresponding process.

[0103] Here, the feature size of the photolithography, LEC etching or HM etching may be less than or equal to 28 nm; the hard mask thereof may include a metal hard mask; and the etching process thereof may include a dual damascene linkage process.

[0104] Furthermore, the control accuracy can be further improved by associating the third linkage first parameter and the third joint electrical second parameter; by sending the linkage relationship quantity of the third linkage first parameter and the third joint electrical second parameter to the APC process control system or other SISO control systems; wherein the linkage relationship quantity may include the relationship between the HM polysilicon groove and the HM etching time.

[0105] Further, the fourth linkage first parameter and the fourth linkage second parameter can be associated; wherein the fourth linkage first parameter is the line width difference between HM etching and LEC etching; and the fourth linkage second parameter is the LEC endpoint parameter Endpt value.

[0106] Further, the fifth linkage first parameter and the fifth linkage second parameter can be associated; wherein, the fifth linkage first parameter is the LEC end point parameter Endpt value; and the fifth linkage second parameter is the HM polysilicon groove back-etching state.

[0107] Furthermore, by establishing a correlation between the HM polysilicon groove and the HM etching time, the line width difference between the LEC and the HM is controlled.

[0108] Among them, by establishing a correlation between the etching back and the etching back time, the line width difference between the LEC and HM etching is controlled through the APC process control system or other SISO control systems.

[0109] Furthermore, the OE time of HM etching is controlled by an APC process control system or other SISO control systems; the control of OE time is used to adjust the line width difference between HM etching and LEC etching; the line width is adjusted by combining HM etching with an APC process control system or other SISO control system.

[0110] like Fig.15 Also disclosed is a line width control device, comprising a first linkage subsystem, a second linkage subsystem, and up to an Mth linkage subsystem; wherein M is a natural number greater than or equal to 4.

[0111] The device also includes a process control subsystem; and receives parameters sent from the linkage parameter set 200 through the first linkage subsystem to the Mth linkage subsystem.

[0112] The linkage parameter set 200 includes a first linkage parameter 201 , a second linkage parameter 202 , and an Nth linkage parameter 20N, where N is a natural number greater than or equal to 4.

[0113] Correspondingly, the first linkage parameter 201 includes the first linkage first parameter 211 and the first linkage second parameter 212; the second linkage parameter 202 includes the second linkage first parameter 221 and the second linkage second parameter 222; until the Nth linkage parameter 20N includes the Nth linkage first parameter 2N1 and the Nth linkage second parameter 2N2; the linkage parameter set 200 is used to integrate the constraint conditions in the etching process; the constraint conditions include the time length of the etching process.

[0114] Furthermore, the process control subsystem associates the first linkage first parameter 211 and the first linkage second parameter 212 to control the first linkage difference between the first linkage first parameter 211 and the first linkage second parameter 212; the first linkage difference is determined according to the control accuracy of the line width control or adjusted with a preset value as the target value.

[0115] Furthermore, the first linkage subsystem establishes the association between the line width difference between HM etching and LEC and LEC Endpt; the second linkage subsystem establishes the information association between LEC Endpt and HM polysilicon groove back-etching; the third linkage subsystem establishes the association between HM polysilicon groove information and HM etching OE time; the fourth linkage subsystem establishes the association between groove and etching time; the process control subsystem adjusts the line width difference between LEC etching and HM etching, and finally realizes indirect control of polysilicon line width.

[0116] It should be noted that the above embodiments are only for more clearly illustrating the technical solutions of the present invention. Those skilled in the art will understand that the implementation methods of the present invention are not limited to the above contents, and obvious changes, replacements or substitutions based on the above contents do not exceed the scope of the technical solutions of the present invention; other implementation methods will also fall within the scope of the present invention without departing from the concept of the present invention.

Claims

1. A polysilicon line width control method, characterized in that: include: Obtaining a linkage parameter set (200); the linkage parameter set (200) includes a first linkage parameter (201), a second linkage parameter (202) up to an Nth linkage parameter (20N); wherein N is a natural number greater than or equal to 4; The first linkage parameter (201) includes a first linkage first parameter (211) and a first linkage second parameter (212); the second linkage parameter (202) includes a second linkage first parameter (221) and a second linkage second parameter (222); and so on, until the Nth linkage parameter (20N) includes an Nth linkage first parameter (2N1) and an Nth linkage second parameter (2N2); the linkage parameter set (200) is used to integrate constraint conditions in an etching process; the constraint conditions include a time length of an etching process; The first linkage first parameter (211) and the first linkage second parameter (212) are associated to control a first linkage difference between the first linkage first parameter (211) and the first linkage second parameter (212); the first linkage difference is determined according to the control accuracy of the line width control or adjusted with a preset value as a target value.

2. The method of claim 1, wherein: The first linkage first parameter (211) is collected or measured from a photolithography system, and the first linkage first parameter (211) is a measurable line width value; the first linkage second parameter (212) is collected or measured from an etching system, and the first linkage second parameter (212) is a measurable etching width value.

3. The method of claim 2, wherein: The first linkage first parameter (211) is a line width value of photolithography, and the line width value of photolithography can be measured; the first linkage second parameter (212) is a line width value of a hard mask HM, and the line width value of the hard mask HM can be measured.

4. The method of claim 1, further comprising: The second linkage first parameter (221) and the second linkage second parameter (222) are associated to control a second linkage difference between the second linkage first parameter (221) and the second linkage second parameter (222); the second linkage difference is determined according to the control accuracy of the line width control or adjusted with a preset value as a target value.

5. The method of claim 4, wherein: The second linkage first parameter (221) is collected or measured from a photolithography system, and the second linkage first parameter (221) is a measurable line width value; the second linkage second parameter (222) is collected or measured from a head-to-head etching system.

6. The method of claim 5, wherein: The second linkage first parameter (221) is a line width value of hard mask HM lithography, and the second linkage second parameter (222) is a line width value of LEC etching; the LEC etching is a line end cutting etching process.

7. The method according to any one of claims 1 to 6, further comprising: The first linkage parameter (201) and / or the second linkage parameter (202) are sent to an APC process control system or other SISO control system; wherein the APC or the other SISO system receives at most one of the first linkage parameter (201) and the second linkage parameter (202) in the same period and implements adjustment of the corresponding process.

8. The method of claim 7, wherein: The feature size of photolithography, LEC etching or HM etching is less than or equal to 28nm; The hard mask includes a metal hard mask; The etching process includes a dual damascene linkage process.

9. The method of claim 8, further comprising: Associating the third linkage first parameter with the third linkage second parameter; Sending the linkage relationship quantity of the third linkage first parameter and the third joint electric second parameter to the APC process control system or the other SISO control system; the linkage relationship quantity includes the relationship between the HM polysilicon groove and the HM etching time.

10. The method of claim 9, further comprising: The fourth linkage first parameter and the fourth linkage second parameter are associated; wherein the fourth linkage first parameter is the line width difference between the HM etching and the LEC etching; and the fourth linkage second parameter is the LEC endpoint parameter Endpt value.

11. The method of claim 10, further comprising: The fifth linkage first parameter and the fifth linkage second parameter are associated; wherein the fifth linkage first parameter is the LEC end point parameter Endpt value; and the fifth linkage second parameter is the HM polysilicon groove back engraving state.

12. The method of claim 11, wherein: By establishing a correlation between the HM polysilicon groove and the HM etching time, the line width difference between the LEC and the HM is controlled.

13. The method of claim 12, wherein: By establishing a correlation between the etching back and the etching back time, the line width difference between the LEC etching and the HM etching is controlled by the APC process control system or the other SISO control system.

14. The method of claim 12 or 13, wherein: The OE time of the HM etching is controlled by the APC process control system or the other SISO control system; the control of the OE time is used to adjust the line width difference between the HM etching and the LEC etching; the line width is adjusted in combination with the HM etching and the APC process control system or the other SISO control system.

15. A line width control device, comprising: The first linkage subsystem, the second linkage subsystem, and so on to the Mth linkage subsystem; wherein M is a natural number greater than or equal to 4; The device further comprises a process control subsystem; the first linkage subsystem receives parameters sent from the linkage parameter set (200) to the Mth linkage subsystem; The linkage parameter set (200) includes a first linkage parameter (201), a second linkage parameter (202) and up to an Nth linkage parameter (20N); wherein N is a natural number greater than or equal to 4; the first linkage parameter (201) includes a first linkage first parameter (211) and a first linkage second parameter (212); the second linkage parameter (202) includes a second linkage first parameter (221) and a second linkage second parameter (222); until the Nth linkage parameter (20N) includes an Nth linkage first parameter (2N1) and an Nth linkage second parameter (2N2); the linkage parameter set (200) is used for the synthesis of constraint conditions in an etching process; the constraint conditions include the time length of the etching process; The process control subsystem associates the first linkage first parameter (211) and the first linkage second parameter (212), and controls a first linkage difference between the first linkage first parameter (211) and the first linkage second parameter (212); the first linkage difference is determined according to the control accuracy of the line width control or adjusted with a preset value as a target value.

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