Cobalt-based interconnects and methods of fabricating the same

Abstract

Embodiments include a metal interconnect structure comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an interconnect line; an adhesion layer disposed over the conductive region and on the sidewalls, the adhesion layer comprising manganese; and a fill material within the opening and on a surface of the adhesion layer, the fill material comprising cobalt. Other embodiments are described herein.

Description

[0001] This application is a divisional application of the Chinese invention patent application with application number 201580002697.9, application date February 21, 2015, and invention name “Cobalt-based interconnect and manufacturing method thereof”. Technical Field

[0002] Embodiments of the present invention generally relate to metal interconnect structures and methods of making the same, and more particularly, to cobalt-based interconnect structures and methods of making the same. Background Art

[0003] Integrated circuit (IC) devices typically include circuit elements, such as transistors, capacitors, and resistors, formed within or on a semiconductor substrate. Interconnect structures are used to electrically couple or connect discrete circuit elements into functional circuits. Typical metal interconnects can include traces and vias.

[0004] The interconnect structures can be made of copper and can include a barrier layer such as titanium or tantalum or a nitride material such as tantalum nitride or titanium nitride, or a combination thereof (e.g., tantalum nitride / tantalum (TNT)). A problem with using copper interconnect structures is that they are highly sensitive to electromigration, which can lead to vacancy formation and failure.

[0005] Tungsten metallization has been successfully used to manufacture front-end contacts and has therefore been proposed for back-end metallization, used to manufacture interconnects. A desirable advantage of using tungsten metallization is its high resistance to harmful electromigration effects. However, a disadvantage of using tungsten metallization is its higher resistivity than copper. More specifically, tungsten line resistance is 4 to 6 times higher than copper interconnects, and via resistance can be as much as 20% higher. These high resistances severely degrade IC performance and are therefore undesirable. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1A-1E is a cross-sectional side view illustration of a method of forming a cobalt interconnect according to an embodiment of the present invention.

[0007] Figure 2 is a cross-sectional side view illustration of an integrated circuit having multiple metallization layers formed with cobalt interconnects in accordance with an embodiment of the present invention.

[0008] Figure 3 is a flow chart illustrating a method of forming a cobalt interconnect according to an embodiment of the present invention.

[0009] Figures 4A-4D is a cross-sectional side view illustration of a method of forming a cobalt interconnect having a cobalt plug in accordance with an embodiment of the present invention.

[0010] Figures 5A-5Dis a cross-sectional side view illustration of a method of forming a cobalt interconnect having a cobalt plug in accordance with an embodiment of the present invention.

[0011] Figure 6 is a flow chart illustrating a method of forming a cobalt interconnect having a cobalt plug according to an embodiment of the present invention.

[0012] Figure 7 A semiconductor field effect transistor (FET) including a cobalt-based metal gate electrode is depicted in accordance with an embodiment of the present invention. DETAILED DESCRIPTION

[0013] Reference will now be made to the accompanying drawings, in which identical structures may be provided with identical suffix reference numerals. To more clearly illustrate the structures of various embodiments, the drawings included herein are diagrammatic representations of semiconductor / circuit structures. Therefore, the actual appearance of a fabricated integrated circuit structure (e.g., in a micrograph) may appear different while still incorporating the claimed structure of the illustrated embodiment. Furthermore, the drawings may only depict structures that are helpful for understanding the illustrated embodiment. Additional structures known in the art may not be included to maintain clarity. For example, not every layer in a semiconductor device needs to be shown. "Embodiment," "various embodiments," etc. indicate that the embodiment(s) described may include particular features, structures, or characteristics, but not every embodiment must include those particular features, structures, or characteristics. Some embodiments may have some, all, or none of the features described for other embodiments. "First," "second," "third," etc., describe common objects and indicate that different instances of the same object are being referred to. Such adjectives do not imply that the objects described are necessarily ordered temporally, spatially, or in any other manner. “Connected” may indicate elements are in direct physical or electrical contact with each other; and “coupled” may indicate elements co-operate or interact with each other, but the elements may or may not be in direct physical or electrical contact.

[0014] One embodiment of the present invention is a cobalt interconnect that includes a manganese (Mn)-based adhesion layer and a cobalt fill material. The adhesion layer (sometimes also referred to herein as a barrier layer or wetting layer) can include various manganese-based compositions, such as Mn, manganese nitride (MnN), or manganese silicon nitride (MnSi x N y ). The Mn-based adhesion layer may include a film deposited in a patterned back-end interconnect structure. These interconnect structures may be metallized using cobalt. In some embodiments, the Mn-based layer adheres well to the interlayer dielectric (ILD), which helps form the interconnect. The Mn-based layer also provides wetting to the cobalt metal. Thus, the Mn-based adhesion layer helps achieve robust gap filling of interconnect structures at small scales (e.g., 22nm, 14nm, 10nm, and smaller).

[0015] Embodiments include cobalt interconnects comprising a cobalt plug layer and a cobalt fill material. The plug layer is formed of a different composition and / or by a different process than that used to form the cobalt fill material. Such cobalt interconnects are advantageous because they have low resistance (e.g., lower than tungsten) and are highly resistant to electromigration (e.g., more resistant to electromigration than copper), thereby enabling the manufacture of high-performance interconnect structures. Due to the scaling of dimensions in conventional interconnect processing, the high resistance of conventional barrier layers (e.g., TNT barrier layers) may significantly impact the performance of conventional copper interconnects. However, a lower resistance Mn layer can mitigate these resistance issues.

[0016] In a first aspect, a conformal Mn-based adhesion layer is formed in an opening in a dielectric layer. A cobalt-based fill material is then deposited or grown on the Mn-based adhesion layer to form a cobalt interconnect.

[0017] Figures 1A-1E A method of forming a cobalt interconnect having a Mn-based adhesion layer and a cobalt-containing fill layer according to an embodiment of the present invention is shown. Figure 1A A substrate 106 having a top surface 118 is shown, which can serve as a substrate on which cobalt interconnects are formed. Substrate 106 can include any portion of a partially fabricated IC on which cobalt interconnects are ultimately fabricated. For example, substrate 106 will typically include active and passive devices or have active and passive devices formed thereon. Figure 1A As shown in FIG, conductive region 150 is included in substrate 106 on which cobalt interconnects will eventually be formed. In one such embodiment, substrate 106 has been processed through a front-end-of-line (FEOL) process, and conductive region 150 is a diffusion region formed in a crystalline semiconductor substrate or layer (e.g., the conductive region is a source or drain region of a transistor). In another such embodiment, as described below in conjunction with Figure 2 In more detail, conductive region 150 is a bottom metal line in a back-end-of-line (BEOL) metallization structure. Thus, although portion 150 is sometimes referred to herein as "conductive region 150," this may or may not indicate that region 150 is more or less conductive than the rest of 106. Additionally, the use of 150 is not intended to indicate that 150 is necessarily non-monolithic with 106, or that 150 is formed using a different process or non-simultaneously with 106. For example, when 106 is an interconnect, region 150 is monolithic with 106 and cannot be distinguished from the rest of 106 in terms of structure and function. However, when 150 acts as a source or drain, region 150 may also be a region that is doped differently from the rest of 106. The above explanation is provided to avoid excessive figures and to provide clarity in a concise manner in other cases.

[0018] While embodiments may be ideally suited for fabricating semiconductor ICs, such as, but not limited to, microprocessors, memories, charge-coupled devices (CCDs), system-on-chip (SoC) ICs, or baseband processors, other applications may include microelectronic machines, MEMS, lasers, optical devices, packaging layers, etc. Embodiments may also be used to fabricate individual semiconductor devices (e.g., the cobalt structures described herein may be used to fabricate gate electrodes for metal oxide semiconductor (MOS) transistors).

[0019] Reference again Figure 1A , a dielectric layer 102 is formed over the substrate 106. The dielectric layer 102 may be made of any suitable dielectric or insulating material, such as, but not limited to, silicon dioxide, SiOF, carbon-doped oxide, glass, or polymer materials. An opening is formed in the dielectric layer. The opening exposes the conductive region 150, and ultimately the cobalt interconnect forms a contact (indirectly or directly) to the conductive region 150. In one embodiment, as Figure 1A As shown in , as is common in dual damascene processes, the openings include a lower opening 114 having sidewalls 116 (e.g., a via hole or slot) and an upper opening 110 having sidewalls 112 (e.g., a metal line trench). Although two openings are depicted (or a single opening having different widths), it is recognized that a single opening may alternatively be formed in the dielectric layer 102 (e.g., as used in a single damascene approach, where only a line or a via is fabricated in a single operation, but not both). The opening or openings may be fabricated in the dielectric layer 102 by known photolithography and etching processing techniques commonly used in damascene and dual damascene type fabrication. Although only a single dielectric layer 102 is depicted, multiple layers of the same or different dielectric materials may alternatively be used (e.g., a first dielectric layer having the opening 114 therein, and a second dielectric layer having the opening 110 therein). Additionally, in embodiments, and as shown Figure 1A As shown in FIG, a dielectric layer 102 is formed on an etch stop layer 104 disposed on a substrate 106. The etch stop layer 104 may be composed of a material such as silicon nitride or silicon oxynitride.

[0020] refer to Figure 1B , depositing a Mn-based adhesion layer 120 (eg, comprising Mn, MnN, MnSi x N y In other systems, a seed layer may be formed on a TNT-based adhesion layer. A seed layer (e.g., a seed layer disclosed in U.S. Patent Application No. 13 / 730,184) may facilitate the formation of the filler material. Figure 1B In the embodiment of Figure 1BIn the embodiment of the present invention, there is no need to deposit an alloy between the adhesion layer and the seed layer. Therefore, as will be seen below, the Mn-based adhesion layer can directly contact the ILD 102 and directly contact the cobalt fill (described below) without the need for a TNT-based adhesion layer, any seed layer, or any alloy layer between the TNT-based adhesion layer and the seed layer.

[0021] exist Figure 1B In the embodiment, an Mn-based adhesion layer 120 can be formed on the top surface 108 of the dielectric layer 102 and on the exposed top surface 118 of the substrate 106 (e.g., on the conductive region 150). Although 106 is referred to as a "substrate," in another embodiment, 106 can be a metal interconnect, etc. The Mn-based adhesion layer 120 is also formed on the sidewalls 116 of the upper opening 114 and on the sidewalls 112 of the lower opening 110.

[0022] The Mn-based adhesion layer 120 may be made of a material including Mn, MnN, MnSi x N y 、MnSi x O y (e.g., Mn2[SiO4], MnSiO3), other Mn-based silicates, etc. In embodiments where the adhesion layer includes Mn, the Mn content may include 90-100% Mn, wherein impurities (i.e., the remaining 10%) may include C, H, O, and combinations thereof. In embodiments where the adhesion layer includes MnN x In the embodiment of the present invention, Mn may constitute 0-50% of Mn and N may constitute 0-50%. x In the embodiment of the present invention, the adhesion layer may include Mn4N or Mn3N2. x Si y In embodiments, Mn and N may comprise up to 50%, with Si constituting the remainder of the material. In embodiments, Mn, N, and Si may be included in various adhesion multilayer combinations with one another, such as bilayers or trilayers (e.g., an adhesion layer comprising one sublayer comprising MnN and another sublayer comprising Mn), (e.g., one adhesion layer comprising a sublayer having Mn and N and another sublayer comprising primarily Mn), (e.g., one adhesion layer comprising a sublayer comprising MnN and another sublayer comprising Mn), (e.g., one adhesion layer comprising a sublayer comprising Mn and N and another sublayer comprising primarily Mn), x Si y and another sublayer mainly containing Mn), etc. As used herein, % of a composition refers to atomic %.

[0023] In one embodiment, the Mn-based adhesion layer 120 is formed to a thickness of less than 3 nm, and typically has a thickness of 1 nm to 3 nm. In an embodiment, the thickness of layer 120 (whether layer 120 comprises a single layer or multiple sub-layers, such as one sub-layer comprising MnN and another adjacent sub-layer comprising Mn) can range from 0.1 Å to 50 Å. In an embodiment, layer 120 is between 10 Å and 20 Å, such as 10, 12, 14, 16, 18, or 20 Å.

[0024] In an embodiment, the conductive region 150 includes at least some germanium (e.g., exposed doped silicon germanium or a doped germanium region, or a metal germanide region). In an embodiment, the conductive region 150 includes at least some silicon (e.g., exposed doped silicon region, or a metal silicide region).

[0025] Layer 120 may be deposited or grown by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating, electroless plating, or other suitable processes for depositing conformal thin films. In an embodiment, layer 120 is deposited to form a high-quality conformal layer that fully and uniformly covers all exposed surfaces and top surfaces within the opening. In one embodiment, the adhesion layer may be formed by depositing a Mn-based material at a low deposition rate to uniformly and consistently deposit a conformal adhesion layer. By forming layer 120 in a conformal manner, the compatibility of subsequently formed filler materials (e.g., cobalt) with the underlying structure may be improved. Specifically, layer 120 can assist the deposition process by providing an appropriate surface energy for deposition thereon.

[0026] The deposition method for thin films using processes such as CVD, ALD, and PVD may vary depending on the desired process time, thickness, and qualified quality. For example, depositing adhesion layer 120 using CVD can create a conformal thin film layer more quickly than depositing the same layer using an ALD process; however, the quality of the film deposited by the CVD process may be lower than that of the film deposited by the ALD process. In another embodiment, layer 120 is deposited using a PVD process. The PVD process can be performed using an increased distance between the receiving substrate and the corresponding sputtering target to form a highly conformal thin film.

[0027] refer to Figure 1C1 , fill material 122 may be formed on the exposed surface of adhesion layer 120 such that fill material 122 completely fills openings 110 and 114 and is formed on the top surface of adhesion layer 120 and on top surface 108 of dielectric 102. Seams 124 may be formed within openings 110, 114 during the deposition of fill material 122. In an embodiment, fill material 122 is composed of a low alloy consisting of approximately 0.25-5% non-cobalt elements (e.g., Al, Ni, Cu, Ag, Au, Mn, Ti, V, Cr, Fe, Ta, W, Ru, P, B, C, N, Si, Ge, Mg, Zn, Rh, Pt, Cd, Hf, In, Sn, C, O, Be, Ca, Zr, Nb, Mo, Ir, Re, or Pd) and the remainder being approximately 95+% cobalt. During deposition or post-deposition processing, such low alloys may contain non-cobalt species that migrate to the surface of fill 122. This migration can provide a diffusion barrier for the cobalt (in addition to the adhesion / barrier layer 120) and / or serve to enhance the adhesion of the cobalt to layer 120. Grain boundaries within the cobalt may also be filled with non-cobalt species. In one embodiment, filler material 122 consists essentially of cobalt. In another embodiment, filler material 122 is at least 90% cobalt. In yet another embodiment, filler material 122 consists of at least 50% cobalt.

[0028] In embodiments of the present invention, cobalt filler material 122 may be formed by processes such as, but not limited to, CVD, ALD, PVD, electroplating, or electroless plating. In one embodiment, the process used to form filler material 122 may be different from the process used to form layer 120. Furthermore, layer 120 may be formed conformally, while filler material 122 may be formed in a non-conformal or bottom-up manner. For example, layer 120 may be formed by an ALD deposition process that forms a conformal layer on an exposed surface of a receiving substrate, while filler material 122 may be formed by a PVD process that directionally sputters filler material onto the surface of layer 120, with a greater deposition rate on flat horizontal surfaces as opposed to more vertically oriented sidewall surfaces. In another example, layer 120 may be formed by an ALD deposition process that forms a conformal layer on an exposed surface of a receiving substrate, while filler material 122 may be formed by an electroplating process that grows filler material from the surface of layer 120. In yet another example, layer 120 may be formed by a CVD deposition process, and the filler material may be formed by a PVD process.

[0029] In another embodiment, layer 120 and filler material 122 can be deposited by the same process (e.g., ALD, CVD, or PVD), but with different sets of deposition parameters, such as pressure, deposition rate, temperature, etc. For example, layer 120 and filler material 122 can be deposited by a CVD process; however, the set of parameters used in the CVD process for adhesion layer 120 (e.g., deposition pressure and temperature) can be different from the set of parameters used in the CVD process for filler material 122. In another example, layer 120 and filler material 122 are formed by a PVD process, but layer 120 can be formed by a PVD process with a larger distance between the target and the receiving substrate than the PVD process used to form the filler material. In another embodiment, metallic filler material 122 is formed by a columnar PVD process, while layer 120 is formed by a non-columnar PVD process. Alternatively, layer 120 is formed by an ALD process having a lower deposition rate than the deposition rate of the ALD process used to form fill material 122 , such that layer 120 is formed more conformally than fill material 122 .

[0030] refer to Figure 1D , an annealing process may be optionally performed to reflow the deposited interconnect layer. The Figure 1C The seams 124 are formed to form a solid structure within the openings 110 and 114 in the dielectric layer 102. The annealing process can help grow a larger grain structure within the filler material 122, thereby reducing resistivity and driving out impurities from undesirable grain structures. In one embodiment, the annealing process uses gases such as nitrogen, hydrogen, and argon. In addition, the annealing process can be performed at a temperature lower than the thermal budget of the back-end structure. For example, in one embodiment, the annealing process is performed at a temperature of 300°C, 400°C, 500°C, or higher. In another embodiment, the annealing process is performed at a temperature above the melting point of the filler material 122 but below the thermal budget of the back-end structure. In various embodiments, the annealing process can vary widely (e.g., 300°C, 400°C, 500°C, or higher for interconnects, and up to 900°C for front-end applications). In such embodiments, the annealing temperature is no higher than the melting point of the material to be annealed because reflow of the material to be annealed can occur at a temperature much lower than the melting point of the material to be annealed. In such embodiments, the annealing temperature for the material to be annealed may be below the thermal budget of the back-end structure.

[0031] In yet another embodiment, a cyclic technique can optionally be used to deposit interconnect layer 122 (also referred to as fill layer 122) within openings 114 and 110 without seams 124. One cycle can involve one deposition of fill material 122 and one annealing process. The annealing operation of one cycle can be set at a certain temperature and duration to briefly reflow the fill material and improve step coverage. The deposition operation of one cycle can be a short deposition to deposit less fill material, so that several operations are required to completely fill the via and line openings 114 and 110. In one embodiment, less than five cycles are required to deposit fill material 122 without seams 124.

[0032] refer to Figure 1E , a chemical mechanical planarization (CMP) process can be performed to remove the fill material 122 and the adhesion layer 120 disposed above the top surface 108 of the dielectric layer 102. In one embodiment, the CMP process can be a timed CMP process that is timed to stop at the top surface 108 of the line dielectric layer. In another embodiment, the CMP process can utilize the top surface 108 of the line dielectric layer as a stop layer. Because the thickness of the fill material deposited above the top surface of the line dielectric layer can vary, utilizing the top surface 108 as a stop layer may be a more reliable approach. In an alternative embodiment, an etching process is used to remove the fill material 122 and the layer 120 disposed above the top surface 108 of the dielectric layer 102.

[0033] Figure 2 A cross section 200 of a portion of an IC structure having a cobalt metal interconnect according to an embodiment of the present invention is shown. The stack of dielectric layers 102 includes a metal interconnect having an adhesion layer 120 and a metal (eg, cobalt) fill layer 124. Figure 2 The portion of the IC structure shown in may be part of a back-end-of-line (BEOL) metallization structure such as found in a microprocessor die or a memory die.

[0034] Figure 3 300 is a flow chart illustrating a method of forming a cobalt metal interconnect according to an embodiment of the present invention. At 302, an opening is formed in a dielectric layer to expose a conductive region in a substrate (or on an additional metal interconnect). At 304, an Mn-based adhesion / barrier layer is formed over the substrate, over the dielectric layer, and on the sidewalls of the opening in contact with the conductive region. At 306, a filler material is formed over the adhesion layer and fills the opening. The filler material is comprised of a cobalt-based material. At 308, in an optional embodiment, heat is applied to reflow the filler material. At 310, the filler material and adhesion layer material disposed over the upper surface of the dielectric layer are removed.

[0035] In one embodiment, a cobalt-based plug is formed in a lower portion of an opening in a dielectric layer (e.g., a via hole or a slot), and a cobalt-based conductive line is then formed on the cobalt-based plug in an upper portion of the opening (e.g., a metal line trench) to form a cobalt interconnect.

[0036] For example, Figures 4A-4D A method for forming a cobalt metal interconnect according to an embodiment of the present invention is shown. The method begins with combining Figure 1B The structure shown and described is the same as that including the adhesion layer 120 and will not be described again for the sake of brevity.

[0037] refer to Figure 4A , plug 420 is formed on adhesion layer 120. In an embodiment, as shown, plug 420 is formed only within lower opening 114 of dielectric layer 102, so that lower opening 114 is completely filled with plug material 420. However, in another embodiment, the top surface of plug 420 may not be coplanar with the top surface of lower opening 114. For example, the top surface of plug 420 may be higher or lower than the top surface of the lower opening. The top surface of plug 420 may be located at, above, or below the horizontal top surface of layer 120, wherein layer 120 is horizontally disposed at the top of 114 and the bottom of 110. As Figure 4A , the top surface of plug 420 is just below the horizontal top surface of layer 120, where layer 120 is horizontally disposed on top of 114 and on the bottom of 110. In another embodiment, the top surface of plug 420 may form a mushroom-shaped dome as a result of a growth curve during formation of plug 420.

[0038] In an embodiment, plug 420 is formed in a bottom-up manner. That is, plug 420 is not formed by conformal deposition. For example, in one embodiment, plug 420 is formed by selective deposition on the surface of layer 120 directly above conductive region 150 and then growing from the surface of layer 120 directly above conductive region 150. In a specific embodiment, plug 420 is formed by electroless plating of the plug material onto the exposed and compatible surface of layer 120. As an example, conductive region 150 has an upper metallized or metal-containing surface, such as cobalt (Co), copper (Cu), or tungsten (W), and cobalt-based plug 420 is formed by electroless deposition, which includes bottom-up growth starting from layer 120 above the metallized or metal-containing surface of conductive region 150. In other embodiments, other suitable bottom-up fill and growth deposition methods may be used, such as, but not limited to, electroplating. A bottom-up fill method is a method in which the deposition rate is faster on a planar or flat surface than on a vertical sidewall surface.

[0039] Plug 420 may be a cobalt-based plug comprised of at least 50% cobalt. In a specific embodiment, plug 420 is comprised of at least 90% cobalt. In any such case, the remainder of the plug 420 composition, if any, other than cobalt, may include one or more of Al, Ni, Cu, Ag, Au, Mn, Ti, V, Cr, Fe, Ta, W, Ru, P, B, C, N, Si, Ge, Mg, Zn, Rh, Pt, Cd, Hf, In, Sn, C, O, Be, Ca, Zr, Nb, Mo, Ir, Re, or Pd. In another embodiment, plug 420 is comprised of a cobalt-based compound or alloy material. For example, in one embodiment, plug 420 is comprised of a low alloy comprising approximately 0.25-5% non-cobalt elements (such as those listed above) and the remainder being approximately 95%+ cobalt. During deposition or post-deposition processing, such low alloys may contain migration of non-cobalt species to the surface or interface of the cobalt plug. Migration may provide a diffusion barrier for cobalt and / or serve to enhance adhesion of cobalt to layer 120. Grain boundaries within the cobalt may also be filled with non-cobalt species. However, in other embodiments, plug 420 may include less than 50% cobalt but still be referred to as a cobalt-based material. Exemplary embodiments of cobalt-based compound plug 420 materials include cobalt silicide or cobalt germanide plug materials. In a specific embodiment of this invention, conductive region 150 includes at least some germanium (e.g., exposed doped silicon germanium or doped germanium regions, or metal germanide regions), and plug 420 material is a cobalt germanide layer. In another specific embodiment of this invention, conductive region 150 includes at least some silicon (e.g., exposed doped silicon regions, or metal silicide regions), and plug 420 material is a cobalt silicide layer. Exemplary embodiments of cobalt-based alloy plug 420 materials include cobalt alloyed with one or more of the following materials: Al, Ni, Cu, Ag, Au, Mn, Ti, V, Cr, Fe, Ta, W, Ru, P, B, C, N, Si, Ge, Mg, Zn, Rh, Pt, Cd, Hf, In, Sn, C, O, Be, Ca, Zr, Nb, Mo, Ir, Re, or Pd. In the aforementioned embodiments, cobalt plug 420 may have a small grain structure. In an embodiment, the aforementioned dopant (i.e., 0.25-5% of a non-cobalt element) may be used without layer 120, so that the cobalt will adhere directly to sidewalls 116 and portion 150. In an embodiment, the dopant essentially creates layer 120 (an adhesion layer) by diffusing to interfaces (e.g., at interfaces 150 and 116). In one embodiment, the dopant forms a layer with portion 150. In another embodiment, the dopant does not form the layer having 150 , so that the barrier has no bottom, and the plug 420 directly contacts the region 150 .

[0040] refer to Figure 4B, a pretreatment 422 may optionally be performed on the exposed top surface of plug 420 and layer 120. The pretreatment may be performed by a plasma process or ion bombardment to enhance adhesion of later formed compounds to the treated surface. In one embodiment, the pretreatment may be performed in a plasma chamber for approximately 20 to 60 seconds at temperatures ranging from room temperature to approximately 300° C., 400° C., 500° C., or higher, using, for example, H2 / He plasma, Ar plasma, NH3 plasma, N2 plasma, and / or combinations thereof. In another embodiment, the pretreatment may include Ar ion bombardment. It is understood that such pretreatment may be performed at other stages of the process flow (e.g., before forming the plug material). In one embodiment, the pretreatment is performed before forming layer 120. However, in other embodiments, the treatment of layer 120 may be quite beneficial to density without affecting dielectrics such as layer 102.

[0041] refer to Figure 4C , filler material 424 is formed over plug 420 and layer 120 within upper opening 110. After depositing filler material 424, a seam 426 may be formed within upper opening 110. In one embodiment, filler material 424 is comprised of a material including cobalt. For example, the filler material may be comprised of the materials described above for filler material 122 and may be deposited using the processes described above for filler material 122. Furthermore, filler material 424 may differ from the plug 420 material in composition and / or deposition technique.

[0042] An annealing process may optionally be performed to reflow the deposited fill material 424. The Figure 4C The seams 426 are formed to form a solid structure within the openings 110 and 114 in the dielectric layer 102. The annealing process can achieve the growth of a larger grain structure within the filler material 424, thereby reducing the resistivity and driving out impurities from an otherwise undesirable grain structure. In one embodiment, the annealing process includes the use of a forming gas such as, but not limited to, nitrogen, hydrogen, or argon. In addition, the annealing process can be performed at a temperature below the thermal budget of the back-end structure. For example, in one embodiment, the annealing process is performed at a temperature ranging from room temperature to 300°C, 400°C, 500°C, or higher. In another embodiment, the annealing process is performed at a temperature above the melting point of the filler material 424 but below the thermal budget of the back-end structure. In an embodiment, the annealing temperature is not higher than the melting point of the material to be annealed because reflow of the material to be annealed can occur at a temperature much lower than the melting point of the material to be annealed. In such an embodiment, the annealing temperature for the material to be annealed can be below the thermal budget of the back-end structure.

[0043] In yet another embodiment, a cyclic technique is optionally used to deposit filler material 424 within opening 110 without seam 426. A cycle can include a single deposition of filler material 424 and a single annealing process. The annealing operation of a cycle can be set at a temperature and duration that briefly reflows filler material 424 to improve step coverage. The deposition operation of a cycle can be a short deposition that deposits less filler material 424, so that several operations are required to completely fill upper opening 110. In one embodiment, less than five cycles are required to deposit filler material 424 without seam 426.

[0044] refer to Figure 4D A CMP process may be performed to remove fill material 424 above the top surface of layer 120 to provide cobalt-based structure 428. In one embodiment, the CMP process may be a timed CMP process, where the CMP process is timed to stop at the top surface 108 of the line dielectric layer. In another embodiment, the CMP process may utilize the top surface 108 of dielectric layer 102 as a stop layer. Because the thickness of the fill material deposited above the top surface of dielectric layer 102 may vary, utilizing the top surface 108 as a stop layer may be a more reliable approach. In an alternative embodiment, an etching process is used to remove fill material 424 above the top surface 108 of dielectric layer 102.

[0045] In an embodiment, a cobalt-based plug is formed in the lower portion of an opening (e.g., a via hole or slot) in a dielectric layer. An adhesion layer is then formed in the upper portion of the opening (e.g., a metal line trench) above the cobalt-based plug. A cobalt-based conductive line is then formed on the portion of the adhesion layer just above the plug to fill the upper portion of the opening to form a cobalt interconnect.

[0046] For example, Figures 5A-5D A method for forming a cobalt interconnect having an Mn-based adhesion layer and a cobalt-containing fill layer according to an embodiment of the present invention is shown. Figure 1A The same structure as shown and described above. Figure 5A , a cobalt-based plug 420 is formed in lower opening 114 of dielectric layer 102 over conductive region 150 of substrate 106. However, in another embodiment, an adhesion layer is first formed along the sidewalls of dielectric 102 and / or on top of portion 150 before forming plug 420.

[0047] refer to Figure 5B ,and Figure 5A The structure of the Mn-based adhesion layer 524 (eg, Mn, MnN, MnSi x N y 、MnSi x O y(e.g., Mn2[SiO4], MnSiO3), other Mn-based silicates, etc.) For example, in one embodiment, a Mn-based adhesion layer 524 is formed in the upper opening 114 of the dielectric layer 102 and on the exposed plug 420. The composition and method of forming the adhesion layer 524 can be as described for Figure 1B As described above for the adhesion layer 120.

[0048] refer to Figure 5C , a filler material 526 is formed on the adhesion layer 524, within the upper opening 110, and on the top surface 108 of the dielectric layer 102. After depositing the filler material 526, a seam 528 may be formed within the upper opening 110. The composition of the filler material layer 526 and the method of forming the filler material layer 526 may be as described for the embodiment of the present invention. Figure 1C Furthermore, while in an embodiment plug 420 and fill material 526 are all cobalt-based, they may all differ from one another in composition and / or deposition technique.

[0049] An annealing process may optionally be performed to reflow the deposited fill material 526. The Figure 5C The seams 528 are formed to form a solid structure within the opening 110 of the dielectric layer 102. The annealing process can achieve the growth of a larger grain structure within the filler material 526, thereby reducing the resistivity and driving out impurities from the undesirable grain structure. In one embodiment, the annealing process includes using a gas, such as but not limited to nitrogen, hydrogen, or argon. In addition, the annealing process can be performed at a temperature below the thermal budget of the back-end structure. For example, in one embodiment, the annealing process is performed at a temperature ranging from room temperature to 300°C, 400°C, 500°C, or higher. In another embodiment, the annealing process is performed at a temperature above the melting point of the filler material 526 but below the thermal budget of the back-end structure. In an embodiment, the annealing temperature is not higher than the melting point of the material to be annealed because the reflow of the material to be annealed can occur at a temperature much lower than the melting point of the material to be annealed. In such an embodiment, the annealing temperature for the material to be annealed can be below the thermal budget of the back-end structure.

[0050] In yet another embodiment, a cyclic technique can be used to deposit filler material 526 within opening 110 without seams 528. One cycle can include one deposition of filler material 526 and one annealing process. The annealing operation of one cycle can be set at a temperature and duration that causes a brief reflow of the filler material to improve step coverage. The deposition operation of one cycle can be a short deposition that deposits less filler material, so that several operations are required to completely fill opening 510. In one embodiment, less than five cycles are required to deposit filler material 526 without seams 528.

[0051] refer to Figure 5D , a CMP process may be performed to remove filler material 526 and adhesion layer 524 disposed above top surface 108 of dielectric layer 102 to provide cobalt-based structure 530. In one embodiment, the CMP process may be a timed CMP process, where the CMP process is timed to stop at top surface 108 of dielectric layer 102. In another embodiment, the CMP process may utilize top surface 108 of dielectric layer 102 as a stop layer. Because the thickness of the filler material deposited above top surface 108 of dielectric layer 102 may vary, utilizing top surface 108 as a stop layer may be a more reliable approach. In an alternative embodiment, an etching process is used to remove filler material 526 and layer 524 disposed above top surface 108 of dielectric layer 102.

[0052] Figure 6 600 is a flow chart illustrating a method of forming a cobalt metal interconnect according to an embodiment of the present invention. At 602, an opening is formed in a dielectric layer to expose a conductive region in a substrate. At 604, a cobalt plug is formed in a lower portion of the opening to contact the conductive region. At 605, an Mn-based adhesion layer (e.g., Mn, MnN, MnSi) is formed in an upper portion of the opening. x N y At 606, a filler material is formed over the plug and the adhesion layer to fill the opening. The filler material is composed of a cobalt-based material. At 608, in an optional embodiment, heat is applied to reflow the filler material. At 610, the filler material disposed above the upper surface of the dielectric layer is removed. In one such embodiment, the filler material and the plug both comprise cobalt, but have different material compositions. In another such embodiment, the filler material and the plug both comprise cobalt, but are formed using different deposition or growth techniques. In yet another such embodiment, the filler material and the plug both comprise cobalt, but have different material compositions and are formed using different deposition or growth techniques.

[0053] In an embodiment, a metal gate electrode of a semiconductor device is composed at least in part of cobalt. That is, embodiments of the present invention are not necessarily limited to forming cobalt-based interconnects.

[0054] In the example, Figure 7A metal oxide semiconductor field effect transistor (MOS-FET) 700 is depicted fabricated on a substrate 702 in accordance with an embodiment of the present invention. A gate dielectric layer 704 is disposed over a channel region 706, and a gate electrode 708 is disposed over the gate dielectric layer 704. The gate dielectric layer 704 and the gate electrode 708 may be isolated by a gate isolation spacer 710. A tip extension 712 may be formed by implanting dopant atoms into the substrate 702. Source and drain regions (e.g., strain-induced source / drain regions 720) may be formed by selectively growing an epitaxial film in an etched portion of the substrate 702, and the source and drain regions may be doped in situ or after the epitaxial film is grown, or both. In an embodiment, the tip extension 712 may be formed simultaneously with the source and drain regions to create an "epitaxial" tip extension. In a typical MOS-FET, the channel region 706 is composed of a semiconductor material such as single crystal silicon. In an embodiment, the gate electrode 708 is a metal gate electrode (e.g., the work function of the gate electrode 708 is based on a metal or a metal-containing layer). In one such embodiment, the metal gate electrode is composed of at least some cobalt. For example, in a specific embodiment, the metal gate electrode 708 includes an Mn-based adhesion layer (e.g., Mn, MnN, MnSi as described above). x N y The cobalt-based material or film 708B is formed of a low alloy having approximately 0.25-5% non-cobalt elements and the remainder being approximately 95%+ cobalt.

[0055] In addition, it is understood that the MOS-FET 700 can be a planar device or include a three-dimensional body (e.g., as in a dual-gate, fin-FET, tri-gate, or gate-all-around transistor). As such, the substrate 702 can be a planar substrate or can depict a cross-sectional view of a three-dimensional body. Finally, it is understood that for the sake of clarity, only a few features of the MOS-FET 700 are depicted. It is understood that, as is well known in the art, isolation layers (e.g., interlayer dielectric layer 740) and metallization wiring layers for integrating the MOS-FET 700 into, for example, an integrated circuit may also be included.

[0056] For example, various cobalt-based embodiments may be included in mobile computing nodes, such as cellular phones, smartphones, tablet computers, Notebooks, laptops, personal digital assistants, and mobile processor-based platforms.

[0057] Example 1 includes: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an additional interconnect structure; an adhesion layer disposed over the conductive region and on the sidewalls, the adhesion layer comprising manganese; and a filler material within the opening and on a surface of the adhesion layer, the filler material comprising cobalt. In some embodiments, the dielectric directly contacts the substrate, but in other embodiments, one or more layers are located between the dielectric and the substrate. In some embodiments, the additional interconnect structure may include vias, metal-filled trenches (interconnect lines), etc. Although the examples include a dual damascene approach, the openings discussed above do not necessarily have different widths, such as those found in FIG. 1 , or lines above vias typically associated with dual damascene processes. As explained below, reference to "an adhesion layer disposed over the conductive region, the adhesion layer comprising manganese" does not necessarily mean that manganese is present in the portion of the adhesion layer over the conductive region. For example, if the manganese is not in the portion of the adhesion layer over the conductive region but in the adhesion layer over the sidewalls, the requirement of "an adhesion layer disposed over the conductive region, the adhesion layer comprising manganese" is still satisfied.

[0058] In Example 2, the subject matter of Example 1 can optionally include wherein the filler material consists of at least 50 atomic % cobalt.

[0059] In Example 3, the subject matter of Examples 1-2 can optionally include wherein the adhesion layer includes at least one element selected from the group consisting of silicon, nitrogen, carbon, hydrogen, and oxygen.

[0060] In Example 4, the subject matter of Examples 1-3 can optionally include, wherein the adhesion layer is no thicker than 50 Å.

[0061] In Example 5, the subject matter of Examples 1-4 can optionally include, wherein the adhesive layer directly contacts the filler material.

[0062] In Example 6, the subject matter of Examples 1-5 can optionally include, wherein the adhesion layer directly contacts the conductive region. In another version of Example 6, the subject matter of Examples 1-5 can optionally include, wherein the adhesion layer directly contacts the conductive region and the dielectric layer.

[0063] In Example 7, the subject matter of Examples 1-6 can optionally include, wherein the fill material includes at least one element selected from the group consisting of silicon and manganese. This may be due to migration of silicon or manganese from the adhesion layer into the fill material and / or this may be due to utilizing the fill material to deposit silicon and / or manganese already present in addition to cobalt.

[0064] In Example 8, the subject matter of Examples 1-7 can optionally include, wherein the fill material includes manganese in direct contact with the manganese included in the adhesion layer. The cobalt fill layer can include manganese and / or silicon. This may not be visually apparent using a scanning electron microscope (SEM) image or a transmission electron microscope (TEM) image, but other detection methods can indicate the presence of manganese and / or silicon in the cobalt fill layer. Manganese and / or silicon may be present along the outer edge of the cobalt fill layer because the manganese and / or silicon may have migrated from the adhesion layer to the cobalt fill layer. For example, there is solubility between manganese and cobalt, and manganese from the adhesion layer in contact with the fill layer may have mixed with the cobalt fill layer. This migration helps the cobalt fill adhere to the adhesion layer and also allows the adhesion layer to act as a wetting layer for the cobalt fill layer. The wetting layer includes an initial layer of atoms epitaxially grown on the surface to create the self-assembled quantum dots or thin film.

[0065] An example involves TEM energy-dispersive x-ray (EDX). Small TEM probe electrons interact with the material being imaged, and the material emits x-rays from different elements present within a pixel of the image. This allows elemental mapping of the image. Higher sensitivity is achieved by using line scans with more dwell time across the structure (e.g., across a via rather than every pixel in the image). In an embodiment (Example 8a), if manganese is present in the cobalt fill layer, it may migrate to the adhesion layer / fill material interface, thereby improving adhesion. EDX can then detect manganese in the cobalt fill layer and near the adhesion layer / fill layer edge / interface. In an embodiment (Example 8b), if manganese is at the adhesion layer / fill layer interface, it may diffuse into the cobalt and other interfaces (e.g., the top layer after CMP). This will be detected both in the fill layer and near the edge / interface. In an embodiment, if manganese diffusion does not occur, then the manganese may be only in the fill layer in Example 8a and at the interface in Example 8b. In an embodiment, if manganese is present in both 120 and the fill layer, it can be detected in both areas. Diffusion may vary with respect to concentration / composition and adhesion or wetting ability so that the processes of Examples 8a and / or 8b occur, but manganese may still be detected in both scenarios of the embodiment.

[0066] Example similar to Figure 5D , but includes a dielectric capping layer / etch stop layer (e.g., similar or directly identical to the material and structure of element 104) that extends from the top surface of the left dielectric portion 102, across the tops of 524 and 526, and then across the top of the right dielectric portion 102. This covers the polished metal and is later etched through to form a via for the next layer, just like Figure 5D116 and through layer 104. The cover hermetically protects the line (e.g., material 530) and manganese (which in this embodiment is mixed and present in the cobalt fill 530) can diffuse into the cover layer to improve the adhesion of the dielectric cover layer / etch stop layer to the cobalt 530 (e.g., by forming silicates). The manganese can diffuse from layer 120 or from an already deposited alloy cobalt fill layer that includes a certain amount of manganese. The dielectric cover can be deposited at a high temperature, and the temperature can then drive the manganese to thermally diffuse from within layers 120 and / or 530 and / or 420 to the top of the trench 110. The manganese can be detected at the new dielectric cover / layer 530 interface by TEM EDX methods, etc.

[0067] In another example, the subject matter of Examples 1-8 can optionally include a dielectric layer formed directly on top of the adhesion layer and the filler material, the dielectric layer including manganese; wherein the filler material also includes manganese. The manganese may have migrated from the adhesion layer and / or the adhesion layer into the dielectric.

[0068] In another example 9, the subject matter of examples 1-8 can optionally include a dielectric layer formed directly on top of the fill material, the dielectric layer including a first material; wherein the first material is also included in the fill material and the first material is selected from the group consisting of Al, Ni, Cu, Ag, Au, Mn, Ti, V, Cr, Fe, Ta, W, Ru, P, B, C, N, Si, Ge, Mg, Zn, Rh, Pt, Cd, Hf, In, Sn, C, O, Be, Ca, Zr, Nb, Mo, Ir, Re, and Pd. The material may have migrated from the fill material into the dielectric.

[0069] In Example 9, the subject matter of Examples 1-8 can optionally include wherein (a) the adhesion layer includes a first portion directly contacting the dielectric layer and a second portion directly contacting the conductive region, and (b) the first portion includes a higher atomic % of manganese than the second portion. Manganese bonds well to the dielectric and the cobalt fill layer. At the adhesion layer / dielectric interface, manganese forms MnSi x O y(e.g., Mn2[SiO4], MnSiO3) and other Mn-based silicates. The silicate functions as a diffusion barrier, preventing cobalt from diffusing into the surrounding dielectric, and also provides an adhesive / wetting function, ensuring good adhesion of the cobalt to the dielectric. At the adhesion layer / cobalt fill layer interface, metal-to-metal bonding occurs (e.g., between manganese and cobalt), and some alloying occurs at the interface. This bonding provides the additional benefit of manganese decomposition at the bottom of the via (where, in embodiments, the adhesion layer directly contacts the metal fill layer and may also directly contact another interconnect or conductive substrate portion). This reduces the resistance in the via at the adhesion layer interface to other interconnects or conductive portions of the substrate. For example, the manganese from 120 formed at the bottom of the via begins as thick as a similar 120 portion on the ILD. After annealing, the manganese may diffuse completely into the cobalt fill or may remain in layer 120. The amount retained can vary. Therefore, in some embodiments, after device processing is completed, there may be little manganese remaining in the adhesion layer near the bottom of the via.

[0070] In Example 10, the subject matter of Examples 1-9 can optionally include, wherein the fill material consists essentially of cobalt. In another example, the subject matter of Examples 1-9 can optionally include, wherein the adhesion layer does not completely separate the conductive region from the fill material, and the fill material directly contacts portions of the conductive region. Thus, there may be regions where there is no manganese in the adhesion layer separating the fill material from the conductive region, as detected by TEM EDX or otherwise (regardless of whether the adhesion layer completely or incompletely separates the fill material from the conductive region). This can be considered a region where there is no detectable adhesion layer (regardless of whether the layer is there or not), and therefore "the adhesion layer does not completely separate the conductive region from the fill material, and the fill material directly contacts portions of the conductive region."

[0071] Example 11 includes a method of forming a metal interconnect structure, comprising: forming an opening in a dielectric layer on a substrate, wherein the opening exposes a conductive region of at least one of the substrate and an additional interconnect structure; forming an adhesion layer comprising manganese in the opening and on the conductive region and also on the sidewalls; forming a fill material comprising cobalt within the opening and on the surface of the adhesion layer; and removing portions of the fill material and the adhesion layer above the upper surface of the dielectric layer.

[0072] In Example 12, the subject matter of Example 11 can optionally include wherein the adhesion layer includes at least one element selected from the group consisting of silicon, nitrogen, carbon, hydrogen, and oxygen.

[0073] In Example 13, the subject matter of Examples 11-12 can optionally include, wherein the adhesive layer directly contacts the filler material.

[0074] In Example 14, the subject matter of Examples 11-13 can optionally include, wherein the adhesion layer directly contacts the conductive region.

[0075] In Example 15, the subject matter of Examples 13-14 can optionally include wherein (a) the adhesion layer includes a first portion directly contacting the dielectric layer and a second portion directly contacting the conductive region, and (b) the first portion includes a higher atomic % manganese than the second portion.

[0076] In Example 16, the subject matter of Examples 13-15 can optionally include forming the adhesion layer using a conformal method, and forming the fill layer using a non-conformal method.

[0077] In another example, the subject matter of Examples 13-15 can optionally include forming a dielectric layer directly on top of the adhesion layer and the fill material, the dielectric layer including manganese; wherein the fill material also includes manganese. Likewise, manganese may have migrated from the adhesion layer and / or the fill material into the dielectric.

[0078] Example 17 includes a metal interconnect structure comprising: a dielectric layer disposed on a substrate; an opening disposed in the dielectric layer and exposing a conductive region of at least one of the substrate and an additional interconnect structure, the opening having a lower portion and an upper portion; a plug disposed in the lower portion of the opening, the plug comprising cobalt; an adhesion layer disposed on the sidewalls, the adhesion layer comprising manganese; and a fill material disposed on the plug and in the upper portion of the opening, the fill material comprising cobalt.

[0079] In Example 18, the subject matter of Example 17 can optionally include, wherein the adhesion layer directly contacts the plug and the dielectric.

[0080] In Example 19, the subject matter of Examples 17-18 can optionally include, wherein the adhesion layer is between the plug and the filler material.

[0081] In Example 20, the subject matter of Examples 17-19 can optionally include wherein the plug and filler material have different compositions.

[0082] In another example 20, the subject matter of examples 17-19 can optionally include a dielectric layer formed directly on top of the adhesion layer and the fill material, the dielectric layer including manganese; wherein the fill material also includes manganese. The manganese may have migrated from the adhesion layer into the dielectric.

[0083] The foregoing description of the embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This specification and the appended claims include terms such as left, right, top, bottom, above, below, upper, lower, first, and second, which are used for descriptive purposes only and are not to be construed as limiting. For example, terms indicating relative vertical positions refer to the case where the device side (or active surface) of a substrate or integrated circuit is the "top" surface of the substrate; the substrate can be in virtually any orientation such that, in a standard terrestrial reference system, the "top" side of the substrate can be lower than the "bottom" side and still fall within the meaning of the term "top." As used herein (including in the claims), the term "on" does not indicate that a first layer "above" a second layer is directly on and in direct contact with the second layer unless explicitly stated otherwise; a third layer or other structure may exist between the first layer and the second layer located above the first layer. The embodiments of the devices or articles described herein may be manufactured, used, or shipped in a number of positions and orientations. Those skilled in the relevant art will appreciate that numerous modifications and variations are possible in light of the above teachings. Those skilled in the art will recognize various equivalent combinations and substitutions for the various components shown in the drawings. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims

1. An integrated circuit structure comprising: dielectric layer; an opening in the dielectric layer, the opening having an upper portion and a lower portion, the upper portion having a width greater than a width of the lower portion; a cobalt plug located in said lower portion of said opening; a manganese-based adhesion layer on sidewalls of the upper portion of the opening and on the cobalt plug and directly contacting the sidewalls of the upper portion of the opening and the cobalt plug, wherein the manganese-based adhesion layer is not a seed layer; and A cobalt fill material is located in the upper portion of the opening and on the manganese-based adhesion layer, wherein the cobalt fill material includes cobalt and copper, and the cobalt fill material includes at least 50% cobalt.

2. The integrated circuit structure according to claim 1, wherein: The cobalt plug comprises at least 50% cobalt.

3. The integrated circuit structure according to claim 2, wherein: The cobalt plug further includes one or more of the following: Al, Ni, Cu, Ag, Au, Mn, Ti, V, Cr, Fe, Ta, W, or Ru.

4. The integrated circuit structure according to claim 1, wherein: The cobalt plug comprises at least 90% cobalt.

5. The integrated circuit structure according to claim 4, wherein: The cobalt plug further includes one or more of the following: Al, Ni, Cu, Ag, Au, Mn, Ti, V, Cr, Fe, Ta, W, or Ru.

6. The integrated circuit structure according to claim 1, wherein: The manganese-based adhesion layer includes a material selected from the group consisting of Mn, MnN, MnSixNy, Mn2[SiO4], and MnSiO3.

7. The integrated circuit structure according to claim 1, wherein: The cobalt filler material comprises at least 90% cobalt.

8. The integrated circuit structure according to claim 1, wherein: The cobalt filler material includes at least 95% cobalt, with the remainder including Cu and one or more of the following: Al, Ni, Ag, Au, Mn, Ti, V, Cr, Fe, Ta, W, or Ru.

9. The integrated circuit structure according to claim 1, wherein: The cobalt fill material includes a material different from that of the cobalt plug.

10. The integrated circuit structure according to claim 1, wherein: The cobalt fill material includes at least 90% cobalt, the cobalt plug includes at least 50% cobalt, the manganese-based adhesion layer includes a material selected from the group consisting of Mn, MnN, MnSixNy, Mn2[SiO4] and MnSiO3, and wherein the cobalt fill material includes a material different from the cobalt plug.

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