Substrate, integrated packaging device, and manufacturing method of integrated packaging device

Abstract

The present invention discloses a substrate, an integrated packaged device, and a method for manufacturing the integrated packaged device. The substrate comprises a patterned conductive layer, an isolation structure layer, and chip pad units. The conductive layer comprises at least three layers arranged in a stacked arrangement. The isolation structure layer comprises several layers, each interposed between two adjacent conductive layers, and includes a base layer and at least one insulating layer. Several chip pad units are provided and arranged in a matrix. Each non-bottom conductive layer corresponds to at least one row of chip pad units. Several types of chip pad units are provided, each corresponding to each conductive layer, and each type of chip pad unit is disposed on the top isolation structure layer. The bottom conductive layer is connected to each non-bottom conductive layer above it via a via. The top conductive layer is connected to the corresponding chip pad unit. The non-top conductive layers are each connected to the corresponding chip pad unit via a connecting hole. The present invention can achieve high resolution of the packaged device and reduce the package size.

Description

Technical Field

[0001] The present invention belongs to the technical field of LED packaging, and in particular relates to a substrate, an integrated packaging device and a method for manufacturing the integrated packaging device. Background Art

[0002] With the development of lighting technology, the pixelation of LED light sources to achieve intelligent matrix lighting has become a trend. Especially in the field of intelligent automotive lighting and displays, the demand for packaging structures that can accommodate higher pixel counts is becoming increasingly urgent. Existing technologies mostly use a method of individually packaging multiple chips and then mounting them on a PCB, or employ COB (chip-on-board) technology, bonding the chip to the circuit board with wires and then encapsulating the chip and wires with encapsulating adhesive.

[0003] Multiple chips are individually packaged and then mounted on a PCB. On the one hand, the LED structure after packaging is large, which limits the size of the entire PCB board. On the other hand, the spacing between different pixels after mounting is large, making it difficult to achieve high-resolution pixel display and resulting in uneven light output.

[0004] The COB (chip on board) technology is used to bond the chip to the circuit board through leads, and then the chip and leads are encapsulated with packaging glue. Since the lead welding position needs to be retained, the package size is larger.

[0005] Therefore, a new technology is needed to solve the problem that packaging devices in the existing technology are difficult to achieve high resolution and the packaging size is large. Summary of the Invention

[0006] In order to solve the problems in the prior art that packaging devices are difficult to achieve high resolution and have large packaging sizes, the present invention provides a substrate, an integrated packaging device, and a method for manufacturing the integrated packaging device.

[0007] The present invention adopts the following technical solutions:

[0008] A substrate for integrated packaging devices, comprising a patterned conductive layer, an isolation structure layer and a chip pad unit;

[0009] The conductive layer is provided with at least three layers and is arranged in a stacked manner;

[0010] The isolation structure layer is provided with a plurality of layers and is respectively inserted between two adjacent conductive layers and fixedly connected to the conductive layers. The isolation structure layer includes a base layer and at least one insulating layer.

[0011] The chip pad unit is used to connect the light-emitting chip. The chip pad units are provided in plurality and arranged in a matrix on the top insulating structure layer. Each conductive layer other than the bottom layer corresponds to at least one row of chip pad units, and a row of chip pad units corresponds to only one conductive layer.

[0012] The chip pad units are provided in several types and correspond to the conductive layers respectively, and each type of chip pad unit is provided on the top insulating structure layer;

[0013] The bottom conductive layer is connected to each non-bottom conductive layer above it through conductive holes; the top conductive layer is connected to the corresponding chip pad unit; and the non-top conductive layers are connected to the corresponding chip pad units through connecting holes.

[0014] In some embodiments, the top conductive layer includes a plurality of first edge pads and a plurality of first graphic leads, one end of the first graphic lead is connected to the first edge pad, and the other end is connected to the corresponding chip pad unit, and the first edge pad is connected to the bottom conductive layer through the via hole.

[0015] In some embodiments, the conductive layers between the top conductive layer and the bottom conductive layer are all inner conductive layers, each of the inner conductive layers includes a plurality of second edge pads, a plurality of second pattern leads, and a plurality of second connecting pads, the second connecting pads are connected to the second edge pads through the second pattern leads, the second connecting pads are connected to the corresponding chip pad units through connecting holes, and the second edge pads are connected to the bottom conductive layer through the conducting holes;

[0016] The second edge pads are vertically staggered with respect to the first edge pads, and the second connecting pads are vertically opposite to the corresponding chip pad units.

[0017] In some embodiments, the bottom conductive layer includes a plurality of third edge pads, and the third edge pads are connected to the first edge pad or the second edge pad through the via hole; the third edge pads and the first edge pad or the second edge pad connected to themselves are opposite to each other in vertical direction.

[0018] In some embodiments, the row of the chip pad units corresponding to the top conductive layer is located at the outermost row of the matrix.

[0019] In some embodiments, it also includes a solder resist layer and a thermal conductive layer; the solder resist layer is arranged on the top insulating structure layer and covers the area on the insulating structure layer except the top conductive layer and the chip pad unit; the thermal conductive layer is arranged on the bottom insulating structure layer.

[0020] In some embodiments, the material of the base layer is a ceramic material, including Al2O3 ceramic, AlN ceramic, Si3N4 ceramic or BeO ceramic.

[0021] In some embodiments, each of the chip pad units includes a positive pad and a negative pad, and the matrix is ​​divided into several rectangular functional areas. Within the same functional area, several chip pad units are arranged in sequence, and the positive pad of one of the two adjacent chip pad units is connected to the negative pad of the other.

[0022] An integrated package device comprises the substrate as described above, the integrated package device further comprising a plurality of light-emitting chips, a light conversion layer corresponding to the light-emitting chips, a connecting adhesive layer, a filling adhesive and a dam;

[0023] Each of the light-emitting chips is connected to each of the chip pad units respectively; in the same functional area, each of the light-emitting chips is arranged adjacent to each other in sequence without any gaps;

[0024] The light conversion layer is fixed on the light emitting chip through the connecting adhesive layer, the dam is fixed on the top insulating structure layer and surrounds the matrix; the filling glue fills the dam and fills the gaps between each light emitting chip, each light conversion layer and the connecting adhesive layer.

[0025] A method for manufacturing an integrated package device, using the substrate as described above, comprises the following steps:

[0026] S1. Soldering a plurality of light-emitting chips to the chip pad units, and placing the light-emitting chips adjacent to each other in the same functional area without any gaps;

[0027] S2. Fixing each light conversion layer on each light emitting chip through a connecting adhesive layer;

[0028] S3, forming a dam surrounding the matrix on the top insulating structural layer using a colloid;

[0029] S4. Filling the dam with a filling glue, so that the filling glue fills the dam and fills the gaps between the light-emitting chips, the light conversion layers, and the connecting glue layer.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] 1. In the substrate of the present invention, a different conductive layer is provided for each chip pad unit. Each patterned conductive layer is connected to the chip pad unit through a through-hole, eliminating the need for external leads. Therefore, the spacing between the chip pad units can be more closely spaced. When used in an integrated packaged device, the spacing between the light-emitting chips is even smaller, thereby achieving an integrated packaged device with higher pixels and a smaller size structure after packaging.

[0032] 2. In the integrated packaging device of the present invention, the above substrate is used, and the matrix of the chip pad unit is divided into several rectangular functional areas. In the same functional area, several chip pad units are arranged in sequence, and the light-emitting chips are arranged adjacent to each other in sequence without any gaps, which can realize small-pitch and irregular matrix pixel packaging; reduce the package size, simplify the circuit layout, and facilitate downstream mounting. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The technology of the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0034] Figure 1 is a front view of the integrated package device of the present invention;

[0035] Figure 2 is a cross-sectional view of the integrated package device of the present invention;

[0036] Figure 3 It is a schematic diagram of the top conductive layer and the chip pad unit on the first insulating layer;

[0037] Figure 4 yes Figure 3 Cross-sectional view along AA;

[0038] Figure 5 yes Figure 3 Cross-sectional view along BB;

[0039] Figure 6 yes Figure 3 Schematic diagram of the chip pad unit at E in the middle;

[0040] Figure 7 is a schematic diagram of an inner conductive layer 1 on the front surface of the base layer;

[0041] Figure 8 yes Figure 7 Cross-sectional view along CC;

[0042] Figure 9 Schematic diagram of the inner conductive layer 2 on the back side of the substrate layer;

[0043] Figure 10 yes Figure 9 Cross-sectional view along DD;

[0044] Figure 11 is a schematic diagram of a bottom conductive layer on a second insulating layer;

[0045] Figure 12 It is a schematic diagram of the steps of the production method of the present invention.

[0046] Reference numerals:

[0047] 11 - top conductive layer; 111 - first edge pad; 112 - first pattern lead; 12 - inner conductive layer; 121 - inner conductive layer one; 122 - inner conductive layer two; 1201 - second edge pad; 1202 - second pattern lead; 1203 - second connection pad; 13 - bottom conductive layer; 131 - third edge pad;

[0048] 2-insulating structure layer; 21-top insulating structure layer; 211-solder resist layer; 22-middle insulating structure layer; 23-bottom insulating structure layer; 231-thermal conductive layer; 201-base layer; 202-first insulating layer; 203-second insulating layer;

[0049] 3-chip pad unit; 31-positive electrode pad; 32-negative electrode pad;

[0050] 41-conducting hole 1; 42-conducting hole 2; 43-conducting hole 3;

[0051] 5-connecting hole; 51-connecting hole 1; 52-connecting hole 2;

[0052] 6-filling glue; 7-dam; 8-light-emitting chip; 9-light conversion layer; 10-connecting glue layer. DETAILED DESCRIPTION

[0053] The following will be combined with the embodiments and drawings to clearly and completely describe the concept, specific structure and technical effects of the present invention so as to fully understand the purpose, scheme and effect of the present invention. It should be noted that the embodiments and features in the embodiments of this application can be combined with each other unless there is a conflict. The same reference numerals used throughout the drawings indicate the same or similar parts.

[0054] It should be noted that, unless otherwise specified, when a feature is referred to as being "fixed" or "connected" to another feature, it may be directly fixed or connected to the other feature or indirectly fixed or connected to the other feature. Furthermore, terms such as "upper," "lower," "left," and "right" used in this disclosure are intended solely to describe the relative positions of the components of the disclosure as shown in the accompanying drawings.

[0055] Example 1:

[0056] Reference Figures 2 to 11 A substrate for integrated packaging devices includes a patterned conductive layer, an isolation structure layer 2 and a chip pad unit 3.

[0057] Reference Figure 4 、 5, 8 and 10, wherein the conductive layer has at least three layers arranged in a stacked manner, that is, the conductive layer can have three or more layers. In this embodiment, the conductive layer has four layers, namely, from top to bottom, a top conductive layer 11, an inner conductive layer 121, an inner conductive layer 2 122, and a bottom conductive layer 13.

[0058] Reference Figure 2 、 4 , 5, 8, and 10, the insulating structure layer 2 comprises several layers, each interposed between two adjacent conductive layers and fixedly connected to the conductive layers. As can be seen from this structure, the number of insulating structure layers 2 is one less than the number of conductive layers. If the number of conductive layers is N (N is a natural number greater than or equal to 3), the number of insulating structure layers 2 is N-1. Specifically, the insulating structure layer 2 includes a base layer 201 and at least one insulating layer.

[0059] In this embodiment, refer to Figure 4 、 5 , 8, and 10, the conductive layer has four layers, and the insulating structural layer 2 has three layers, namely, a top insulating structural layer 21, a middle insulating structural layer 22, and a bottom insulating structural layer 23. The middle insulating structural layer 22 is the base layer 201, and the top insulating structural layer 21 and the bottom insulating structural layer 23 are insulating layers, namely, a first insulating layer 202 and a second insulating layer 203. The inner conductive layer 121 and the inner conductive layer 2 122 are disposed on the upper and lower surfaces of the base layer 201, respectively. The first insulating layer 202 and the second insulating layer 203 cover the inner conductive layer 121 and the inner conductive layer 2 122 on the upper and lower surfaces of the base layer 201, respectively. The top conductive layer 11 is located on the first insulating layer 202.

[0060] Reference Figure 3 The chip pad unit 3 is used to connect the light-emitting chip 8. The chip pad units 3 are provided in plurality and are arranged in a matrix on the top insulating structure layer 2. That is, in this embodiment, the matrix of the chip pad units 3 is provided on the first insulating layer 202.

[0061] Reference Figure 3 , each non-bottom conductive layer corresponds to at least one row of chip pad units 3, and a row of chip pad units 3 corresponds to only one conductive layer. The chip pad units 3 are provided in several categories and correspond to each of the conductive layers, and each category of chip pad units 3 is arranged on the top insulating structure layer 2. From this correspondence, it can be seen that the rows of chip pad units 3 are divided into N-1 categories, each category corresponds to a non-bottom conductive layer, and each category has at least one row, which can be multiple rows. In this embodiment, there are a total of 4 conductive layers, and there are 3 non-bottom conductive layers. The corresponding rows of chip pad units 3 are divided into 3 categories, each category has 2 rows, and a total of 6 rows.

[0062] Reference Figure 4、 5 , 8 and 10, the bottom conductive layer 13 and the non-bottom conductive layers 13 above it are connected through respective via holes, that is, each non-bottom conductive layer 13 is connected to the bottom conductive layer 13. It can be understood that since the spacing between each non-bottom conductive layer 13 and the bottom conductive layer 13 is different, the length of each via hole is also different, and the structure of each via hole is also different. In this embodiment, the vias are respectively via hole 1 41, via hole 2 42, and via hole 3 43. The top conductive layer 11 is connected to the bottom conductive layer 13 through via hole 1 41, the inner conductive layer 121 is connected to the bottom conductive layer 13 through via hole 2 42, and the inner conductive layer 2 122 is connected to the bottom conductive layer 13 through via hole 3 43. Correspondingly, via hole 1 41 passes through the top insulating structure layer 21, the middle insulating structure layer 22, and the bottom insulating structure layer 23, the via hole 2 42 passes through the middle insulating structure layer 22 and the bottom insulating structure layer 23, and the via hole 3 43 passes through the bottom insulating structure layer 23.

[0063] Reference Figure 4 , the top conductive layer 11 is connected to the corresponding chip pad unit 3; Figure 5 、 8 and 10, the non-top conductive layers 11 are respectively connected to the corresponding chip pad units 3 through the connecting holes 5. That is, each type of chip pad unit 3 is respectively connected to each non-bottom conductive layer, and each non-bottom conductive layer is connected to the bottom conductive layer 13, so that each type of chip pad unit 3 is connected to the bottom conductive layer 13. In this embodiment, there are 4 conductive layers, and there are 3 non-bottom conductive layers. There are 3 types of corresponding chip pad units 3, each type has 2 rows, and a total of 6 rows. Among them, the first row and the sixth row are of the same type, both corresponding to the top conductive layer 11; the second row and the fifth row are of the same type, both corresponding to the inner conductive layer 1 121; the third row and the fourth row are of the same type, both corresponding to the inner conductive layer 2 122.

[0064] Based on the above structure, in the substrate of the present invention, a conductive layer is used to connect each chip pad unit 3 arranged on the top insulating structure layer 21 to the bottom conductive layer, so that each chip pad unit 3 can be powered without the need to weld external leads. During integrated packaging, the light-emitting chip 8 can be welded to the chip pad unit 3 for power supply, and no external leads are required, so that the spacing between each chip pad unit 3 and the spacing between the light-emitting chips 8 can be set smaller and closer, thereby realizing an integrated packaging device with higher pixels and a smaller size structure after packaging.

[0065] Specifically, refer to Figures 3 to 5The top conductive layer 11 includes a plurality of first edge pads 111 and a plurality of first pattern leads 112. One end of the first pattern lead 112 is connected to the first edge pad 111, and the other end is connected to the corresponding chip pad unit 3. The first edge pad 111 is connected to the bottom conductive layer 13 through the conductive via. Through the above structure, the first edge pad 111 is connected to the bottom conductive layer 13. There are multiple chip pad units 3 of the same type corresponding to the top conductive layer 11, and each chip pad unit 3 is equipped with a first edge pad 111 and a first pattern lead 112. In this embodiment, the chips of the same type corresponding to the top conductive layer 11 are divided into two rows, the first and sixth rows, each row having seven chip pad units 3, for a total of 14. Accordingly, there are 14 first edge pads 111 and 14 first pattern leads 112. Each first edge pad 111 is disposed on the outer edge of the top insulating structural layer 21.

[0066] Similarly, refer to Figures 7 to 10 The conductive layers located between the top conductive layer 11 and the bottom conductive layer 13 are all inner conductive layers. Each inner conductive layer includes a plurality of second edge pads 1201, a plurality of second pattern leads 1202, and a plurality of second connection pads 1203. The second connection pads 1203 are connected to the second edge pads 1201 via the second pattern leads 1202. The second connection pads 1203 are connected to the corresponding chip pad units 3 via the connecting holes 5. The second edge pads 1201 are connected to the bottom conductive layer 13 via the vias. The second edge pads 1201 are vertically staggered from the first edge pads 111 to prevent contact and short circuiting when the vias penetrate. The second connection pads 1203 are vertically opposed to the corresponding chip pad units 3, facilitating connection to the vias without the need for additional leads. This structure connects the chip pad units 3 corresponding to the inner conductive layers to the bottom conductive layer 13.

[0067] In this embodiment, referring to Figure 7 and Figure 8 The inner conductive layer has two layers, inner conductive layer 121 and inner conductive layer 2 122. The communication holes 5 are divided into communication holes 1 51 and communication holes 2 52. The chip pad units 3 in the second and fifth rows are of the same type, both corresponding to inner conductive layer 121. Therefore, there are a total of 14 chip pad units 3 in the second and fifth rows. The inner conductive layer 121 has 17 second connection pads 1203, second pattern leads 1202, and second edge pads 1201. The second connection pads 1203 are connected to the corresponding chip pad units 3 through communication holes 1 51, and the second edge pads 1201 are connected to the bottom conductive layer 13 through vias 2 42.

[0068] Reference Figure 9 and Figure 10 The chip pad units 3 in the 3rd and 4th rows are of the same type and correspond to the inner conductive layer 2 122. Therefore, there are 14 chip pad units 3 in the 3rd and 4th rows in total, and the second connecting pads 1203, the second graphic leads 1202, and the second edge pads 1201 of the inner conductive layer 2 122 are all 17. The second connecting pads 1203 are connected to the corresponding chip pad units 3 through the connecting hole 2 52, and the second edge pads 1201 are connected to the bottom conductive layer 13 through the conducting hole 3 43.

[0069] It can be understood that each conductive layer is a patterned conductive layer. Therefore, each edge pad and pattern lead are also a patterned structure. Compared with the external leads, they occupy a smaller volume and space and are all attached to the base layer 201, embedded in the insulating layer or attached to the insulating layer.

[0070] Specifically, refer to Figure 4 、 8 , 10 and 11, the bottom conductive layer 13 includes a plurality of third edge pads 131, each of which is connected to the first edge pad 111 or the second edge pad 1201 via the vias; the third edge pads are vertically opposed to the first edge pad 111 or the second edge pad 1201 to which they are connected. The bottom conductive layer 13 is connected to other conductive layers via vias, so they need to be aligned vertically to avoid the use of wire connections. In this embodiment, since there are a total of 42 chip pad units 3, the total number of first edge pads 111 and the total number of second edge pads 1201 is also 42, and therefore, there are also a total of 42 third edge pads 131.

[0071] In some embodiments, reference Figure 3 The row of chip pad units 3 corresponding to the top conductive layer 11 is located in the outermost row of the matrix. Since the top conductive layer 11 and the chip pad units 3 are both located on the top insulating structural layer 21 and are not connected using vias, the row of chip pad units 3 corresponding to the top conductive layer 11 is located in the outermost row of the matrix. This allows for direct connection to the top conductive layer 11, preventing interference from other chip pad units 3 on the connection between the two and increasing the spacing between chip pad units 3. In this embodiment, even if the chip pad units 3 in the 1st and 6th rows correspond to the top conductive layer 11.

[0072] Preferably, refer to Figure 4 and Figure 11The substrate of the present invention further includes a solder resist layer 211 and a thermal conductive layer 231. The solder resist layer 211 is disposed on the top insulating structural layer 2 and covers the area of ​​the insulating structural layer 2 except for the top conductive layer 11 and the chip pad unit 3. The thermal conductive layer 231 is disposed on the bottom insulating structural layer 2. The solder resist layer 211 is provided to prevent short circuits caused by subsequent soldering. The thermal conductive layer 231 is a metal layer, which is used to expedite the dissipation of heat generated during operation of the substrate.

[0073] The base layer 201 is made of ceramic material, including Al2O3 ceramic, AlN ceramic, Si3N4 ceramic or BeO ceramic. The conductive layer is made of one or more of Cu, Ni, Pd, W, Ag and Au.

[0074] Specifically, refer to Figure 3 and 6 , each of the chip pad units 3 includes a positive pad 31 and a negative pad 32, and the matrix is ​​divided into several rectangular functional areas. In the same functional area, several chip pad units 3 are arranged in sequence, and the positive pad 31 of one of the two adjacent chip pad units 3 is connected to the negative pad 32 of the other. During welding, the positive and negative poles of the light-emitting chip 8 are welded to the positive pad 31 and the negative pad 32 respectively. In the same functional area, due to the positive pad 31 of one of the two adjacent chip pad units 3, the light-emitting units in the same area are connected in series after welding. By connecting the external circuit for input through each edge pad, each light-emitting chip 8 can be lit independently or a functional area can be lit together. For example Figure 3 In the example, each row is a functional area, and each light-emitting chip 8 in the row can be lit independently or the entire functional area can be lit together. Alternatively, several adjacent rows can be divided into one functional area, and the positive electrode pad 31 or negative electrode pad 32 at the end of each row is connected to the pad of the opposite electrode in the next row.

[0075] Example 2:

[0076] Reference Figures 1 to 11 An integrated packaging device includes the substrate as described in Example 1, and the integrated packaging device also includes a plurality of light-emitting chips 8, a light conversion layer 9 corresponding to the light-emitting chips 8, a connecting glue layer 10, a filling glue 6 and a dam 7.

[0077] Reference Figure 1 and Figure 2Each of the light-emitting chips 8 is connected to each of the chip pad units 3. In the same functional area, the light-emitting chips 8 are arranged adjacent to each other without any gaps, so as to realize the series connection of the light-emitting chips 8 in the functional area. Each edge pad is connected to the external circuit for input, and each chip can be lit independently or a functional area can be lit together.

[0078] The light conversion layer 9 is fixed on the light emitting chip 8 through the connecting adhesive layer 10, and the dam 7 is fixed on the top insulating structure layer 2 and surrounds the matrix; the filling glue 6 fills the dam 7 and fills the gaps between each light emitting chip 8, each light conversion layer 9, and the connecting adhesive layer 10.

[0079] In the integrated packaging device of the present invention, the substrate of Example 1 is adopted, and the matrix of the chip pad unit 3 is divided into several rectangular functional areas. In the same functional area, several of the chip pad units 3 are arranged in sequence, and the light-emitting chips 8 are arranged adjacent to each other in sequence without any gaps, which can realize small-pitch and irregular matrix pixel packaging; reduce the package size, simplify the circuit layout, and facilitate downstream mounting.

[0080] Example 3

[0081] Reference Figures 1 to 12 A method for manufacturing an integrated package device, using the substrate described in Example 1, comprises the following steps:

[0082] S1. Reference Figure 12 , welding a plurality of light-emitting chips 8 to each of the chip pad units 3, and in the same functional area, the light-emitting chips 8 are sequentially arranged adjacent to each other without any gaps;

[0083] S2, reference Figure 12 , fixing each light conversion layer 9 on each light emitting chip 8 respectively through a connecting adhesive layer 10;

[0084] S3. Reference Figure 12 , using colloid to form a dam 7 surrounding the matrix on the top insulating structure layer 2;

[0085] S4, reference Figure 12 , filling the dam 7 with a filling glue 6 so that the filling glue 6 fills the dam 7 and fills the gaps between the light emitting chips 8 , the light conversion layers 9 , and the connecting glue layer 10 .

[0086] The dam 7 , the connecting adhesive layer 10 and the filling adhesive 6 are all made of silicone.

[0087] The manufacturing method of the present invention adopts the substrate of Example 1. During the manufacturing process, no external leads are required to solder the light-emitting chips 8, the operation is simpler, the spacing between the light-emitting chips 8 is smaller, the integrated packaged device has higher pixels, and the size structure after packaging is smaller.

[0088] For other details of the substrate, integrated packaging device and the method for manufacturing the integrated packaging device described in the present invention, please refer to the prior art and will not be repeated here.

[0089] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Therefore, any modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall still fall within the scope of the technical solution of the present invention.

Claims

1. An integrated package device, characterized in that: It includes a substrate and a plurality of light-emitting chips, a light conversion layer corresponding to the light-emitting chips, a connecting adhesive layer, a filling adhesive and a dam; the substrate includes a patterned conductive layer, an isolation structure layer and a chip pad unit; The conductive layer is provided with at least three layers and is arranged in a stacked manner; The insulating structure layer is provided with a plurality of layers and is respectively inserted between two adjacent conductive layers and fixedly connected to the conductive layers. The insulating structure layer includes a base layer and at least one insulating layer. The chip pad unit is used to connect the light-emitting chip. The chip pad units are provided in plurality and arranged in a matrix on the top insulating structure layer. Each conductive layer other than the bottom layer corresponds to at least one row of chip pad units, and a row of chip pad units corresponds to only one conductive layer. The chip pad units are provided in several types and correspond to the conductive layers respectively, and each type of chip pad unit is provided on the top insulating structure layer; The bottom conductive layer is connected to each non-bottom conductive layer above it through a conductive hole; the top conductive layer is connected to the corresponding chip pad unit; the non-top conductive layers are connected to the corresponding chip pad units through a connecting hole; The top conductive layer includes a plurality of first edge pads and a plurality of first pattern leads, one end of the first pattern lead is connected to the first edge pad, and the other end is connected to the corresponding chip pad unit, and the first edge pad is connected to the bottom conductive layer through the via hole; The conductive layers located between the top conductive layer and the bottom conductive layer are all inner conductive layers, each of the inner conductive layers includes a plurality of second edge pads, a plurality of second pattern leads, and a plurality of second connecting pads, the second connecting pads are connected to the second edge pads through the second pattern leads, the second connecting pads are connected to the corresponding chip pad units through connecting holes, and the second edge pads are connected to the bottom conductive layer through the conducting holes; The second edge pad is staggered with respect to the first edge pad in vertical direction, and the second connection pad is vertically opposite to the corresponding chip pad unit; The inner conductive layer includes an inner conductive layer 1 and an inner conductive layer 2, and the connecting hole includes a connecting hole 1 and a connecting hole 2; the second connecting pad is connected to the corresponding chip pad unit through the connecting hole 1, and the second edge pad is connected to the bottom conductive layer through the connecting hole 2; the second connecting pad is connected to the corresponding chip pad unit through the connecting hole 2, and the second edge pad is connected to the bottom conductive layer through the connecting hole 3; The vias include via one, via two, and via three. The top conductive layer is connected to the bottom conductive layer through via one, the inner conductive layer is connected to the bottom conductive layer through via two, and the inner conductive layer is connected to the bottom conductive layer through via three. Correspondingly, via one passes through the top insulating structure layer, the middle insulating structure layer, and the bottom insulating structure layer, via two passes through the middle insulating structure layer and the bottom insulating structure layer, and via three passes through the bottom insulating structure layer.

2. The integrated package device according to claim 1, wherein: The bottom conductive layer includes a plurality of third edge pads, which are connected to the first edge pad or the second edge pad through the vias; the third edge pads are vertically opposite to the first edge pad or the second edge pad connected to them.

3. The integrated package device according to claim 1, wherein: The row of the chip pad units corresponding to the top conductive layer is located at the outermost row of the matrix.

4. The integrated package device according to claim 1, wherein: It also includes a solder resist layer and a heat conducting layer; the solder resist layer is arranged on the top insulating structure layer and covers the area on the insulating structure layer except the top conductive layer and the chip pad unit; the heat conducting layer is arranged on the bottom insulating structure layer.

5. The integrated package device according to claim 1, wherein: The material of the base layer is a ceramic material, including Al2O3 ceramic, AlN ceramic, Si3N4 ceramic or BeO ceramic.

6. The integrated package device according to any one of claims 1 to 5, characterized in that: Each of the chip pad units includes a positive pad and a negative pad. The matrix is ​​divided into several rectangular functional areas. Within the same functional area, several chip pad units are arranged in sequence. The positive pad of one of the two adjacent chip pad units is connected to the negative pad of the other.

7. The integrated package device according to claim 6, characterized in that: Each of the light-emitting chips is connected to each of the chip pad units respectively; in the same functional area, each of the light-emitting chips is arranged adjacent to each other in sequence without any gaps; The light conversion layer is fixed on the light emitting chip through the connecting adhesive layer, the dam is fixed on the top insulating structure layer and surrounds the matrix; the filling glue fills the dam and fills the gaps between each light emitting chip, each light conversion layer and the connecting adhesive layer.

8. A method for manufacturing an integrated packaging device, characterized in that: The integrated packaging device according to claim 6 comprises the following steps: S1. Soldering a plurality of light-emitting chips to the chip pad units, and placing the light-emitting chips adjacent to each other in the same functional area without any gaps; S2. Fixing each light conversion layer on each light emitting chip through a connecting adhesive layer; S3, forming a dam surrounding the matrix on the top insulating structural layer using a colloid; S4. Filling the dam with a filling glue, so that the filling glue fills the dam and fills the gaps between the light-emitting chips, the light conversion layers, and the connecting glue layer.

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