Three-dimensional memory and methods of making the same

Abstract

The application provides a three-dimensional memory and a preparation method thereof. The three-dimensional memory comprises a stacked source layer and a stacked structure, and a first semiconductor layer, the first semiconductor layer comprises a first part and a second part connected with the first part, and the stacked structure comprises alternately stacked gate layers and interlayer insulating layers; a channel structure passes through the stacked structure and extends to the source layer; the first part is located between the source layer and the stacked structure and is connected with a channel layer of the channel structure, the second part is arranged on a side of the source layer away from the stacked structure and penetrates in the source layer. The three-dimensional memory has good electrical performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a three-dimensional memory and its fabrication method. Background Technology

[0002] As the number of stacked layers in a 3D memory increases, during the process of removing the bottom oxide-nitride-oxide (ONO) layer to form an opening, if the opening is not opened or not fully opened, the bottom epitaxial structure and the channel layer may not be able to connect or the connection area may be small, thus affecting the electrical performance of the 3D memory. Summary of the Invention

[0003] The purpose of this invention is to provide a three-dimensional memory and its fabrication method to solve the technical problem of poor electrical performance of three-dimensional memory.

[0004] The present invention provides a three-dimensional memory, comprising: a stacked source layer and a stacked structure, and a first semiconductor layer, the first semiconductor layer comprising a first portion and a second portion connected to the first portion, the stacked structure comprising alternately stacked gate layers and interlayer insulating layers; a channel structure passing through the stacked structure and extending to the source layer; the first portion being located between the source layer and the stacked structure and connected to the channel layer of the channel structure, the second portion being disposed on the side of the source layer opposite to the stacked structure and penetrating within the source layer.

[0005] The three-dimensional memory includes a first oxide layer, a nitride layer, and a second oxide layer disposed sequentially. The first oxide layer, the nitride layer, and the second oxide layer are located between the source layer and the stacked structure, and the first oxide layer is stacked with the source layer, and the second oxide layer is stacked with the stacked structure. The end faces of the first oxide layer, the nitride layer, and the second oxide layer are connected to the end face of the first portion.

[0006] The three-dimensional memory further includes a connection layer, which connects the stacked structure and the source layer. The channel structure extends through the connection layer, and a first portion of the first semiconductor layer is connected to the connection layer.

[0007] Wherein, the first part is a hollow structure or a solid structure; and / or, the structure of the second part penetrating the source layer is a hollow structure or a solid structure.

[0008] The first part has a plurality of spaced-apart gaps; and / or the second part has a plurality of spaced-apart gaps in its structure penetrating the source layer.

[0009] The three-dimensional memory further includes: a first insulating layer located on the side of the first semiconductor layer away from the source layer, and the first insulating layer fills the hollow structure of the first part and the hollow structure of the second part.

[0010] The three-dimensional memory further includes: a second insulating layer covering the stacked structure and the source layer; a first contact passing through the second insulating layer and connected to the gate layer of the stacked structure; an interconnect structure located on the side of the stacked structure away from the source layer, the interconnect structure being electrically connected to the channel structure; and peripheral circuitry located on the side of the interconnect structure away from the stacked structure and electrically connected to the interconnect structure. The peripheral circuitry includes: a peripheral substrate, peripheral devices disposed on the peripheral substrate, and a dielectric layer covering the peripheral devices and the peripheral substrate.

[0011] The three-dimensional memory further includes: a second contact extending through the second insulating layer into the source layer; a first lead-out contact extending through the first insulating layer and through the first semiconductor layer into the source layer, wherein the second contact is connected to the first lead-out contact; a source contact extending through the first insulating layer and through the first semiconductor layer into the source layer and connected to the source layer; and a first bridge layer located on the side of the first insulating layer opposite to the first semiconductor layer and connecting the first lead-out contact and the source contact.

[0012] The three-dimensional memory further includes a connection contact point that extends through the second insulating layer into the connection layer and connects to the connection layer.

[0013] The three-dimensional memory further includes: a third contact extending through the second insulating layer into the source layer; and a second lead-out contact extending through the first insulating layer and through the first semiconductor layer into the source layer, wherein the third contact and the second lead-out contact are respectively connected.

[0014] The three-dimensional memory further includes: a fourth contact extending through the dielectric layer into the peripheral substrate; and a third lead-out contact extending into the peripheral substrate and connected to the fourth contact.

[0015] The source layer is an N-type doped semiconductor layer, and the first semiconductor layer is an N-type doped semiconductor layer. This invention provides a method for fabricating a three-dimensional memory, comprising: providing stacked source layers, sacrificial layers, and a stacked structure, wherein the sacrificial layer is located between the source layer and the stacked structure, and the stacked structure includes alternately stacked gate layers and interlayer insulating layers; forming a plurality of channel structures passing through the stacked structure and through the sacrificial layer and extending to the source layer; forming vias penetrating the source layer and the sacrificial layer, wherein the vias expose the channel layer of the channel structure; forming a first semiconductor layer on the wall of the vias and on the side of the source layer opposite to the stacked structure, wherein the first semiconductor layer is connected to the channel layer of the channel structure.

[0016] The via includes a first sub-via and a second sub-via communicating with the first sub-via; the first sub-via is surrounded by the source layer and the stacked structure; or, the first sub-via is surrounded by the stacked structure, the source layer and the etched sacrificial layer; the second sub-via is located within the source layer.

[0017] The sacrificial layer includes a first oxide layer, a nitride layer, and a second oxide layer disposed sequentially. The first oxide layer, the nitride layer, and the second oxide layer are located between the source layer and the stacked structure, and the first oxide layer is stacked with the source layer, and the second oxide layer is stacked with the stacked structure.

[0018] The phrase "providing a stacked source layer, a sacrificial layer, and a stacked structure, wherein the sacrificial layer is located between the source layer and the stacked structure" includes: providing a stacked source layer, a sacrificial layer, a connection layer, and a stacked structure, wherein the connection layer is located between the sacrificial layer and the stacked structure.

[0019] The phrase "forming a via through the source layer and the sacrificial layer, wherein the via exposes the channel layer of the channel structure" includes: forming a first initial via on the source layer and the sacrificial layer, wherein the first initial via exposes the nitride layer; selectively etching the nitride layer to enlarge the first initial via into a second initial via, wherein the second initial via exposes the memory film layer of the channel structure; and etching the memory film layer exposed by the second initial via to expose the channel layer of the channel structure.

[0020] The phrase "etching the memory film layer exposed by the second initial via" includes: when etching the memory film layer, etching the first oxide layer and the second oxide layer to enlarge the second initial via into the via.

[0021] The fabrication method further includes, after etching the memory film layer, etching the first oxide layer and the second oxide layer to enlarge the second initial via into the via.

[0022] Wherein, "etching the second oxide layer" includes: etching the second oxide layer so that the via exposes the interconnect layer; "forming a first semiconductor layer on the wall of the via" includes: when forming the first semiconductor layer, the first semiconductor layer is connected to the interconnect layer.

[0023] The fabrication method further includes, after forming the first semiconductor layer, forming a first insulating layer on the side of the first semiconductor layer away from the source layer, such that the first insulating layer fills the hollow structure of the first semiconductor layer.

[0024] The fabrication method further includes, after forming the stacked structure, the following steps: forming a second insulating layer covering the stacked structure, the sacrificial layer, and the source layer; forming a first contact point through the second insulating layer on the second insulating layer, wherein the first contact point is connected to the gate layer of the stacked structure; forming an interconnect structure on the side of the stacked structure away from the source layer, wherein the interconnect structure is electrically connected to the channel structure; and forming a peripheral circuit on the side of the interconnect structure away from the stacked structure, wherein the peripheral circuit is electrically connected to the interconnect structure; the peripheral circuit includes: a peripheral source layer, peripheral devices disposed on the peripheral source layer, and a dielectric layer covering the peripheral devices and the peripheral source layer.

[0025] The fabrication method, after forming the peripheral circuit, further includes: forming a second contact extending into the source layer on the second insulating layer; forming a first lead-out contact on the first insulating layer and the first semiconductor layer, wherein the first lead-out contact extends into the source layer and is connected to the second contact; forming a source contact on the first insulating layer and the first semiconductor layer, wherein the source contact is connected to the source layer; and forming a first bridge layer on the side of the first insulating layer opposite to the first semiconductor layer, wherein the first bridge layer connects the first lead-out contact and the source contact.

[0026] Wherein, "forming a first contact point through the second insulating layer on the second insulating layer" includes:

[0027] When the first contact is formed, a connecting contact is formed, wherein the connecting contact extends through the second insulating layer into the connecting layer and connects to the connecting layer.

[0028] The preparation method further includes: forming a third contact on the second insulating layer, wherein the third contact extends into the source layer; forming a second lead-out contact on the first insulating layer and through the first semiconductor layer, wherein the second lead-out contact extends into the source layer and is connected to the third contact.

[0029] The preparation method further includes: forming a fourth contact on the dielectric layer, wherein the fourth contact extends into the peripheral source layer; and forming a third lead-out contact on the peripheral source layer, wherein the third lead-out contact is connected to the fourth contact.

[0030] In summary, by providing a first semiconductor layer connection layer on the side of the source layer facing away from the stacked structure, and by connecting a first portion of the first semiconductor layer to the channel layer of the channel structure, the first semiconductor layer connection layer connects the channel layer of the channel structure to the source layer. This eliminates the need to form an epitaxial structure within the 3D memory to connect the channel layer to the source layer, resulting in better electrical performance of the 3D memory. Furthermore, the formation method of the first semiconductor layer in this application is simple, has a large process operation window, and is not limited by the number of stacked structure layers. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of a structure in which a first sacrificial oxide layer, a first sacrificial nitride layer, a second sacrificial oxide layer, and a source layer are formed on a substrate.

[0033] Figure 2 This is a schematic diagram of the structure in which a first oxide layer, a nitride layer, and a second oxide layer are formed on the source layer.

[0034] Figure 3 This is a schematic diagram of a structure in which a connecting layer is formed on the second oxide layer.

[0035] Figure 4 It is a schematic diagram of a structure in which a stacked structure is formed on the connecting layer, and a channel structure extending to the source layer is formed on the stacked structure.

[0036] Figure 5 This is a schematic diagram of the structure forming the stepped structure and the second insulating layer.

[0037] Figure 6 This is a schematic diagram of a gate trench formed between channel structures.

[0038] Figure 7 This is a schematic diagram of a structure that removes the gate sacrificial layer by using a gate trench as the entry point.

[0039] Figure 8 This is a schematic diagram of a structure in which a gate layer is formed at the location corresponding to the gate sacrificial layer.

[0040] Figure 9 This is a schematic diagram of a structure filled with gate trenches.

[0041] Figure 10 This is a schematic diagram of the structure that forms the first contact and the second contact.

[0042] Figure 11 This is a schematic diagram of the interconnect structure.

[0043] Figure 12 This is a schematic diagram of the interconnection structure and its connection to the peripheral circuit.

[0044] Figure 13 This is a schematic diagram of the structure after removing the substrate, the first sacrificial oxide layer, the first sacrificial nitride layer, and the second sacrificial oxide layer.

[0045] Figure 14 This is a schematic diagram of the structure forming the first initial via.

[0046] Figure 15 This is a schematic diagram of the structure forming the second initial via.

[0047] Figure 16 This is a schematic diagram of the structure forming a via.

[0048] Figure 17 This is a schematic diagram of the structure forming the first semiconductor layer.

[0049] Figure 18 This is a schematic diagram of the structure forming the first insulating layer.

[0050] Figure 19 This is a schematic diagram of the structure that forms the lead-out hole.

[0051] Figure 20 This is a schematic diagram of the structure that forms the initial spacer layer.

[0052] Figure 21 This is a schematic diagram of the structure that forms the spacer layer.

[0053] Figure 22 This is a schematic diagram of the structure that forms the lead-out contact layer.

[0054] Figure 23 This is a schematic diagram of the structure that forms the first lead-out contact and the second lead-out contact.

[0055] Figure 24 This is a schematic diagram of the structure of the first type of three-dimensional memory in this application.

[0056] Figure 25 This is a schematic diagram of the structure of the second type of three-dimensional memory in this application.

[0057] Figure 26 This is a schematic diagram of the third type of three-dimensional memory in this application.

[0058] Figure 27 This is a schematic diagram of the structure of the fourth type of three-dimensional memory in this application.

[0059] Figure 28 This is a schematic diagram of the structure of the fifth type of three-dimensional memory in this application.

[0060] Figure 29 This is a schematic diagram of the structure of the sixth type of three-dimensional memory in this application. Detailed Implementation

[0061] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0062] Please see Figure 17 The present invention provides a three-dimensional memory, comprising:

[0063] The stacked source layer 10, stacked structure 30, and first semiconductor layer 50 are provided. The first semiconductor layer 50 includes a first portion 501 and a second portion 502 connected to the first portion 501. The stacked structure 30 includes alternately stacked gate layers and interlayer insulating layers. Optionally, the source layer 10 is an N-type doped semiconductor layer, and the material of the source layer 10 can be polysilicon. The first semiconductor layer 50 is an N-type doped semiconductor layer, and the material of the first semiconductor layer 50 can be polysilicon.

[0064] A channel structure 40 extends through the stacked structure 30 and to the source layer 10. It is understood that the channel structure 40 is formed by: forming a channel hole extending to the source layer 10 on the stacked structure 30; and forming a memory film and a channel layer on the wall of the channel hole in the direction from the hole wall to the hole center. The memory film includes a barrier insulating layer, a charge trapping layer, and a tunneling insulating layer along the hole wall to the hole center. An exemplary material for the barrier insulating layer and the tunneling insulating layer is silicon oxide, and an exemplary material for the charge trapping layer is silicon nitride. The memory film forms a silicon oxide-silicon nitride-silicon oxide (ONO) stacked structure. An exemplary material for the channel layer is silicon (Si). Other materials can be selected for the barrier insulating layer, the charge trapping layer, and the tunneling insulating layer, and are not limited herein.

[0065] The first part 501 is located between the source layer 10 and the stacked structure 30 and is connected to the channel layer of the channel structure 40. The second part 502 is located on the side of the source layer 10 away from the stacked structure 30 and extends through the source layer 10.

[0066] In this application, a first semiconductor layer 50 is formed on the side of the source layer 10 facing away from the stacked structure 30, and a first portion 501 of the first semiconductor layer 50 is connected to the channel layer of the channel structure 40. The first semiconductor layer 50 connects the channel layer of the channel structure 40 to the source layer 10, eliminating the need to form an epitaxial structure connecting the channel layer to the source layer 10 within the three-dimensional memory, resulting in better electrical performance of the three-dimensional memory. The formation method of the first semiconductor layer 50 in this application is simple, the process operation window is large, and it is not limited by the number of layers in the stacked structure 30.

[0067] In one specific embodiment, the first part 501 is a hollow structure or a solid structure.

[0068] It is understandable that a via 300 is formed within the source layer 10 before the first semiconductor layer 50 is formed; if the first portion 501 adheres to the wall of the via 300 but does not completely fill the via 300, the first portion 501 is a hollow structure. Figure 24 If the first part 501 completely fills the via 300, the first part 501 is a solid structure. Figure 26 ).

[0069] In one specific embodiment, the hollow structure of the first part 501 is specifically manifested as follows: the first part 501 is provided with a plurality of gaps 570, and the plurality of gaps 570 are spaced apart. Figure 25 ); or, multiple gaps 570 connect to form a larger space ( Figure 24 It is understandable that the gap 570 provided in the first part 501 can resist thermal expansion and contraction caused by temperature changes.

[0070] In one specific embodiment, the structure of the second part 502 penetrating the source layer 10 is a hollow structure or a solid structure.

[0071] It is understandable that if the structure of the second part 502 penetrating the source layer 10 is attached to the wall of the via 300 in the source layer 10 and does not completely fill the via 300 in the source layer 10, the second part 502 is a hollow structure; if the structure of the second part 502 penetrating the source layer 10 completely fills the via 300 in the source layer 10, the second part 502 is a solid structure.

[0072] The structure of the second part 502 penetrating the source layer 10 is a hollow structure. Specifically, the structure of the second part 502 penetrating the source layer 10 has multiple gaps 570, which are spaced apart or connected to form a larger space. It is understood that the gaps 570 in the second part 502 can resist thermal expansion and contraction caused by temperature changes.

[0073] In one specific embodiment, the three-dimensional memory includes a first oxide layer 201, a nitride layer 202, and a second oxide layer 203 disposed sequentially. The first oxide layer 201, the nitride layer 202, and the second oxide layer 203 are located between the source layer 10 and the stacked structure 30, and the first oxide layer 201 is stacked with the source layer 10, and the second oxide layer 203 is stacked with the stacked structure 30. The end faces of the first oxide layer 201, the nitride layer 202, and the second oxide layer 203 are connected to the end face of the first portion 501.

[0074] Understandably, the via 300 extends within the first oxide layer 201, nitride layer 202, and second oxide layer 203, with the end faces of the first oxide layer 201, nitride layer 202, and second oxide layer 203 exposed. When the first semiconductor layer 50 is formed within the via 300, the first portion 501 of the first semiconductor layer 50 connects to the end faces of the first oxide layer 201, nitride layer 202, and second oxide layer 203. The first oxide layer 201, nitride layer 202, and second oxide layer 203 can support the first semiconductor layer 50, making the connection of the first semiconductor layer 50 more stable.

[0075] In one specific embodiment, the three-dimensional memory further includes a connection layer 204, which connects the stacked structure 30 and the source layer 10. A channel structure 40 extends through the connection layer 204, and a first portion 501 of the first semiconductor layer 50 is connected to the connection layer 204. Optionally, the connection layer 204 is located between the stacked structure 30 and the second oxide layer 203. It is understood that when the via 300 is formed, at least a portion of the surface of the connection layer 204 is exposed. When the first semiconductor layer 50 is formed within the via 300, the first portion 501 of the first semiconductor layer 50 is connected to the connection layer 204. The connection layer 204 can connect and conduct the first semiconductor layer 50 to the internal structure of the three-dimensional memory.

[0076] In one specific embodiment, the three-dimensional memory further includes:

[0077] Please see Figure 18 The first insulating layer 340 is located on the side of the first semiconductor layer 50 opposite to the source layer 10, and the first insulating layer 340 fills the hollow structure of the first portion 501 and the hollow structure of the second portion 502. It can be understood that if the first portion 501 is a hollow structure and the second portion 502 is a hollow structure, then when forming the first insulating layer 340, the first insulating layer 340 will fill the hollow structure of the first portion 501 and the hollow structure of the second portion 502; if the first portion 501 is a solid structure and the second portion 502 is a hollow structure, then the first insulating layer 340 will fill the hollow structure of the second portion 502.

[0078] In one specific embodiment, the three-dimensional memory further includes:

[0079] A second insulating layer 60 covering the stacked structure 30 and the source layer 10;

[0080] The first contact 70 passes through the second insulating layer 60 and is connected to the gate layer 301 of the stacked structure 30.

[0081] In this application, by setting the first contact 70, the gate layer 301 can be connected to other structures through the first contact 70.

[0082] In one specific embodiment, the three-dimensional memory further includes:

[0083] Interconnect structure 80 is located on the side of stacked structure 30 opposite to source layer 10, and interconnect structure 80 is electrically connected to channel structure 40. It is understood that interconnect structure 80 is also formed within second insulating layer 60. Interconnect structure 80 includes pads, conductive channels, and wiring connected in sequence. The pads are connected to channel structure 40, and the wiring is electrically connected to other structures of the 3D memory, such as the peripheral circuitry 90 described below.

[0084] In one specific embodiment, the three-dimensional memory further includes:

[0085] The peripheral circuit 90 is located on the side of the interconnect structure 80 away from the stacked structure 30 and is electrically connected to the interconnect structure 80.

[0086] The peripheral circuit 90 includes: a peripheral substrate 902, a peripheral device 903 disposed on the peripheral substrate 902, and a dielectric layer 904 covering the peripheral device 903. In this application, the peripheral circuit 90 supplies power to the channel structure 40 through the interconnect structure 80.

[0087] The following will introduce four specific structures of three-dimensional memory.

[0088] The first type:

[0089] Please see Figures 24-26 The three-dimensional memory also includes:

[0090] The second contact 610 extends through the second insulating layer 60 into the source layer 10; the material of the second contact 610 can be silver (Ag).

[0091] The first lead-out contact 620 extends through the first insulating layer 340 and through the first semiconductor layer 50 within the source layer 10, wherein the second contact 610 is connected to the first lead-out contact 620; the material of the first lead-out contact 620 may be silver (Ag).

[0092] The source contact 630 extends through the first insulating layer and through the first semiconductor layer 50 within the source layer 10 and is connected to the source layer 10; the source contact 630 may be made of silver (Ag).

[0093] The first bridging layer 640 is located on the side of the first insulating layer 340 opposite to the first semiconductor layer 50, and connects the first lead-out contact 620 and the source contact 630. The material of the first bridging layer 640 may be silver (Ag).

[0094] It is understood that the source contact 630, the first bridging layer 640, the first lead-out contact 620, and the second contact 610 form a connection path. The first bridging layer 640 is mainly used to transmit the potential supplied to the source layer 10 to the source layer 10 through the first bridging layer 640, the first lead-out contact 620, the second contact 610, and the source contact 630 that overlaps with the source layer 10.

[0095] In this method, the three-dimensional memory also includes:

[0096] The third contact 650 extends through the second insulating layer 60 into the source layer 10;

[0097] The second lead-out contact 660 extends through the first insulating layer and through the first semiconductor layer 50 within the source layer 10, wherein the third contact 650 is connected to the second lead-out contact 660.

[0098] This method also includes a first lead-out layer 130, located on the side of the first insulating layer 340 away from the first semiconductor layer 50, and connected to the third contact 650 through the second lead-out contact 660.

[0099] Thus, the first lead-out layer 130 can lead out the three-dimensional memory, and the first bridging layer 640 can connect the internal structure of the three-dimensional memory.

[0100] The second type:

[0101] Please see Figure 27 The three-dimensional memory also includes:

[0102] The connecting contact 710 extends through the second insulating layer 60 and into the connecting layer 204, where it connects. The material of the connecting contact 710 can be silver (Ag).

[0103] It is understandable that the first semiconductor layer 50, the interconnect layer 204, and the interconnect contact 710 form an interconnection path.

[0104] In this method, the three-dimensional memory also includes:

[0105] The third contact 650 extends through the second insulating layer 60 into the source layer 10;

[0106] The second lead-out contact 660 extends through the first insulating layer and through the first semiconductor layer 50 within the source layer 10, wherein the third contact 650 is connected to the second lead-out contact 660.

[0107] This method also includes a first lead-out layer 130, located on the side of the first insulating layer 340 away from the first semiconductor layer 50, and connected to the third contact 650 through the second lead-out contact 660.

[0108] Thus, the first lead-out layer 130 can lead out the three-dimensional memory, and the contact point 710 can connect the internal structure of the three-dimensional memory.

[0109] The third type differs from the first type in that:

[0110] Please see Figure 28 The three-dimensional memory of this method includes:

[0111] The fourth contact 670 extends through the dielectric layer 904 into the outer substrate 902;

[0112] The third lead-out contact 680 extends into the outer substrate 902 and is connected to the fourth contact 670.

[0113] It also includes a second lead-out layer 690, located on the side of the peripheral substrate 902 away from the peripheral device 903, and connected to the fourth contact 670 through a third lead-out contact 680.

[0114] Thus, the second lead-out layer 690 can lead out the three-dimensional memory, and the first bridging layer 640 can connect the internal structure of the three-dimensional memory.

[0115] The fourth type differs from the second type in that:

[0116] Please see Figure 29 The three-dimensional memory of this method includes:

[0117] The fourth contact 670 extends through the dielectric layer 904 into the outer substrate 902;

[0118] The third lead-out contact 680 extends into the outer substrate 902 and is connected to the fourth contact 670.

[0119] It also includes a second lead-out layer 690, located on the side of the peripheral substrate 902 away from the peripheral device 903, and connected to the fourth contact 670 through a third lead-out contact 680.

[0120] Thus, the second lead-out layer 690 can lead out the three-dimensional memory, and the contact point 710 can connect the internal structure of the three-dimensional memory.

[0121] In addition to the three-dimensional memory described above, this application also provides a method for fabricating a three-dimensional memory.

[0122] Methods for fabricating three-dimensional memory include:

[0123] S1, please refer to Figure 13 The present invention provides a stacked source layer 10, a sacrificial layer 20 and a stacked structure 30, wherein the sacrificial layer 20 is located between the source layer 10 and the stacked structure 30, and the stacked structure 30 includes alternately stacked gate layers and interlayer insulating layers.

[0124] S2, forming a plurality of channel structures 40 that pass through the stacked structure 30 and through the sacrificial layer 20 and extend to the source layer 10;

[0125] S3, please refer to Figure 16 A via 300 is formed that penetrates the source layer 10 and the sacrificial layer 20, wherein the via 300 exposes the channel layer of the channel structure 40;

[0126] S4, please refer to Figure 17A first semiconductor layer 50 is formed on the wall of the via 300 and on the side of the source layer 10 away from the stacked structure 30, wherein the first semiconductor layer 50 is connected to the channel layer of the channel structure 40.

[0127] In this application, a via 300 is formed from the side of the source layer 10 facing away from the stacked structure 30. A first semiconductor layer 50 is formed on the wall of the via 300, and the first semiconductor layer 50 is connected to the channel layer of the channel structure 40. The first semiconductor layer 50 connects the channel layer of the channel structure 40 to the source layer 10, eliminating the need to form an epitaxial structure connecting the channel layer to the source layer 10 within the 3D memory, resulting in better electrical performance of the 3D memory. The formation method of the first semiconductor layer 50 in this application is simple, has a large process operation window, and is not limited by the number of layers in the stacked structure 30.

[0128] In one specific embodiment, the via 300 includes a first sub-via and a second sub-via communicating with the first sub-via;

[0129] The first sub-via is formed by the source layer 10 and the stacked structure 30; or, the first sub-via is formed by the stacked structure 30, the source layer 10 and the etched sacrificial layer 20.

[0130] The second sub-hole is located within the source layer 10.

[0131] It is understandable that during the formation of via 300, if the sacrificial layer 20 is completely etched away, the first sub-via is formed by the source layer 10 and the stacked structure 30; if the sacrificial layer 20 is partially etched away, the first sub-via is formed by the stacked structure 30, the source layer 10 and the etched sacrificial layer 20.

[0132] In this application, the provision of the sacrificial layer 20 facilitates the formation of vias 300 when the sacrificial layer 20 is removed, thereby facilitating the formation of the first semiconductor layer 50 within the vias 300.

[0133] In one specific embodiment, the sacrificial layer 20 includes a first oxide layer 201, a nitride layer 202, and a second oxide layer 203 sequentially disposed therefrom. The first oxide layer 201, the nitride layer 202, and the second oxide layer 203 are located between the source layer 10 and the stacked structure 30, with the first oxide layer 201 stacked with the source layer 10 and the second oxide layer 203 stacked with the stacked structure 30. It is understood that the exemplary material for the first oxide layer 201 and the second oxide layer 203 is silicon oxide, and the exemplary material for the nitride layer 202 is silicon nitride. The first oxide layer 201, the nitride layer 202, and the second oxide layer 203 form a silicon oxide-silicon nitride-silicon oxide (ONO) stacked structure. Understandably, via 300 can penetrate the first oxide layer 201, nitride layer 202, and second oxide layer 203, exposing the end faces of the first oxide layer 201, nitride layer 202, and second oxide layer 203. When the first semiconductor layer 50 is formed within the via 300, the first semiconductor layer 50 connects to the end faces of the first oxide layer 201, nitride layer 202, and second oxide layer 203. The first oxide layer 201, nitride layer 202, and second oxide layer 203 can support the first semiconductor layer 50, making the connection of the first semiconductor layer 50 more stable.

[0134] In this application, by setting a sacrificial layer 20 including a first oxide layer 201, a nitride layer 202 and a second oxide layer 203 arranged in sequence, the sacrificial layer 20 is easy to form and easy to etch away.

[0135] In one specific embodiment, “providing a stacked source layer 10, a sacrificial layer 20, and a stacked structure 30, wherein the sacrificial layer 20 is located between the source layer 10 and the stacked structure 30” includes:

[0136] A stacked source layer 10, a sacrificial layer 20, a connection layer 204, and a stacked structure 30 are provided, wherein the connection layer 204 is located between the sacrificial layer 20 and the stacked structure 30. Optionally, the connection layer 204 is located between the stacked structure 30 and a second oxide layer 203. It is understood that when the via 300 is formed, the via 300 exposes at least a portion of the surface of the connection layer 204, and when the first semiconductor layer 50 is formed within the via 300, a first portion 501 of the first semiconductor layer 50 is connected to the connection layer 204. The arrangement of the connection layer 204 can conduct a connection between the first semiconductor layer 50 and the internal structure of the three-dimensional memory.

[0137] Please see Figure 14 In one specific embodiment, "forming a via 300 penetrating the source layer 10 and the sacrificial layer 20, wherein the via 300 exposes the channel layer of the channel structure 40" includes:

[0138] Please see Figure 15A first initial via 440 is formed on the source layer 10 and the sacrificial layer 20, wherein the first initial via 440 exposes the nitride layer 202;

[0139] Selectively etch the nitride layer 202 to enlarge the first initial via 440 into a second initial via 450, wherein the second initial via 450 exposes the memory film layer of the channel structure 40;

[0140] The memory film layer exposed by the second initial via 300 is etched to expose the channel layer of the channel structure 40. It is understood that the source layer 10, the first oxide layer 201, and the nitride layer 202 are made of different materials and have different etching ratios.

[0141] In this application, a first initial via 440 is first formed, then the first initial via 440 is expanded into a second initial via 450, and finally the memory film layer exposed by the second initial via 450 is etched. The appropriate etchant can be selected according to the etching requirements to improve the etching efficiency.

[0142] In one specific embodiment, "etching the memory film layer exposed by the second initial via 450" includes:

[0143] When etching the memory film, the first oxide layer 201 and the second oxide layer 203 are etched to enlarge the second initial via 450 into via 300.

[0144] It is understandable that the etching ratios of the first oxide layer 201, the second oxide layer 203 and the memory film are similar. In this application, the first oxide layer 201 and the second oxide layer 203 are etched simultaneously when etching the memory film. As a result, the volume of the via 300 formed by the expansion of the second initial via 450 is larger, the formation area of ​​the first semiconductor layer 50 is larger, and the connection area between the first semiconductor layer 50 and the channel layer is larger, thereby improving the electrical performance of the three-dimensional memory.

[0145] In one specific embodiment, after etching the memory film layer, the fabrication method further includes:

[0146] The first oxide layer 201 and the second oxide layer 203 are etched to enlarge the second initial via 450 into via 300.

[0147] It is understandable that the etching ratios of the first oxide layer 201, the second oxide layer 203 and the memory film are different. In this application, the first oxide layer 201 and the second oxide layer 203 are not etched when etching the memory film. After the memory film is etched, the first oxide layer 201 and the second oxide layer 203 are etched. In this way, the etching processes of the memory film and the first oxide layer 201 and the second oxide layer 203 do not affect each other, and the size of the via 300 can be better controlled, and the first semiconductor layer 50 can be set as needed.

[0148] Please see Figure 16 In one specific embodiment, "etching the second oxide layer 203" includes:

[0149] The second oxide layer 203 is etched so that the via 300 exposes the interconnect layer 204;

[0150] "Forming a first semiconductor layer 50 on the wall of via 300" includes:

[0151] When the first semiconductor layer 50 is formed, the first semiconductor layer 50 is connected to the interconnect layer 204.

[0152] It is understandable that during the etching process of the second oxide layer 203, the structure of the second oxide layer 203 facing the interconnect layer 204 needs to be etched away to expose the interconnect layer 204, so as to facilitate the subsequent connection of the interconnect layer 204 with the first semiconductor layer 50.

[0153] It is understood that the methods for forming the stacked source layer 10, sacrificial layer 20, interconnect layer 204, and stacked structure 30 include:

[0154] Substrate 280 is provided;

[0155] Please see Figure 1 A first sacrificial oxide layer 290, a first sacrificial nitride layer 310, a second sacrificial oxide layer 320, and a source layer 10 are sequentially formed on a substrate 280.

[0156] Please see Figure 2 A first oxide layer 201, a nitride layer 202, and a second oxide layer 203 are formed on the source layer 10.

[0157] Please see Figure 3 A connecting layer 204 is formed on the second oxide layer 202;

[0158] Please see Figure 4 A stacked structure 30 is formed on the interconnect layer 204, and a channel structure 40 extending to the source layer 10 is formed on the stacked structure 30; the stacked structure 30 includes alternating stacked interlayer insulating layers and gate sacrificial layers 20.

[0159] Please see Figure 5 The ends of the stacked structure 30 are etched to form a stepped structure, and a second insulating layer 60 is formed on the etched stacked structure 30, the sacrificial layer 20 and the source layer 10.

[0160] Please see Figure 6 Gate trenches 330 are formed between the channel structures 40;

[0161] Please see Figure 7 The gate sacrificial layer 20 is removed by using the gate trench 330 as the entry point;

[0162] Please see Figure 8 A gate layer 301 is formed at the position corresponding to the gate sacrificial layer 20;

[0163] Please see Figure 9 , fill gate trench 330;

[0164] Please see Figure 10 A first contact 70 is formed on the second insulating layer 60, passing through the second insulating layer 60, and the first contact 70 is connected to the gate layer 301. A second contact 610 is formed on the second insulating layer 60, extending into the source layer 10.

[0165] Please see Figure 11 An interconnect structure 80 is formed on the side of the stacked structure 30 away from the source layer 10, wherein the interconnect structure 80 is electrically connected to the channel structure 40.

[0166] Please see Figure 12 A peripheral circuit 90 is formed on the side of the interconnect structure 80 away from the stacked structure 30, wherein the peripheral circuit 90 is electrically connected to the interconnect structure 80; the peripheral circuit 90 includes: a peripheral substrate 902, a peripheral device 903 disposed on the peripheral substrate 902, and a dielectric layer 904 covering the peripheral device 903 and the peripheral substrate 902.

[0167] Please see Figure 13 Remove the substrate 280, the first sacrificial oxide layer 290, the first sacrificial nitride layer 310, and the second sacrificial oxide layer 320.

[0168] Please see Figure 18 In one specific embodiment, after forming the first semiconductor layer 50, the fabrication method further includes:

[0169] A first insulating layer 340 is formed on the side of the first semiconductor layer 50 opposite to the source layer 10, and the first insulating layer 340 fills the hollow structure of the first semiconductor layer 50. It is understood that filling the hollow structure of the first semiconductor layer 50 with the first insulating layer 340 can make the three-dimensional memory structure flat.

[0170] In this application, by setting the first contact 770, the gate layer 301 can be connected to other structures through the first contact 770. The peripheral circuit 90 supplies power to the channel structure 40 through the interconnect structure 80.

[0171] The following will introduce the specific methods for forming a three-dimensional memory.

[0172] The first type:

[0173] In one specific embodiment, after forming the peripheral circuit 90, the fabrication method further includes:

[0174] A first lead-out contact 620 is formed on the first insulating layer 340 and the first semiconductor layer 50, wherein the first lead-out contact 620 extends within the source layer 10 and is connected to a second contact 610; and

[0175] Source contacts 630 are formed on the first insulating layer 340 and the first semiconductor layer 50, wherein the source contacts 630 are connected to the source layer 10;

[0176] A first bridging layer 640 is formed on the side of the first insulating layer 340 away from the first semiconductor layer 50, wherein the first bridging layer 640 connects the first lead-out contact 620 and the source contact 630.

[0177] It is understood that the source contact 630, the first bridging layer 640, the first lead-out contact 620, and the second contact 610 form a connection path. The first bridging layer 640 is mainly used to transfer the potential applied to the source layer to the source layer 10 through the first bridging layer 640, the first lead-out contact 620, the second contact 610, and the source contact 630 that overlaps with the source layer.

[0178] In this approach, the fabrication method of the three-dimensional memory also includes:

[0179] A third contact 650 is formed on the second insulating layer 60, wherein the third contact 650 extends into the source layer 10;

[0180] A second lead-out contact 660 is formed on the first insulating layer 340 and through the first semiconductor layer 50, wherein the second lead-out contact 660 extends into the source layer 10 and is connected to the third contact 650.

[0181] In this method, the preparation method further includes: a first lead-out layer 130 on the side of the first insulating layer 340340 away from the first semiconductor layer 50, the first lead-out layer 130 being connected to a third contact 650 through a second lead-out contact 660.

[0182] Thus, the first lead-out layer 130 can lead out the three-dimensional memory, and the first bridging layer 640 can connect the internal structure of the three-dimensional memory.

[0183] The second type:

[0184] In the fabrication methods of three-dimensional memory,

[0185] "Forming a first contact 70 through the second insulating layer 60 on the second insulating layer 60" includes:

[0186] When the first contact 70 is formed, a connecting contact 710 is formed, wherein the connecting contact 710 extends through the second insulating layer 60 and into the connecting layer 204 and is connected to the connecting layer 204.

[0187] In this approach, the fabrication method of the three-dimensional memory also includes:

[0188] A third contact 650 is formed on the second insulating layer 60, wherein the third contact 650 extends into the source layer 10;

[0189] A second lead-out contact 660 is formed on the first insulating layer 340 and through the first semiconductor layer 50, wherein the second lead-out contact 660 extends into the source layer 10 and is connected to the third contact 650.

[0190] In this method, the preparation method further includes: a first lead-out layer 130 on the side of the first insulating layer 340340 away from the first semiconductor layer 50, the first lead-out layer 130 being connected to a third contact 650 through a second lead-out contact 660.

[0191] Thus, the first lead-out layer 130 can lead out the three-dimensional memory, and the contact point 710 can connect the internal structure of the three-dimensional memory.

[0192] The third type differs from the first type in that:

[0193] The method for fabricating the three-dimensional memory in this approach includes:

[0194] A fourth contact 670 is formed on the dielectric layer 904, wherein the fourth contact 670 extends into the peripheral substrate 902;

[0195] A third lead-out contact 680 is formed on the peripheral substrate 902, wherein the third lead-out contact 680 is connected to the fourth contact 670.

[0196] In this approach, the fabrication method of the three-dimensional memory also includes:

[0197] A second lead-out layer 690 is formed on the side of the peripheral substrate away from the peripheral device. The second lead-out layer 690 is connected to the fourth contact 670 through a third lead-out contact 680.

[0198] Thus, the second lead-out layer 690 can lead out the three-dimensional memory, and the first bridging layer 640 can connect the internal structure of the three-dimensional memory.

[0199] The fourth method differs from the second method in that:

[0200] The method for fabricating the three-dimensional memory in this approach includes:

[0201] A fourth contact 670 is formed on the dielectric layer 904, wherein the fourth contact 670 extends into the peripheral substrate 902;

[0202] A third lead-out contact 680 is formed on the peripheral substrate 902, wherein the third lead-out contact 680 is connected to the fourth contact 670.

[0203] In this approach, the fabrication method of the three-dimensional memory also includes:

[0204] A second lead-out layer 690 is formed on the side of the peripheral substrate 902 away from the peripheral device 903. The second lead-out layer 690 is connected to the fourth contact 670 through the third lead-out contact 680.

[0205] Thus, the second lead-out layer 690 can lead out the three-dimensional memory, and the contact point 710 can connect the internal structure of the three-dimensional memory.

[0206] It is understandable that, before forming the aforementioned lead-out contacts (first lead-out contact 620, second lead-out contact 660, and third lead-out contact 680), a spacer layer 540 is first formed on the sidewall of the lead-out hole 510 for forming the lead-out contacts. For example, the lead-out hole 510 can be formed on the first insulating layer 340, the first semiconductor layer 50, and the source layer 10. Figure 19 The lead-out hole 510 exposes the corresponding contact, and an initial spacer layer 530 is formed between the lead-out hole 510 and the first insulating layer 340. Figure 20 ); Etch the initial spacer layer 530 to form the spacer layer 540 on the sidewall of the lead-out hole 510 ( Figure 21 ).

[0207] It is understandable that, when forming the lead-out contacts, a full-layer lead-out contact layer 520 can be formed on the first insulating layer 340. Figure 22 The lead-out contact layer 520 is connected to the lead-out contact, and then the lead-out contact layer 520 on the first insulating layer 340 is removed. Figure 23 ).

[0208] The above-disclosed embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the invention. Those skilled in the art will understand that implementing all or part of the above-described embodiments and making equivalent changes in accordance with the claims of the present invention are still within the scope of the invention.

Claims

1. A three-dimensional memory, comprising: The three-dimensional memory comprises a first source layer, a stack structure and a first semiconductor layer, the first semiconductor layer comprises a first part and a second part connected with the first part, and the stack structure comprises gate layers and interlayer insulating layers which are alternately stacked; A channel structure passes through the stack structure and extends to the source layer, and the source layer is formed with a via hole; A peripheral circuit is electrically connected to the channel structure, and the peripheral circuit and the first semiconductor layer are respectively located on opposite sides of the stack structure; The first part is located between the source layer and the stack structure, and is connected with a channel layer of the channel structure, the second part comprises a first sub-part and a second sub-part connected with the first sub-part, the first sub-part is located on a side of the source layer away from the stack structure, and the second sub-part is located on a hole wall of the via hole. The three-dimensional memory comprises a first oxide layer, a nitride layer and a second oxide layer which are sequentially arranged, the first oxide layer, the nitride layer and the second oxide layer are located between the source layer and the stack structure, and the first oxide layer is stacked with the source layer, and the second oxide layer is stacked with the stack structure; end faces of the first oxide layer, the nitride layer and the second oxide layer are connected with an end face of the first part.

2. The three-dimensional memory of claim 1, wherein, The three-dimensional memory further comprises a connecting layer connected between the stack structure and the source layer, the channel structure penetrates through the connecting layer, and the first part of the first semiconductor layer is connected with the connecting layer.

3. The three-dimensional memory of claim 1, wherein, The first part is a hollow structure or a solid structure; and / or, a structure penetrating through the source layer of the second part is a hollow structure or a solid structure.

4. The three-dimensional memory of claim 1, wherein, A plurality of gaps are arranged in the first part; and / or, a plurality of gaps are arranged in the structure penetrating through the source layer of the second part.

5. The three-dimensional memory of claim 1, wherein, The three-dimensional memory further comprises:

6. The three-dimensional memory of claim 4, wherein, A first insulating layer is located on a side of the first semiconductor layer away from the source layer, and the first insulating layer fills the hollow structure of the first part and the hollow structure of the second part. The three-dimensional memory further comprises:

7. The three-dimensional memory as recited in claim 6, further comprising, A second insulating layer covers the stack structure and the source layer; A first contact passes through the second insulating layer and is connected with a gate layer of the stack structure; An interconnection structure is located on a side of the stack structure away from the source layer, and the interconnection structure is electrically connected with the channel structure; The peripheral circuit is located on a side of the interconnection structure away from the stack structure, and is electrically connected with the interconnection structure; The peripheral circuit comprises a peripheral substrate, a peripheral device arranged on the peripheral substrate, and a dielectric layer covering the peripheral device and the peripheral substrate. The three-dimensional memory further comprises:

8. The three-dimensional memory as recited in claim 7, further comprising, A second contact penetrates through the second insulating layer and extends into the source layer; A first lead-out contact penetrates through the first insulating layer and the first semiconductor layer and extends into the source layer, wherein the second contact is connected with the first lead-out contact; A source contact penetrates through the first insulating layer and the first semiconductor layer and extends into the source layer, and is connected with the source layer; ​ A first bridge layer is located on a side of the first insulating layer away from the first semiconductor layer, and connects the first lead-out contact and the source contact.

9. The three-dimensional memory as recited in claim 7, further comprising, The three-dimensional memory further comprises: A connection contact extends into the connection layer through the second insulating layer.

10. The three-dimensional memory as claimed in claim 8 or 9, wherein, The three-dimensional memory further comprises: A third contact extends into the source layer through the second insulating layer. A second lead-out contact extends into the source layer through the first insulating layer and through the first semiconductor layer, wherein the third contact and the second lead-out contact are connected respectively.

11. The three-dimensional memory as claimed in claim 8 or 9, wherein, The three-dimensional memory further comprises: A fourth contact extends into the peripheral substrate through the dielectric layer. A third lead-out contact extends into the peripheral substrate and is connected with the fourth contact.

12. The three-dimensional memory of claim 1, wherein, The source layer is an N-type doped semiconductor layer, and the first semiconductor layer is an N-type doped semiconductor layer.

13. A method of making a three-dimensional memory, comprising: Comprise: A stacked source layer, a sacrificial layer and a stacked structure are provided, wherein the sacrificial layer is located between the source layer and the stacked structure, and the stacked structure comprises alternately stacked gate layers and interlayer insulating layers; A plurality of channel structures extending through the stacked structure and through the sacrificial layer and to the source layer are formed; A via hole is formed through the source layer and the sacrificial layer, wherein the via hole exposes a channel layer of the channel structure; A first semiconductor layer is formed on a side of the via hole away from the source layer and on a side of the source layer away from the stacked structure, wherein the first semiconductor layer is connected with the channel layer of the channel structure; After the stacked structure is formed, the preparation method further comprises: A second insulating layer covering the stacked structure, the sacrificial layer and the source layer is formed; A first contact is formed on the second insulating layer and extending through the second insulating layer, wherein the first contact is connected with the gate layer of the stacked structure; An interconnection structure is formed on a side of the stacked structure away from the source layer, wherein the interconnection structure is electrically connected with the channel structure; A peripheral circuit is formed on a side of the interconnection structure away from the stacked structure, wherein the peripheral circuit is electrically connected with the interconnection structure, and the peripheral circuit and the first semiconductor layer are located on opposite sides of the stacked structure respectively; the peripheral circuit comprises a peripheral source layer, a peripheral device on the peripheral source layer and a dielectric layer covering the peripheral device and the peripheral source layer.

14. The method of claim 13, wherein, The via hole comprises a first sub-hole and a second sub-hole in communication with the first sub-hole; The first sub-hole is surrounded by the source layer and the stacked structure; Alternatively, the first sub-hole is surrounded by the stacked structure, the source layer and the etched sacrificial layer; The second sub-hole is located in the source layer.

15. The preparation method according to claim 13, characterized in that, The sacrificial layer comprises a first oxide layer, a nitride layer and a second oxide layer arranged in sequence, the first oxide layer, the nitride layer and the second oxide layer are located between the source layer and the stacked structure, and the first oxide layer is stacked with the source layer, and the second oxide layer is stacked with the stacked structure.

16. The method of claim 15, wherein, "providing a stack of a source layer, a sacrificial layer, and a stack structure, wherein the sacrificial layer is between the source layer and the stack structure" includes: providing a stack of a source layer, a sacrificial layer, a connection layer, and a stack structure, wherein the connection layer is between the sacrificial layer and the stack structure.

17. The preparation method according to claim 16, characterized in that, "forming a via through the source layer and the sacrificial layer, wherein the via exposes a channel layer of the channel structure" includes: forming a first initial via on the source layer and the sacrificial layer, wherein the first initial via exposes the nitride layer; selectively etching the nitride layer to enlarge the first initial via to a second initial via, wherein the second initial via exposes a memory film layer of the channel structure; etching the memory film layer exposed by the second initial via to expose a channel layer of the channel structure.

18. The method of claim 17, wherein, "etching the memory film layer exposed by the second initial via" includes: when etching the memory film layer, etching the first oxide layer and the second oxide layer to enlarge the second initial via to the via.

19. The method of claim 17, wherein, after etching the memory film layer, the preparation method further includes: etching the first oxide layer and the second oxide layer to enlarge the second initial via to the via.

20. The method of manufacturing according to claim 18 or 19, wherein, "etching the second oxide layer" includes: etching the second oxide layer such that the via exposes the connection layer; "forming a first semiconductor layer on a hole wall of the via" includes: when forming the first semiconductor layer, the first semiconductor layer is connected with the connection layer.

21. The method of claim 20, wherein, after forming the first semiconductor layer, the preparation method further includes: forming a first insulating layer on a side of the first semiconductor layer away from the source layer, and such that the first insulating layer fills a hollow structure of the first semiconductor layer.

22. The method of claim 21, wherein, after forming the peripheral circuit, the preparation method further includes: forming a second contact on the second insulating layer, the second contact extending into the source layer; forming a first lead-out contact on the first insulating layer and the first semiconductor layer, wherein the first lead-out contact extends into the source layer and is connected with the second contact; and forming a source contact on the first insulating layer and the first semiconductor layer, wherein the source contact is connected with the source layer; forming a first bridge layer on a side of the first insulating layer away from the first semiconductor layer, wherein the first bridge layer connects the first lead-out contact and the source contact.

23. The preparation method according to claim 21, characterized in that, "forming a first contact on the second insulating layer, the first contact extending through the second insulating layer" includes: when forming the first contact, forming a connection contact, wherein the connection contact extends through the second insulating layer into the connection layer and is connected with the connection layer.

24. The method of manufacturing according to claim 22 or 23, wherein, the preparation method further includes: forming a third contact on the second insulating layer, wherein the third contact extends into the source layer; forming a second lead-out contact on the first insulating layer and through the first semiconductor layer, wherein the second lead-out contact extends into the source layer and is connected with the third contact.

25. The method of manufacturing according to claim 22 or 23, wherein, the preparation method further includes: forming a fourth contact on the dielectric layer, wherein the fourth contact extends into the peripheral source layer; forming a third lead-out contact on the peripheral source layer, wherein the third lead-out contact is connected to the fourth contact.

Images