Display panel, preparation method thereof and display device

Abstract

The application discloses a display panel and a preparation method thereof and a display device, and relates to the technical field of display. In the display panel, the gate of the first thin film transistor in the first sub-pixel group and the gate of the second thin film transistor in the second sub-pixel group are connected with the first gate signal line. That is, the gate of the first thin film transistor in the first sub-pixel group and the gate of the second thin film transistor in the second sub-pixel group share the first gate signal line. Thus, the space of the display panel can be saved, the fingerprint identification area can be reserved, the display panel can realize the function of under-screen fingerprint identification, and the screen ratio of the display panel is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel, a preparation method thereof and a display device. BACKGROUND

[0002] The display panel comprises a substrate substrate, and a plurality of sub-pixels located on one side of the substrate substrate. Each sub-pixel comprises a pixel circuit and a light emitting unit, and the pixel circuit is used to drive the light emitting unit to emit light.

[0003] In the related art, the pixel circuit of the sub-pixel in the low temperature polycrystalline oxide (LTPO) display panel comprises at least one oxide thin film transistor (TFT). The pixel circuit of the sub-pixel in the low temperature poly silicon (LTPS) display panel comprises LTPS TFT. Since the oxide TFT can save power and reduce the power consumption of the display device compared with the LTPS TFT, the existing display panel is usually designed as an LTPO display panel.

[0004] However, the process of the LTPO display panel is relatively complex, and there are more signal lines, so it is difficult to reserve a fingerprint recognition area for placing a fingerprint recognition device, thereby the LTPO display panel cannot realize the function of fingerprint sensor on display, and the screen ratio of the LTPO display panel is low. SUMMARY

[0005] The present application provides a display panel, a preparation method thereof and a display device, which can solve the problem of low screen ratio of the display panel in the related art. The technical solution is as follows:

[0006] In one aspect, a display panel is provided, comprising:

[0007] a substrate substrate;

[0008] a plurality of sub-pixel groups located on one side of the substrate substrate and arranged along a first direction; each sub-pixel group comprises a plurality of sub-pixels arranged along a second direction, and the second direction intersects the first direction; each sub-pixel comprises a pixel circuit and a light emitting unit connected to the pixel circuit; and the pixel circuit of each sub-pixel comprises at least a first thin film transistor and a second thin film transistor;

[0009] The first thin film transistor in the first sub-pixel group and the second thin film transistor in the second sub-pixel group are connected with the first gate signal line.

[0010] Optionally, the first electrode of the first thin film transistor is connected with the first reset power supply line.

[0011] The first electrode of the second thin film transistor is connected with the data signal line.

[0012] Optionally, in the first direction, a first distance between the first thin film transistor in the first sub-pixel group and the second thin film transistor in the second sub-pixel group is smaller than a second distance between the first thin film transistor in the first sub-pixel group and other thin film transistors in the second sub-pixel group except the second thin film transistor.

[0013] Optionally, there are a first sub-pixel and a second sub-pixel adjacent to each other in each sub-pixel group.

[0014] The first sub-pixel and the second sub-pixel are symmetrically arranged.

[0015] Optionally, each pixel circuit further comprises a third thin film transistor; the first electrode of the third thin film transistor in the first sub-pixel and the first electrode of the third thin film transistor in the second sub-pixel are connected with the driving power supply line through a first connecting part.

[0016] In the second direction, a third distance between the third thin film transistor in the first sub-pixel and the third thin film transistor in the second sub-pixel is smaller than a fourth distance between the third thin film transistor in the first sub-pixel and other thin film transistors in the second sub-pixel except the third thin film transistor.

[0017] Optionally, each pixel circuit further comprises a fourth thin film transistor; each sub-pixel group has a third sub-pixel adjacent to the first sub-pixel, and the third sub-pixel is located on a side of the first sub-pixel away from the second sub-pixel.

[0018] The first electrode of the fourth thin film transistor in the first sub-pixel and the first electrode of the fourth thin film transistor in the third sub-pixel are connected with the second reset power supply line through a second connecting part.

[0019] In the second direction, a fifth distance between the fourth thin film transistor in the first sub-pixel and the fourth thin film transistor in the third sub-pixel is smaller than a sixth distance between the fourth thin film transistor in the first sub-pixel and other thin film transistors in the third sub-pixel except the fourth thin film transistor.

[0020] Optionally, the pixel circuit of each of the sub-pixels further comprises a fifth thin film transistor, a sixth thin film transistor and a seventh thin film transistor.

[0021] The second electrode of the first thin film transistor is connected with the light emitting unit.

[0022] The second electrode of the second thin film transistor is connected with the first node.

[0023] The gate electrode of the third thin film transistor is connected with a light emitting control signal line, the first electrode of the third thin film transistor is connected with a driving power supply line, and the second electrode of the third thin film transistor is connected with the first node.

[0024] The gate electrode of the fourth thin film transistor is connected with a reset signal line, the first electrode of the fourth thin film transistor is connected with a second reset power supply line, and the second electrode of the fourth thin film transistor is connected with the second node.

[0025] The gate electrode of the fifth thin film transistor is connected with the light emitting control signal line, the first electrode of the fifth thin film transistor is connected with a third node, and the second electrode of the fifth thin film transistor is connected with the light emitting unit.

[0026] The gate electrode of the sixth thin film transistor is connected with a second gate electrode signal line, the first electrode of the sixth thin film transistor is connected with the third node, and the second electrode of the sixth thin film transistor is connected with the second node.

[0027] The gate electrode of the seventh thin film transistor is connected with the second node, the first electrode of the seventh thin film transistor is connected with the first node, and the second electrode of the seventh thin film transistor is connected with the third node.

[0028] Optionally, the fourth thin film transistor and the sixth thin film transistor are oxide thin film transistors.

[0029] The first thin film transistor, the second thin film transistor, the third thin film transistor, the fifth thin film transistor and the seventh thin film transistor are low temperature polysilicon thin film transistors.

[0030] Optionally, the fourth thin film transistor and the sixth thin film transistor are N-type transistors.

[0031] The first thin film transistor, the second thin film transistor, the third thin film transistor, the fifth thin film transistor and the seventh thin film transistor are P-type transistors.

[0032] Optionally, the display panel comprises, in sequence from the side of the substrate away, an active layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, a buffer layer, an oxide layer, a third gate insulating layer, a third gate layer, an interlayer dielectric layer, a first source-drain layer, a passivation layer, a first planarization layer, and a second source-drain layer, which constitute the pixel circuit.

[0033] The display panel comprises, in sequence from the side of the substrate away, an anode layer, a pixel defining layer, a light-emitting layer, and a cathode layer, which constitute the light-emitting unit.

[0034] Optionally, the fourth thin-film transistor and the sixth thin-film transistor are composed of the second gate layer, the oxide layer, and the third gate layer.

[0035] The first thin-film transistor, the second thin-film transistor, the third thin-film transistor, the fifth thin-film transistor, and the seventh thin-film transistor are composed of the active layer, the first gate layer, and the first source-drain layer.

[0036] Optionally, the first gate signal line and the light-emitting control signal line are located in the first gate layer; the reset signal line and the second gate signal line are located in the third gate layer; the first reset power line and the second reset power line are located in the first source-drain layer; the data signal line is located in the second source-drain layer; and the driving power line is located in the first source-drain layer and the second source-drain layer.

[0037] Optionally, the pixel circuit of each of the sub-pixels further comprises a storage capacitor.

[0038] One end of the storage capacitor is connected to the driving power line, and the other end of the storage capacitor is connected to the second node.

[0039] In another aspect, a method for manufacturing a display panel is provided, the method comprising:

[0040] providing a substrate;

[0041] forming a plurality of sub-pixel groups arranged in a first direction on one side of the substrate;

[0042] wherein each of the sub-pixel groups comprises a plurality of sub-pixels arranged in a second direction intersecting the first direction; each of the sub-pixels comprises a pixel circuit and a light-emitting unit connected to the pixel circuit; and the pixel circuit of each of the sub-pixels comprises at least a first thin-film transistor and a second thin-film transistor.

[0043] The first thin film transistor in the first sub-pixel group and the second thin film transistor in the second sub-pixel group share the first gate signal line.

[0044] In another aspect, a display device is provided, including a power supply component and the display panel of the above aspect.

[0045] The power supply component is configured to supply power to the display panel.

[0046] The technical solutions provided in the present application have at least the following beneficial effects:

[0047] The display panel provided in the present application has the following beneficial effects: the gate of the first thin film transistor in the first sub-pixel group and the gate of the second thin film transistor in the second sub-pixel group are connected to the first gate signal line, i.e., the gate of the first thin film transistor in the first sub-pixel group and the gate of the second thin film transistor in the second sub-pixel group share the first gate signal line. Thus, the space of the display panel can be saved, the fingerprint recognition area can be reserved, the display panel can realize the function of fingerprint recognition under the screen, and the screen ratio of the display panel can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0049] Figure 1 is a structural schematic diagram of a display panel provided in the present application;

[0050] Figure 2 is a local structural schematic diagram of a pixel circuit provided in the present application;

[0051] Figure 3 is an equivalent circuit diagram of a pixel circuit provided in the present application;

[0052] Figure 4 is a structural schematic diagram of an active layer and a first gate layer provided in the present application;

[0053] Figure 5 is Figure 2 is a local structural schematic diagram of an AA region;

[0054] Figure 6A timing diagram of each signal line in a pixel circuit is provided by the embodiment of the present application.

[0055] Figure 7 A Figure 2 A local structure schematic diagram of the BB region is provided by the embodiment of the present application.

[0056] Figure 8 A Figure 2 A local structure schematic diagram of the CC region is provided by the embodiment of the present application.

[0057] Figure 9 A cross-sectional view of a display panel is provided by the embodiment of the present application.

[0058] Figure 10 A flowchart of a preparation method of a display panel is provided by the embodiment of the present application.

[0059] Figure 11 A flowchart of another preparation method of a display panel is provided by the embodiment of the present application.

[0060] Figure 12 A schematic diagram of a light shielding layer is provided by the embodiment of the present application.

[0061] Figure 13 A schematic diagram of forming an active layer is provided by the embodiment of the present application.

[0062] Figure 14 A schematic diagram of forming a first gate layer is provided by the embodiment of the present application.

[0063] Figure 15 A schematic diagram of forming a second gate layer is provided by the embodiment of the present application.

[0064] Figure 16 A schematic diagram of forming an oxide layer is provided by the embodiment of the present application.

[0065] Figure 17 A schematic diagram of forming a third gate layer is provided by the embodiment of the present application.

[0066] Figure 18 A schematic diagram of forming an interlayer dielectric layer is provided by the embodiment of the present application.

[0067] Figure 19 A schematic diagram of forming a first source-drain layer is provided by the embodiment of the present application.

[0068] Figure 20 A schematic diagram of forming a passivation layer is provided by the embodiment of the present application.

[0069] Figure 21 A schematic diagram of forming a first planarization layer is provided by the embodiment of the present application.

[0070] Figure 22 is a schematic diagram of forming a second source-drain layer provided by an embodiment of the present application;

[0071] Figure 23 is a schematic diagram of forming a second planar layer provided by an embodiment of the present application;

[0072] Figure 24 is a schematic diagram of forming an anode layer provided by an embodiment of the present application;

[0073] Figure 25 is a schematic diagram of forming a pixel defining layer provided by an embodiment of the present application;

[0074] Figure 26 is a structural schematic diagram of a display device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0075] In order to make the purpose, technical solutions and advantages of the present application more clear, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0076] The transistors adopted in all embodiments of the present application can be field effect tubes or other devices with the same characteristics, and the transistors adopted in the embodiments of the present application are mainly switching transistors according to the role in the circuit. Since the source and the drain of the switching transistor adopted here are symmetrical, the source and the drain can be interchangeable. In the embodiments of the present application, the source is referred to as the first pole and the drain is referred to as the second pole, or the drain is referred to as the first pole and the source is referred to as the second pole. According to the form in the drawings, the middle end of the transistor is defined as the gate, the signal input end is defined as the source, and the signal output end is defined as the drain. In addition, the switching transistor adopted in the embodiments of the present application can include any one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level and is turned off when the gate is at a high level, and the N-type switching transistor is turned on when the gate is at a high level and is turned off when the gate is at a low level. In addition, the plurality of signals in each embodiment of the present application correspond to an effective potential and an ineffective potential, and the effective potential and the ineffective potential only represent that the potential of the signal has two states, and do not represent that the effective potential or the ineffective potential in the full text has a specific value.

[0077] The terms used in the embodiments of the present application are for the purpose of describing particular embodiments only and are not intended to limit the present application. Unless otherwise defined, technical terms or scientific terms used in the embodiments of the present application shall have the ordinary meanings commonly used in the art to which the present application belongs. The terms "first", "second", "third", and the like used in the specification and the claims of the present application do not denote any order, quantity, or importance, but are used to distinguish different components. Similarly, the terms "one", "another", and the like do not denote a quantity of quantity limitation, but mean at least one. The terms "include", "comprise", and the like mean that the elements or objects before the "include" or "comprise" encompass the elements or objects listed after the "include" or "comprise" and equivalents thereof, and do not exclude other elements or objects. The terms "connected", "coupled", and the like do not mean only physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are used only to indicate relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0078] Figure 1 is a top view of a display panel provided by an embodiment of the present application. Referring to Figure 1 It can be seen that the display panel 10 can include a substrate 101, and a plurality of sub-pixel groups 102 located on one side of the substrate 101. The plurality of sub-pixel groups 102 can be arranged along a first direction X. Each sub-pixel group 102 includes a plurality of sub-pixels 1021 arranged along a second direction Y. The second direction Y intersects the first direction X. For example Figure 1 The second direction Y is perpendicular to the first direction X in the figure. The first direction X can be the pixel column direction of the display panel 10, and the second direction Y can be the pixel row direction of the display panel 10.

[0079] In an embodiment of the present application, each sub-pixel 1021 can include a pixel circuit a1 and a light-emitting unit a2 connected to the pixel circuit a1. The pixel circuit a1 can be used to drive the light-emitting unit a2 to emit light. Figure 2 is a partial structure schematic diagram of a pixel circuit provided by an embodiment of the present application. Figure 3 is an equivalent circuit diagram of a pixel circuit provided by an embodiment of the present application. In combination with Figure 2 and Figure 3 It can be seen that the pixel circuit a1 of each sub-pixel 1021 can include at least a first thin film transistor T1 and a second thin film transistor T2. In addition, in order to clearly show the area of the pixel circuit a1 of each sub-pixel 1021, Figure 4 only the relevant structures of the active layer b1 and the first gate layer b3 are shown.

[0080] Figure 5 is Figure 2 A schematic diagram of the local structure in the AA region. In combination with Figure 1 , Figure 2 , Figure 4 and Figure 5 It can be seen that there are adjacent first sub-pixel group 102a and second sub-pixel group 102b in the plurality of sub-pixel groups 102. The gate of the first thin film transistor T1 in the first sub-pixel group 102a is connected with the first gate signal line Gate1, and the gate of the second thin film transistor T2 in the second sub-pixel group 102b is connected with the first gate signal line Gate1. The first gate signal line Gate1 can provide signals for the gate of the first thin film transistor T1 in the first sub-pixel group 102a and the gate of the second thin film transistor T2 in the second sub-pixel group 102b.

[0081] That is, the gate of the first thin film transistor T1 in the first sub-pixel group 102a and the gate of the second thin film transistor T2 in the second sub-pixel group 102b are connected with the same first gate signal line Gate1. The display panel provided by the embodiment of the present application does not need to be provided with two gate signal lines to provide signals for the first thin film transistor T1 in the first sub-pixel group 102a and the second thin film transistor T2 in the second sub-pixel group 102b respectively.

[0082] In addition, the scheme of providing one first gate signal line Gate1 to connect the gate of the first thin film transistor T1 in the first sub-pixel group 102a and the gate of the second thin film transistor T2 in the second sub-pixel group 102b can save the space of the display panel compared with the scheme of providing two gate signal lines to connect the gate of the first thin film transistor T1 in the first sub-pixel group 102a and the gate of the second thin film transistor T2 in the second sub-pixel group 102b respectively. Further, the display panel 10 can reserve a fingerprint recognition area to set a fingerprint recognition device, so as to facilitate the display panel to realize the function of under-screen fingerprint recognition and improve the screen ratio of the display panel.

[0083] Among them, the fingerprint recognition area of the display panel 10 can be the area of the display panel 10 which is not provided with a thin film transistor and a signal line, for example Figure 2 the hollow white area m.

[0084] In summary, the display panel provided by the embodiment of the present application has the following advantages: in the first and second sub-pixel groups, the gate of the first thin film transistor in the first sub-pixel group and the gate of the second thin film transistor in the second sub-pixel group are connected to the first gate signal line, that is, the gate of the first thin film transistor in the first sub-pixel group and the gate of the second thin film transistor in the second sub-pixel group share the first gate signal line, thereby saving the space of the display panel, reserving a fingerprint recognition area, enabling the display panel to realize the function of fingerprint recognition under the screen, and improving the screen ratio of the display panel.

[0085] In the embodiment of the present application, referring to Figure 3 , the first electrode of the first thin film transistor T1 can be connected to the first reset power supply line Vinit1. The first electrode of the second thin film transistor T2 can be connected to the data signal line Data. That is, the first thin film transistor T1 can be a reset transistor in the pixel circuit a1, and the second thin film transistor T2 can be a data writing transistor in the pixel circuit a1.

[0086] Referring to Figure 4 , the first sub-pixel group 102a is located on the upper side of the second sub-pixel group 102b, and the gate of the reset transistor (the first thin film transistor T1) in the pixel circuit a1 of each sub-pixel 1021 in the first sub-pixel group 102a can share a first gate signal line Gate1 with the gate of the data writing transistor in the pixel circuit a1 of each sub-pixel 1021 in the second sub-pixel group 102b.

[0087] Referring to Figure 3 , the pixel circuit a1 of each sub-pixel 1021 can further include a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6, a seventh thin film transistor T7, and a storage capacitor Cst.

[0088] The second electrode of the first thin film transistor T1 can be connected to the light emitting unit a2.

[0089] The second electrode of the second thin film transistor T2 can be connected to the first node N1.

[0090] The gate of the third thin film transistor T3 can be connected to the light emitting control signal line EM, the first electrode of the third thin film transistor T3 can be connected to the driving power supply line VDD, and the second electrode of the third thin film transistor T3 can be connected to the first node N1. Since the gate of the third thin film transistor T3 is connected to the light emitting control signal line EM, the third thin film transistor T3 can also be referred to as a light emitting control transistor.

[0091] The gate of the fourth thin film transistor T4 can be connected with a reset signal line RST, the first electrode of the fourth thin film transistor T4 can be connected with a second reset power supply line Vinit2, and the second electrode of the fourth thin film transistor T4 can be connected with the second node N2. The fourth thin film transistor T4 can also be referred to as a reset transistor.

[0092] The gate of the fifth thin film transistor T5 can be connected with an emission control signal line EM, the first electrode of the fifth thin film transistor T5 can be connected with the third node N3, and the second electrode of the fifth thin film transistor T5 can be connected with the light emitting unit a2. Since the gate of the fifth thin film transistor T5 is connected with the emission control signal line EM, the fifth thin film transistor T5 can also be referred to as an emission control transistor.

[0093] The gate of the sixth thin film transistor T6 can be connected with a second gate signal line Gate2, the first electrode of the sixth thin film transistor T6 can be connected with the third node N3, and the second electrode of the sixth thin film transistor T6 can be connected with the second node N2. The sixth thin film transistor T6 can also be referred to as a compensation transistor.

[0094] The gate of the seventh thin film transistor T7 can be connected with the second node N2, the first electrode of the seventh thin film transistor T7 can be connected with the first node N1, and the second electrode of the seventh thin film transistor T7 can be connected with the third node N3. The seventh thin film transistor T7 can also be referred to as a drive transistor.

[0095] One end of the storage capacitor Cst can be connected with a drive power supply line VDD, and the other end of the storage capacitor Cst can be connected with the second node N2. Optionally, the storage capacitor Cst can include two capacitor plates Cst1 and Cst2. In the embodiment of the present application, the capacitor plate Cst1 can be referred to as one end, a first end, or a first storage capacitor electrode of the storage capacitor Cst, and the capacitor plate Cst2 can be referred to as the other end, a second end, or a second storage capacitor electrode of the storage capacitor Cst.

[0096] It can be known from the above embodiment that, in the embodiment of the present application, the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fifth thin film transistor T5, and the seventh thin film transistor T7 can all be P-type transistors. The fourth thin film transistor T4 and the sixth thin film transistor T6 can all be N-type transistors.

[0097] Optionally, each N-type transistor in the pixel circuit a1 can be an oxide thin film transistor, and each P-type transistor can be an LTPS thin film transistor. The oxide material can include indium gallium zinc oxide (IGZO), i.e., the oxide thin film transistor can be an IGZO thin film transistor. The pixel circuit a1 formed by the seven transistors can also be referred to as an LTPO pixel circuit a1. The display panel in which the pixel circuit is the LTPO pixel circuit a1 can be referred to as an LTPO display panel.

[0098] In the pixel circuit a1 shown in FIG. 1, the first potential is higher than the second potential. The driving principle of the pixel circuit a1 of the 2n-th row of sub-pixels according to the embodiments of the present application is described as follows. Figure 3 Figure 6 is a timing diagram of the signal lines in the pixel circuit according to the embodiments of the present application. As shown in FIG. 2, the first potential is higher than the second potential. Figure 6

[0099] In the initialization phase t1, the potential of the reset signal provided by the reset signal line RST, the potential of the first gate drive signal provided by the first gate signal line Gate1(2n), the potential of the first gate drive signal provided by the first gate signal line Gate1(2n+1), and the potential of the emission control signal provided by the emission control signal line EM(2n) are all the first potential. The potential of the second gate drive signal provided by the second gate signal line Gate2(2n) and the potential of the data signal provided by the data signal line Data are both the second potential. Correspondingly, the fourth thin film transistor T4 is turned on. The first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fifth thin film transistor T5, and the sixth thin film transistor T6 are all turned off. In this way, the reset power signal of the second potential provided by the first reset power line Vinit1 can be transmitted to the second node N2 through the turned-on fourth thin film transistor T4, so as to reset the second node N2, and the seventh thin film transistor T7 is turned off.

[0100] ​​In the compensation stage t2, the potential of the reset signal provided by the reset signal line RST, the potential of the first gate drive signal provided by the first gate signal line Gate1(2n) and the potential of the first gate drive signal provided by the first gate signal line Gate1(2n+1) all jump to the second potential, the potential of the second gate drive signal provided by the second gate signal line Gate2(2n) and the potential of the data signal provided by the data signal line Data all jump to the first potential, and the potential of the light-emitting control signal provided by the light-emitting control signal line EM(2n) remains the first potential. Under the bootstrap action of the storage capacitor Cst, the potential of the second node N2 remains the second potential. Correspondingly, the first thin-film transistor T1, the second thin-film transistor T2, the sixth thin-film transistor T6 and the seventh thin-film transistor T7 are all turned on, and the third thin-film transistor T3, the fourth thin-film transistor T4 and the fifth thin-film transistor T5 are all turned off. In this way, the data signal of the first potential can be transmitted to the first node N1 through the turned-on second thin-film transistor T2, then transmitted to the third node N3 through the turned-on seventh thin-film transistor T7, and the sixth thin-film transistor T6 adjusts the potential of the second node N2 based on the potential of the third node N3. In addition, the reset power signal of the second potential provided by the second reset power line Vinit2 can be transmitted to the light-emitting unit a2 through the turned-on first thin-film transistor T1, so as to reset the light-emitting unit a2.

[0101] In the compensation stage t2, the potential of the reset signal provided by the reset signal line RST, the potential of the first gate drive signal provided by the first gate signal line Gate1(2n) and the potential of the first gate drive signal provided by the first gate signal line Gate1(2n+1) all jump to the second potential, the potential of the second gate drive signal provided by the second gate signal line Gate2(2n) and the potential of the data signal provided by the data signal line Data all jump to the first potential, and the potential of the light-emitting control signal provided by the light-emitting control signal line EM(2n) remains the first potential. Under the bootstrap action of the storage capacitor Cst, the potential of the second node N2 remains the second potential. Correspondingly, the first thin-film transistor T1, the second thin-film transistor T2, the sixth thin-film transistor T6 and the seventh thin-film transistor T7 are all turned on, and the third thin-film transistor T3, the fourth thin-film transistor T4 and the fifth thin-film transistor T5 are all turned off. In this way, the data signal of the first potential can be transmitted to the first node N1 through the turned-on second thin-film transistor T2, then transmitted to the third node N3 through the turned-on seventh thin-film transistor T7, and the sixth thin-film transistor T6 adjusts the potential of the second node N2 based on the potential of the third node N3. In addition, the reset power signal of the second potential provided by the second reset power line Vinit2 can be transmitted to the light-emitting unit a2 through the turned-on first thin-film transistor T1, so as to reset the light-emitting unit a2.

[0102] It should be noted that the display panel 10 can include a plurality of first gate signal lines Gate1, and for the first thin film transistor T1 and the second thin film transistor T2 in the pixel circuit a1 of the first sub-pixel 1021, the first gate signal line Gate1 connected to the first thin film transistor T1 and the second thin film transistor T2 is different from the first gate signal line Gate1 in the display panel.

[0103] For example, the first thin film transistor T1 can share one first gate signal line Gate1 with the second thin film transistor T2 in the pixel circuit a1 of the first sub-pixel 1021, and the second thin film transistor T2 can share another first gate signal line Gate1 with the first thin film transistor T1 in the pixel circuit a1 of the second sub-pixel 1021. Wherein, the sub-pixel 1021 can be located on the upper side of the first sub-pixel 1021 and on the lower side of the second sub-pixel 1021.

[0104] In the embodiments of the present application, it is referred to Figure 4 In the first direction X, the first distance between the first thin film transistor T1 in the first sub-pixel group 102a and the second thin film transistor T2 in the second sub-pixel group 102b is less than the second distance between the first thin film transistor T1 in the first sub-pixel group 102a and other thin film transistors in the second sub-pixel group 102b except the second thin film transistor T2.

[0105] That is, the distance between the first thin film transistor T1 in the first sub-pixel group 102a and the second thin film transistor T2 in the second sub-pixel group 102b is small, so that the gate of the first thin film transistor T1 in the first sub-pixel group 102a and the gate of the second thin film transistor T2 in the second sub-pixel group 102b can be connected to the first gate signal line Gate1, so as to realize the sharing of the first gate signal line Gate1.

[0106] In the embodiments of the present application, it is referred to Figure 4 There are adjacent first sub-pixels 1021a and second sub-pixels 1021b in each sub-pixel group 102. The first sub-pixel 1021a can be symmetrically arranged with the second sub-pixel 1021b. For example, the first sub-pixel 1021a and the second sub-pixel 1021b are symmetrically arranged about a first axis, and the first axis can be an axis between a pattern constituting the first sub-pixel 1021a and a pattern constituting the second sub-pixel 1021b.

[0107] The first sub-pixel 1021a and the second sub-pixel 1021b are symmetrically arranged along the first axis, which can mean that each transistor in the first sub-pixel 1021a is symmetrically arranged with a corresponding transistor in the second sub-pixel 1021b along the first axis. For example, the first thin film transistor T1 in the first sub-pixel 1021a corresponds to the first thin film transistor T1 in the second sub-pixel 1021b, and the first thin film transistor T1 in the first sub-pixel 1021a is symmetrically arranged with the first thin film transistor T1 in the second sub-pixel 1021b along the first axis.

[0108] Referring to Figure 4 and Figure 7 The third thin film transistor T3 in the first sub-pixel 1021a corresponds to the third thin film transistor T3 in the second sub-pixel 1021b, and the third thin film transistor T3 in the first sub-pixel 1021a is symmetrically arranged with the third thin film transistor T3 in the second sub-pixel 1021b along the first axis. In addition, in the second direction Y, the third distance between the third thin film transistor T3 in the first sub-pixel 1021a and the third thin film transistor T3 in the second sub-pixel 1021b is less than the fourth distance between the third thin film transistor T3 in the first sub-pixel 1021a and other thin film transistors in the second sub-pixel 1021b except the third thin film transistor T3. That is, the distance between the third thin film transistor T3 in the first sub-pixel 1021a and the third thin film transistor T3 in the second sub-pixel 1021b is smaller.

[0109] Referring to Figure 8 The first electrode of the third thin film transistor T3 in the first sub-pixel 1021a and the first electrode of the third thin film transistor T3 in the second sub-pixel 1021b are both connected to the driving power supply line VDD through the first connection L1. That is, the driving power supply line VDD can provide signals for the third thin film transistor T3 in the first sub-pixel 1021a and the third thin film transistor T3 in the second sub-pixel 1021b through the same first connection L1.

[0110] Therefore, by making the third thin film transistor T3 in the first sub-pixel 1021a and the third thin film transistor T3 in the second sub-pixel 1021b adjacent to each other share one first connection L1, the space of the display panel can be further saved, and thus the fingerprint recognition area can be reserved.

[0111] Referring to Figure 4Each of the sub-pixel groups 102 has a third sub-pixel 1021c adjacent to the first sub-pixel 1021a, which is located on the side of the first sub-pixel 1021a away from the second sub-pixel 1021b. The first sub-pixel 1021a and the third sub-pixel 1021c are symmetrically arranged. For example, the first sub-pixel 1021a and the third sub-pixel 1021c are symmetrically arranged about a second axis, which can be an axis between a pattern constituting the first sub-pixel 1021a and a pattern constituting the third sub-pixel 1021c.

[0112] The first sub-pixel 1021a and the third sub-pixel 1021c being symmetrically arranged about the second axis can mean that each transistor in the first sub-pixel 1021a and a corresponding transistor in the third sub-pixel 1021c are symmetrically arranged about the second axis. For example, the fourth thin film transistor T4 in the first sub-pixel 1021a and the fourth thin film transistor T4 in the third sub-pixel 1021c correspond to each other, and the fourth thin film transistor T4 in the first sub-pixel 1021a and the fourth thin film transistor T4 in the second sub-pixel 1021b are symmetrically arranged about the second axis.

[0113] In the second direction Y, a fifth distance between the fourth thin film transistor T4 in the first sub-pixel 1021a and the fourth thin film transistor T4 in the third sub-pixel 1021c is smaller than a sixth distance between the fourth thin film transistor T4 in the first sub-pixel 1021a and other thin film transistors in the third sub-pixel 1021c except the fourth thin film transistor T4. That is, the distance between the fourth thin film transistor T4 in the first sub-pixel 1021a and the fourth thin film transistor T4 in the third sub-pixel 1021c is smaller.

[0114] Reference Figure 8 The first electrode of the fourth thin film transistor T4 in the first sub-pixel 1021a and the first electrode of the fourth thin film transistor T4 in the third sub-pixel 1021c are both connected to the second reset power line Vinit2 through the second connection L2. That is, the second reset power line Vinit2 can provide signals for the fourth thin film transistor T4 in the first sub-pixel 1021a and the fourth thin film transistor T4 in the third sub-pixel 1021c through the same second connection L2.

[0115] Therefore, by making the fourth thin film transistor T4 in the adjacent first sub-pixel 1021a and the fourth thin film transistor T4 in the third sub-pixel 1021c share one second connection L2, the space of the display panel 10 can be further saved, and thus the fingerprint recognition area can be reserved.

[0116] Figure 9 is a cross-sectional view of a display panel provided by an embodiment of the present application. Reference Figure 9As can be seen, the display panel can include, in order from the direction away from the substrate 101, an active layer b1, a first gate insulator (GI) b2, a first gate layer b3, a second gate insulator b4, a second gate layer b5, a third gate insulator b6, an oxide layer b7, a fourth gate insulator b8, a third gate layer b9, an inter level dielectric (ILD) b10, a first source-drain layer b11, a passivation layer (PVX) b12, a first planarization layer (PLN) b13, and a second source-drain layer b14, which constitute the pixel circuit a1.

[0117] Also, referring to Figure 9 The display panel 10 can further include, in order from the direction away from the substrate 101, an anode layer c1, a pixel definition layer (PDL) c2, a light-emitting layer c3, and a cathode layer c4, which constitute the light-emitting unit a2.

[0118] It should be noted that Figure 9 This is only to show the stacking relationship of each film layer, and is not used to represent the cross-sectional view of a specific part of the display panel and the connection relationship of the thin film transistor of the pixel circuit a1 in the display panel.

[0119] In the embodiments of the present application, the fourth thin film transistor T4 and the sixth thin film transistor T6 are both oxide thin film transistors, so that the fourth thin film transistor T4 and the sixth thin film transistor T6 can be composed of the second gate layer b5, the oxide layer b7, and the third gate layer b9. The material of the oxide layer b7 can be IGZO.

[0120] For example, the fourth thin film transistor T4 and the sixth thin film transistor T6 can both be double-gate transistors. The second gate layer b5 can include the gate pattern of the bottom gate of the fourth thin film transistor T4 and the gate pattern of the bottom gate of the sixth thin film transistor T6. The oxide layer b7 can include the oxide pattern of the fourth thin film transistor T4 and the oxide pattern of the sixth thin film transistor T6. The third gate layer b9 can include the gate pattern of the top gate of the fourth thin film transistor T4 and the gate pattern of the top gate of the sixth thin film transistor T6.

[0121] In addition, the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fifth thin film transistor T5, and the seventh thin film transistor T7 are LTPS thin film transistors, so that the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fifth thin film transistor T5, and the seventh thin film transistor T7 can be composed of the active layer b1, the first gate layer b3, and the first source-drain layer b11.

[0122] For example, the active layer b1 can include an active pattern of the first thin film transistor T1, an active pattern of the second thin film transistor T2, an active pattern of the third thin film transistor T3, an active pattern of the fifth thin film transistor T5, and an active pattern of the seventh thin film transistor T7.

[0123] The first gate layer b3 can include a gate pattern of the first thin film transistor T1, a gate pattern of the second thin film transistor T2, a gate pattern of the third thin film transistor T3, a gate pattern of the fifth thin film transistor T5, and a gate pattern of the seventh thin film transistor T7.

[0124] The first source-drain layer b11 can include a source pattern and a drain pattern of the first thin film transistor T1, a source pattern and a drain pattern of the second thin film transistor T2, a source pattern and a drain pattern of the third thin film transistor T3, a source pattern and a drain pattern of the fifth thin film transistor T5, a source pattern and a drain pattern of the sixth thin film transistor T6, a source pattern and a drain pattern of the fourth thin film transistor T4, and a source pattern and a drain pattern of the seventh thin film transistor T7.

[0125] Figure 9 An oxide thin film transistor and an LTPS thin film transistor are shown. The oxide thin film transistor can be the fourth thin film transistor T4 or the sixth thin film transistor T6. The LTPS thin film transistor is connected with the light emitting unit a2, so that it can be the fifth thin film transistor T5.

[0126] In the embodiment of the present application, the first gate signal line Gate1, the light emitting control signal line EM, and the capacitor plate Cst1 of the storage capacitor Cst can be located in the first gate layer b3. The capacitor plate Cst2 of the storage capacitor Cst can be located in the second gate layer b5. The reset signal line RST and the second gate signal line Gate2 can be located in the third gate layer b9. The first reset power line Vinit1 and the second reset power line Vinit2 can be located in the first source-drain layer b11. The data signal line Data can be located in the second source-drain layer b14. The driving power line VDD can be located in the first source-drain layer b11 and the second source-drain layer b14.

[0127] The driving power supply line VDD is located in the first source-drain layer b11 and the second source-drain layer b14, which means that the driving power supply line VDD can include a first layer of traces and a second layer of traces connected to the first layer of traces. The first layer of traces is located in the first source-drain layer b11, and the second layer of traces is located in the second source-drain layer b14.

[0128] The first gate signal line Gate1, the light-emitting control signal line EM, and the capacitor plate Cst1 of the storage capacitor Cst are located in the first gate layer b3, which means that the first gate signal line Gate1, the light-emitting control signal line EM, the capacitor plate Cst1 of the storage capacitor Cst, the gate pattern of the first thin-film transistor T1, the gate pattern of the second thin-film transistor T2, the gate pattern of the third thin-film transistor T3, the gate pattern of the fifth thin-film transistor T5, and the gate pattern of the seventh thin-film transistor T7 are made of the same material and prepared by the same patterning process.

[0129] The capacitor plate Cst2 of the storage capacitor Cst is located in the second gate layer b5, which means that the capacitor plate Cst2 of the storage capacitor Cst and the gate pattern of the bottom gate of the fourth thin-film transistor T4 and the gate pattern of the bottom gate of the sixth thin-film transistor T6 are made of the same material and prepared by the same patterning process.

[0130] The reset signal line RST and the second gate signal line Gate2 are located in the third gate layer b9, which means that the reset signal line RST and the second gate signal line Gate2 and the gate pattern of the top gate of the fourth thin-film transistor T4 and the gate pattern of the top gate of the sixth thin-film transistor T6 are made of the same material and prepared by the same patterning process.

[0131] The first reset power supply line Vinit1, the second reset power supply line Vinit2, and the first layer of traces of the driving power supply line VDD are located in the first source-drain layer b11, which means that the first reset power supply line Vinit1, the second reset power supply line Vinit2, the first layer of traces of the driving power supply line VDD, and the source pattern and drain pattern of the first thin-film transistor T1, the source pattern and drain pattern of the second thin-film transistor T2, the source pattern and drain pattern of the third thin-film transistor T3, the source pattern and drain pattern of the fourth thin-film transistor T4, the source pattern and drain pattern of the fifth thin-film transistor T5, the source pattern and drain pattern of the sixth thin-film transistor T6, and the source pattern and drain pattern of the seventh thin-film transistor T7 are made of the same material and prepared by the same patterning process.

[0132] The data signal line Data and the second layer of traces of the driving power supply line VDD are located in the second source-drain layer b14, which means that the data signal line Data and the second layer of traces of the driving power supply line VDD are made of the same material and prepared by the same patterning process.

[0133] Referring to Figure 9 The substrate substrate 101 in the display panel provided by the embodiments of the present application can include a first flexible substrate 1011, a second flexible substrate 1012, and a first barrier layer 1013 located between the first flexible substrate 1011 and the second flexible substrate 1012. For example, the materials of the first flexible substrate 1011 and the second flexible substrate 1012 can include polyimide (PI).

[0134] Referring to Figure 9 The display panel can further include a second planar layer 103, and a second barrier layer 104, a line shied (LS) 105, a first buffer layer 106, and a second buffer layer 107 which are sequentially stacked in a direction away from the substrate substrate 101 and located on one side of the substrate substrate 101. Among them, the second planar layer 103 is located between the film layer constituting the pixel circuit a1 and the film layer constituting the light emitting unit a2, that is, between the second source-drain layer b14 and the anode layer c1.

[0135] In summary, the embodiments of the present application provide a display panel, in which, in the first sub-pixel group and the second sub-pixel group adjacent to each other, the gate of the first thin film transistor in the first sub-pixel group and the gate of the second thin film transistor in the second sub-pixel group are both connected to the first gate signal line. That is, the gate of the first thin film transistor in the first sub-pixel group and the gate of the second thin film transistor in the second sub-pixel group share the first gate signal line. Thus, the space of the display panel can be saved, the fingerprint recognition area can be reserved, the display panel can realize the function of under-screen fingerprint recognition, and the screen ratio of the display panel can be improved.

[0136] Figure 10 is a flowchart of a method for manufacturing a display panel provided by the embodiments of the present application. The method can be used to manufacture the display panel provided by the above embodiments. Referring to Figure 10 The method can include:

[0137] Step 201, providing a substrate substrate.

[0138] In the embodiments of the present application, when manufacturing the display panel, a substrate substrate 101 can be obtained first. The material of the substrate substrate 101 can include a flexible material. For example, the material of the substrate substrate 101 can include PI.

[0139] Step 202, forming a plurality of sub-pixel groups arranged in a first direction on one side of the substrate substrate.

[0140] In the embodiment of the present application, after the substrate 101 is obtained, a plurality of sub-pixel groups 102 arranged along a first direction X can be formed on one side of the substrate 101. Each sub-pixel group 102 includes a plurality of sub-pixels 1021 arranged along a second direction Y, which can be perpendicular to the first direction X. For example, the second direction Y can be perpendicular to the first direction X, the first direction X can be the pixel column direction of the display panel, and the second direction Y can be the pixel row direction of the display panel.

[0141] Reference Figure 1 Each sub-pixel 1021 can include a pixel circuit a1 and a light-emitting unit a2 connected to the pixel circuit a1. The pixel circuit a1 is used to drive the light-emitting unit a2 to emit light. In combination with Figure 2 And Figure 3 It can be seen that the pixel circuit a1 of each sub-pixel 1021 can include at least a first thin film transistor T1 and a second thin film transistor T2.

[0142] In combination with Figure 1 , Figure 2 , Figure 4 And Figure 5 There are adjacent first sub-pixel group 102a and second sub-pixel group 102b in the plurality of sub-pixel groups 102. The gate of the first thin film transistor T1 in the first sub-pixel group 102a is connected to a first gate signal line Gate1, and the gate of the second thin film transistor T2 in the second sub-pixel group 102b is connected to the first gate signal line Gate1. The first gate signal line Gate1 can provide signals for the gates of the first thin film transistor T1 in the first sub-pixel group 102a and the second thin film transistor T2 in the second sub-pixel group 102b.

[0143] That is, the gate of the first thin film transistor T1 in the first sub-pixel group 102a and the gate of the second thin film transistor T2 in the second sub-pixel group 102b are connected to the same first gate signal line Gate1. The display panel prepared by the embodiment of the present application does not need to be provided with two gate signal lines to provide signals for the first thin film transistor T1 in the first sub-pixel group 102a and the second thin film transistor T2 in the second sub-pixel group 102b, respectively.

[0144] Further, the scheme of arranging one first gate signal line Gate1 to connect the gate of the first thin film transistor T1 in the first sub-pixel group 102a and the gate of the second thin film transistor T2 in the second sub-pixel group 102b can save the space of the display panel, compared with the scheme of arranging two gate signal lines to respectively connect the gate of the first thin film transistor T1 in the first sub-pixel group 102a and the gate of the second thin film transistor T2 in the second sub-pixel group 102b. Further, the display panel can reserve a fingerprint recognition area to arrange a fingerprint recognition device, so as to facilitate the display panel to realize the function of under-screen fingerprint recognition, and improve the screen ratio of the display panel.

[0145] In the display panel, the fingerprint recognition area can be an area where no thin film transistor and signal line is arranged, for example, a hollow white area m. Figure 2 In the display panel, the fingerprint recognition area can be an area where no thin film transistor and signal line is arranged, for example, a hollow white area m.

[0146] In summary, the embodiment of the present application provides a preparation method of a display panel. In the display panel prepared by the method, the gate of the first thin film transistor in the first sub-pixel group and the gate of the second thin film transistor in the second sub-pixel group are both connected to the first gate signal line. That is, the gate of the first thin film transistor in the first sub-pixel group and the gate of the second thin film transistor in the second sub-pixel group share the first gate signal line. Thus, the space of the display panel can be saved, the fingerprint recognition area can be reserved, the display panel can realize the function of under-screen fingerprint recognition, and the screen ratio of the display panel can be improved.

[0147] Figure 11 FIG. 7 is a flowchart of another preparation method of a display panel provided by an embodiment of the present application. The method can be used to prepare the display panel provided by the above-mentioned embodiments. Referring to FIG. 7, Figure 11 The method can include the following steps.

[0148] Step 301: providing a substrate.

[0149] In the embodiment of the present application, when the display panel is prepared, a substrate 101 can be obtained first. The substrate 101 can include a first flexible substrate 1011, a second flexible substrate 1012, and a first barrier layer 1013 between the first flexible substrate 1011 and the second flexible substrate 1012. The materials of the first flexible substrate 1011 and the second flexible substrate 1012 can both include flexible materials. For example, the materials of the first flexible substrate 1011 and the second flexible substrate 1012 can include PI.

[0150] Step 302: sequentially forming a second barrier layer, a light shielding layer, a first buffer layer, and a second buffer layer on one side of the substrate.

[0151] In the embodiments of the present application, the second barrier layer 104, the first buffer layer 106 and the second buffer layer 107 can all cover the substrate 101 integrally. Referring to Figure 12 The light-blocking layer 105 can include a plurality of light-blocking patterns. The light-blocking layer 105 is used to block light, so as to avoid the light from the side of the substrate 101 away from the light-blocking layer from affecting the normal light emission of the sub-pixel 1021 formed subsequently.

[0152] Optionally, the material for making the buffer layer can include silicon nitride and silicon oxide.

[0153] Optionally, the light-blocking layer 105 can be prepared by patterning processing, and the patterning processing can include photoresist coating, exposure, development, etching and photoresist removal. For the light-blocking layer 105, a light-blocking film layer can be first formed on one side of the substrate 101 (the light-blocking film layer can cover the substrate 101 integrally), and the light-blocking film layer is subjected to patterning processing to obtain the light-blocking layer 105.

[0154] In step 303, an active layer is formed on the side of the second buffer layer away from the substrate.

[0155] In the embodiments of the present application, referring to Figure 13 After the second barrier layer 104, the light-blocking layer 105, the first buffer layer 106 and the second buffer layer 107 are prepared, an active layer b1 can be formed on the side of the second buffer layer 107 away from the substrate 101. Optionally, the material for making the active layer b1 can include polycrystalline silicon (poly).

[0156] In the embodiments of the present application, the second barrier layer 104, the first buffer layer 106 and the second buffer layer 107 can all cover the substrate 101 integrally. Referring to Figure 12 If it is necessary to show the second barrier layer 104, the first buffer layer 106 and the second buffer layer 107, all regions of FIG. 1B can be shown. Figure 12

[0157] Optionally, the active layer b1 can be prepared by patterning processing. For the active layer b1, an active film layer can be first formed on one side of the substrate 101 (the active film layer can cover the substrate 101 integrally), and the active film layer is subjected to patterning processing to obtain the active layer b1.

[0158] The active layer b1 can have a curved or bent shape, and include an active pattern of the first thin film transistor T1, an active pattern of the second thin film transistor T2, an active pattern of the third thin film transistor T3, an active pattern of the fifth thin film transistor T5 and an active pattern of the seventh thin film transistor T7.

[0159] ​In the embodiments of the present application, each active pattern includes a channel region, a source region and a drain region. The channel region can not be doped or have a different doping type from the source region and the drain region, and thus has semiconductor characteristics. The source region and the drain region are respectively located on both sides of the channel region, and are doped with impurities, and thus have conductivity. The impurities can vary depending on whether the thin film transistor is an N-type or a P-type transistor.

[0160] In step 304, a first gate insulating layer and a first gate layer are formed on a side of the active layer away from the substrate.

[0161] In the embodiments of the present application, after the active layer b1 is formed, a first gate insulating layer b2 can be formed on a side of the active layer b1 away from the substrate 101. The first gate insulating layer b2 can cover the substrate 101 as a whole, and the first gate insulating layer b2 can have a plurality of pores. Each via hole in the first gate insulating layer b2 is used for connecting a subsequently formed film layer to a film layer on the side of the first gate insulating layer b2 close to the substrate 101. That is, each via hole in the first gate insulating layer b2 is a via hole for film layer connection.

[0162] Reference Figure 14 After the first gate insulating layer b2 is formed, a first gate layer b3 can be formed on a side of the first gate insulating layer b2 away from the substrate 101.

[0163] Optionally, the first gate layer b3 can be prepared by patterning. For the first gate layer b3, a first gate film layer can be first formed on a side of the substrate 101 (the first gate film layer can cover the substrate 101 as a whole), and the first gate film layer is subjected to patterning to obtain the first gate layer b3.

[0164] The first gate layer b3 can include a gate pattern of the first thin film transistor T1, a gate pattern of the second thin film transistor T2, a gate pattern of the third thin film transistor T3, a gate pattern of the fifth thin film transistor T5 and a gate pattern of the seventh thin film transistor T7. The portion of the first gate layer b3 overlapping the active pattern of the first thin film transistor T1 can constitute the gate pattern of the first thin film transistor T1. The portion of the first gate layer b3 overlapping the active pattern of the second thin film transistor T2 can constitute the gate pattern of the second thin film transistor T2. The portion of the first gate layer b3 overlapping the active pattern of the third thin film transistor T3 can constitute the gate pattern of the third thin film transistor T3. The portion of the first gate layer b3 overlapping the active pattern of the fifth thin film transistor T5 can constitute the gate pattern of the fifth thin film transistor T5. The portion of the first gate layer b3 overlapping the active pattern of the seventh thin film transistor T7 can constitute the gate pattern of the seventh thin film transistor T7.

[0165] Reference is made to Figure 14 The first gate signal line Gate1, the light-emitting control signal line EM, and the capacitor plate Cst1 of the storage capacitor Cst in the display panel 10 can be located in the first gate layer b3. That is, the first gate signal line Gate1, the light-emitting control signal line EM, the capacitor plate Cst1 of the storage capacitor Cst, the gate pattern of the first thin-film transistor T1, the gate pattern of the second thin-film transistor T2, the gate pattern of the third thin-film transistor T3, the gate pattern of the fifth thin-film transistor T5, and the gate pattern of the seventh thin-film transistor T7 are made of the same material and obtained by the same patterning process. Figure 14 The capacitor plate Cst1 of the storage capacitor Cst in the display panel 10 is used as the gate pattern of the seventh thin-film transistor T7 and one electrode of the storage capacitor Cst.

[0166] In step 305, a second gate insulating layer and a second gate layer are formed on the side of the first gate layer away from the substrate.

[0167] In the embodiment, after the first gate layer b3 is formed, a second gate insulating layer b4 can be formed on the side of the first gate layer b3 away from the substrate 101. The second gate insulating layer b4 can cover the substrate 101 entirely, and the second gate insulating layer b4 can have a plurality of pores. Each via hole in the second gate insulating layer b4 is used for connecting the film layer formed later and the film layer on the side of the second gate insulating layer b4 close to the substrate 101. That is, each via hole in the second gate insulating layer b4 is a via hole for film layer connection.

[0168] Reference is made to Figure 15 After the second gate insulating layer b4 is formed, a second gate layer b5 can be formed on the side of the second gate insulating layer b4 away from the substrate 101.

[0169] Optionally, the second gate layer b5 can be obtained by patterning. For the second gate layer b5, a second gate film layer can be first formed on the side of the substrate 101 (the second gate film layer can cover the substrate 101 entirely), and the second gate film layer is subjected to patterning to obtain the second gate layer b5.

[0170] The second gate layer b5 can include the gate pattern of the bottom gate of the fourth thin-film transistor T4 and the gate pattern of the bottom gate of the sixth thin-film transistor T6.

[0171] Reference is made to Figure 15The capacitor plate Cst2 of the storage capacitor Cst in the display panel can be located at the second gate layer b5. That is, the capacitor plate Cst2 of the storage capacitor Cst, the gate pattern of the bottom gate of the fourth thin film transistor T4, and the gate pattern of the bottom gate of the sixth thin film transistor T6 are made of the same material and obtained by the same patterning process.

[0172] Step 306: forming a third gate insulating layer and an oxide layer on the side of the second gate layer away from the substrate.

[0173] In the embodiment of the present application, after the second gate layer b5 is formed, a third gate insulating layer b6 can be formed on the side of the second gate layer b5 away from the substrate 101. The third gate insulating layer b6 can cover the substrate 101 entirely, and the third gate insulating layer b6 can have a plurality of pores. Each via hole in the third gate insulating layer b6 is used for connecting the film layer formed later and the film layer on the side of the third gate insulating layer b6 close to the substrate 101. That is, each via hole in the third gate insulating layer b6 is a via hole for film layer connection.

[0174] Reference Figure 16 After the third gate insulating layer b6 is formed, an oxide layer b7 can be formed on the side of the third gate insulating layer b6 away from the substrate 101. Optionally, the oxide layer b7 can be prepared by patterning. For the oxide layer b7, an oxide film layer can be first formed on the side of the substrate 101 (the oxide film layer can cover the substrate 101 entirely), and the oxide film layer is subjected to patterning to obtain the oxide layer b7.

[0175] The oxide layer b7 can include the oxide pattern of the fourth thin film transistor T4 and the oxide pattern of the sixth thin film transistor T6. In the embodiment of the present application, the oxide pattern of the fourth thin film transistor T4 and the oxide pattern of the sixth thin film transistor T6 each include a channel region, a source region, and a drain region. The part of the oxide pattern of the fourth thin film transistor T4 overlapping with the gate pattern of the bottom gate of the fourth thin film transistor T4 is the channel region of the oxide pattern of the fourth thin film transistor T4, and the part of the oxide pattern of the sixth thin film transistor T6 overlapping with the gate pattern of the bottom gate of the sixth thin film transistor T6 is the channel region of the oxide pattern of the sixth thin film transistor T6.

[0176] Step 307: forming a fourth gate insulating layer and a third gate layer on the side of the oxide layer away from the substrate.

[0177] In the embodiments of the present application, after the oxide layer b7 is formed, a fourth gate insulating layer b8 can be formed on the side of the oxide layer b7 away from the substrate 101. The fourth gate insulating layer b8 can cover the substrate 101 entirely, and the fourth gate insulating layer b8 can have a plurality of pores. Each via hole in the fourth gate insulating layer b8 is used for connecting a film layer formed later to the film layer on the side of the fourth gate insulating layer b8 close to the substrate 101. That is, each via hole in the fourth gate insulating layer b8 is a via hole for film layer connection.

[0178] Reference Figure 17 After the fourth gate insulating layer b8 is formed, a third gate layer b9 can be formed on the side of the fourth gate insulating layer b8 away from the substrate 101. Optionally, the third gate layer b9 can be prepared by patterning. For the third gate layer b9, a third gate film layer can be first formed on the side of the substrate 101 (the third gate film layer can cover the substrate 101 entirely), and the third gate film layer is subjected to patterning to obtain the third gate layer b9.

[0179] The third gate layer b9 can include a gate pattern of a top gate of the fourth thin film transistor T4 and a gate pattern of a top gate of the sixth thin film transistor T6. Reference Figure 17 The reset signal line RST and the second gate signal line Gate2 in the display panel 10 can be located in the third gate layer b9. That is, the reset signal line RST, the second gate signal line Gate2, the gate pattern of the top gate of the fourth thin film transistor T4, and the gate pattern of the top gate of the sixth thin film transistor T6 are prepared by using the same material and by the same patterning process.

[0180] Optionally, the orthographic projection of the gate pattern of the top gate of the fourth thin film transistor T4 on the substrate 101 can at least partially overlap the orthographic projection of the gate pattern of the top gate of the fourth thin film transistor T4 on the substrate 101. The orthographic projection of the gate pattern of the top gate of the sixth thin film transistor T6 on the substrate 101 can at least partially overlap the orthographic projection of the gate pattern of the bottom gate of the sixth thin film transistor T6 on the substrate 101.

[0181] In step 308, an interlayer dielectric layer and a first source-drain layer are formed on the side of the third gate layer away from the substrate.

[0182] In the embodiments of the present application, reference Figure 18After the third gate layer b9 is formed, an interlayer dielectric layer b10 can be formed on the side of the third gate layer b9 away from the substrate base plate 101. The interlayer dielectric layer b10 can cover the substrate base plate 101 entirely, and the interlayer dielectric layer b10 can have a plurality of pores. Each via hole in the interlayer dielectric layer b10 is used for connecting a film layer formed later to the film layer on the side of the interlayer dielectric layer b10 close to the substrate base plate 101. That is, each via hole in the interlayer dielectric layer b10 is a via hole for film layer connection.

[0183] To facilitate the illustration of each via hole in the interlayer dielectric layer b10, Figure 18 In the drawings, the via holes are represented by filled patterns. The areas not drawn with filled patterns represent areas where the interlayer dielectric layer b10 has solid material.

[0184] Reference is made to Figure 19 After the interlayer dielectric layer b10 is formed, a first source-drain layer b11 can be formed on the side of the interlayer dielectric layer b10 away from the substrate base plate 101. Optionally, the first source-drain layer b11 can be prepared by patterning. For the first source-drain layer b11, a first source-drain film layer can be first formed on the side of the substrate base plate 101 (the first source-drain layer can cover the substrate base plate 101 entirely), and the first source-drain film layer can be patterned to obtain the first source-drain layer b11.

[0185] The first source-drain layer b11 can include the source and drain patterns of the first thin film transistor T1, the source and drain patterns of the second thin film transistor T2, the source and drain patterns of the third thin film transistor T3, the source and drain patterns of the fourth thin film transistor T4, the source and drain patterns of the fifth thin film transistor T5, the source and drain patterns of the sixth thin film transistor T6, and the source and drain patterns of the seventh thin film transistor T7.

[0186] Optionally, the source pattern of the first thin film transistor T1 is connected with the source region of the active pattern of the first thin film transistor T1, and the drain pattern of the first thin film transistor T1 is connected with the drain region of the active pattern of the first thin film transistor T1. The source pattern of the second thin film transistor T2 is connected with the source region of the active pattern of the second thin film transistor T2, and the drain pattern of the second thin film transistor T2 is connected with the drain region of the active pattern of the second thin film transistor T2. The source pattern of the third thin film transistor T3 is connected with the source region of the active pattern of the third thin film transistor T3, and the drain pattern of the third thin film transistor T3 is connected with the drain region of the active pattern of the third thin film transistor T3. The source pattern of the fourth thin film transistor T4 is connected with the source region of the oxide pattern of the fourth thin film transistor T4, and the drain pattern of the fourth thin film transistor T4 is connected with the drain region of the oxide pattern of the fourth thin film transistor T4. The source pattern of the fifth thin film transistor T5 is connected with the source region of the active pattern of the fifth thin film transistor T5, and the drain pattern of the fifth thin film transistor T5 is connected with the drain region of the active pattern of the fifth thin film transistor T5. The source pattern of the sixth thin film transistor T6 is connected with the source region of the oxide pattern of the sixth thin film transistor T6, and the drain pattern of the sixth thin film transistor T6 is connected with the drain region of the oxide pattern of the sixth thin film transistor T6. The source pattern of the seventh thin film transistor T7 is connected with the source region of the active pattern of the seventh thin film transistor T7, and the drain pattern of the seventh thin film transistor T7 is connected with the drain region of the active pattern of the seventh thin film transistor T7.

[0187] In addition, referring to Figure 19 , the first layer traces of the first reset power line Vinit1, the second reset power line Vinit2 and the driving power line VDD in the display panel 10 can be located in the first source-drain layer b11. That is, the first layer traces of the first reset power line Vinit1, the second reset power line Vinit2 and the driving power line VDD and the source and drain patterns of the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6 and the seventh thin film transistor T7 are made of the same material and obtained by the same patterning process.

[0188] In step 309, a passivation layer, a first planarization layer and a second source-drain layer are formed on the side of the first source-drain layer away from the substrate.

[0189] In the embodiments of the present application, referring to Figure 20After the first source-drain layer b11 is formed, a passivation layer b12 can be formed on the side of the first source-drain layer b11 away from the substrate 101. The passivation layer b12 can cover the substrate 101 entirely, and the passivation layer b12 can have a plurality of pores. Each via hole in the passivation layer b12 is for connecting a film layer formed later to a film layer on the side of the passivation layer b12 close to the substrate 101. That is, each via hole in the passivation layer b12 is a via hole for film layer connection.

[0190] For the convenience of showing each via hole in the passivation layer b12, Figure 20 In the figure, the via holes are represented by filled patterns. Other areas not drawn with filled patterns represent areas where the passivation layer b12 has solid material.

[0191] Reference is made to Figure 21 After the passivation layer b12 is formed, a first planarization layer b13 can be formed on the side of the passivation layer b12 away from the substrate 101. The first planarization layer b13 can cover the substrate 101 entirely, and the first planarization layer b13 can have a plurality of pores. Each via hole in the first planarization layer b13 is for connecting a film layer formed later to a film layer on the side of the first planarization layer b13 close to the substrate 101. That is, each via hole in the first planarization layer b13 is a via hole for film layer connection.

[0192] For the convenience of showing each via hole in the first planarization layer b13, Figure 21 In the figure, the via holes are represented by filled patterns. Other areas not drawn with filled patterns represent areas where the first planarization layer b13 has solid material.

[0193] Reference is made to Figure 22 After the first planarization layer b13 is formed, a second source-drain layer b14 can be formed on the side of the first planarization layer b13 away from the substrate 101. Optionally, the second source-drain layer b14 can be prepared by patterning. For the second source-drain layer b14, a second source-drain film layer can be first formed on the side of the substrate 101 (the second source-drain film layer can cover the substrate 101 entirely), and the second source-drain film layer is then patterned to obtain the second source-drain layer b14.

[0194] The second source-drain layer b14 can include a connection pattern for connecting a drain pattern of the fifth thin film transistor T5 and an anode pattern of the fifth thin film transistor T5. In addition, reference is made to Figure 22 The second layer of the data signal line Data and the driving power supply line VDD can be located in the second source-drain layer b14. That is, the data signal line Data, the second layer of the driving power supply line VDD, and the connection pattern are made of the same material and prepared by the same patterning process.

[0195] Step 310, a second planar layer, an anode layer, a pixel defining layer, a light emitting layer and a cathode layer are sequentially formed on the side of the second source-drain layer away from the substrate.

[0196] In the embodiments of the present application, reference is made to Figure 23 After the second source-drain layer b14 is formed, a second planar layer 103 can be formed on the side of the second source-drain layer b14 away from the substrate 101. The second planar layer 103 can cover the substrate 101 entirely, and the second planar layer 103 can have a plurality of pores. Each of the pores in the second planar layer 103 is used for connecting the film layer formed later and the film layer on the side of the second planar layer 103 close to the substrate 101. That is, each of the pores in the second planar layer 103 is a pore for film layer connection.

[0197] In order to show the pores in the second planar layer 103 more clearly, Figure 23 In the drawings, the pores are represented by filled patterns. The areas not drawn with filled patterns represent the areas of the second planar layer 103 with solid material.

[0198] Reference is made to Figure 24 After the second planar layer 103 is formed, an anode layer c1 can be formed on the side of the second planar layer 103 away from the substrate 101. Optionally, the anode layer c1 can be prepared by patterning. For the anode layer c1, an anode film layer can be first formed on the side of the substrate 101 (the anode film layer can cover the substrate 101 entirely), and the anode film layer is patterned to obtain the anode layer c1. The anode layer c1 can include anode patterns of each of the sub-pixels 1021, and each of the anode patterns of the sub-pixels 1021 is connected to the pixel circuit a1 of the sub-pixel 1021.

[0199] Reference is made to Figure 25 After the anode layer c1 is formed, a pixel defining layer c2 can be formed on the side of the anode layer c1 away from the substrate 101. Optionally, the pixel defining layer c2 can have a plurality of hollow areas, and each of the hollow areas can be used to expose the anode pattern of one of the sub-pixels 1021, so that the light emitting pattern of the sub-pixel 1021 formed later is in contact with the anode pattern.

[0200] Optionally, the pixel defining layer c2 can be prepared by patterning. For the pixel defining layer c2, a pixel defining film layer can be first formed on the side of the substrate 101 (the pixel defining film layer can cover the substrate 101 entirely), and the pixel defining film layer is patterned to obtain the pixel defining layer c2.

[0201] In the embodiments of the present application, after the pixel defining layer c2 is formed, the light-emitting layer c3 and the cathode layer c4 can be formed. The light-emitting layer c3 can include a light-emitting pattern of each sub-pixel 1021, and the light-emitting pattern of each sub-pixel 1021 is located in a hollow region. In addition, the cathode layer c4 of each sub-pixel 1021 can be a shared film layer.

[0202] In summary, the embodiments of the present application provide a preparation method of a display panel. In the display panel prepared by the method, the gate of the first thin film transistor of the first sub-pixel group and the gate of the second thin film transistor of the second sub-pixel group are connected to the first gate signal line. That is, the gate of the first thin film transistor in the first sub-pixel group and the gate of the second thin film transistor in the second sub-pixel group share the first gate signal line. Thus, the space of the display panel can be saved, the fingerprint recognition area can be reserved, the display panel can realize the function of under-screen fingerprint recognition, and the screen ratio of the display panel is improved.

[0203] Figure 26 FIG. 1 is a structural schematic diagram of a display device provided by an embodiment of the present application. Referring to FIG. 1, Figure 26 The display device can include a power supply component 40 and the display panel 10 provided by the above embodiments. The power supply component 40 can be connected to the display panel and used to supply power to the display panel 10.

[0204] Optionally, the display device can be an OLED display device, electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator or any product or component with a display function.

[0205] The above description is only optional embodiments of the present application and is not used to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A display panel, characterized by, The display panel comprises: a substrate substrate; a plurality of sub-pixel groups arranged along a first direction on one side of the substrate substrate; each of the sub-pixel groups comprises a plurality of sub-pixels arranged along a second direction intersecting the first direction; each of the sub-pixels comprises a pixel circuit and a light-emitting unit connected to the pixel circuit; each of the pixel circuits comprises at least a first thin-film transistor, a second thin-film transistor, a third thin-film transistor, and a fourth thin-film transistor; wherein there are adjacent first and second sub-pixel groups in the plurality of sub-pixel groups, there are adjacent first and second sub-pixels in each of the sub-pixel groups, and there is a third sub-pixel adjacent to the first sub-pixel, the third sub-pixel being located on a side of the first sub-pixel away from the second sub-pixel; a gate of the first thin-film transistor in the first sub-pixel group and a gate of the second thin-film transistor in the second sub-pixel group are connected to the same first gate signal line; the first thin-film transistor and the second thin-film transistor in the pixel circuit of each of the sub-pixels are connected to different first gate signal lines; a first pole of the first thin-film transistor is connected to a first reset power supply line; and a first pole of the second thin-film transistor is connected to a data signal line; in the first direction, a first distance between the first thin-film transistor in the first sub-pixel group and the second thin-film transistor in the second sub-pixel group is smaller than a second distance between the first thin-film transistor in the first sub-pixel group and other thin-film transistors in the second sub-pixel group except the second thin-film transistor; a first pole of the third thin-film transistor in the first sub-pixel and a first pole of the third thin-film transistor in the second sub-pixel are both connected to a driving power supply line through a first connecting part; wherein in the second direction, a third distance between the third thin-film transistor in the first sub-pixel and the third thin-film transistor in the second sub-pixel is smaller than a fourth distance between the third thin-film transistor in the first sub-pixel and other thin-film transistors in the second sub-pixel except the third thin-film transistor; a first pole of the fourth thin-film transistor in the first sub-pixel and a first pole of the fourth thin-film transistor in the third sub-pixel are both connected to a second reset power supply line through a second connecting part; wherein in the second direction, a fifth distance between the fourth thin-film transistor in the first sub-pixel and the fourth thin-film transistor in the third sub-pixel is smaller than a sixth distance between the fourth thin-film transistor in the first sub-pixel and other thin-film transistors in the third sub-pixel except the fourth thin-film transistor.

2. The display panel of claim 1, wherein, The first sub-pixel and the second sub-pixel are symmetrically arranged.

3. The display panel of claim 1, wherein, The pixel circuit of each of the sub-pixels further comprises a fifth thin-film transistor, a sixth thin-film transistor, and a seventh thin-film transistor; a second pole of the first thin-film transistor is connected to the light-emitting unit; a second pole of the second thin-film transistor is connected to a first node; and a second pole of the third thin-film transistor is connected to a second node. A gate of the third thin film transistor is connected with a light-emitting control signal line, a first electrode of the third thin film transistor is connected with a driving power supply line, and a second electrode of the third thin film transistor is connected with the first node; A gate of the fourth thin film transistor is connected with a reset signal line, a first electrode of the fourth thin film transistor is connected with a second reset power supply line, and a second electrode of the fourth thin film transistor is connected with the second node; A gate of the fifth thin film transistor is connected with the light-emitting control signal line, a first electrode of the fifth thin film transistor is connected with the third node, and a second electrode of the fifth thin film transistor is connected with the light-emitting unit; A gate of the sixth thin film transistor is connected with a second gate signal line, a first electrode of the sixth thin film transistor is connected with the third node, and a second electrode of the sixth thin film transistor is connected with the second node; A gate of the seventh thin film transistor is connected with the second node, a first electrode of the seventh thin film transistor is connected with the first node, and a second electrode of the seventh thin film transistor is connected with the third node.

4. The display panel of claim 3, wherein, The fourth thin film transistor and the sixth thin film transistor are oxide thin film transistors; The first thin film transistor, the second thin film transistor, the third thin film transistor, the fifth thin film transistor, and the seventh thin film transistor are low-temperature polysilicon thin film transistors.

5. The display panel of claim 4, wherein, The fourth thin film transistor and the sixth thin film transistor are N-type transistors; The first thin film transistor, the second thin film transistor, the third thin film transistor, the fifth thin film transistor, and the seventh thin film transistor are P-type transistors.

6. The display panel of claim 4, wherein, The display panel comprises, in a direction away from a substrate base plate, an active layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, a buffer layer, an oxide layer, a third gate insulating layer, a third gate layer, an interlayer dielectric layer, a first source-drain layer, a passivation layer, a first planarization layer, and a second source-drain layer, which are sequentially stacked and constitute the pixel circuit. The display panel comprises, in a direction away from a substrate base plate, an anode layer, a pixel definition layer, a light-emitting layer, and a cathode layer, which are sequentially stacked and constitute the light-emitting unit.

7. The display panel of claim 6, wherein, The fourth thin film transistor and the sixth thin film transistor are constituted by the second gate layer, the oxide layer, and the third gate layer. The first thin film transistor, the second thin film transistor, the third thin film transistor, the fifth thin film transistor, and the seventh thin film transistor are constituted by the active layer, the first gate layer, and the first source-drain layer.

8. The display panel of claim 6, wherein, The first gate signal line and the light-emitting control signal line are located in the first gate layer; the reset signal line and the second gate signal line are located in the third gate layer; the first reset power supply line and the second reset power supply line are located in the first source-drain layer; the data signal line is located in the second source-drain layer; and the driving power supply line is located in the first source-drain layer and the second source-drain layer.

9. The display panel of any of claims 3 to 8, wherein, The pixel circuit of each sub-pixel further comprises a storage capacitor. One end of the storage capacitor is connected with the driving power supply line, and the other end of the storage capacitor is connected with the second node.

10. A method for manufacturing a display panel, characterized by, The method comprises: providing a substrate; forming a plurality of sub-pixel groups arranged along a first direction on one side of the substrate; wherein each of the sub-pixel groups comprises: a plurality of sub-pixels arranged along a second direction intersecting the first direction; each of the sub-pixels comprises a pixel circuit and a light-emitting unit connected with the pixel circuit; and the pixel circuit of each of the sub-pixels comprises at least a first thin-film transistor, a second thin-film transistor, a third thin-film transistor and a fourth thin-film transistor; there are adjacent first and second sub-pixel groups in the plurality of sub-pixel groups, there are adjacent first and second sub-pixels in each of the sub-pixel groups, and there is a third sub-pixel adjacent to the first sub-pixel, the third sub-pixel being located on a side of the first sub-pixel away from the second sub-pixel; the gate of the first thin-film transistor in the first sub-pixel group and the gate of the second thin-film transistor in the second sub-pixel group are connected with the same first gate signal line; the first thin-film transistor and the second thin-film transistor in the pixel circuit of each of the sub-pixels are connected with different first gate signal lines; the first pole of the first thin-film transistor is connected with a first reset power supply line; and the first pole of the second thin-film transistor is connected with a data signal line; in the first direction, a first distance between the first thin-film transistor in the first sub-pixel group and the second thin-film transistor in the second sub-pixel group is smaller than a second distance between the first thin-film transistor in the first sub-pixel group and other thin-film transistors in the second sub-pixel group except the second thin-film transistor; the first pole of the third thin-film transistor in the first sub-pixel and the first pole of the third thin-film transistor in the second sub-pixel are both connected with a driving power supply line through a first connecting part; wherein in the second direction, a third distance between the third thin-film transistor in the first sub-pixel and the third thin-film transistor in the second sub-pixel is smaller than a fourth distance between the third thin-film transistor in the first sub-pixel and other thin-film transistors in the second sub-pixel except the third thin-film transistor; the first pole of the fourth thin-film transistor in the first sub-pixel and the first pole of the fourth thin-film transistor in the third sub-pixel are both connected with a second reset power supply line through a second connecting part; wherein in the second direction, a fifth distance between the fourth thin-film transistor in the first sub-pixel and the fourth thin-film transistor in the third sub-pixel is smaller than a sixth distance between the fourth thin-film transistor in the first sub-pixel and other thin-film transistors in the third sub-pixel except the fourth thin-film transistor.

11. A display device comprising: The display device comprises: a power supply assembly and the display panel of any one of claims 1 to 9; the power supply assembly is configured to supply power to the display panel.

Images