Display substrate, manufacturing method thereof, display panel and display device

Abstract

The application discloses a display substrate, a manufacturing method thereof, a display panel and a display device. The display substrate comprises a first electrode in a first display area and a second electrode in a second display area; a first light-emitting layer in the first display area and a second light-emitting layer in the second display area; and a third electrode in the first display area and a fourth electrode in the second display area. The third electrode is optimally patterned and designed, and the third electrode wiring mode in the first display area is optimized to improve the display effect in the first display area, reduce glare interference, and optimize and improve the transmittance of the first display area to ensure the camera shooting effect of the under-screen camera arranged in the first display area.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to display substrates, their manufacturing methods, display panels, and display devices. Background Technology

[0002] With the increasing demand for diverse uses of display devices and the emergence of high screen-to-body ratio design requirements, the "under-display camera" solution has emerged. In this solution, imaging modules such as cameras are embedded within the display area to reduce the size of the display's bezels, thereby increasing the screen-to-body ratio. Currently, the wiring layout of the display device and the placement of pixel light-emitting units are key research areas and challenges in the "under-display camera" solution.

[0003] The information disclosed in this section is only for understanding the background of the technical concept of this disclosure, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0004] The display substrate provided in this embodiment includes a substrate; and

[0005] The first display area and the second display area are located on the substrate;

[0006] Thin-film transistors disposed on the substrate and a planarization layer located on the side of the thin-film transistors facing away from the substrate.

[0007] Signal traces electrically connected to the thin-film transistor are disposed in the first display area;

[0008] A plurality of first electrodes are disposed in the first display area and a plurality of second electrodes are disposed in the second display area, wherein the first electrodes and the second electrodes are located on the side of the planarization layer opposite to the substrate;

[0009] A pixel defining layer is disposed on the side of the first electrode and the second electrode facing away from the substrate. The pixel defining layer includes a plurality of first openings located in the first display area and a plurality of second openings located in the second display area. Each first opening exposes at least a portion of the first electrode, and each second opening exposes at least a portion of the second electrode.

[0010] A light-emitting layer disposed on the first opening and the second opening;

[0011] A plurality of third electrodes and fourth electrodes are disposed on the side of the light-emitting layer opposite to the substrate, wherein the third electrodes are located in the first display area and the fourth electrodes are located in the second display area;

[0012] The orthographic projection of each of the third electrodes on the substrate covers M orthographic projections of the first opening on the substrate, and the orthographic projection of the fourth electrode on the substrate covers N orthographic projections of the second opening on the substrate, wherein M is less than N.

[0013] In some examples, M equals 1, N is greater than or equal to 2, and the number of the fourth electrode is 1.

[0014] In some examples, a third electrode trace is also included, which is located on the side of the planarization layer opposite to the substrate.

[0015] In some examples, each of the third electrodes further includes a third electrode connection portion that corresponds to it, and the third electrode is electrically connected to the third electrode trace through the third electrode connection portion. The number of the third electrode connection portions is less than or equal to the number of the first openings.

[0016] In some examples, the signal trace is disposed on the same layer as the source and drain of the thin-film transistor layer, and the orthographic projection of the third electrode trace on the substrate overlaps with the orthographic projection of the signal trace on the substrate, with an overlap area of ​​not less than 90%.

[0017] In some examples, there is also a transition region between the first region and the second region;

[0018] The thin-film transistor layer is provided with a first pixel circuit structure for controlling and driving the light emission of the pixels in the first display area and a transition pixel circuit structure for controlling and driving the light emission of the pixels in the transition area in the transition region.

[0019] In some examples, the first electrode is electrically connected to the first signal line through a first electrode via;

[0020] The first signal line extends from the first display area to the transition area, transmitting the circuit signal of the first pixel circuit structure located in the transition area to the first electrode located in the first display area corresponding to it.

[0021] In some examples, a peripheral wiring area is also provided around the display substrate, and the fourth electrode is electrically connected to the second signal line by overlapping the second electrode wiring to access the second power supply voltage signal.

[0022] In some examples, in the peripheral routing area, the third electrode trace is directly connected to the second signal line so that the third electrode is connected to the second power supply voltage signal.

[0023] In some examples, the peripheral trace area is provided with a first peripheral barrier and a second peripheral barrier. The projection of the first peripheral barrier on the substrate side falls within the projection of the second electrode trace and the second signal line on the substrate side. The projection of the second peripheral barrier on the substrate side only partially overlaps with the orthographic projection of the second electrode trace and the second signal line on the substrate side.

[0024] In some examples, the orthographic projection of the third electrode trace on the substrate side does not overlap with either the first peripheral barrier or the second peripheral barrier.

[0025] In some examples, the materials of the third electrode, the fourth electrode, the third electrode trace, and the signal trace include at least one of indium tin oxide or indium zinc oxide;

[0026] The fourth electrode also includes at least one of magnesium or silver.

[0027] This disclosure provides a method for manufacturing a display substrate, including:

[0028] Provide a substrate;

[0029] A first display area and a second display area are disposed on the substrate;

[0030] A thin-film transistor layer and a planarization layer are sequentially formed on the substrate;

[0031] The thin-film transistor layer forms a first pixel circuit structure in the first display area on the substrate and a second pixel circuit structure in the second display area on the substrate;

[0032] On the side of the planarization layer opposite to the substrate, a plurality of first electrodes located in the first display area and a plurality of second electrodes located in the second display area are also formed;

[0033] A first light-emitting layer is formed on the side of the first electrode facing away from the substrate, and a second light-emitting layer is formed on the side of the second electrode facing away from the substrate;

[0034] A third electrode is formed on the side of the first light-emitting layer away from the substrate, and a fourth electrode is formed on the side of the second light-emitting layer away from the substrate.

[0035] In some examples, the step of forming a third electrode on the side of the first light-emitting layer away from the substrate and forming a fourth electrode on the side of the second light-emitting layer away from the substrate includes: forming a first cathode material layer on the side of the second light-emitting layer away from the substrate in the second display area, wherein the material of the first cathode material layer includes at least one of magnesium or silver;

[0036] A second cathode material layer is formed on the side of the first light-emitting layer in the first display area and the side of the second light-emitting layer in the second display area that is away from the substrate. In the second display area, the second cathode material layer is located on the side of the first cathode material layer that is away from the substrate.

[0037] In the first display area, the second cathode material layer is laser-cut to form a plurality of the third electrodes and the third electrode traces.

[0038] In some examples, a transition region is also formed on the substrate, the transition region being located between the first display region and the second display region, and the first pixel circuit structure and the transition pixel circuit structure are disposed in the transition region;

[0039] A fifth electrode, a third light-emitting layer, and a sixth electrode are sequentially formed on the side of the transition pixel circuit structure facing away from the substrate.

[0040] In some examples, a sixth electrode is formed on the side of the transition pixel circuit structure opposite to the substrate, specifically including: forming a second cathode material layer in the transition region and the first display region;

[0041] The second cathode material layer is laser-cut to form the sixth electrode and the third electrode.

[0042] This disclosure also provides a display panel, including the above-described display substrate.

[0043] This disclosure also provides a display device, including the above-described display panel. Attached Figure Description

[0044] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1A This is one of the schematic diagrams of a planar structure provided in an embodiment of the present invention;

[0046] Figure 1B This is a second schematic diagram of a planar structure provided in an embodiment of the present invention;

[0047] Figure 1C This is the third schematic diagram of the planar structure provided in the embodiment of the present invention;

[0048] Figure 1DThe fourth schematic diagram of the planar structure provided in the embodiment of the present invention;

[0049] Figure 2 for Figure 1A or Figure 1B Cross-sectional view;

[0050] Figure 3A This is one of the top view structural diagrams of the display substrate provided in an embodiment of the present invention;

[0051] Figure 3B This is a second top view schematic diagram of the display substrate structure provided in an embodiment of the present invention;

[0052] Figure 4 This is a partial top view of the display substrate structure provided in an embodiment of the present invention;

[0053] Figure 5A One of the partial top view structural schematic diagrams of the junction of the first display area, the transition area and the second display area of ​​the display substrate provided in an embodiment of the present invention;

[0054] Figure 5B A second partial top view of the junction of the first display area, the transition area, and the second display area of ​​the display substrate provided in an embodiment of the present invention;

[0055] Figure 6A One of the schematic diagrams of a partial cross-sectional structure at the junction of the first display area, the transition area, and the second display area of ​​the display substrate provided in an embodiment of the present invention;

[0056] Figure 6B A second schematic diagram of a partial cross-sectional structure at the junction of the first display area, the transition area, and the second display area of ​​the display substrate provided in an embodiment of the present invention;

[0057] Figure 7 for Figure 1A Cross-sectional view;

[0058] Figure 8 for Figure 1B One of the cross-sectional views;

[0059] Figure 9 for Figure 1B The second cross-sectional view. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the protection scope of this disclosure.

[0061] It should be noted that, for clarity and / or descriptive purposes, the dimensions and relative dimensions of components may be enlarged in the accompanying drawings. Therefore, the dimensions and relative dimensions of the individual components are not necessarily limited to those shown in the drawings. In the specification and accompanying drawings, the same or similar reference numerals indicate the same or similar parts.

[0062] When an element is described as being "on" another element, "connected to" another element, or "bonded to" another element, the element may be directly on, directly connected to, or directly bonded to the other element, or there may be intermediate elements. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly bonded to" another element, there are no intermediate elements. Other terms and / or expressions used to describe relationships between elements should be interpreted in a similar manner, such as "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. Furthermore, the term "connection" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. As used herein, the term "and / or" includes any and all combinations of one or more of the listed related items.

[0063] It should be noted that although the terms "first," "second," etc., may be used herein to describe various components, members, elements, regions, layers, and / or parts, these components, members, elements, regions, layers, and / or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and / or part from another. Thus, for example, the first component, first member, first element, first region, first layer, and / or first part discussed below may be referred to as a second component, second member, second element, second region, second layer, and / or second part without departing from the teachings of this disclosure.

[0064] For ease of description, spatial relation terms, such as “above,” “below,” “left,” “right,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figure. It should be understood that spatial relation terms are intended to cover other orientations of the device in use or operation besides those described in the figure. For example, if the device in the figure were inverted, an element described as “below” or “under” other elements or features would be oriented “above” or “on top” other elements or features.

[0065] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0066] This invention provides a display substrate, characterized in that the display substrate includes a first display area and a second display area formed on a substrate; a thin-film transistor layer disposed on the substrate and a planarization layer located on the side of the thin-film transistor layer facing away from the substrate; a plurality of first electrodes disposed in the first display area and a plurality of second electrodes disposed in the second display area, the first electrodes and second electrodes being located on the side of the planarization layer facing away from the substrate; a pixel defining layer disposed on the side of the first electrodes and second electrodes facing away from the substrate, the pixel defining layer including a plurality of first openings located in the first display area and a plurality of second openings located in the second display area, each first opening exposing at least a portion of a first electrode, and each second opening exposing at least a portion of a second electrode; a light-emitting layer disposed on the first openings and second openings; a plurality of third electrodes and fourth electrodes disposed on the side of the light-emitting layer facing away from the substrate, the third electrodes being located in the first display area and the fourth electrodes being located in the second display area; the orthographic projection of each third electrode on the substrate covers M orthographic projections of the first openings on the substrate, and the orthographic projection of the fourth electrode on the substrate covers N orthographic projections of the second openings on the substrate, wherein M is less than N.

[0067] Figure 1A and Figure 1B This is a plan view of a display substrate according to some exemplary embodiments of the present disclosure. (Refer to...) Figure 1A and Figure 1B The display substrate includes a first display region I and a second display region II formed on a substrate. The first display region I can be surrounded by the second display region II, or the second display region II can only surround a portion of the boundary of the first display region I. Figure 1A and Figure 1B As shown, the display substrate also has a peripheral wiring region III located on the substrate. The wiring region is used to provide electrical signals to the first display area I or the second display area II to ensure that the first display area I and the second display area II emit light and display normally.

[0068] Figure 2 for Figure 1A or Figure 1B A cross-sectional view of the connection between the first display area I and the second display area II. Figure 3A This is a top view of a portion of the adjacent junction of the first display area I and the second display area II. In one exemplary embodiment of the invention, as shown... Figure 2 As shown, a thin-film transistor layer 2 is formed on substrate 1. Thin-film transistor layer 2 specifically includes an active layer 21, a gate layer 22, a source layer 23, and a drain layer 24. Thin-film transistor layer 2 also includes signal traces 25 located on the same layer as the source layer 23 and the drain layer 24. Figure 3A As shown, the embodiments of this application exemplify only by using a TFT structure to represent the thin-film transistor layer 2. The actual thin-film transistor layers driving each pixel to emit light include, but are not limited to, nTmC (n and m are positive integers) pixel circuit structures such as 3T1C, 6T1C, 7T1C, and 9T1C. Furthermore, the signal trace 25 also includes different signal lines for transmitting a first power supply voltage signal (VDD) or a second power supply voltage signal (VSS). Exemplarily, the signal trace 25 includes a first signal line 251, which is electrically connected to the thin-film transistor layer 2 through a via structure 26 to transmit the power supply signal to different control transistors. Figure 3A Only one via structure 26 is shown as an example; in actual use, the position and number of via structures 26 are not limited. In addition, the thin-film transistor layer 2 also includes other functional layers, such as gate insulating layer, interlayer dielectric layer and inorganic passivation layer, which are functional films that play an insulating role. Figure 3A In the first display area I, the thin-film transistor layer 2 includes a first pixel circuit structure 2A disposed in the first display area I and a second pixel circuit structure 2B disposed in the second display area II. In the first display area I, the first pixel circuit structure 2A of each pixel is electrically connected to the first electrode 51 of its light-emitting unit structure through a first electrode via 31, thereby driving the first display area I to achieve display. In the second display area II, the second pixel circuit structure 2B of each pixel is electrically connected to the second electrode 52 of its light-emitting structure through a second electrode via 32, thereby driving the second display area II to achieve display.

[0069] In one exemplary embodiment of the present invention, a planarization layer 3 is further formed on the side of the thin-film transistor layer 2 away from the substrate 1. The display substrate also includes a first electrode 51 and a second electrode 52 disposed on the side of the planarization layer 3 away from the substrate 1. Figure 2The illustration only shows one first electrode 51 and two second electrodes 52, with the first electrode 51 located in a first display region I and the second electrodes 52 located in a second display region II. There are multiple first electrodes 51 and multiple second electrodes 52. On the side of the first electrode 51 and the second electrode 52 facing away from the substrate 1, a first pixel definition layer 41 and a second pixel definition layer 42 are simultaneously formed in the first region I and the second region II. The first pixel definition layer 41 defines multiple first openings in the first display region I, and the second pixel definition layer 42 defines multiple second openings in the second display region II. The first and second openings expose at least a portion of the first electrode 51 and the second electrode 52. A first light-emitting layer 61 located in the first display region I and a second light-emitting layer 62 located in the second display region II are also formed on the first and second openings. The display substrate also includes a third electrode 71 located in the first display region I and a fourth electrode 72 located in the second display region II, with the third electrode 71 and the fourth electrode 72 disposed on the side of the light-emitting layer 61 and the light-emitting layer 62 facing away from the substrate 1. The first electrode 51, the first light-emitting layer 61, and the third electrode 71 together form the pixel light-emitting unit structure in the first display area I, and the second electrode 52, the second light-emitting layer 62, and the fourth electrode 72 together form the pixel light-emitting unit structure in the second display area II. There are multiple third electrodes 71 and fourth electrodes 72. The orthographic projection of each third electrode 71 onto the substrate 1 covers M orthographic projections of the first opening onto the substrate 1, and the orthographic projection of each fourth electrode onto the substrate covers N orthographic projections of the second opening onto the substrate 1, where M is less than N.

[0070] In one exemplary embodiment of the present invention, such as Figure 3A As shown, in the first display area I, the orthogonal projection of the third electrode 71 onto the substrate 1 covers the orthogonal projections of 1, 3, or 6 first openings onto the substrate 1; in the second display area II, there is one fourth electrode 72, and the orthogonal projection of the fourth electrode 72 onto the substrate 1 covers the orthogonal projections of all second openings onto the substrate 1.

[0071] In one exemplary embodiment of the present invention, such as Figure 2 As shown, a third electrode trace 701 is also provided in the first display area I. It should be noted that the number of third electrode traces 701 is not limited in this embodiment. Figure 2 This is merely an exemplary cross-sectional view of the first display area I, showing only a partial cross-sectional view of one third electrode trace 701, and does not represent the actual length of the third electrode trace 701. Due to the high transmittance requirements in the first display area I, the lower signal trace 25 is prone to glare on the light-emitting side. Therefore, as... Figure 3AAs shown, in the first display area I, the orthogonal projection of the third electrode trace 701 onto the substrate 1 covers the orthogonal projection of the signal trace 25 in the thin-film transistor layer 2 onto the substrate 1. This arrangement minimizes the glare problem caused by the patterning of the third electrode 71 in the first display area I. It should be noted that... Figure 3A The dimensional projection coverage relationship between the third electrode 71 and the fourth electrode 72 is shown only as an example; the signal connected to the third electrode 71 will be described in other exemplary embodiments. In one exemplary embodiment of the invention, as... Figure 3B As shown, the third electrode 71 in the first display area I can be directly electrically connected to the fourth electrode 72 in the second display area II through protrusions 71A or 71C to receive the same voltage signal. Alternatively, the third electrode 71 can also be electrically connected to the fourth electrode 72 through the protrusion 71B of the third electrode trace 701. In this embodiment, the size and position of the protrusions are not limited, as long as they can electrically connect all the third electrodes 71 in the first display area I and the fourth electrode 72 in the second display area II.

[0072] In one exemplary embodiment of the present invention, such as Figure 4 As shown, in the first display area I, the third electrode 71 is electrically connected to the third electrode connection portion 800 and the third electrode trace 701. In addition, Figure 4 Different connection methods with different installation positions of the third electrode connection portion 800 are also exemplarily shown. For example... Figure 4 As shown, the orthographic projection of the third electrode connection portion 801 (800) on the substrate 1 covers the orthographic projection of the via structure 26 on the substrate 1. This arrangement minimizes glare caused by signal traces in the thin-film transistor layer. Exemplarily, the location of the third electrode connection portion in this embodiment can also be specially designed according to the actual display substrate traces, pixel aperture ratio, or transmittance requirements. Figure 4 As shown, the orthographic projection of the third electrode connection portion 802 (800) on the substrate 1 does not overlap with the orthographic projection of the via structure 26 on the substrate 1. Alternatively, the orthographic projection of the third electrode connection portion 803 (800) on the substrate 1 may also be located within the orthographic projection of the gate line of the gate layer 22 on the substrate. Alternatively, the orthographic projection of the third electrode connection portion 804 (800) on the substrate 1 does not overlap with the orthographic projection of the third electrode 71 on the substrate 1. With this arrangement, the transmittance of the pixel light-emitting unit corresponding to the third electrode 71 electrically connected thereto can be guaranteed not to be affected. In this embodiment, the number of third electrode connections is less than or equal to the number of first openings. Figure 4As shown, the third electrode 71 corresponding to the third electrode connection portion 804 exemplarily covers three first openings, corresponding to three pixel light-emitting units. This arrangement reduces the number of third electrode connection portions 804, further ensuring the transmittance requirement of the first display area I. Of course, in this embodiment, the number of openings covered by the third electrode 71 corresponding to the third electrode connection portion 804 can also be 1, 3, 6, etc. Similarly, Figure 4 The relationship between the third electrode 71, the third electrode trace 701, and the third electrode connection portion 800 in the first display area I is only described by way of example. The voltage signal transmitted by the third electrode 71 and its access position will be described in other embodiments.

[0073] In one exemplary embodiment of the present invention, such as Figure 2 As shown, the first signal line 251 is located on the side of the third electrode trace 701 near the substrate 1. A first electrode via 31 located in the first display area I and a second electrode via 32 located in the second display area II are disposed on the same layer as the first signal line 251. The first electrode 51 in the light-emitting unit structure of each pixel in the first display area I is electrically connected to its first pixel circuit structure 2A through the first electrode via 31. The second electrode 52 in the light-emitting unit structure of each pixel in the second display area II is electrically connected to its second pixel circuit structure 2B through the second electrode via 32.

[0074] like Figure 1C and Figure 1D As shown, in an exemplary embodiment of the present invention, a transition region IV is further provided between the first display area I and the second display area II. The transition region IV may be provided around the first display area I, or it may be provided only on one side or part of the side of the first display area I. The present invention does not limit this. Both the first display area I and the transition region IV are located in the under-display camera area. Figure 5A for Figure 1C or Figure 1D A top-view magnified view of the cross section BB at the junction of the first display area I, the transition area IV, and the second display area II. Figure 6A This is a cross-sectional view of the interface at the junction of the first display area I and the transition area IV. (See diagram below.) Figure 5A and Figure 6AAs shown, the light-emitting unit structure of the pixel in the first display area I is disposed in the first display area I, while the corresponding first pixel circuit structure 2A is disposed in the transition area. Specifically, there is also a transition pixel's orthogonal projection on the substrate between the orthogonal projection of the pixel light-emitting unit structure in the first display area I and the orthogonal projection of the corresponding first pixel circuit structure 2A on the substrate. The light-emitting unit structure and the transition pixel circuit structure 2C of the transition pixel are both disposed in the transition area. The light-emitting unit structure of the transition pixel specifically includes a fifth electrode 53, a third light-emitting layer 63, and a sixth electrode 73. By additionally setting a transition area IV between the first display area I and the second display area II, and setting the transition pixel and the first pixel circuit structure 2A in IV, the balance between the number of pixel units and the light transmittance in the under-display camera area can be further optimized. Setting the first display area I in the under-display camera area can ensure the required transmittance of the image captured by the camera, and additionally setting the transition area can improve the pixel resolution of the under-display camera area and avoid the pixel density of the under-display camera area from differing too much from the pixel density of the second display area II.

[0075] In one exemplary embodiment of the present invention, such as Figure 5A and Figure 6A As shown, the first electrode 51 of the pixel light-emitting unit structure disposed in the first display area I is electrically connected to the first signal line 251 through the first electrode via 31. The first signal line 251 extends from the first display area I into the transition area IV, and is electrically connected to the corresponding first pixel circuit structure 2A. A third electrode trace 701 is also formed on the side of the first signal line 251 away from the substrate 1. The third electrode trace 701 connects the third electrode 71 in the first display area I and the sixth electrode 73 in the transition area IV, and finally connects to the second display area II or the peripheral trace area III to receive the same electrode voltage (VSS) signal. In addition, the orthographic projection of the third electrode trace 701 on the substrate 1 overlaps with the orthographic projection of the signal trace 25 on the substrate 1. This arrangement can reduce the glare problem of the signal trace 25 in the first display area I and the transition area IV.

[0076] In one exemplary embodiment of the present invention, such as Figure 5B As shown, the third electrode 71 in the first display area I is electrically connected to the sixth electrode 73 in the transition area IV through the third electrode trace 701. It should be noted that in this embodiment, the sixth electrode 73 in the transition area IV and the fourth electrode 72 in the second display area II can be integrally formed in the same layer and with the same material to simplify the process and reduce the fabrication difficulty of the sixth electrode 73.

[0077] also, Figure 5B and Figure 6BThe diagram also shows signal traces 25 including two types, 25A and 25B. In an exemplary embodiment of the invention, signal trace 25A is used to transmit the signal of the first pixel circuit structure 2A to the first electrode 51; signal trace 25B is used to transmit the signal of the transition pixel circuit structure 2C to the fifth electrode 53. In this embodiment, the materials of signals 25A and 25B are inorganic metal oxides, such as indium tin oxide (ITO). Using inorganic metal oxides instead of traditional metals such as titanium, aluminum, and copper can reduce adverse effects such as metal glare and further improve transmittance. In this embodiment, the third electrode trace 701 can also be disposed on the same layer as signal traces 25A and 25B. Figure 6B (Not shown). Preferably, the third electrode trace 701, signal traces 25A and 25B can use the same inorganic metal oxide. Further, the third electrode 71 is transferred to the signal trace 25A layer via the third electrode connection portion 800, and then connected to the third electrode trace 701. Of course, as a possible alternative, the third electrode trace 701 can also be disposed between the signal trace 25 and the first electrode 51. This arrangement provides more sufficient trace space and reduces signal crosstalk between them.

[0078] Figure 7 for Figure 1A A cross-sectional view of the connection between the second display area II and the peripheral wiring area III. In the peripheral wiring area III, a second signal line 252 is disposed on the same layer as the signal line 25 to transmit the second power supply voltage (VSS) signal. In an exemplary embodiment of the present invention, the fourth electrode 72 of the second display area II is connected to the second signal line 252 via a second electrode wiring 502 to receive the second power supply voltage (VSS) signal transmitted by the second signal line 252. Specifically, as shown... Figure 7As shown. A first peripheral barrier 341 and a second peripheral barrier 342 are also provided in the peripheral trace area III. The first peripheral barrier 341 is formed in the same layer and with the same material as the second pixel definition layer 42 in the second display area II. The second peripheral barrier 342 includes a first raised portion 3421 and a second raised portion 3422. The first raised portion 3421 is formed in the same layer and with the same material as the planarization layer 3 in the second display area II. The second raised portion 3422 is formed in the same layer and with the same material as the second pixel definition layer 42 in the second display area II. Preferably, the orthographic projection of the first peripheral barrier 341 on the substrate 1 side completely falls within the orthographic projection of the second electrode trace 502 and the second signal line 252 on the substrate 1 side. The orthographic projection of the second peripheral barrier 342 on the substrate 1 side only partially overlaps with the orthographic projection of the second electrode trace 502 and the second signal line 252 on the substrate 1 side. Furthermore, the overlapping area is closer to the second display area II. This configuration ensures the overlap area between the second electrode trace 502 and the second signal line 252, reducing the risk of wire breakage. Simultaneously, it ensures that the first outer perimeter barrier 341 and the second outer perimeter barrier 342 effectively block external water and oxygen intrusion, preventing the second light-emitting layer 62 in the second display area II from malfunctioning.

[0079] Figure 8 for Figure 1B A cross-sectional view of the connection between the first display area I and the peripheral trace area III. In an exemplary embodiment of the present invention, the third electrode trace 701 of the first display area I directly overlaps with the second signal line 252 in the peripheral trace area III, and then connects to the first display area I, so that the patterned third electrode 71 in the first display area I is connected to the second power supply voltage (VSS) signal. In this embodiment, the orthographic projection of the third electrode trace 701 on the substrate 1 does not overlap with the orthographic projections of the first peripheral baffle 341 and the second peripheral baffle 342 on the substrate. Furthermore, in another embodiment of the present invention, as Figure 9 As shown, a third electrode trace 701 is also provided between the first outer perimeter barrier 341 and the second outer perimeter barrier 342 in the outer perimeter wiring area III. This arrangement can further shield the lower second signal line 252 to reduce glare. Of course, the third electrode trace 701 can also be omitted between the first outer perimeter barrier 341 and the second outer perimeter barrier 342 to improve the sealing effect of the barrier against water and oxygen.

[0080] In one exemplary embodiment of the present invention, when a transition region IV is further provided between the first display area I and the second display area II, the third electrode trace in the transition region IV can be connected to the signal trace 25 in the peripheral display area III, so that the patterned third electrode 71 in the first display area I can access the second power supply voltage (VSS) signal. Furthermore, when the fourth electrode 72 of the second display area II is connected to the second signal line 252 via the second electrode trace 502 and accesses the second power supply voltage (VSS) signal transmitted by the second signal line 252, the third electrode trace in the transition region IV can be connected to the fourth electrode 72 in the second display area II to access the same second power supply voltage (VSS) signal.

[0081] Based on the same inventive concept, embodiments of the present invention also provide a method for manufacturing a display substrate, comprising:

[0082] Provide a substrate 1;

[0083] Thin film transistor layer 2 and planarization layer 3 are sequentially formed on the substrate;

[0084] A thin-film transistor layer forms a first pixel circuit structure 2A in a first display area I on a substrate 1 and a second pixel circuit structure 2B in a second display area II on a substrate 1.

[0085] On the side of the planarization layer 3 facing away from the substrate 1, a plurality of first electrodes 51 located in the first display area I and a plurality of second electrodes 52 located in the second display area II are also formed.

[0086] A first light-emitting layer 61 is formed on the side of the first electrode 51 that is away from the substrate 1, and a second light-emitting layer 62 is formed on the side of the second electrode 52 that is away from the substrate 1.

[0087] A third electrode 71 is formed on the side of the first light-emitting layer 61 away from the substrate 1, and a fourth electrode 72 is formed on the side of the second light-emitting layer away from the substrate 1.

[0088] In an exemplary embodiment of the present invention, the step of forming a first light-emitting layer 61 on the side of the first electrode 51 facing away from the substrate 1 and forming a second light-emitting layer 62 on the side of the second electrode 52 facing away from the substrate 1 further includes forming a first pixel definition layer 41 located in the first display area I on the side of the first electrode 51 facing away from the substrate 1, and etching the first pixel definition layer 41 to form a plurality of first openings, each first opening exposing at least a portion of the first electrode 51 disposed therewith. A second pixel definition layer 42 located in the second display area II is also formed on the side of the second electrode 52 facing away from the substrate 1, and etching the second pixel definition layer 42 to form a plurality of second openings, each second opening exposing at least a portion of the second electrode disposed therewith.

[0089] In an exemplary embodiment of the present invention, the steps of forming a third electrode 71 on the side of the first light-emitting layer 61 facing away from the substrate 1 and forming a fourth electrode 72 on the side of the second light-emitting layer 62 facing away from the substrate 1 include: forming a first cathode material layer 711 on the side of the second light-emitting layer 62 facing away from the substrate 1 in the second display region II. The material of the first cathode material layer 711 can be a magnesium-silver alloy. Then, a second cathode material layer 712 is formed on the side of the first light-emitting layer 61 in the first display region I and the second light-emitting layer 62 in the second display region II facing away from the substrate. In the second display region II, the second cathode material layer 712 is located on the side of the first cathode material layer 711 facing away from the substrate. Only the second cathode material layer 712 is provided in the first display region I to ensure high transmittance of the first display region I. The material of the second cathode material layer 712 can be a high-transmittance metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO). Multiple third electrodes 71 are formed by laser cutting the cathode material layer 712 in the first display region I. The orthographic projection of each third electrode 71 on the substrate 1 covers the orthographic projections of M first openings on the substrate 1, and the orthographic projection of the fourth electrode 72 on the substrate 1 covers the orthographic projections of N second openings on the substrate 1. Where M is less than N. In an exemplary embodiment of the present invention, as... Figure 3A As shown, in the first display area I, the orthographic projection of the third electrode 71 onto the substrate 1 covers the orthographic projections of 1, 3, or 6 first openings onto the substrate 1; in the second display area II, there is one fourth electrode 72, and the orthographic projection of the fourth electrode 72 onto the substrate 1 covers the orthographic projections of all second openings onto the substrate 1. Only the third electrode 71 is laser-cut, while the fourth electrode 72 is not subsequently etched or cut after being formed by vapor deposition or sputtering. This can improve the manufacturing yield of the entire display substrate and reduce the risk of failure of the first light-emitting layer 61 and the second light-emitting layer 62 located near the substrate side.

[0090] In one exemplary embodiment of the present invention, a second cathode material layer 712 is formed on the side of the first light-emitting layer 61 and the second light-emitting layer 62 facing away from the substrate. The step of laser-cutting the second cathode material layer 712 in the first display area I to form a plurality of third electrodes 71 further includes: laser-cutting the second cathode material layer 712 in the first display area I to form a plurality of third electrode traces 701 and third electrode connection portions 800. The third electrodes 701 and third electrode connection portions 800 connect all the third electrodes 71 in the first display area I and connect them to the second power supply voltage (VSS) signal of the peripheral trace area III. Alternatively, the third electrodes 701 and third electrode connection portions 800 can also connect all the third electrodes 71 in the first display area I to the fourth electrode 72 in the second display area II to connect to the same second power supply voltage (VSS) signal. This scheme has been described in detail in other embodiments of the present invention, and will not be repeated in this embodiment.

[0091] In an exemplary embodiment of the present invention, a transition region IV is further formed on the substrate 1, located between the first display region I and the second display region II. A thin-film transistor layer 2 is formed on the substrate 1 with a second pixel circuit structure 2B in the second display region II, and a first pixel circuit structure 2A and a transition pixel circuit structure 2C in the transition region IV. A fifth electrode 53 is formed on the side of the transition pixel circuit structure 2C facing away from the substrate. The fifth electrode 53, the first electrode 51, and the second electrode 52 are formed in the same layer, with the same material, and in the same process. Preferably, the fifth electrode 53, the first electrode 51, and the second electrode 52 can be formed using indium tin oxide / silver / indium tin oxide (ITO / Ag / ITO) material. In the transition region IV, a third light-emitting layer 63 is also formed on the side of the fifth electrode 53 facing away from the substrate. Preferably, the third light-emitting layer 63 can be formed in the same step as the first light-emitting layer 61 and the second light-emitting layer 62 to save costs and improve display uniformity. It should be noted that although the first light-emitting layer 61, the second light-emitting layer 62, and the third light-emitting layer are formed in a unified step, this does not mean that the arrangement and configuration of the light-emitting unit structures in the three regions are the same. Of course, different photomasks can also be fabricated to form the light-emitting layers in the three regions separately. In this application, the light-emitting layer specifically includes at least one layer selected from hole injection, hole transport, organic light emission, electron transport, and electron injection. Furthermore, the three regions can be formed in any two pairs; for example, the first light-emitting layer 61 and the third light-emitting layer 63 can be formed together in the first display region I and the transition region IV, while the second light-emitting layer 62 in the second display region II can be formed separately. This invention does not limit this to any particular method.

[0092] In one exemplary embodiment of the present invention, a sixth electrode 73 located in the transition region IV is further formed on the side of the third light-emitting layer 63 facing away from the substrate 1. The sixth electrode 73 is fabricated in the same step as the third electrode 71 in the first display region I. Specifically, after the first cathode material layer 711 is formed in the second display region II, a second cathode material layer 712 is formed in the first display region I, the second display region II, and the transition region IV. Subsequently, the second cathode material layer 712 in the first display region I and the transition region IV is laser-cut to form a plurality of third electrodes 71 and sixth electrodes 73, respectively.

[0093] Based on the same inventive concept, embodiments of the present invention also provide a display panel, which includes the display substrate provided in any of the above embodiments.

[0094] The display panel also includes other necessary structures known to those skilled in the art, which will not be described in detail here.

[0095] Based on the same inventive concept, embodiments of the present invention also provide a display device, which includes the display panel provided in the above embodiments.

[0096] The display panel and display device have all the advantages of the display substrate provided in the above embodiments, and can be implemented by referring to any embodiment of the display substrate, which will not be described in detail here.

[0097] The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of this display device are readily understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the invention. Implementation of this display device can be found in the embodiments of the display panel described above; repeated details will not be elaborated upon.

[0098] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A display substrate, characterized by, The display substrate comprises a substrate; and a first display region and a second display region on the substrate; a thin film transistor disposed on the substrate and a planarization layer on a side of the thin film transistor away from the substrate, a signal trace disposed in the first display region and electrically connected to the thin film transistor; a plurality of first electrodes disposed in the first display region and a plurality of second electrodes disposed in the second display region, the first electrodes and the second electrodes being on a side of the planarization layer away from the substrate; a pixel definition layer disposed on a side of the first electrodes and the second electrodes away from the substrate, the pixel definition layer comprising a plurality of first openings in the first display region and a plurality of second openings in the second display region, each of the first openings exposing at least part of one of the first electrodes, and each of the second openings exposing at least part of one of the second electrodes; an emission layer disposed on the first openings and the second openings; a plurality of third electrodes and fourth electrodes disposed on a side of the emission layer away from the substrate, the third electrodes being in the first display region and the fourth electrodes being in the second display region; a projection of each of the third electrodes on the substrate covers projections of M of the first openings on the substrate, and a projection of the fourth electrodes on the substrate covers projections of N of the second openings on the substrate, wherein M is less than N; the display substrate further comprises a third electrode trace disposed in the first display region, the third electrode trace being on a side of the planarization layer away from the substrate; each of the third electrodes further comprises a third electrode connecting portion disposed one-to-one corresponding to the third electrode, the third electrode forms an electrical connection with the third electrode trace through the third electrode connecting portion, and the number of the third electrode connecting portions is less than or equal to the number of the first openings; a projection of the third electrode trace on the substrate overlaps a projection of the signal trace on the substrate, and the overlapping area is not less than 90%; the signal trace comprises a first signal line, the first signal line forms an electrical connection with the thin film transistor through a via structure, and a projection of the third electrode connecting portion on the substrate covers at least part of a projection of the via structure on the substrate; the display substrate further comprises a peripheral trace region around the display substrate, and the third electrode trace directly overlaps a second signal line of the peripheral trace region, so that the third electrode is connected to a second power voltage signal.

2. The display substrate of claim 1, wherein, M is equal to 1, N is greater than or equal to 2, and the number of the fourth electrodes is 1.

3. The display substrate of claim 1, wherein, The signal trace is disposed in the same layer as a source electrode and a drain electrode in the thin film transistor.

4. The display substrate of claim 1, wherein, The first display region and the second display region further comprise a transition region therebetween; the thin film transistor is provided with a first pixel circuit structure for driving the first display region to emit light and a transition pixel circuit structure for driving the transition region to emit light in the transition region.

5. The display substrate of claim 4, wherein, In the first display region, the first electrodes form an electrical connection with the first signal line through first electrode vias. The first signal line extends from the first display area to the transition area, and transmits a circuit signal of the first pixel circuit structure located in the transition area to the first electrode arranged correspondingly in the first display area. 6.The display substrate of claim 1, wherein, The fourth electrode is electrically connected with the second signal line through the third electrode trace, so as to access the second power voltage signal. 7.The display substrate of claim 6, wherein, The peripheral trace area is provided with a first peripheral barrier and a second peripheral barrier, a projection of the first peripheral barrier on the substrate side falls within the projection of the second electrode trace and the second signal line on the substrate side, and a projection of the second peripheral barrier on the substrate side only partially overlaps with the orthographic projection of the second electrode trace and the second signal line on the substrate side. 8.The display substrate of claim 7, wherein, The orthographic projection of the third electrode trace on the substrate side does not overlap with the first peripheral barrier and the second peripheral barrier.

9. The display substrate of claim 1, wherein a material of the third electrode, the fourth electrode, the third electrode trace, and the signal trace comprises at least one of indium tin oxide or indium zinc oxide. The fourth electrode further comprises at least one of magnesium or silver metal.

10. A method for manufacturing a display substrate according to any one of claims 1 to 9, characterized by, Comprising: providing a substrate; the substrate is provided with a first display area and a second display area; a thin film transistor layer and a planarization layer are sequentially formed on the substrate; the thin film transistor layer forms a first pixel circuit structure in the first display area on the substrate and a second pixel circuit structure in the second display area on the substrate; a plurality of first electrodes in the first display area and a plurality of second electrodes in the second display area are further formed on the side of the planarization layer away from the substrate; a first light emitting layer is further formed on the side of the first electrode away from the substrate, and a second light emitting layer is further formed on the side of the second electrode away from the substrate; a third electrode is formed on the side of the first light emitting layer away from the substrate, and a fourth electrode is further formed on the side of the second light emitting layer away from the substrate.

11. The manufacturing method of claim 10, wherein: the step of forming the third electrode on the side of the first light emitting layer away from the substrate and the fourth electrode on the side of the second light emitting layer away from the substrate comprises: forming a first cathode material layer on the side of the second light emitting layer away from the substrate in the second display area, and a material of the first cathode material layer comprises at least one of magnesium or silver; a second cathode material layer is formed on the side of the first light emitting layer in the first display area and the side of the second light emitting layer in the second display area away from the substrate, and in the second display area, the second cathode material layer is located on the side of the first cathode material layer away from the substrate; the second cathode material layer is laser cut in the first display area to form a plurality of third electrodes and third electrode traces.

12. The manufacturing method of claim 10, wherein: A transition region is further formed on the substrate, the transition region is located between the first display region and the second display region, and the first pixel circuit structure and a transition pixel circuit structure are arranged in the transition region; A fifth electrode, a third light-emitting layer and a sixth electrode are sequentially formed on a side of the transition pixel circuit structure away from the substrate.

13. The manufacturing method of claim 12, wherein: The sixth electrode is formed on a side of the transition pixel circuit structure away from the substrate, and specifically includes: forming a second cathode material layer in the transition region and the first display region; The second cathode material layer is laser cut to form the sixth electrode and the third electrode.

14. A display panel, characterized by A display substrate as claimed in any one of claims 1-9.

15. A display device comprising: A display panel as claimed in claim 14.

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