Chip and method of manufacturing the same

Abstract

The application discloses a chip and a manufacturing method thereof. The chip comprises a silicon wafer, an epitaxial layer and a barrier layer which are sequentially stacked. One side of the silicon wafer is provided with a groove, the epitaxial layer and the barrier layer are arranged on the side of the silicon wafer provided with the groove and cover the groove, and the barrier layer and the epitaxial layer directly below the barrier layer form a barrier region. The application increases the area of the barrier region by arranging the groove on the surface of the silicon wafer, thereby increasing the current density that the barrier region can withstand and reducing the forward voltage drop of the chip. Thus, the application has obvious advantages due to the low forward voltage drop under the same chip size, and the product competitiveness is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor integrated circuit manufacturing process, in particular to a chip and a manufacturing method thereof. BACKGROUND

[0002] With the rapid development of information society, as the most basic semiconductor devices of information industry, the semiconductor devices are also developing towards high performance and low cost, so that the market size and electrical performance of the semiconductor diodes are greatly improved. Whether the market demand or the device manufacturer, a new diode chip process is urgently expected to appear to meet the needs of low cost and high performance.

[0003] Miniaturization of chip area is a development trend, and the size of the chip has been made to 0.28*0.28mm; but the miniaturization of the chip must sacrifice the current characteristics, so that the current capacity of the chip in the unit area is reduced, resulting in the increase of the forward voltage drop in the chip. SUMMARY

[0004] The purpose of the present application is to provide a chip and a manufacturing method thereof to reduce the forward voltage drop in the chip.

[0005] The present application discloses a chip, comprising a silicon wafer, an epitaxial layer and a barrier layer, one side of the silicon wafer is provided with a groove, the epitaxial layer is arranged on the side of the silicon wafer provided with the groove and covers the groove; the barrier layer is arranged on the epitaxial layer and covers the groove; the barrier layer and the epitaxial layer directly below the barrier layer form a barrier region.

[0006] Optionally, the number of the grooves is multiple, and the multiple grooves are arranged in an array.

[0007] Optionally, the shape of the groove is one or more of hexagonal, square, rectangular and circular.

[0008] Optionally, the width of the groove is equal to the spacing between the adjacent two grooves.

[0009] Optionally, the top of the epitaxial layer is flush.

[0010] Optionally, the depth of the groove is 1-5um.

[0011] The present application also discloses a manufacturing method of the above chip, comprising the steps of:

[0012] forming an etching stop layer on the silicon wafer;

[0013] etching the etching stop layer to form an etching stop layer pattern;

[0014] etching the surface of the silicon wafer exposed by the etching barrier layer pattern to form a trench on the exposed surface of the silicon wafer; and

[0015] forming an epitaxial layer and a barrier layer on the surface of the silicon wafer with the trench in sequence.

[0016] Optionally, the etching the surface of the silicon wafer exposed by the etching barrier layer pattern to form a trench on the exposed surface of the silicon wafer further comprises the step of etching away all the etching barrier layer pattern.

[0017] Optionally, the forming the etching barrier layer on the silicon wafer specifically comprises:

[0018] polishing one surface of the high-purity single crystal silicon wafer and one surface of the low-purity single crystal silicon wafer respectively;

[0019] bonding the polished surface of the high-purity single crystal silicon wafer with the polished surface of the low-purity single crystal silicon wafer to form a bonded silicon wafer;

[0020] polishing the high-purity single crystal silicon wafer surface of the bonded silicon wafer; and

[0021] forming the etching barrier layer on the polished high-purity single crystal silicon wafer surface.

[0022] Optionally, the etching barrier layer comprises a silicon oxide film.

[0023] The present application sets a trench on the surface of the silicon wafer in the chip, so that the epitaxial layer subsequently set on the silicon wafer in the chip will be deposited in the trench, so that the bottom area of the epitaxial layer is increased, and the area of the entire barrier region is increased. Compared with the current scheme of not setting a groove on the back of the epitaxial layer, the area of the barrier region in the present application is increased, so that the current density that the barrier region can withstand is increased, resulting in a decrease in the forward voltage drop of the chip. Thus, under the same chip size, the present application has obvious advantages due to the lower forward voltage drop, so that the product competitiveness is improved. BRIEF DESCRIPTION OF DRAWINGS

[0024] The accompanying drawings are included to provide a further understanding of the embodiments of the present application, constitute a part of the specification, illustrate embodiments of the present application, and together with the text description serve to explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor. In the drawings:

[0025] Figure 1 is a schematic diagram of a chip provided by an embodiment of the present application;

[0026] Figure 2 is a schematic diagram of the relationship between the trench depth and the epitaxial layer thickness of a silicon wafer according to an embodiment of the present application;

[0027] Figure 3 is a schematic diagram of a silicon wafer in a chip according to an embodiment of the present application

[0028] Figure 4 is a schematic diagram of the arrangement of trenches in a silicon wafer according to an embodiment of the present application;

[0029] Figure 5 is a schematic diagram of a trench according to an embodiment of the present application;

[0030] Figure 6 is a flowchart of a chip manufacturing method according to an embodiment of the present application;

[0031] Figure 7 is a schematic diagram of the relationship between the bonding resistance of a silicon wafer and the surface roughness of the silicon wafer according to an embodiment of the present application;

[0032] Figure 8 is a schematic diagram of the relationship between the polishing depth of a silicon wafer surface and the defect distribution of the silicon wafer surface according to an embodiment of the present application;

[0033] Figure 9 is a schematic diagram of the relationship between the bonding resistance of a silicon wafer and the heating time according to an embodiment of the present application.

[0034] wherein 100, chip; 200, silicon wafer; 210, low-purity single crystal silicon wafer; 220, high-purity single crystal silicon wafer; 230, epitaxial layer; 240, barrier layer; 250, trench; 260, barrier region. DETAILED DESCRIPTION

[0035] It is to be understood that the terminology used herein is for the purpose of describing specific embodiments only and is not intended to be limiting. It is also possible that the terms "first", "second", etc. are used herein to describe various embodiments only and are not intended to be limiting.

[0036] In the description of the present application, the terms "first", "second", etc. are used only for the purpose of description, and should not be interpreted as indicating relative importance or implying the number of technical features indicated. Therefore, unless otherwise specified, the features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features; the meaning of "multiple" is two or more. The term "comprising" and any variation thereof means non-exclusive inclusion, and one or more other features, integers, steps, operations, units, components and / or combinations thereof can be present or added.

[0037] In addition, the terms of orientation or positional relationship indicated by "center", "transverse", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like are described based on the orientation or relative position relationship shown in the drawings, and are only for the convenience of the simplified description of the present application, and are not intended to indicate that the devices or elements indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0038] In addition, unless specifically defined and limited otherwise, the terms "mount", "connect", "connect" should be broadly understood, for example, can be fixed connection, can also be detachable connection, or integral connection; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through intermediate medium, or the communication between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0039] The present application will be described in detail below with reference to the drawings and optional embodiments.

[0040] As Figure 1 shown is a schematic diagram of a chip, as an embodiment of the present application, a chip 100 is disclosed, the chip 100 comprises a silicon wafer 200, and an epitaxial layer 230, a barrier layer 240 and other functional devices arranged on the silicon wafer 200, one side of the silicon wafer 200 is provided with a groove 250, the epitaxial layer 230 is arranged on the side of the silicon wafer 200 provided with the groove 250, and covers the groove 250; the barrier layer 240 is arranged on the epitaxial layer 230, and covers the groove 250; the barrier layer 240 and the epitaxial layer 230 directly below the barrier layer 240 form a barrier region 260. The present application sets the groove 250 on one side of the silicon wafer 200, that is, sets the groove 250 on the back of the epitaxial layer 230, so that after the barrier layer 240 is formed, the area of the whole barrier region 260 increases, and then the current density that the barrier layer 240 can withstand increases, according to the formula P=I 2 RIt is known that the power will also increase, thereby improving the performance of the chip 100; in addition, according to the formula U=2VT(W / 2LD) 2It can be seen that, in the formula, VT is a constant of 0.026V, W is the width of the high resistance region N-, and LD is the diffusion length. In this case, W does not change, and LD represents the surface area of the barrier region. When LD increases, the forward voltage drop U of the chip decreases. Taking a Schottky diode as an example, if the Schottky diode is normally turned on at 0.45V, if the forward voltage drop is large, it needs 0.7V to turn on, which means more electrical energy is needed. Therefore, by reducing the forward voltage drop of the chip 100, the electrical energy required to turn on the devices in the chip 100 is reduced. Therefore, the forward voltage drop of the chip 100 in the present application is lower under the same chip size, which has obvious advantages and improves the competitiveness of the product.

[0041] The prior art usually sets a groove on the front surface of the epitaxial layer (a groove is set in the film layer above the epitaxial layer) to achieve the effect of enhancing the withstand voltage, while the present application sets a groove on the silicon wafer, i.e. the back surface of the epitaxial layer, which can effectively increase the current density. As can be seen from Table 1 below, when the size of the chip is the same, when the back surface of the epitaxial layer has a groove, the current capacity is improved, the current density is also improved, and the forward voltage is reduced. This cannot be achieved by setting a groove on the front surface of the epitaxial layer.

[0042] Chip area Process feature Current capability Vf forward voltage 40 mile Epilayer backside no trench @36V 1A 0.455V 40 mile Epilayer backside with trench @36V 2A 0.446V

[0043] Table 1: Current density and forward voltage when the back surface of the epitaxial layer has a groove

[0044] As Figure 2 shown, it is a schematic diagram of the relationship between the groove depth and the thickness of the epitaxial layer on the silicon wafer, and Figure 2 it can be seen that the greater the depth of the groove, the thicker the thickness of the epitaxial layer. In chip manufacturing, the thicker the thickness of the epitaxial layer, the higher the manufacturing cost of the chip. In combination with Table 2, when the depth of the groove in the present application is 1-5um, the thickness of the epitaxial layer can meet the use requirements, and at the same time, the voltage distribution range is small, which is beneficial to reduce the voltage loss and reduce the cost proportion of the epitaxial layer. Further, when the depth of the groove is between 1-2um, the slope of the line segment in Figure 2 is the gentlest, the growth of the thickness of the epitaxial layer is relatively stable, and the quality of the film layer is good, so the cost of the epitaxial layer can be greatly reduced.

[0045] Epilayer um Voltage distribution range V Epilayer to substrate silicon cost ratio % 5 45-55 100 12 100-200 130 30 200-350 160 60 400-500 ＞200

[0046] Table 2: Voltage and cost corresponding to different thicknesses of the epitaxial layer

[0047] As Figure 3The diagram shows a silicon wafer 200. The surface of the silicon wafer 200 is provided with trenches 250. By simply setting the surface of the silicon wafer 200, without changing the manufacturing process of other films and devices in the chip 100, the area of ​​the barrier region 260 in the chip 100 can be increased, thus avoiding defects caused by changing other films and devices in the chip 100.

[0048] Specifically, the silicon wafer 200 in this application can be a bonded silicon wafer, formed by bonding a low-purity single-crystal silicon wafer 210 and a high-purity single-crystal silicon wafer 220. The trench 250 is disposed on the surface of the high-purity single-crystal silicon wafer 220, which can reduce the overall cost of the high-purity single-crystal silicon wafer. Because existing chip wafers are generally processed directly using high-purity single-crystal silicon, the substrate thickness of high-purity silicon material (semiconductor-grade single-crystal silicon material purity is 9N, and the single-crystal silicon content is not less than 99.9999999%) produced by existing 6-inch epitaxial technology is 625µm, while the final thickness of the chip after fabrication is only 100-300µm. This results in a waste of over 300µm of ineffective silicon substrate thickness, and the high cost of high-purity silicon material significantly increases production costs. This application reduces the cost of a low-purity single-crystal silicon wafer 210 by bonding a low-purity single-crystal silicon wafer 210... A bonded silicon wafer is formed by bonding a high-purity single-crystal silicon wafer (220) to a high-purity single-crystal silicon wafer. The thickness of the bonded silicon wafer is comparable to that of the original high-purity silicon substrate, ensuring that the thickness of the entire bonded silicon wafer meets the processing requirements. This allows the high-purity single-crystal silicon wafer to be processed smoothly, thereby reducing the overall thickness of the high-purity single-crystal silicon wafer. Since the material cost of low-purity single-crystal silicon material (semiconductor-grade single-crystal silicon material with a purity of 6N-7N and a single-crystal silicon content between 99.9999% and 99.99999%) is low, the material cost of the high-purity single-crystal silicon wafer is greatly reduced.

[0049] like Figure 4 The diagram shows a schematic of the arrangement of trenches 250 in a silicon wafer 200. The trenches 250 on the surface of the silicon wafer 200 are distributed in a grid-like array, meaning that the silicon wafer 200 has multiple rows of trenches 250, with equal distances between adjacent rows of trenches 250, and equal spacing between adjacent trenches 250 within each row. The trenches 250 cover the entire surface of the silicon wafer 200, resulting in a large number of trenches 250 and a uniform arrangement. This not only increases the area of ​​the barrier layer 240 but also ensures the uniformity of the trenches 250, thereby ensuring the uniformity of the current density. Of course, the trenches 250 in this application can also be randomly distributed on the surface of the silicon wafer 200, and the number of trenches 250 can also be only one. Furthermore, as... Figure 5As shown is a plan view of a groove, the shape of the groove 250 in the present application is honeycomb, that is, regular hexagon, so that the utilization rate of the groove 250 can reach a high degree; of course, the groove 250 can also be other regular polygons or circular, when the shape of the groove 250 is square, the spacing between two adjacent grooves 250 is equal to the width of the groove 250, so that the recessed and protruding parts on the silicon wafer are relatively uniform, which can increase the adsorption effect of the epitaxial layer on the silicon wafer. In addition, the depth of the groove 250 in the present application is 1-5um, since the thickness of the existing epitaxial layer 230 is generally about 5um, if the depth of the groove 250 is greater than the thickness of the epitaxial layer 230, the part of the epitaxial layer 230 located in the groove 250 will be lower than the surface of the silicon wafer 200, which is easy to cause functional defects of the epitaxial layer 230, and seriously affects the safety of the chip 100.

[0050] The top of the epitaxial layer 230 in the present application is flush, so that the thickness of the barrier layer 240 subsequently arranged above the epitaxial layer 230 is uniform, thereby making the current density flowing through the barrier layer 240 uniform.

[0051] As Figure 6 As shown is a flow chart of a chip manufacturing method, as another embodiment of the present application, a manufacturing method of the above-mentioned chip 100 is also disclosed, comprising the steps of:

[0052] S1: forming an etching stop layer on a silicon wafer;

[0053] S2: etching the etching stop layer to form an etching stop layer pattern;

[0054] S3: etching the exposed silicon wafer surface of the etching stop layer pattern to form a groove on the exposed silicon wafer surface;

[0055] S4: forming an epitaxial layer and a barrier layer covering the groove on the side of the silicon wafer with the groove.

[0056] In the S1 step, it also includes:

[0057] S11: polishing one side of a high-purity single crystal silicon wafer and one side of a low-purity single crystal silicon wafer, respectively;

[0058] S12: bonding the polished surface of the high-purity single crystal silicon wafer with the polished surface of the low-purity single crystal silicon wafer to form a bonded silicon wafer;

[0059] S13: polishing the high-purity single crystal silicon wafer side of the bonded silicon wafer;

[0060] S14: forming the etching stop layer on the high-purity single crystal silicon wafer side after polishing.

[0061] The silicon wafer in the present application is bonded by high-purity single crystal silicon wafer and low-purity single crystal silicon wafer, thereby saving the material cost of high-purity single crystal silicon wafer and being conducive to cost reduction.

[0062] In the S11 step, the surface of the silicon wafer is easy to contact with oxygen in the air to form an oxide layer or form a hydrophobic layer and other impurity layers during placement, which will affect the bonding between the silicon wafers; the current commonly used etching method is used to remove the impurity layer on the surface of the silicon wafer, which can simultaneously process all surfaces of the silicon wafer and has a faster processing rate, but the etching method is easy to make the surface of the etched silicon wafer not smooth enough, which affects the bonding effect of the silicon wafers. As shown in Table 3, 9 groups of silicon wafer bonding experiments, the surface of the untreated silicon wafer has an oxide layer or a surface hydrophobic layer and other impurity layers, under high-temperature bonding conditions, if two surfaces of two silicon wafers are not polished, it will lead to poor bonding effect. Therefore, the surface of the two silicon wafers is treated by polishing in the present application, and the two polished surfaces can be bonded well after being attached.

[0063]

[0064]

[0065] Table 3: Silicon-silicon bonding DOE experiment

[0066] As shown in Table 3, 9 groups of silicon wafer bonding experiments, the surface of the untreated silicon wafer has an oxide layer or a surface hydrophobic layer and other impurity layers, under high-temperature bonding conditions, if two surfaces of two silicon wafers are not polished, it will lead to poor bonding effect. Therefore, the surface of the two silicon wafers is treated by polishing in the present application, and the two polished surfaces can be bonded well after being attached. Figure 7 As shown in Table 3, 9 groups of silicon wafer bonding experiments, the surface of the untreated silicon wafer has an oxide layer or a surface hydrophobic layer and other impurity layers, under high-temperature bonding conditions, if two surfaces of two silicon wafers are not polished, it will lead to poor bonding effect. Therefore, the surface of the two silicon wafers is treated by polishing in the present application, and the two polished surfaces can be bonded well after being attached.

[0067] As shown in Table 3, 9 groups of silicon wafer bonding experiments, the surface of the untreated silicon wafer has an oxide layer or a surface hydrophobic layer and other impurity layers, under high-temperature bonding conditions, if two surfaces of two silicon wafers are not polished, it will lead to poor bonding effect. Therefore, the surface of the two silicon wafers is treated by polishing in the present application, and the two polished surfaces can be bonded well after being attached. Figure 8 As shown in Table 3, 9 groups of silicon wafer bonding experiments, the surface of the untreated silicon wafer has an oxide layer or a surface hydrophobic layer and other impurity layers, under high-temperature bonding conditions, if two surfaces of two silicon wafers are not polished, it will lead to poor bonding effect. Therefore, the surface of the two silicon wafers is treated by polishing in the present application, and the two polished surfaces can be bonded well after being attached.

[0068] Specifically, one side of the high-purity single crystal silicon wafer and one side of the low-purity single crystal silicon wafer are first subjected to rough polishing and then subjected to fine polishing; wherein the polishing depth of rough polishing is between 15-20um, and the polishing depth of fine polishing is between 5-10um. At this time, rough polishing can process the damage layer, scratch layer and spot layer on the surface of the silicon wafer, as the corresponding surface roughness of the three layers is high, which is not conducive to bonding, so all three layers need to be processed; and the three layers are processed by rough polishing because the polishing speed of rough polishing is fast, although the precision of rough polishing is not high, but combined with subsequent fine polishing, the surface of the silicon wafer can be polished at a faster speed, and the precision requirement of the silicon wafer surface for bonding can be met.

[0069] In the S11 step, the initial thickness of the high-purity single crystal silicon wafer is between 200-400um, which can ensure the performance of the high-purity single crystal silicon wafer as a chip substrate, and at the same time, it can prevent the high-purity single crystal silicon wafer from being easily broken during processing; the initial thickness of the low-purity single crystal silicon wafer can also be set to between 200-400um, which is equal to the initial thickness of the high-purity single crystal silicon wafer, thereby improving the uniformity of the bonded silicon wafer. Moreover, polishing the high-purity single crystal silicon wafer and the low-purity single crystal silicon wafer can clean the impurities on the surface of the silicon wafer, and can also improve the defect problem of the surface of the silicon wafer, preventing the defect from expanding under high temperature, so that the high-purity single crystal silicon wafer and the low-purity single crystal silicon wafer can be better combined.

[0070] Moreover, the high-purity single crystal silicon wafer and the low-purity single crystal silicon wafer are both N-type or P-type; in this way, the high-purity single crystal silicon wafer and the low-purity single crystal silicon wafer will not conflict with each other, and for the high-purity single crystal silicon wafer, the low-purity single crystal silicon wafer is equivalent to increasing the height of the high-purity single crystal silicon wafer, so that the bonded silicon wafer can be normally processed; and the PN junction will not be generated due to the different types of the two silicon wafers, and other abnormalities will not occur.

[0071] In the S12 step, the silicon wafer bonding needs to pre-bond the high-purity single crystal silicon wafer and the low-purity single crystal silicon wafer in the bonding chamber, and then heat treat the pre-bonded silicon wafer inside the bonding chamber, and simultaneously introduce nitrogen or argon gas to obtain a bonded silicon wafer. Figure 9As shown in the figure, the heating time also has an influence on the bonding resistance, the longer the heating time, the lower the bonding resistance, in the application, when the pre-bonding silicon wafer is at 900-1200℃, the heating time is 1-3 hours, which can effectively reduce the bonding resistance, so as to meet the bonding conditions; further, the heating time can be controlled in 1.5-2.5h, in this range, the bonding resistance is low and changes slowly, which can improve the bonding effect and save the heating time. In the application, nitrogen or argon is introduced during the heating process; the purpose of introducing nitrogen or argon is to protect the furnace tube from being polluted, so as to ensure the bonding quality and prevent pollution; wherein, the heat treatment time and the time of introducing gas are the same, which ensures the full bonding of the two silicon wafers, and makes the high-purity single crystal silicon wafer and the low-purity single crystal silicon wafer not be polluted by other gases in the whole heating process.

[0072] In the S2 step, the material of the etching stop layer can be silicon oxide, and the etching can be performed by using BOE (Buffered Oxide Etch). The BOE solution is mixed by hydrofluoric acid (49%) and water or ammonium fluoride and water. In the S3 step, the etching of the silicon wafer can be performed by using wet etching or dry etching. If the wet etching is used, the etching solution can be selected from a silicon etching solution. The silicon etching solution can be prepared by using nitric acid, hydrofluoric acid and glacial acetic acid in a ratio of 3:2:1. The silicon etching solution has a low cost, which is conducive to reducing the etching cost. In the S3 step, after the groove is etched, the etching stop layer pattern is etched, and then the subsequent epitaxial layer is prepared. Of course, the etching stop layer pattern can also be reserved to increase the depth of the groove. In the S4 step, after the epitaxial layer is formed, a barrier layer is formed on the surface of the epitaxial layer by using a metal sputtering process.

[0073] It should be noted that the limitations of each step involved in the present scheme do not limit the order of the steps without affecting the implementation of the specific scheme. The steps written in the front can be executed first, or executed later, or even executed at the same time, as long as the scheme can be implemented, it should be considered to belong to the protection scope of the present application.

[0074] The above content is a further detailed description of the present application in combination with specific optional embodiments, and the specific implementation of the present application cannot be limited to these descriptions. For ordinary skilled persons in the technical field to which the present application belongs, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, which should be considered to belong to the protection scope of the present application.

Claims

1. A chip, characterized in that, include: A silicon wafer, wherein a groove is provided on one side of the silicon wafer; An epitaxial layer is disposed on one side of the silicon wafer in which trenches are formed, and covers the trenches. The epitaxial layer is partially deposited in the trenches, and the depth of the trenches does not exceed the thickness of the epitaxial layer. A barrier layer is disposed on the epitaxial layer and covers the trench; The barrier layer and the epitaxial layer directly below the barrier layer form a barrier region. The top of the epitaxial layer is flush with the surface, and the depth of the trench is 1-5 μm.

2. The chip as described in claim 1, characterized in that, The number of trenches is multiple, and the multiple trenches are arranged in an array.

3. The chip as described in claim 2, characterized in that, The groove is one or more of the following shapes: hexagonal, square, rectangular, and circular.

4. The chip as described in claim 2, characterized in that, The width of the groove is equal to the distance between two adjacent grooves.

5. A method for manufacturing a chip as described in any one of claims 1 to 4, characterized in that, include: An etch barrier layer is formed on the silicon wafer; The etch barrier layer is etched to form an etch barrier layer pattern; Etching is performed on the silicon wafer surface exposed by the etch barrier layer pattern to form trenches on the exposed silicon wafer surface; as well as On one side of the silicon wafer where trenches are provided, an epitaxial layer and a barrier layer covering the trenches are formed sequentially. The top of the epitaxial layer is flush with the surface, and the depth of the trench is 1-5 μm.

6. The method for manufacturing a chip as described in claim 5, characterized in that, The step of etching the exposed silicon wafer surface of the etch barrier layer pattern to form trenches on the exposed silicon wafer surface also includes the step of etching away all of the etch barrier layer pattern.

7. The method for manufacturing a chip as described in claim 5, characterized in that, The formation of an etch barrier layer on the silicon wafer specifically includes: One side of a high-purity single-crystal silicon wafer and one side of a low-purity single-crystal silicon wafer are polished respectively. The polished surface of the high-purity single-crystal silicon wafer is bonded to the polished surface of the low-purity single-crystal silicon wafer to form a bonded silicon wafer. Polishing the surface of the high-purity single-crystal silicon wafer of the bonded silicon wafer; and The etching barrier layer is formed on the surface of the high-purity single-crystal silicon wafer after polishing.

8. The method for manufacturing a chip as described in any one of claims 5 to 7, characterized in that, The etch barrier layer comprises a silicon oxide film.

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