Chip packaging structure and manufacturing method therefor, and electronic device

Abstract

The present application provides a chip packaging structure and a manufacturing method therefor, and an electronic device. The chip packaging structure comprises: a substrate, a plurality of interposers, and a first chip that are sequentially stacked; the plurality of interposers are sequentially stacked in a direction from the substrate to the first chip; each interposer comprises a conductive pillar, and the conductive pillar penetrates the interposer where the conductive pillar is located in the thickness direction of the interposer; and at least part of the interposers each further comprises a device, and the device and the conductive pillar located in the same interposer are spaced apart from each other, and the device comprises at least one of a passive device and a second chip. In this way, the devices can be arranged in the interposers having a relatively large thickness, the size of the devices can be large or small, and the selection is relatively flexible, thereby increasing the flexibility of device design and even chip packaging structure design; a variety of different chip combination forms are also realized, reducing the limitation on the size of the chip, and the manufacturing process of through silicon vias of the second chip arranged in each interposer can also be removed, reducing the manufacturing cost of the chip packaging structure.

Description

A chip packaging structure, its fabrication method and electronic device

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410911640.1, filed on July 8, 2024, entitled "A Chip Packaging Structure, Its Manufacturing Method and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of chip technology, and in particular to a chip packaging structure, its manufacturing method, and an electronic device. Background Technology

[0004] Chip packaging typically integrates multiple bare dies onto the same substrate via a redistribution layer, allowing for higher packaging density and greater interconnect density. However, if at least some of the chips on the redistribution layer are stacked, the dimensions of all chips in the stack must be identical to facilitate interconnection and packaging, thus limiting chip size. Furthermore, through-silicon vias (TSVs) are required in the stacked chips for interconnection, increasing process complexity and hindering cost reduction. Summary of the Invention

[0005] This application provides a chip packaging structure, its manufacturing method, and an electronic device to solve the problem of chip size limitations and reduce the manufacturing cost of the chip packaging structure.

[0006] Firstly, embodiments of this application provide a chip packaging structure, comprising: a substrate, multiple interposers, and a first chip stacked sequentially. The multiple interposers are stacked sequentially along the direction from the substrate to the first chip. Each interposer includes a conductive pillar that penetrates the interposer along its thickness direction. At least a portion of the interposers also includes a device, which is separated from the conductive pillar within the same interposer. The device includes at least one of a passive device and a second chip. Thus, by setting multiple interposers between the first chip and the substrate, and because the interposers have a relatively large thickness, devices can be placed within at least a portion of the interposers, and the size of the devices can be large or small, offering greater flexibility and increasing the flexibility of device design and even chip packaging structure design. Furthermore, some of the chips stacked in the prior art can be placed within the interposers, reducing the number of first chips stacked on top of the interposers. This allows multiple chips of different sizes to be packaged together, achieving various chip combination forms, reducing limitations on chip size, and eliminating the need for through-silicon via (TSV) fabrication processes for second chips located within the interposers, thereby reducing the manufacturing cost of the chip packaging structure.

[0007] Optionally, the thickness of at least part of the interlayer is not less than 50 μm, and further, the thickness of at least part of the interlayer can be hundreds of μm. The specific thickness of the interlayer can be set according to actual needs and is not limited here.

[0008] The thickness of the device is no greater than the thickness of the interposer layer it is in. For example, the thickness of the device is less than the thickness of the interposer layer, or the thickness of the device is equal to the thickness of the interposer layer. This allows the device to be made up of various sizes, reducing the restrictions on device size and increasing the flexibility of device setup. It also makes full use of the space within the interposer layer.

[0009] Optionally, the surface of the device facing the first chip is designated as the first bonding surface, and the first bonding surface of the device within the same interposer is flush with the surface of the conductive pillar facing the first chip. This exposes the first bonding surface of the interposer with the device on the surface facing the first chip, facilitating bonding between the device and other structures to achieve the device's function. The surface of the device facing the substrate is designated as the second bonding surface, and the second bonding surface of the device within the same interposer is flush with the surface of the conductive pillar facing the substrate. This exposes the bonding surface of the interposer with the device on the surface facing the substrate, facilitating bonding between the device and other structures to achieve the device's function. For each interposer with the device, one or more devices may be disposed within the interposer, and each device may have at least one of the first and second bonding surfaces, depending on actual needs and not limited herein.

[0010] Optionally, the chip package structure may further include: a first wiring layer disposed between two adjacent interposers; the first wiring layer has a first interconnect portion, and conductive pillars in two adjacent interposers are connected through the first interconnect portion. Thus, the first interconnect portion can be used to connect conductive pillars disposed in different interposers; and, if devices are disposed in two adjacent interposers and need to be connected, a device in one interposer can be connected to a device in the adjacent other interposer through the first interconnect portion, thereby achieving connection between devices located in different interposers. It should be understood that the first wiring layer can be a single-layer structure or a multi-layer structure, which can be set according to the actual situation and is not limited here.

[0011] Optionally, the interposer closest to the substrate among multiple interposers is the first interposer. The chip packaging structure further includes a second redistribution layer and a first bonding portion disposed between the first interposer and the substrate. The first bonding portion is used to bond with bonding points on the side surface of the substrate facing the interposer. The second redistribution layer is provided with a second interconnect portion, and the conductive pillars in the first interposer are connected to the first bonding portion through the second interconnect portion. In this way, one end of the conductive pillar in the first interposer can be bonded to the bonding points on the side surface of the substrate facing the interposer through the corresponding second interconnect portion and the first bonding portion. When the other end of the conductive pillar in the first interposer is connected to the first chip through other structures, it is beneficial to realize the connection between the first chip and the substrate, and realize the function of the chip packaging structure. The first bonding portion can be, but is not limited to, solder balls, solder pillars, solder pads, or other structures used to realize bonding, which are not specifically limited here. It should be understood that the second redistribution layer can be a single-layer structure or a multi-layer structure, which can be set according to the actual situation and is not limited here.

[0012] Furthermore, the surface of the device facing the substrate is the second bonding surface. At least some of the bonding points on the second bonding surface of the devices within the first interposer are connected to the first bonding portion via second interconnect portions. That is, among all the second interconnect portions in the second redistribution layer, some second interconnect portions are connected to the conductive pillars within the first interposer, and some second interconnect portions are connected to the bonding points on the second bonding surface of the devices within the first interposer, thereby achieving the connection between the device and the substrate, and thus enabling signal transmission between the device and the substrate. The surface of the device facing the substrate is the first non-bonding surface. The first non-bonding surface of the devices within the first interposer is connected to the second redistribution layer, allowing the first non-bonding surface of the device to be fixed onto the second redistribution layer, thereby fixing the device and preventing positional displacement of the device during the fabrication of the chip packaging structure, thus improving the fabrication yield of the chip packaging structure.

[0013] Optionally, the interposer closest to the first chip among multiple interposers is the second interposer. The chip packaging structure further includes a third wiring layer and a second bonding portion disposed between the second interposer and the first chip. The second bonding portion is used to bond with bonding points on the surface of the first chip facing the interposer. The third wiring layer is provided with a third interconnect portion, and conductive pillars in the second interposer are connected to the second bonding portion through the third interconnect portion. In this way, one end of the conductive pillar in the second interposer can be bonded to bonding points on the surface of the first chip through the corresponding third interconnect portion and the second bonding portion. When the other end of the conductive pillar in the second interposer is connected to the substrate through other structures, it is beneficial to realize the connection between the first chip and the substrate, and realize the function of the chip packaging structure. The second bonding portion can be, but is not limited to, solder balls, solder pillars, solder pads, or other structures used to realize bonding, which are not specifically limited here. It should be understood that the third wiring layer can be a single-layer structure or a multi-layer structure, which can be set according to the actual situation and is not limited here.

[0014] Furthermore, the surface of the device facing the first chip is the first bonding surface. At least some of the bonding points on the first bonding surface of the devices within the second interposer are connected to the second bonding portion via a third interconnect portion. That is, among all the third interconnect portions in the third redistribution layer, some third interconnect portions are connected to the conductive pillars within the second interposer, and some third interconnect portions are connected to the bonding points on the first bonding surface of the devices within the second interposer, thereby achieving the connection between the device and the first chip, and thus enabling signal transmission between the device and the first chip. The surface of the device facing the first chip is the second non-bonding surface. The second non-bonding surface of the devices within the second interposer is connected to the third redistribution layer, allowing the second non-bonding surface of the device to be fixed onto the third redistribution layer, thereby fixing the device and preventing positional displacement of the device during the chip packaging structure fabrication process, thus improving the manufacturing yield of the chip packaging structure.

[0015] Secondly, embodiments of this application also provide a method for fabricating a chip package structure. This method is used to fabricate the chip package structure described in the first aspect and any embodiment thereof. The method may include: stacking multiple interposers on a substrate; fixing a first chip to the multiple interposers; wherein each interposer includes a conductive pillar that penetrates the interposer along its thickness direction; at least a portion of the interposers also includes a device, which is separated from the conductive pillar within the same interposer, and the device includes at least one of a passive device and a second chip. Thus, the fabricated chip package structure can increase the flexibility of device design and even chip package structure design, enabling various different chip combination forms, reducing limitations on chip size, and eliminating the need for the fabrication process of through-silicon vias (TSVs) of the second chip within the interposers, thereby reducing the fabrication cost of the chip package structure.

[0016] Optionally, the entire structure consisting of multiple interposers can be referred to as a composite interposer. In this case, the composite interposer can be formed first, and then fixedly attached to the substrate. The fabrication process of the composite interposer can include: forming each interposer separately; and stacking the interposers to form the composite interposer. By processing different interposers separately, the significant losses caused by chip quality issues during layer-by-layer processing in the later stages of the packaging process are reduced. If a quality problem is found in a device within a particular interposer, measures can be taken to resolve it before stacking, thereby improving the yield rate of the chip packaging structure.

[0017] Of course, the embodiments of this application are not limited to forming each intermediary layer first and then stacking and connecting them to form a composite intermediary layer. It can also be configured as follows: first, form an intermediary layer, and then form intermediary layers layer by layer on top of that intermediary layer until a predetermined number of intermediary layers are obtained, thereby obtaining a composite intermediary layer. This achieves the layer-by-layer formation of intermediary layers, and after the formation of a later intermediary layer, it can be stacked and connected with the intermediary layer in the previous layer. In other words, the embodiments of this application do not limit the manufacturing method of each intermediary layer in the composite intermediary layer; the above are merely two examples for illustration. Any method that can obtain a composite intermediary layer is applicable in this application.

[0018] Optionally, the manufacturing method further includes: forming a second wiring layer on the substrate before stacking multiple interposers on the substrate, and then forming multiple interposers on the second wiring layer; or forming a second wiring layer on the surface of multiple interposers, and then placing the second wiring layer and multiple interposers on the substrate, such that the second wiring layer is disposed between the multiple interposers and the substrate.

[0019] Optionally, the manufacturing method further includes: forming a third wiring layer on the multiple interposers before fixing the first chip on the multiple interposers, and fixing the first chip on the third wiring layer.

[0020] It should be understood that since the principle behind this manufacturing method is similar to that of the aforementioned chip packaging structure, the implementation and technical effects of this manufacturing method can be found in the implementation and technical effects of the aforementioned chip packaging structure, and the repetitions will not be repeated.

[0021] Thirdly, embodiments of this application also provide an electronic device, which may include: a housing, and a chip packaging structure as described in the first aspect and any of the embodiments described above; the chip packaging structure is disposed within the housing. Thus, by increasing the design flexibility and reducing the manufacturing cost of the chip packaging structure, the design flexibility of the electronic device is also increased, and the manufacturing cost is also reduced.

[0022] It should be understood that since the principle of solving the problem by the chip packaging structure of this electronic device is similar to that of solving the problem by the aforementioned chip packaging structure, the implementation and technical effects of this electronic device can be referred to the implementation and technical effects of the aforementioned chip packaging structure, and the repeated parts will not be repeated. Attached Figure Description

[0023] Figure 1 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0024] Figure 2 is a schematic diagram of a chip packaging structure provided in an embodiment of this application;

[0025] Figure 3 is a schematic diagram of another chip packaging structure provided in an embodiment of this application;

[0026] Figure 4 is a flowchart of a chip packaging structure provided in an embodiment of this application;

[0027] Figure 5 is a schematic diagram of the fabrication process of a composite interposer layer provided in an embodiment of this application;

[0028] Figure 6 is a schematic diagram of the fabrication process of an intermediary layer provided in an embodiment of this application. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0030] It should be noted that the same reference numerals in the accompanying drawings of this application denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all such modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0031] To facilitate understanding of the technical solutions provided in the embodiments of this application, the application scenarios will be explained first below.

[0032] The chip packaging structure proposed in this application can be applied to various electronic devices, such as smartphones, smart TVs, smart TV set-top boxes, personal computers (PCs), wearable devices, and smart broadband devices. It should be noted that the chip packaging structure proposed in this application is intended for application in these and any other suitable types of electronic devices, including but not limited to. Figure 1 exemplarily shows a schematic diagram of an electronic device. Referring to Figure 1, the electronic device may include: a housing 100, and a circuit board 200 disposed within the housing 100, with the chip packaging structure 300 disposed on the circuit board 200. The circuit board 200 can be a printed circuit board (PCB), but other types of circuit boards 200 are not limited here.

[0033] Typically, chip packaging structures integrate multiple bare dies onto the same substrate via a redistribution layer, achieving higher packaging density and greater interconnect density. For example, if at least some chips are stacked on top of the redistribution layer, the dimensions of each chip in the stack must be identical to facilitate connection and packaging, thus limiting chip size. Furthermore, through-silicon vias (TSVs) are required in the stacked chips for interconnection, increasing process complexity and hindering cost reduction.

[0034] Based on this, this application provides a chip packaging structure, which includes: a substrate, multiple interposers, and a first chip stacked sequentially. The multiple interposers are stacked sequentially along the direction from the substrate to the first chip. Each interposer includes a conductive pillar that penetrates the interposer along its thickness direction. At least a portion of the interposers also includes a device, which is separated from the conductive pillar within the same interposer. The device includes at least one of a passive device and a second chip. Thus, by setting multiple interposers between the first chip and the substrate, and because the interposers have a relatively large thickness, devices can be placed within at least a portion of the interposers, and the size of the devices can be large or small, offering greater flexibility and increasing the flexibility of device design and even chip packaging structure design. Furthermore, some of the chips stacked in the prior art can be placed within the interposers, reducing the number of first chips stacked on top of the interposers. This allows multiple chips of different sizes to be packaged together, achieving various chip combination forms, reducing limitations on chip size, and eliminating the need for through-silicon via (TSV) fabrication processes for second chips located within the interposers, thereby reducing the manufacturing cost of the chip packaging structure.

[0035] The chip packaging structure will be described below with reference to specific embodiments.

[0036] Figure 2 illustrates a schematic diagram of a chip packaging structure provided in this application. As shown in Figure 2, the chip packaging structure includes a substrate 30, a plurality of interposers 20 and a first chip 11 stacked sequentially. For ease of description, the whole composed of the plurality of interposers can be referred to as a composite interposer.

[0037] The substrate can be made of a material that can serve a load-bearing function, such as, but not limited to, silicon. The specific material can be chosen according to actual needs and is not limited here. Furthermore, the substrate can be a printed circuit board or various types of circuit boards to facilitate signal transmission.

[0038] Multiple first chips 11 can be provided. These first chips 11 can be stacked on the side of the composite interposer away from the substrate 30, or some first chips 11 can be stacked and some chips can be arranged side by side. The specific arrangement can be determined according to actual needs and is not limited here. Figure 2 shows two first chips 11 arranged side by side as an example, but this does not mean that the chip package structure only has two such first chips 11. The first chip 11 can be various types of chips known to those skilled in the art, such as, but not limited to, memory chips, logic chips, etc., and is not specifically limited here.

[0039] The number of interposer layers 20 can be at least two, such as two, three, four or more, depending on actual needs. Figure 2 illustrates this with two interposer layers 20 as an example. Each interposer layer 20 is stacked sequentially along the direction from the substrate 30 to the first chip 11, or it can be understood that multiple interposer layers 20 are stacked sequentially along the direction from the substrate 30 to the first chip 11 (as shown in the z-direction in Figure 2), or the direction from the first chip 11 to the substrate 30, thereby achieving the superposition and use of multiple interposer layers 20. Each interposer layer 20 includes a conductive post 40, which can penetrate the interposer layer 20 along its thickness direction (as shown in the z-direction in Figure 2). The thickness of the interposer layers 20 is generally large; at least some interposer layers 20 can have a thickness of not less than 50 μm, and further, at least some interposer layers 20 can have a thickness of hundreds of μm. The specific thickness of the interposer layers 20 can be set according to actual needs and is not limited here. It should be understood that in the embodiments of the application, the thickness refers to the length along the z-direction.

[0040] Furthermore, at least a portion of the interposer layer 20 also includes a device 12. The device 12 located within the same interposer layer 20 is separated from the conductive pillars. The device 12 includes at least one of a passive device 12 and a second chip. The passive device 12 may include, but is not limited to, resistors, inductors, capacitors, etc. The second chip may be various types of chips known to those skilled in the art, such as, but not limited to, a bridge chip for connecting two first chips 11 arranged side by side, a filter chip for increasing signal transmission effect, a heat dissipation chip for increasing heat dissipation effect, a power supply chip for providing a certain signal, or a control chip for switch control, etc. The device 12 may be a silicon-based device or a glass-based device. The specific configuration can be determined according to actual needs and is not specifically limited here.

[0041] Thus, due to the relatively large thickness of the interposer layer 20, it can accommodate both large and small devices 12, allowing for flexible selection of device 12 size and increasing the flexibility of device 12 design and even chip packaging structure design. Furthermore, when the sizes of the first chip 11 and the second chip in the device 12 are different, the second chip can be placed within at least a portion of the interposer layer 20, while the first chip 11 is placed on the side of the composite interposer layer facing away from the substrate 30. This reduces the number of first chips 11 stacked on the composite interposer layer and allows for the packaging of different sized first chips 11 and second chips together, enabling various chip combination forms, reducing limitations on chip size, and fully utilizing the space within the interposer layer 20, increasing the space utilization rate of the chip packaging structure and improving the chip integration density within the chip packaging structure. In addition, placing the second chip in the device within at least a portion of the interposer layer 20 can eliminate the need for through-silicon vias (TSVs) in the second chip, thereby reducing the manufacturing cost of the chip packaging structure.

[0042] It is worth noting that by placing a second chip within the interposer layer 20, good isolation can be created between chips with different needs and types, enabling advanced packaging to achieve functional leaps in the vertical direction and top-to-bottom packaging of chips of different sizes. It can also improve signal and thermal interference issues faced by high-density interconnects in multi-chip applications, thereby enhancing the reliability of the chip packaging structure. Furthermore, compared to connecting the first chip 11 to the substrate 30 via a redistribution layer, the conductive pillars 40 within the composite interposer layer can be used to connect the first chip 11 to the substrate 30. This shortens the electrical interconnect length, increases interconnect density, and makes it possible to integrate more functions within the same packaging structure. It also offers high flexibility, allowing for the combination of different types of chips and wiring layers as needed, thus broadening the boundaries of multi-chip integration.

[0043] The thickness of device 12 is not greater than the thickness of the interposer layer 20. For example, the thickness of device 12 is less than the thickness of the interposer layer 20, or the thickness of device 12 is equal to the thickness of the interposer layer 20. This allows the size of device 12 to be large or small, reducing the limitation on the size of device 12, thereby increasing the flexibility of device 12 setting, and also making full use of the space within the interposer layer 20.

[0044] For example, a chip typically includes: a substrate, a device layer and an interconnect layer sequentially disposed on the substrate (not shown). The device layer contains semiconductor devices, and the interconnect layer contains interconnect structures connected to the semiconductor devices for signal transmission between the semiconductor devices and external structures. The surface of the interconnect layer facing away from the device layer typically has pads, also known as bonding points, which enable bonding between the chip and other structures. The surface of the substrate facing away from the device layer may or may not have bonding points, depending on the specific requirements, and is not specifically limited here. In this case, the surface of the interconnect layer facing away from the substrate can be called the bonding surface. If the surface of the substrate facing away from the interconnect layer has bonding points, then this surface can also be called the bonding surface, and the chip has two opposing bonding surfaces. If the surface of the substrate facing away from the interconnect layer does not have bonding points, then this surface can be called the back surface or non-bonded surface, and the chip has opposing bonding and non-bonded surfaces. Similarly, device 12 can also have two opposite surfaces. The surface with bonding points can be called the bonding surface, and the surface without bonding points can be called the back surface or non-bonding surface. Therefore, device 12 can have two opposite bonding surfaces, or opposite bonding and non-bonding surfaces. The specific configuration can be set according to the actual situation, and no specific limitation is made here.

[0045] Based on this, if the surface of device 12 facing the first chip 11 is the first bonding surface m1, then for the conductive pillar 40 and device 12 located in the same interposer layer 20, the first bonding surface m1 of device 12 is flush with the surface of conductive pillar 40 facing the first chip 11. In this way, the surface of interposer layer 20 with device 12 facing the first chip 11 can expose the first bonding surface m1 of device 12, facilitating bonding of device 12 with other structures and realizing the function of device 12. Alternatively, if the surface of device 12 facing the substrate 30 is the second bonding surface m2, then for the conductive pillar 40 and device 12 located in the same interposer layer 20, the second bonding surface m2 of device 12 is flush with the surface of conductive pillar 40 facing the substrate 30. In this way, the surface of interposer layer 20 with device 12 facing the substrate 30 can expose the second bonding surface m2 of device 12, facilitating bonding of device 12 with other structures and realizing the function of device 12. In this context, for each intermediary layer 20 provided with device 12, there may be one or more devices 12 provided in the intermediary layer 20, and device 12 may have at least one of a first bonding surface m1 and a second bonding surface m2. The specific details can be determined according to actual needs and are not limited here.

[0046] For example, the chip package structure may further include: a first wiring layer 61, a second wiring layer 62, a third wiring layer 63, a first bonding portion 71 and a second bonding portion 72, which will be described in detail below.

[0047] First wiring layer: The first wiring layer 61 is disposed between two adjacent intermediate layers 20. The first wiring layer 61 has a first interconnect portion b1. The conductive posts 40 in the two adjacent intermediate layers 20 are connected through the first interconnect portion b1, as shown in Figure 2. Thus, the first interconnect portion b1 can connect conductive posts 40 disposed in different intermediate layers 20. Furthermore, if devices 12 are disposed in two adjacent intermediate layers 20 and need to be connected, the device 12 in one intermediate layer 20 can be connected to the device 12 in the adjacent intermediate layer 20 through the first interconnect portion b1, thereby achieving the connection of devices 12 located in different intermediate layers 20. It should be understood that the first wiring layer 61 can be a single-layer structure or a multi-layer structure, depending on the actual situation. It is not limited here, but Figure 2 illustrates a single-layer structure as an example of the first wiring layer.

[0048] Second wiring layer: If the interposer 20 closest to the substrate 30 among the multiple interposer layers 20 is referred to as the first interposer layer 21, the second wiring layer 62 and the first bonding portion 71 are both disposed between the first interposer layer 21 and the substrate 30. The first bonding portion 71 is used to bond with bonding points on the side surface of the substrate 30 facing the interposer layer 20. The first bonding portion 71 can be, but is not limited to, solder balls, solder pillars, solder pads, or other structures used to achieve bonding, and is not specifically limited here. The second wiring layer 62 is provided with a second interconnect portion b2, and the conductive pillars 40 in the first interposer layer 21 are connected to the first bonding portion 71 through the second interconnect portion b2. Thus, one end of the conductive post 40 within the first interposer layer 21 can be bonded to a bonding point on the side surface of the substrate 30 facing the interposer layer 20 via the corresponding second interconnect portion b2 and first bonding portion 71. When the other end of the conductive post 40 within the first interposer layer 21 is connected to the first chip 11 via other structures, it facilitates the connection between the first chip 11 and the substrate 30, thereby realizing the function of the chip packaging structure. It should be understood that the second redistribution layer 62 can be a single-layer structure or a multi-layer structure, which can be set according to the actual situation and is not limited here. Figure 2 illustrates the second redistribution layer 62 as a single-layer structure.

[0049] Furthermore, when the surface of device 12 facing the substrate 30 is the second bonding surface m2, at least some of the bonding points in the second bonding surface m2 of device 12 in the first interposer layer 21 are connected to the first bonding portion 71 through the second interconnect portion b2. That is, among all the second interconnect portions b2 in the second redistribution layer 62, some of the second interconnect portions b2 are connected to the conductive pillars 40 in the first interposer layer 21, and some of the second interconnect portions b2 are connected to the bonding points in the second bonding surface m2 of device 12 in the first interposer layer 21, thereby realizing the connection between device 12 and substrate 30, and thus realizing the transmission of signals between device 12 and substrate 30. When the surface of device 12 facing the substrate 30 is the first non-bonded surface, at least a portion of the first non-bonded surface of device 12 in the first interposer layer 21 can be connected to the second redistribution layer 62, so that the first non-bonded surface of device 12 can be fixed on the second redistribution layer 62, thereby fixing device 12 and preventing the position of device 12 from shifting during the fabrication of the chip packaging structure, thereby improving the fabrication yield of the chip packaging structure.

[0050] The third wiring layer: If the interposer 20 closest to the first chip 11 among the multiple interposer layers 20 is referred to as the second interposer layer 22, the third wiring layer 63 and the second bonding portion 72 are both disposed between the second interposer layer 22 and the first chip 11. The second bonding portion 72 is used to bond with the bonding points on the surface of the first chip 11 facing the interposer layer 20. The second bonding portion 72 can be, but is not limited to, solder balls, solder pillars, solder pads, or other structures used to achieve bonding, and is not specifically limited here. The third wiring layer 63 is provided with a third interconnect portion b3, and the conductive pillar 40 in the second interposer layer 22 is connected to the second bonding portion 72 through the third interconnect portion b3. In this way, one end of the conductive pillar 40 in the second interposer layer 22 can be bonded to the bonding points on the surface of the first chip 11 through the corresponding third interconnect portion b3 and the second bonding portion 72. When the other end of the conductive pillar 40 in the second interposer layer 22 is connected to the substrate 30 through other structures, it is beneficial to realize the connection between the first chip 11 and the substrate 30, and realize the function of the chip packaging structure. It should be understood that the third wiring layer 63 can be a single-layer structure or a multi-layer structure, which can be set according to the actual situation and is not limited here. Figure 2 is used as an example of the third wiring layer 63 being a single-layer structure.

[0051] Furthermore, when the surface of device 12 facing the first chip 11 is the first bonding surface m1, at least some of the bonding points in the first bonding surface m1 of device 12 in the second interposer layer 22 are connected to the second bonding portion 72 through the third interconnect portion b3. That is, among all the third interconnect portions b3 in the third redistribution layer 63, some third interconnect portions b3 are connected to the conductive pillars 40 in the second interposer layer 22, and some third interconnect portions b3 are connected to the bonding points in the first bonding surface m1 of device 12 in the second interposer layer 22, thereby realizing the connection between device 12 and the first chip 11, and thus realizing the transmission of signals between device 12 and the first chip 11. When the surface of device 12 facing the first chip 11 is the second unbonded surface, at least a portion of the second unbonded surface of device 12 in the second interposer 22 is connected to the third wiring layer 63, so that the second unbonded surface of device 12 can be fixed on the third wiring layer 63, thereby fixing device 12 and preventing the position of device 12 from shifting during the fabrication of the chip packaging structure, thereby improving the fabrication yield of the chip packaging structure.

[0052] Based on this, taking the first interposer layer 21 as an example, when a second redistribution layer 62 and a first redistribution layer 61 are provided, a device 12 can exist with a thickness substantially equal to the thickness of the first interposer layer 21. The bonding points of this device 12 on the second bonding surface m2 facing the substrate 30 are connected to the first bonding portion 71 via the second interconnect portion b2. The second non-bonding surface of this device 12 facing the first chip 11 is connected to the first redistribution layer 61. Alternatively, a device 12 can exist with a thickness substantially equal to the thickness of the first interposer layer 21. The bonding points of this device 12 on the first bonding surface m1 facing the first chip 11 are connected to the first interconnect portion b1. The first non-bonding surface of this device 12 on the substrate 30 side is connected to the second redistribution layer 62. Alternatively, a device 12 with a thickness substantially less than that of the interposer 20 can exist. The bonding points on the second bonding surface m2 of the device 12 facing the substrate 30 are connected to the first bonding portion 71 via the second interconnect portion b2. The second non-bonding surface of the device 12 facing the first chip 11 is connected to the first redistribution layer 61 via a fixing layer (not shown in FIG. 2). The fixing layer can be made of an adhesive insulating material, thereby fixing the device 12 to the first redistribution layer 61. Alternatively, a device 12 with a thickness substantially less than that of the interposer 20 can exist. The bonding points on the first bonding surface m1 of the device 12 facing the first chip 11 are connected to the first interconnect portion b1. The first non-bonding surface of the device 12 facing the substrate 30 is connected to the second redistribution layer 62 via a fixing layer. The fixing layer can be made of an adhesive insulating material, thereby fixing the device 12 to the second redistribution layer 62. Therefore, the first intermediary layer 21 can simultaneously contain all four types of devices 12, or contain only some of the four types of devices 12. The specific configuration can be determined according to actual needs and is not specifically limited here. Of course, the configuration of devices 12 in other intermediary layers 20 is similar to that in the first intermediary layer 21, and will not be described in detail here.

[0053] For example, a third chip (not shown) may be provided between the composite interposer and the first chip 11, or between the composite interposer and the substrate 30. This third chip can be a larger chip, for example, but not limited to: the size of the third chip being comparable to the size of the interposer 20, in which case the third chip itself can act as the interposer 20, enabling the connection between the composite interposer and the substrate 30 or between the composite interposer and the first chip 11; or, the size of the third chip being smaller than the size of the interposer 20, in which case this third chip can be considered as the device 12 mentioned above. This allows for more flexible chip packaging, enabling the co-packaging of chips of different sizes, types, and functions.

[0054] Figure 3 illustrates a schematic diagram of another chip packaging structure provided in this application. Referring to Figure 3, the chip packaging structure in this embodiment is basically the same as the chip packaging structure described in Figure 2 of the previous embodiment, except that at least one of the first super-wiring layer 61, the second super-wiring layer 62, and the third super-wiring layer 63 is not provided. For example, when no first super-wiring layer 61 is provided between any two adjacent interposer layers 20, the two adjacent interposer layers 20 can be directly connected, and the conductive posts 40 in the two adjacent interposer layers 20 are correspondingly provided and connected, thereby realizing signal transmission; or, a third bonding portion can be provided between two adjacent interposer layers 20 (not shown). The third bonding portion can realize the connection of the conductive posts 40 correspondingly provided in different interposer layers 20. The third bonding portion can be, but is not limited to, solder balls, solder posts, solder pads, or other structures used to achieve bonding, and is not specifically limited here.

[0055] When no second redistribution layer 62 is provided between the composite interposer and the substrate 30, a first bonding portion 71 may be provided between the composite interposer and the substrate 30. The first bonding portion 71 is directly connected to one end of the conductive post 40 in the first interposer 21, so that the conductive post 40 in the first interposer 21 can also be connected to the substrate 30 through the first bonding portion 71.

[0056] When no third wiring layer 63 is provided between the composite interposer and the first chip 11, a second bonding portion 72 is provided between the composite interposer and the first chip 11. The second bonding portion 72 can be directly connected to the other end of the conductive post 40 in the second interposer 22, so that the conductive post 40 in the second interposer 22 can be connected to the first chip 11 through the second bonding portion 72.

[0057] The configuration can be configured as follows: No first wiring layer 61 is provided between any two adjacent interposer layers 20, and no second wiring layer 62 is provided between the composite interposer layer and the substrate 30, but a third wiring layer 63 is provided between the composite interposer layer and the first chip 11 (not shown in the figure); or, no first wiring layer 61 is provided between any two adjacent interposer layers 20, and a second wiring layer 62 is provided between the composite interposer layer and the substrate 30, but a third wiring layer 63 is not provided between the composite interposer layer and the first chip 11 (not shown in the figure); or, a first wiring layer 61 is provided between any two adjacent interposer layers 20, but a second wiring layer 62 is not provided between the composite interposer layer and the substrate 30, and a third wiring layer 63 is not provided between the composite interposer layer and the first chip 11 (not shown in the figure); or, no first wiring layer 61 is provided between any two adjacent interposer layers 20, and a second wiring layer 62 is not provided between the composite interposer layer and the substrate 30, and a third wiring layer 63 is not provided between the composite interposer layer and the first chip 11, as shown in Figure 3. The specific settings can be configured according to actual needs, and are not limited here.

[0058] Furthermore, since a second wiring layer 62 is not provided, when the thickness of device 12 is approximately equal to the thickness of the interposer 20, and the surface of device 12 facing the substrate 30 is the first unbonded surface, the first unbonded surface of device 12 within the first interposer 21 does not need to be fixed to the second wiring layer 62. The dielectric material 82 filling the spaces between conductive pillars 40 and between conductive pillars 40 and device 12 can also serve to fix device 12. Similarly, when a third wiring layer 63 is not provided, and the surface of device 12 facing the first chip 11 is the second unbonded surface, the second unbonded surface of device 12 within the second interposer 22 does not need to be fixed to the third wiring layer 63. The dielectric material 82 filling the spaces between conductive pillars 40 and between conductive pillars 40 and device 12 can also serve to fix device 12. This further simplifies the chip packaging structure, simplifies the chip packaging process, and reduces the manufacturing cost of the chip packaging structure.

[0059] It should be understood that the chip packaging structure in this embodiment is similar to the chip packaging structure shown in Figure 2 of the previous embodiment. For details, please refer to the relevant descriptions in the previous embodiments. Repeated descriptions will not be repeated.

[0060] Figures 4 to 6 illustrate, by way of example, a fabrication process of a chip packaging structure provided in this application. Referring to Figure 4, the fabrication process may include:

[0061] Step 401: Stack multiple interposers on the substrate;

[0062] Step 402: Fix the first chip onto multiple interposers; wherein each interposer includes a conductive post that penetrates the interposer along its thickness direction; at least some interposers also include devices, which are separated from the conductive posts within the same interposer, and the devices include at least one of a passive device and a second chip.

[0063] For example, in step 401 above, the entire structure composed of multiple interposers can be referred to as a composite interposer. In this case, the composite interposer can be formed first, and then fixedly connected to the substrate. The fabrication process of the composite interposer may include: step s1, forming each interposer separately, as shown in Figure 5(a) and Figure 5(b); step s2, stacking and connecting the interposers, as shown in Figure 5(c), to form the composite interposer. Thus, by processing different interposers separately, the significant losses caused by chip quality problems during layer-by-layer processing in the later stages of the packaging process are reduced. If a quality problem is found in a device within a certain interposer, measures can be taken to resolve it before stacking, thereby improving the yield of the chip packaging structure.

[0064] Of course, the embodiments of this application are not limited to forming each intermediary layer first and then stacking and connecting them to form a composite intermediary layer. It can also be configured as follows: first, form an intermediary layer, and then form intermediary layers layer by layer on top of that intermediary layer until a predetermined number of intermediary layers are obtained, thereby obtaining a composite intermediary layer. This achieves the layer-by-layer formation of intermediary layers, and after the formation of a later intermediary layer, it can be stacked and connected with the intermediary layer in the previous layer. In other words, the embodiments of this application do not limit the manufacturing method of each intermediary layer in the composite intermediary layer; the above are merely two examples for illustration. Any method that can obtain a composite intermediary layer is applicable in this application.

[0065] In one example, a composite interposer layer includes two interposer layers 20, with a first overlay layer 61 between them. In step s1, the first overlay layer 61 can be formed on the surface of one of the two interposer layers 20, as shown in Figure 5(b), while the first overlay layer 61 is not formed on the surface of the other interposer layer 20, as shown in Figure 5(a). This results in the first overlay layer 61 being present in the middle of the stacked interposer layers 20. To facilitate differentiation between the two interposer layers 20, they are not connected in Figure 5(c), but in reality, they are connected. In step s2, the surface of the other interposer layer 20 without the first overlay layer 61 can be bonded to the first overlay layer 61 on one of the interposer layers 20, thereby achieving the stacked connection of the two interposer layers 20. Of course, when the first routing layer is a multi-layer structure and the intermediate layers 20 are formed and stacked, a portion of the first routing layer can be formed on one surface of each intermediate layer 20, and then the portions of the first routing layers on the surfaces of the two intermediate layers 20 are connected and stacked face to face, thereby realizing the stacked connection of the two intermediate layers 20.

[0066] For each intermediary layer, the specific formation process may include:

[0067] As shown in Figure 6(a), a photoresist layer 83 with a preset thickness is formed on the second redistribution layer 62 of the substrate. The photoresist layer 83 is then patterned to form a certain number of vias 84. Next, conductive material is deposited in the vias 84 by means of electroplating, but not limited to electroplating. Then, the photoresist layer 83 is removed to obtain multiple conductive pillars 40. The conductive pillars 40 are spaced apart to obtain the structure shown in Figure 6(b). The conductive material can be, but is not limited to, copper, aluminum, or other conductive materials.

[0068] As shown in Figure 6(c), a fixing layer 81 is formed at a portion of the gap between the conductive pillars 40. The fixing layer 81 can be made of materials such as polyimide, epoxy, resin, ABF resin, silicon, glass, and ceramic.

[0069] As shown in Figure 6(c), the non-bonding surface m2' of device 12 is fixed on the fixing layer 81 to fix device 12; if the bonding surface m1' of device 12 faces the substrate, device 12 can be placed directly on the second redistribution layer 62 instead of being fixed on the fixing layer 81, so as to prevent the fixing layer 81 from covering the bonding surface m1 of device 12, and the second interconnect portion b2 in the second redistribution layer 62 is connected to the bonding point in the bonding surface m1' of device 12;

[0070] Continuing as shown in Figure 6(c), the dielectric material 82 is filled such that the dielectric material 82 fills the gaps between adjacent conductive pillars 40 and between conductive pillars 40 and device 12.

[0071] As shown in Figure 6(d), grinding, chemical polishing and other treatments are performed to expose the bonding points that need to be electrically connected, such as the bonding points in the bonding surfaces of the conductive post 40 and at least some of the devices.

[0072] Continuing as shown in Figure 6(d), the substrate is removed to obtain the interposer layer 20.

[0073] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. A chip packaging structure, characterized in that, include: A substrate, multiple interposer layers, and a first chip are stacked sequentially, with the multiple interposer layers stacked sequentially along the direction from the substrate to the first chip; Each of the interposers includes a conductive post that penetrates the interposer along its thickness direction. The interposer layer at least partially includes devices, which are separated from the conductive pillars within the same interposer layer. The devices include at least one of a passive device and a second chip.

2. The chip packaging structure as described in claim 1, characterized in that, The thickness of at least part of the intermediate layer is not less than 50 μm.

3. The chip packaging structure as described in claim 1 or 2, characterized in that, The thickness of the device is no greater than the thickness of the interposer layer in which it is located.

4. The chip packaging structure as described in any one of claims 1-3, characterized in that, The surface of the device facing the first chip is the first bonding surface, and the first bonding surface of the device located in the same interposer layer is flush with the surface of the conductive pillar facing the first chip.

5. The chip packaging structure as described in any one of claims 1-3, characterized in that, The surface of the device facing the substrate is a second bonding surface, and the second bonding surface of the device located in the same interposer layer is flush with the surface of the conductive pillar facing the substrate.

6. The chip packaging structure according to any one of claims 1-5, characterized in that, The chip packaging structure further includes: a first rewiring layer disposed between two adjacent interposer layers; The first rewiring layer is provided with a first interconnection section, and the conductive pillars in two adjacent intermediate layers are connected through the first interconnection section.

7. The chip packaging structure according to any one of claims 1-6, characterized in that, The interposer layer closest to the substrate among the plurality of interposer layers is the first interposer layer; The chip packaging structure further includes: a second redistribution layer and a first bonding portion disposed between the first interposer layer and the substrate, wherein the first bonding portion is used to: bond with a bonding point on a side surface of the substrate facing the interposer layer; The second rewiring layer is provided with a second interconnection section, and the conductive post in the first interposer layer is connected to the first bonding section through the second interconnection section.

8. The chip packaging structure as described in claim 7, characterized in that, The surface of the device facing the substrate is a second bonding surface, and at least a portion of the bonding points of the device in the second bonding surface within the first interposer layer are connected to the first bonding portion through the second interconnect portion.

9. The chip packaging structure as described in claim 7, characterized in that, The surface of the device facing the substrate is a first unbonded surface, and the first unbonded surface of the device within the first interposer is connected to the second redistribution layer.

10. The chip packaging structure according to any one of claims 1-9, characterized in that, The intermediary layer that is closest to the first chip among the plurality of intermediary layers is the second intermediary layer; The chip packaging structure further includes: a third wiring layer and a second bonding portion disposed between the second interposer layer and the first chip, wherein the second bonding portion is used to: bond with a bonding point on one side surface of the first chip facing the interposer layer; The third wiring layer is provided with a third interconnection section, and the conductive post in the second interposer layer is connected to the second bonding section through the third interconnection section.

11. The chip packaging structure as described in claim 10, characterized in that, The surface of the device facing the first chip is a first bonding surface, and at least a portion of the bonding points of the device within the second interposer layer are connected to the second bonding portion through the third interconnect portion.

12. The chip packaging structure as described in claim 10, characterized in that, The surface of the device facing the first chip is a second unbonded surface, and the second unbonded surface of the device within the second interposer is connected to the third redistribution layer.

13. A method for fabricating a chip packaging structure, characterized in that, include: Multiple interposers are stacked on the substrate; The first chip is fixedly connected to the plurality of intermediary layers; Each of the interposers includes a conductive pillar that penetrates the interposer along its thickness direction; at least a portion of the interposers also include devices, which are separated from the conductive pillars within the same interposer, and the devices include at least one of a passive device and a second chip.

14. An electronic device, characterized in that, include: The housing and the chip packaging structure as described in any one of claims 1-12, wherein the chip packaging structure is disposed within the housing.

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