A chip system, a method for processing virtual interrupts, and a corresponding device

Abstract

The present application discloses a chip system, which is applied to the field of virtualization technology. The chip system includes a source physical processor, a control device, an intermediate device, a sending device, and a target physical processor. A host machine or a virtual machine runs on the source physical processor. A register in the control device receives information for triggering a virtual interrupt written by the host machine or the virtual machine, and the control device sends the information for triggering the virtual interrupt in the register to the intermediate device; the intermediate device triggers the virtual interrupt according to the information for triggering the virtual interrupt, and sends the virtual interrupt to the sending device; the sending device sends the virtual interrupt to the target physical processor. This solution is used to reduce the switching overhead from the virtual machine to the host machine or from the user state of the host machine to the kernel state of the host machine caused by virtual interrupts.

Description

Technical Field

[0001] This application relates to the field of virtualization technology, and particularly to a chip system, a method for processing virtual interrupts, and a corresponding device. Background Art

[0002] Virtual interrupt is an essential part of virtualization technology. A virtual machine (VM) runs on a computer device. Notifications from hardware devices such as disks and input / output (I / O) devices in the computer device to the virtual machine, as well as various synchronization and coordination operations within the virtual machine, all rely on virtual interrupts. A virtual interrupt is an event, and such events can have various sources. Different sources will result in different processing procedures for the event, but each event of this type from a certain source will be notified to the virtual machine in the form of an interrupt received during the operation of the virtual machine.

[0003] Regardless of the source of the virtual interrupt, before the virtual interrupt finally reaches the virtual machine, the host needs to use its own various mechanisms to complete the work of sending the virtual interrupt from the source to the destination virtual machine. During the process of sending this virtual interrupt, it is necessary for the control flow of the processor to switch from the virtual machine being executed to the host, or from the user state of the host to the kernel state of the host, resulting in a relatively large switching overhead. Summary of the Invention

[0004] Embodiments of this application provide a chip system, a method for processing virtual interrupts, and a corresponding device, which are used to reduce the switching overhead from the virtual machine to the host, or from the user state of the host to the kernel state of the host caused by virtual interrupts. Embodiments of this application also provide corresponding computer devices, computer storage media, computer program products, etc.

[0005] In a first aspect of this application, a chip system is provided, including: a source physical processor, a control device, an intermediate device, a sending device, and a target physical processor. The source physical processor is used to run the host or the virtual machine. The control device includes a register, and the register is used to receive information for triggering a virtual interrupt. The information for triggering a virtual interrupt can come from the host or the virtual machine. The control device is used to: send the information for triggering a virtual interrupt in the register to the intermediate device; the intermediate device is used to: trigger a virtual interrupt according to the information for triggering a virtual interrupt, and send the virtual interrupt to the sending device; the sending device is used to: receive the virtual interrupt from the intermediate device, and send the virtual interrupt to the target physical processor.

[0006] In this application, the chip system may be a system on chip (SOC). The source physical processor and the target physical processor may each be a processing unit, such as a physical core. The control device, the intermediate device, and the sending device may all be implemented by hardware circuits or by software. The source physical processor and the target physical processor may be physical cores in a multi-core processor. The multi-core processor includes multiple physical cores. The physical core is a core integrated in the processor, and the physical core is a type of processing unit. For example, a dual-core processor can be understood as a processor with two physical cores. The control device and the sending device may be deployed in the multi-core processor and coupled to the source physical processor and the target physical processor. The intermediate device may be deployed in the multi-core processor or on a peripheral device / peripheral component coupled to the multi-core processor. The system on chip may include a multi-core processor and a peripheral device / peripheral component coupled to the multi-core processor. Any physical processor in the chip system may serve as either the source physical processor or the target physical processor.

[0007] In this application, a virtual interrupt refers to an interrupt sent to a virtual machine (VM) by a hardware device, a host computer, the clock of the virtual machine, or the virtual processor of the virtual machine, etc., in a computer device. The hardware device that generates the virtual interrupt may be a disk, a network card, a sound card, a mouse, a hard disk, etc., in the computer device. A physical interrupt refers to an interrupt sent by a hardware device to a physical processor. The physical interrupt is processed by the host computer, while the virtual interrupt is processed by the virtual machine.

[0008] It should be noted that a specific implementation of the virtual processor mentioned in various embodiments of this application may be a virtual central processing unit (vCPU). The subsequent mention of "vCPU" may also be understood by replacing it with "virtual processor".

[0009] In this application, virtual interrupts may include virtual local interrupts, virtual software interrupts, virtual device interrupts, and direct peripheral interrupts. Among them, a virtual local interrupt refers to an interrupt issued by a virtual local device simulated by a virtual machine or a local device of a certain vCPU of the virtual machine. For example, a clock interrupt issued by a timer of a certain vCPU of the virtual machine. A virtual software interrupt is triggered by software, usually an interrupt sent from one vCPU of a virtual machine to another vCPU of the same virtual machine. A virtual machine can have multiple vCPUs, and these vCPUs can run on different physical processors at a certain moment to execute different tasks of the virtual machine. When there are dependencies or scheduling requirements between the tasks executed by different vCPUs, a virtual software interrupt will occur. A virtual device interrupt refers to an interrupt triggered by a host computer simulating a hardware device. For example, an interrupt generated by the host computer simulating a virtual machine disk controller or other hardware devices.

[0010] In this application, the control device may include at least one register. Each register may be used to receive a type of information for triggering a virtual interrupt. For example, there are three registers. One register is used to receive information for triggering a virtual local interrupt, one register is used to receive information for triggering a virtual software interrupt, and one register is used to receive information for triggering a virtual device interrupt. Of course, in this control device, only one register may also be configured for virtual interrupts. Since the information for triggering each type of virtual interrupt is different, the type of virtual interrupt can be identified by the information received by the register.

[0011] There may be one or more intermediate devices. The sending device may be one sending device for each physical processor, or multiple physical processors may share one sending device.

[0012] As can be seen from the first aspect above, a register dedicated to processing virtual interrupts is provided in the control device. In this way, a host machine or a virtual machine in the user state or the kernel state can directly write the information for triggering a virtual interrupt into this register. The control device can send the information for triggering the virtual interrupt to an intermediate device, and the intermediate device triggers the virtual interrupt. Moreover, the intermediate device sends the virtual interrupt to a sending device, and the sending device sends the virtual interrupt to a target physical processor. In the solution provided in this application, both the host machine and the virtual machine can directly access the register and write the information for triggering the virtual interrupt into the register, so as to send out the virtual interrupt. Therefore, compared with the prior art, the solution provided in this application does not require the source physical processor to execute the switch from the virtual machine to the host machine, nor does it require the source physical processor to execute the switch from the user state of the host machine to the kernel state of the host machine, thus reducing the switching overhead generated by processing the virtual interrupt and improving the performance of the chip system.

[0013] In a possible implementation manner of the first aspect, the virtual interrupt is a virtual local interrupt, and the target physical processor and the source physical processor are the same physical processor. The register is used for: receiving the information for triggering the virtual local interrupt written by the virtual machine; the sending device is used for: sending the virtual local interrupt to the first virtual central processing unit (vCPU) of the virtual machine, and the first vCPU runs on the source physical processor.

[0014] In this possible implementation manner, since the virtual local interrupt is an in-core interrupt, the target physical processor and the source physical processor are the same physical processor. The intermediate device can be a timer, and the virtual local interrupt can be a clock interrupt. A physical processor will only run one vCPU of one virtual machine at a time. Sending the virtual local interrupt to this vCPU can complete the operation of sending the virtual local interrupt to the virtual machine. As can be seen from this possible implementation manner, the process of processing this virtual local interrupt does not require the source physical processor to execute the switch from the virtual machine to the host machine, thus reducing the switching overhead generated by processing the virtual local interrupt and improving the performance of the chip system.

[0015] In a possible implementation of the first aspect, the virtual interruption is a virtual software interruption, and the information used to trigger the virtual interruption includes the identifier of the second vCPU written by the first vCPU of the virtual machine to the register, where the second vCPU is the vCPU of the virtual machine running on the target physical processor; the control device is configured to: read the identifier of the second vCPU from the register and obtain the identifier of the virtual machine; and send the identifier of the virtual machine and the identifier of the second vCPU to the intermediate device; the intermediate device is configured to: determine the target physical processor corresponding to the identifier of the virtual machine and the identifier of the second vCPU from the first correspondence; where the first correspondence is used to record the correspondence between the target physical processor, the second vCPU running on the target physical processor, and the virtual machine; send the virtual software interruption to the sending device corresponding to the target physical processor; the sending device is configured to: send the virtual software interruption to the second vCPU running on the target physical processor.

[0016] In this possible implementation, the virtual software interrupt is an interrupt sent from the first vCPU of a virtual machine to the second vCPU of the same virtual machine. Therefore, when the first vCPU of the virtual machine needs to trigger this virtual software interrupt, it needs to write the identifier of the second vCPU into a register. A virtual machine can have multiple vCPUs. The vCPUs belonging to the same virtual machine can run on a physical processor in a time-sharing multiplexing manner. For example, on physical processor 1, first run vCPU1 of virtual machine 1. After physical processor 1 finishes running vCPU1, it can then run vCPU2 of virtual machine 1. Multiple vCPUs belonging to the same virtual machine can also run on different physical processors. At a certain moment, different vCPUs can run on different physical processors. For example, vCPU1 of virtual machine 1 runs on physical processor 1, and vCPU2 of virtual machine 1 runs on physical processor 2. In the scenario of this virtual software interrupt, the first vCPU runs on the source physical processor, and the second vCPU runs on the target physical processor. The control device can obtain the identifier of the virtual machine from the register dedicated to storing the identifier of the virtual machine running on the source physical processor. Because each virtual machine can have multiple vCPUs, and the identifiers of vCPUs of different virtual machines may be the same, the control device needs to send the identifier of the virtual machine and the identifier of the second vCPU to the intermediate device. The above-mentioned first correspondence can be stored on the intermediate device. This first correspondence can be located in the in-position vCPU identifier group, which records the correspondence between each physical processor in the chip system, the vCPUs running on each physical processor, and the virtual machines to which the running vCPUs belong. This application can target the physical processor by looking up the in-position vCPU identifier group. As can be seen from this possible implementation, the process of handling this virtual software interrupt does not require the source physical processor to perform a switch from the virtual machine to the host, thereby reducing the switching overhead generated by handling the virtual software interrupt and improving the performance of the chip system.

[0017] In a possible implementation of the first aspect, the virtual interrupt is a virtual device interrupt. The information used to trigger the virtual interrupt includes the target interrupt number written by the host to the register and the identifier of the virtual machine. The target interrupt number is the identifier of the interrupt triggered when the host simulates a hardware device; the control device is configured to: read the target interrupt number and the identifier of the virtual machine from the register, and send the identifier of the virtual machine and the target interrupt number to the intermediate device; the intermediate device is configured to: according to the identifier of the virtual machine and the target interrupt number, look up in the second correspondence relationship the identifier of the first vCPU of the virtual machine corresponding to the identifier of the virtual machine and the target interrupt number. The second correspondence relationship is used to record the correspondence relationship among the virtual machine, the target interrupt number, and the first vCPU; according to the identifier of the virtual machine and the identifier of the first vCPU, determine from the third correspondence relationship the target physical processor corresponding to the identifier of the virtual machine and the identifier of the first vCPU; wherein, the third correspondence relationship is used to record the correspondence relationship among the target physical processor, the first vCPU running on the target physical processor, and the virtual machine; send the virtual device interrupt to the sending device corresponding to the target physical processor; the sending device is configured to: send the virtual device interrupt to the first vCPU running on the target physical processor.

[0018] In this possible implementation, the virtual device interrupt is an interrupt triggered by the host in the user state simulating a hardware device. There can be multiple types of hardware devices, and the interrupt numbers of each type of hardware device are different. If the host simulates a disk, then the target interrupt number is the interrupt number of the disk. Since the host can manage multiple virtual machines, the host needs to write the identifier of the virtual machine and the target interrupt number to the register. The second correspondence relationship can be located in the interrupt affinity table. This interrupt affinity table can be configured by the virtual machine, so there is an interrupt affinity table for each virtual machine. In this way, the interrupt affinity table of the virtual machine can be found according to the identifier of the virtual machine, and then the corresponding vCPU can be determined from the interrupt affinity table of the virtual machine according to the target interrupt number. The target interrupt number is 10. If in the interrupt affinity table, interrupt number 10 corresponds to vCPU ID1, then it can be determined that the vCPU ID corresponding to the target interrupt number is 1. After the routing device determines that the vCPU ID is 1, it can find the physical processor corresponding to this vCPU ID1 according to the in-place vCPU identifier group. The meaning of the in-place vCPU identifier group can be understood by referring to the description in the foregoing virtual software interrupt part. The third correspondence relationship can also be understood by referring to the foregoing first correspondence relationship. It can be seen from this possible implementation that the process of processing this virtual device interrupt does not require the source physical processor to perform a switch from the user state of the host to the kernel state of the host, thereby reducing the switching overhead generated by processing the virtual device interrupt and improving the performance of the chip system.

[0019] In a possible implementation of the first aspect, the intermediate device includes an address register, which is used to store the address of the second correspondence in the memory and the identifier of the virtual machine; the intermediate device is further configured to: find the address register according to the identifier of the virtual machine, and obtain the second correspondence from the memory according to the address in the address register.

[0020] In this possible implementation, the above-mentioned interrupt affinity table can be stored in the intermediate device or in the memory. One address register can be provided for each physical processor in the intermediate device. The address register can be a base address register, and the base address register can store the address of the interrupt affinity table in the memory and the identifier of the virtual machine. This can avoid occupying too much storage space of the intermediate device.

[0021] In a possible implementation of the first aspect, the sending device is configured to: write the virtual interrupt into the pending register of the target physical processor, and the pending register is used to receive the commands of the process executed by the target physical processor.

[0022] In this possible implementation, the pending register is used to receive the commands that the target physical processor will execute next. By writing the virtual interrupt into the pending register, the target physical processor will execute the virtual interrupt next, which can interrupt the currently executing process, thereby shielding the action of switching to the host in the existing solution. This reduces the switching overhead of the target physical processor from the virtual machine to the host.

[0023] The second aspect of the present application provides a chip system, which includes a source physical processor, a control device, an intermediate device, a sending device, and a target physical processor. The source physical processor is used to run the host or the virtual machine; the chip system further includes a hardware device for direct communication between virtual machines; the intermediate device is configured to: receive the passthrough peripheral interrupt triggered by the hardware device; find the corresponding identifier of the virtual machine and the virtual interrupt number from the virtual interrupt table according to the physical interrupt number of the passthrough peripheral interrupt. The virtual interrupt table records the correspondence between the physical interrupt number and the identifier of the virtual machine and the virtual interrupt number; determine the corresponding interrupt affinity table according to the identifier of the virtual machine, and determine the identifier of the target virtual processor vCPU corresponding to the identifier of the virtual machine and the virtual interrupt number from the interrupt affinity table. The interrupt affinity table records the correspondence between the virtual interrupt number and the virtual processor; determine the target physical processor corresponding to the identifier of the target vCPU from the in-use vCPU identifier group according to the identifier of the target vCPU; send the passthrough peripheral interrupt to the sending device corresponding to the target physical processor. The sending device sends the passthrough peripheral interrupt to the virtual machine running on the target physical processor.

[0024] In this second aspect, the direct-pass external device interrupt refers to an interrupt triggered by an external device directly passed to the virtual machine, such as an interrupt generated by a graphics card directly passed to the virtual machine. During the process of handling the direct-pass external device interrupt, the virtual interrupt table, the interrupt affinity table, and the in-place vCPU identification group are used in sequence. The interrupt affinity table and the in-place vCPU identification group can be understood by referring to the descriptions in the possible implementation manners of the first aspect above. The virtual interrupt table is introduced below. The virtual interrupt table maintains the correspondence between the physical interrupt number and the identification of the virtual machine and the virtual interrupt number. Inputting a physical interrupt number can output the identification of the virtual machine and the virtual interrupt number. During the process of handling the direct-pass external device interrupt, the intermediate device receives the physical interrupt number sent by the direct-pass external device, and looks up the corresponding identification of the virtual machine and the virtual interrupt number in the virtual interrupt table through this physical interrupt number. For example: inputting a physical interrupt number 100 can output the identification 1 of the virtual machine and the virtual interrupt number 10. Then, according to the identification 1 of the virtual machine and the virtual interrupt number 10, the interrupt affinity table is looked up, and the corresponding vCPU ID is found, such as: the vCPU ID is found to be 1. Further, according to this vCPU ID, the corresponding physical processor is looked up in the in-place vCPU identification group, such as: the physical processor 1 is found, then the intermediate device can send the direct-pass external device interrupt to the sending device corresponding to the physical processor 1, and the sending device sends the direct-pass external device interrupt to the vCPU corresponding to the vCPU ID1.

[0025] The processing process of the direct-pass external device interrupt provided in this second aspect can complete the sending process through the lookup of three correspondences, improving the flexibility of handling the direct-pass external device interrupt.

[0026] A third aspect of the present application provides a control device, which is applied to a chip system. The chip system further includes a source physical processor, an intermediate device, and a sending device. The source physical processor is used to run the host machine or the virtual machine. The control device includes a register; the register is used to receive the information for triggering the virtual interrupt, and the information for triggering the virtual interrupt comes from the host machine or the virtual machine; the control device is used to: read the information for triggering the virtual interrupt from the register, and send the information for triggering the virtual interrupt to the intermediate device. The information for triggering the virtual interrupt is used to enable the intermediate device to trigger the virtual interrupt, and the virtual interrupt is sent by the sending device to the target physical processor.

[0027] In a possible implementation of the third aspect, the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, and the register is used to receive the information written by the virtual machine for triggering the virtual local interrupt; the control device is configured to: send the information for triggering the virtual local interrupt to the intermediate device, and the information for triggering the virtual local interrupt is used to cause the intermediate device to trigger the virtual local interrupt, and the virtual local interrupt is sent by the sending device to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.

[0028] In a possible implementation of the third aspect, the virtual interrupt is a virtual software interrupt, and the information for triggering the virtual interrupt includes the identifier of the second vCPU written by the first VCPU of the virtual machine to the register, and the second vCPU is the vCPU of the virtual machine running on the target physical processor; the control device is configured to: read the identifier of the second vCPU from the register, and obtain the identifier of the virtual machine; and send the identifier of the virtual machine and the identifier of the second vCPU to the intermediate device, and the identifier of the virtual machine and the identifier of the second vCPU are used for the intermediate device to determine the target physical processor and trigger the virtual software interrupt, and the virtual software interrupt is sent by the sending device to the second vCPU of the target physical processor.

[0029] In a possible implementation of the third aspect, the virtual interrupt is a virtual device interrupt, and the information for triggering the virtual interrupt includes the target interrupt number written by the host to the register and the identifier of the virtual machine, and the target interrupt number is the identifier of the interrupt triggered when the host simulates the hardware device; the control device is configured to: read the target interrupt number and the identifier of the virtual machine from the register, and send the identifier of the virtual machine and the target interrupt number to the intermediate device, and the identifier of the virtual machine and the target interrupt number are used for the intermediate device to determine the target physical processor and trigger the virtual device interrupt, and the virtual device interrupt is sent by the sending device to the first vCPU of the virtual machine of the target physical processor.

[0030] A fourth aspect of the present application provides an intermediate device, which is applied to a chip system. The chip system further includes a source physical processor, a control device, a sending device, and a target physical processor. The source physical processor is used to run the host or the virtual machine, and the control device includes a register; the register is used to receive the information for triggering the virtual interrupt, and the information for triggering the virtual interrupt comes from the host or the virtual machine; the intermediate device is configured to: receive the information for triggering the virtual interrupt from the control device, trigger the virtual interrupt according to the information for triggering the virtual interrupt, and send the virtual interrupt to the sending device, and the virtual interrupt is sent by the sending device to the target physical processor.

[0031] In a possible implementation of the fourth aspect, the virtual interruption is a virtual local interruption, the target physical processor and the source physical processor are the same physical processor, and the register is used to receive the information written by the virtual machine for triggering the virtual local interruption; the intermediate device is configured to: trigger the virtual local interruption according to the information for triggering the virtual local interruption, and send the virtual local interruption to the sending device, and the virtual local interruption is sent by the sending device to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.

[0032] In a possible implementation of the fourth aspect, the virtual interruption is a virtual software interruption, and the information for triggering the virtual interruption includes the identifier of the second vCPU written by the first vCPU of the virtual machine to the register, and the second vCPU is the vCPU of the virtual machine running on the target physical processor; the intermediate device is configured to: receive the identifier of the virtual machine and the identifier of the second vCPU from the control device; determine the target physical processor corresponding to the identifier of the virtual machine and the identifier of the second vCPU from the first corresponding relationship according to the identifier of the virtual machine and the identifier of the second vCPU, where the first corresponding relationship is used to record the corresponding relationship among the target physical processor, the second vCPU running on the target physical processor, and the virtual machine; trigger the virtual software interruption; send the virtual software interruption to the sending device corresponding to the target physical processor, and the virtual software interruption is sent by the sending device to the second vCPU of the target physical processor.

[0033] In a possible implementation of the fourth aspect, the virtual interruption is a virtual device interruption, and the information for triggering the virtual interruption includes the target interrupt number written by the host to the register and the identifier of the virtual machine, and the target interrupt number is the identifier of the interruption triggered when the host simulates a hardware device; the intermediate device is configured to: receive the identifier of the virtual machine and the target interrupt number from the control device; search for the identifier of the first vCPU of the virtual machine corresponding to the identifier of the virtual machine and the target interrupt number in the second corresponding relationship according to the identifier of the virtual machine and the target interrupt number, where the second corresponding relationship is used to record the corresponding relationship among the virtual machine, the target interrupt number, and the first vCPU; determine the target physical processor corresponding to the identifier of the virtual machine and the identifier of the first vCPU from the third corresponding relationship according to the identifier of the virtual machine and the identifier of the first vCPU, where the third corresponding relationship is used to record the corresponding relationship among the target physical processor, the first vCPU running on the target physical processor, and the virtual machine; trigger the virtual device interruption; send the virtual device interruption to the sending device corresponding to the target physical processor, and the virtual device interruption is sent by the sending device to the first vCPU of the target physical processor.

[0034] In a possible implementation of the fourth aspect, the intermediate device includes an address register, which is used to store the address of the second correspondence in the memory and the identifier of the virtual machine; the intermediate device is further configured to: find the address register according to the identifier of the virtual machine, and obtain the second correspondence from the memory according to the address in the address register.

[0035] The fifth aspect of the present application provides a sending device, which is applied to a chip system. The chip system further includes a source physical processor, an intermediate device, and a target physical processor control device. The source physical processor is used to run a host or a virtual machine. The control device includes a register; the register is used to receive information for triggering a virtual interruption, and the information for triggering the virtual interruption comes from the host or the virtual machine; the sending device is used to: receive the virtual interruption from the intermediate device and send the virtual interruption to the target physical processor.

[0036] In a possible implementation of the fifth aspect, the virtual interruption is a virtual local interruption, and the target physical processor and the source physical processor are the same physical processor; the sending device is used to: receive the virtual local interruption from the intermediate device and send the virtual local interruption to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.

[0037] In a possible implementation of the fifth aspect, the virtual interruption is a virtual software interruption, and the information for triggering the virtual interruption includes the identifier of the second vCPU written by the first vCPU of the virtual machine into the register, and the second vCPU is the vCPU of the virtual machine running on the target physical processor; the sending device is used to: receive the virtual software interruption from the intermediate device and send the virtual software interruption to the second vCPU running on the target physical processor.

[0038] In a possible implementation of the fifth aspect, the virtual interruption is a virtual device interruption, and the information for triggering the virtual interruption includes the target interruption number written by the host into the register and the identifier of the virtual machine, and the target interruption number is the identifier of the interruption triggered when the host simulates a hardware device; the sending device is used to: receive the virtual device interruption from the intermediate device and send the virtual device interruption to the first vCPU running on the target physical processor.

[0039] In a possible implementation of the fifth aspect, the sending device is used to: write the virtual interruption into the pending register of the target physical processor, and the pending register is used to receive commands of the process executed by the target physical processor.

[0040] For the features and corresponding intended effects described in the above third aspect to fifth aspect, and any possible implementation thereof, reference may be made to the description in the first aspect and any possible implementation of the first aspect for understanding, and will not be repeated here.

[0041] A sixth aspect of the present application provides a method for processing virtual interrupts. The method is applied to a control device in a chip system, and the chip system further includes a source physical processor, an intermediate device, a sending device, and a target physical processor. The source physical processor is used to run a host or a virtual machine, and the control device includes a register. The register is used to receive information for triggering a virtual interrupt, and the information for triggering the virtual interrupt comes from the host or the virtual machine. The method includes: reading the information for triggering the virtual interrupt from the register; sending the information for triggering the virtual interrupt to the intermediate device, and the information for triggering the virtual interrupt is used for the intermediate device to trigger a virtual interrupt, and the virtual interrupt is sent by the sending device to the target physical processor.

[0042] In a possible implementation of the sixth aspect, the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, and the register is used to receive information for triggering the virtual local interrupt written by the virtual machine; the information for triggering the virtual local interrupt is used to cause the intermediate device to trigger a virtual local interrupt, and the virtual local interrupt is sent by the sending device to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.

[0043] In a possible implementation of the sixth aspect, the virtual interrupt is a virtual software interrupt, and the information for triggering the virtual interrupt includes the identifier of the second vCPU written by the first VCPU of the virtual machine to the register, and the second vCPU is the vCPU of the virtual machine running on the target physical processor; the method further includes: obtaining the identifier of the virtual machine; sending the identifier of the virtual machine to the intermediate device, and the identifier of the virtual machine and the identifier of the second vCPU are used for the intermediate device to determine the target physical processor and trigger a virtual software interrupt, and the virtual software interrupt is sent by the sending device to the second vCPU of the target physical processor.

[0044] In a possible implementation of the sixth aspect, the virtual interrupt is a virtual device interrupt, and the information for triggering the virtual interrupt includes the target interrupt number written by the host to the register and the identifier of the virtual machine, and the target interrupt number is the identifier of the interrupt triggered when the host simulates a hardware device; the identifier of the virtual machine and the target interrupt number are used for the intermediate device to determine the target physical processor and trigger a virtual device interrupt, and the virtual device interrupt is sent by the sending device to the first vCPU of the target physical processor.

[0045] A seventh aspect of the present application provides a method for processing virtual interrupts. This method is applied to an intermediate device in a chip system, and the chip system further includes a source physical processor, a control device, a sending device, and a target physical processor. The source physical processor is used to run a host or a virtual machine. The control device includes registers; the registers are used to receive information for triggering a virtual interrupt, and the information for triggering the virtual interrupt comes from the host or the virtual machine. The method includes: receiving the information for triggering the virtual interrupt from the control device; triggering the virtual interrupt according to the information for triggering the virtual interrupt; and sending the virtual interrupt to the sending device, and the virtual interrupt is sent by the sending device to the target physical processor.

[0046] In a possible implementation of the seventh aspect, the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, and the register is used to receive the information for triggering the virtual local interrupt written by the virtual machine; the information for triggering the virtual local interrupt is used to trigger the virtual local interrupt, and the virtual local interrupt is sent by the sending device to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.

[0047] In a possible implementation of the seventh aspect, the virtual interrupt is a virtual software interrupt, and the information for triggering the virtual interrupt includes the identifier of the second vCPU written by the first vCPU of the virtual machine into the register. The second vCPU is the vCPU of the virtual machine running on the target physical processor; the above step: triggering the virtual interrupt according to the information for triggering the virtual interrupt includes: determining the target physical processor corresponding to the identifier of the virtual machine and the identifier of the second vCPU from the first corresponding relationship; where the first corresponding relationship is used to record the corresponding relationship between the target physical processor, the second vCPU running on the target physical processor, and the virtual machine; triggering the virtual software interrupt, and the virtual software interrupt is sent by the sending device to the second vCPU of the target physical processor.

[0048] In a possible implementation of the seventh aspect, the virtual interrupt is a virtual device interrupt. The information used to trigger the virtual interrupt includes the target interrupt number written by the host to the register and the identifier of the virtual machine. The target interrupt number is the identifier of the interrupt triggered when the host simulates a hardware device. The above step of triggering the virtual interrupt according to the information used to trigger the virtual interrupt includes: according to the identifier of the virtual machine and the target interrupt number, searching in the second correspondence relationship for the identifier of the first vCPU of the virtual machine corresponding to the identifier of the virtual machine and the target interrupt number. The second correspondence relationship is used to record the correspondence relationship among the virtual machine, the target interrupt number, and the first vCPU; according to the identifier of the virtual machine and the identifier of the first vCPU, determining from the third correspondence relationship the target physical processor corresponding to the identifier of the virtual machine and the identifier of the first vCPU. The third correspondence relationship is used to record the correspondence relationship among the target physical processor, the first vCPU running on the target physical processor, and the virtual machine; triggering the virtual device interrupt, and the virtual device interrupt is sent by the sending device to the first vCPU of the target physical processor.

[0049] In a possible implementation of the seventh aspect, the method further includes: searching for the address register according to the identifier of the virtual machine, and obtaining the second correspondence relationship from the memory according to the address in the address register. The address register is used to store the address of the second correspondence relationship in the memory and the identifier of the virtual machine.

[0050] The eighth aspect of the present application provides a method for processing virtual interrupts. The method is applied to a sending device in a chip system. The chip system further includes a source physical processor, an intermediate device, a control device, and a target physical processor. The source physical processor is used to run the host or the virtual machine. The control device includes a register. The register is used to receive the information used to trigger the virtual interrupt. The information used to trigger the virtual interrupt comes from the host or the virtual machine. The method includes: receiving the virtual interrupt from the intermediate device; sending the virtual interrupt to the target physical processor.

[0051] In a possible implementation of the eighth aspect, the virtual interrupt is a virtual local interrupt, and the target physical processor and the source physical processor are the same physical processor. The above step of sending the virtual interrupt to the target physical processor includes: sending the virtual local interrupt to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.

[0052] In a possible implementation of the eighth aspect, the virtual interrupt is a virtual software interrupt. The information used to trigger the virtual interrupt includes the identifier of the second vCPU written by the first vCPU of the virtual machine to the register. The second vCPU is the vCPU of the virtual machine running on the target physical processor. The above step of sending the virtual interrupt to the target physical processor includes: sending the virtual software interrupt to the second vCPU running on the target physical processor.

[0053] In a possible implementation of the eighth aspect, the virtual interrupt is a virtual device interrupt. The information used to trigger the virtual interrupt includes the target interrupt number written by the host computer to the register and the identifier of the virtual machine. The target interrupt number is the identifier of the interrupt triggered when the host computer simulates a hardware device. The above step of sending the virtual interrupt to the target physical processor includes: sending the virtual device interrupt to the first vCPU running on the target physical processor.

[0054] In a possible implementation of the eighth aspect, the method further includes: writing the virtual interrupt into the pending register of the target physical processor, and the pending register is used to receive the commands of the process executed by the target physical processor.

[0055] For the features described in the above sixth aspect to the eighth aspect, and any possible implementation manners thereof, as well as the corresponding intended effects, reference can be made to the description in the first aspect and any possible implementation manner of the first aspect for understanding, and details will not be repeated here.

[0056] The ninth aspect of the present application provides a control device, which is applied to a chip system. The chip system further includes a source physical processor, an intermediate device, a sending device, and a target physical processor. The source physical processor is used to run a host computer or a virtual machine. The control device includes a register. The register is used to receive the information for triggering a virtual interrupt, and the information for triggering the virtual interrupt comes from the host computer or the virtual machine. The control device includes: a reading unit, configured to read the information for triggering the virtual interrupt from the register; and a sending unit, configured to send the information for triggering the virtual interrupt to the intermediate device. The information for triggering the virtual interrupt is used for the intermediate device to trigger a virtual interrupt, and the virtual interrupt is sent by the sending device to the target physical processor.

[0057] In a possible implementation of the ninth aspect, the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, and the register is used to receive the information for triggering the virtual local interrupt written by the virtual machine. The information for triggering the virtual local interrupt is used to enable the intermediate device to trigger a virtual local interrupt, and the virtual local interrupt is sent by the sending device to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.

[0058] In a possible implementation manner of the ninth aspect, the virtual interruption is a virtual software interruption. The information used to trigger the virtual interruption includes the identifier of the second vCPU written by the first VCPU of the virtual machine to the register. The second vCPU is the vCPU of the virtual machine running on the target physical processor. The control device further includes a processing unit, which is used to obtain the identifier of the virtual machine, and a sending unit, which is used to send the identifier of the virtual machine to the intermediate device. The identifier of the virtual machine and the identifier of the second vCPU are used by the intermediate device to determine the target physical processor and trigger the virtual software interruption. The virtual software interruption is sent by the sending device to the second vCPU of the target physical processor.

[0059] In a possible implementation manner of the ninth aspect, the virtual interruption is a virtual device interruption. The information used to trigger the virtual interruption includes the target interruption number written by the host to the register and the identifier of the virtual machine. The target interruption number is the identifier of the interruption triggered when the host simulates a hardware device. The identifier of the virtual machine and the target interruption number are used by the intermediate device to determine the target physical processor and trigger the virtual device interruption. The virtual device interruption is sent by the sending device to the first vCPU of the target physical processor.

[0060] The tenth aspect of the present application provides an intermediate device, which is applied to a chip system. The chip system further includes a source physical processor, a control device, a sending device, and a target physical processor. The source physical processor is used to run a host or a virtual machine. The control device includes a register. The register is used to receive the information used to trigger a virtual interruption, and the information used to trigger the virtual interruption comes from the host or the virtual machine. The intermediate device includes: a receiving unit, which is used to receive the information used to trigger the virtual interruption from the control device; a processing unit, which is used to trigger the virtual interruption according to the information used to trigger the virtual interruption; and a sending unit, which is used to send the virtual interruption to the sending device. The virtual interruption is sent by the sending device to the target physical processor.

[0061] In a possible implementation manner of the tenth aspect, the virtual interruption is a virtual local interruption. The target physical processor and the source physical processor are the same physical processor. The register is used to receive the information written by the virtual machine and used to trigger the virtual local interruption. The information used to trigger the virtual local interruption is used to trigger the virtual local interruption. The virtual local interruption is sent by the sending device to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.

[0062] In a possible implementation of the tenth aspect, the virtual interruption is a virtual software interruption. The information used to trigger the virtual interruption includes the identifier of the second vCPU written by the first vCPU of the virtual machine to a register, where the second vCPU is the vCPU of the virtual machine running on the target physical processor; a processing unit, configured to determine, according to the identifier of the virtual machine and the identifier of the second vCPU, a target physical processor corresponding to the identifier of the virtual machine and the identifier of the second vCPU from a first corresponding relationship, where the first corresponding relationship is used to record the corresponding relationship among the target physical processor, the second vCPU running on the target physical processor, and the virtual machine; trigger the virtual software interruption, and the virtual software interruption is sent by a sending device to the second vCPU of the target physical processor.

[0063] In a possible implementation of the tenth aspect, the virtual interruption is a virtual device interruption. The information used to trigger the virtual interruption includes the target interruption number written by the host to a register and the identifier of the virtual machine, where the target interruption number is the identifier of the interruption triggered when the host simulates a hardware device; a processing unit, configured to find, according to the identifier of the virtual machine and the target interruption number, the identifier of the first vCPU of the virtual machine corresponding to the identifier of the virtual machine and the target interruption number in a second corresponding relationship, where the second corresponding relationship is used to record the corresponding relationship among the virtual machine, the target interruption number, and the first vCPU; determine, according to the identifier of the virtual machine and the identifier of the first vCPU, a target physical processor corresponding to the identifier of the virtual machine and the identifier of the first vCPU from a third corresponding relationship, where the third corresponding relationship is used to record the corresponding relationship among the target physical processor, the first vCPU running on the target physical processor, and the virtual machine; trigger the virtual device interruption, and the virtual device interruption is sent by a sending device to the first vCPU of the target physical processor.

[0064] In a possible implementation of the tenth aspect, the processing unit is further configured to find an address register according to the identifier of the virtual machine, and obtain the second corresponding relationship from the memory according to the address in the address register, where the address register is used to store the address of the second corresponding relationship in the memory and the identifier of the virtual machine.

[0065] The eleventh aspect of the present application provides a sending device, which is applied to a chip system. The chip system further includes a source physical processor, an intermediate device, a control device, and a target physical processor. The source physical processor is configured to run a host or a virtual machine. The control device includes a register; the register is configured to receive information used to trigger a virtual interruption, and the information used to trigger the virtual interruption comes from the host or the virtual machine. The sending device includes: a receiving unit, configured to receive a virtual interruption from the intermediate device; a sending unit, configured to send the virtual interruption to the target physical processor.

[0066] In a possible implementation of the eleventh aspect, the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor; the sending unit is configured to send the virtual local interrupt to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.

[0067] In a possible implementation of the eleventh aspect, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes the identifier of the second vCPU written by the first vCPU of the virtual machine to the register, and the second vCPU is the vCPU of the virtual machine running on the target physical processor; the sending unit is configured to send the virtual software interrupt to the second vCPU running on the target physical processor.

[0068] In a possible implementation of the eleventh aspect, the virtual interrupt is a virtual device interrupt, and the information used to trigger the virtual interrupt includes the target interrupt number written by the host to the register and the identifier of the virtual machine, and the target interrupt number is the identifier of the interrupt triggered when the host simulates a hardware device; the sending unit is configured to send the virtual device interrupt to the first vCPU running on the target physical processor.

[0069] In a possible implementation of the eleventh aspect, the sending unit is configured to write the virtual interrupt into the pending register of the target physical processor, and the pending register is used to receive commands of the process executed by the target physical processor.

[0070] For the features described in the above ninth aspect to the eleventh aspect, and any possible implementation thereof, as well as the corresponding intended effects, reference can be made to the description in the first aspect and any possible implementation of the first aspect for understanding, and details will not be repeated here.

[0071] The twelfth aspect of the present application provides a computer-readable storage medium storing one or more computer-executable instructions. When the computer-executable instructions are executed by a processor, the processor executes the method according to the sixth aspect or any possible implementation of the sixth aspect as described above.

[0072] The thirteenth aspect of the present application provides a computer-readable storage medium storing one or more computer-executable instructions. When the computer-executable instructions are executed by a processor, the processor executes the method according to the seventh aspect or any possible implementation of the seventh aspect as described above.

[0073] The fourteenth aspect of the present application provides a computer-readable storage medium storing one or more computer-executable instructions. When the computer-executable instructions are executed by a processor, the processor executes the method according to the eighth aspect or any possible implementation of the eighth aspect as described above.

[0074] A fifteenth aspect of the present application provides a computer program product storing one or more computer-executable instructions. When the computer-executable instructions are executed by a processor, the processor executes the method according to the sixth aspect or any possible implementation manner of the sixth aspect as described above.

[0075] A sixteenth aspect of the present application provides a computer program product storing one or more computer-executable instructions. When the computer-executable instructions are executed by a processor, the processor executes the method according to the seventh aspect or any possible implementation manner of the seventh aspect as described above.

[0076] A seventeenth aspect of the present application provides a computer program product storing one or more computer-executable instructions. When the computer-executable instructions are executed by a processor, the processor executes the method according to the eighth aspect or any possible implementation manner of the eighth aspect as described above.

[0077] An eighteenth aspect of the present application provides a computer device, which includes the chip system according to the first aspect or any possible implementation manner of the first aspect as described above.

[0078] A nineteenth aspect of the present application provides a chip system, which includes a source physical processor, a control device, a sending device, and a target physical processor. The control device is as described in the third aspect, the ninth aspect, any possible implementation manner of the third aspect, or any possible implementation manner of the ninth aspect. The sending device is as described in the fifth aspect, the eleventh aspect, any possible implementation manner of the eleventh aspect, or any possible implementation manner of the fifth aspect.

[0079] In one implementation manner, the chip system may further include an intermediate device as described in the fourth aspect, the tenth aspect, any possible implementation manner of the tenth aspect, or any possible implementation manner of the fourth aspect.

[0080] In one implementation manner, the chip system provided in the nineteenth aspect is a processor. The source physical processor and the target physical processor are physical cores in the processor, and the control device is a component in the processor and coupled to the source physical processor. The sending device is a component in the processor and coupled to the target physical processor. It can be understood that since any physical core in the processor may be a receiver of a virtual interruption, a physical core may act as both the source physical processor and the target physical processor. Correspondingly, what is coupled to the physical core may include both the control device and the sending device.

[0081] In the chip system provided by the embodiment of the present application, a register dedicated to processing virtual interrupts is set in the control device. In this way, the host machine or virtual machine in the user state can directly write the information for triggering the virtual interrupt into this register. The control device can send the information for triggering the virtual interrupt to the intermediate device, and the intermediate device triggers the virtual interrupt. Moreover, the intermediate device sends the virtual interrupt to the sending device, and the sending device sends the virtual interrupt to the target physical processor. In the solution provided by the present application, both the host machine and the virtual machine can directly access the register and write the information for triggering the virtual interrupt into the register, so as to send out the virtual interrupt. Therefore, compared with the prior art, the solution provided by the present application does not require the source physical processor to execute the switch from the virtual machine to the host machine, or execute the switch from the user state of the host machine to the kernel state of the host machine, thereby reducing the switching overhead generated by processing virtual interrupts and improving the performance of the chip system. Description of the Drawings

[0082] Figure 1 is a schematic structural diagram of a computer device provided by an embodiment of the present application;

[0083] Figure 2 is a schematic diagram of the types of virtual interrupts provided by an embodiment of the present application;

[0084] Figure 3 is a schematic structural diagram of a chip system provided by an embodiment of the present application;

[0085] Figure 4 is another schematic structural diagram of a chip system provided by an embodiment of the present application;

[0086] Figure 5 is a schematic diagram of a virtual clock interrupt provided by an embodiment of the present application;

[0087] Figure 6 is a schematic example diagram of an in-place virtual processor identification group provided by an embodiment of the present application;

[0088] Figure 7 is a schematic example diagram of a virtual software interrupt provided by an embodiment of the present application;

[0089] Figure 8 is a schematic structural diagram of a routing device provided by an embodiment of the present application;

[0090] Figure 9 is a schematic example diagram of a direct peripheral interrupt provided by an embodiment of the present application;

[0091] Figure 10 is a schematic structural diagram of a chip system in the RISC-V microarchitecture provided by an embodiment of the present application;

[0092] Figure 11It is a schematic diagram of a process for handling clock interrupts in the RISC-V microarchitecture provided by an embodiment of this application;

[0093] Figure 12 It is a schematic diagram of a process for handling virtual software interrupts in the RISC-V microarchitecture provided by an embodiment of this application;

[0094] Figure 13 It is a schematic diagram of a process for handling virtual device interrupts in the RISC-V microarchitecture provided by an embodiment of this application;

[0095] Figure 14 It is another schematic diagram of a process for handling virtual device interrupts in the RISC-V microarchitecture provided by an embodiment of this application;

[0096] Figure 15 It is a schematic diagram of a process for handling direct-through peripheral interrupts in the RISC-V microarchitecture provided by an embodiment of this application;

[0097] Figure 16 It is a schematic diagram of an embodiment of a method for handling virtual interrupts provided by an embodiment of this application;

[0098] Figure 17 It is a schematic diagram of an embodiment of a control device provided by an embodiment of this application;

[0099] Figure 18 It is a schematic diagram of an embodiment of an intermediate device provided by an embodiment of this application;

[0100] Figure 19 It is a schematic diagram of an embodiment of a sending device provided by an embodiment of this application;

[0101] Figure 20 It is another structural schematic diagram of a computer device provided by an embodiment of this application. Detailed implementation manners

[0102] Next, in conjunction with the accompanying drawings, the embodiments of this application will be described. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all of the embodiments. Those of ordinary skill in the art can understand that with the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0103] In the description and claims of this application and the above-mentioned drawings, terms such as "first" and "second" are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments described here can be implemented in an order other than that illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0104] Embodiments of this application provide a chip system, a method for processing virtual interrupts, and corresponding devices, which are used to reduce the switching overhead from a virtual machine to a host machine or from the user mode of the host machine to the kernel mode of the host machine caused by virtual interrupts. Embodiments of this application also provide corresponding computer devices, computer storage media, computer program products, etc. The following will be described in detail respectively.

[0105] Virtualization is to virtualize the hardware resources (such as processors, storage spaces in memories, and network resources) in the hardware layer of a computer device and share them for use by multiple virtual computers. A virtual computer is a general term for a running environment virtualized by software in all types of virtualized devices, and this concept includes virtual machines or containers.

[0106] As Figure 1 shown, the computer device 100 includes a hardware layer 112, a host machine layer 109, and a virtualization layer, and the virtualization layer includes virtual machines 101 and 102. The number of virtual machines can also be more or less, and only two are taken as examples here. The hardware layer 112 includes a processor system 114, a memory 113, a communication interface 115, and an interrupt controller 116.

[0107] A virtual machine (VM) is simulated on a computer device through virtualization software. On the virtual machines ( Figure 1 101 and 102 in the figure), a guest operating system (guest OS) ( Figure 1 105 and 106 in the figure) can be installed, and one or more application programs ( Figure 1 103 and 104 in the figure) run on the guest operating system. The virtual machine can also access network resources. For application programs running in the virtual machine, it is like working in a real computer.

[0108] A virtual processor (such as Figure 1107 and 108): Under virtualization technology, it represents a processing unit provided to a virtual computer in a shared or sharded manner, such as a virtual central processing unit (vCPU). A virtual computer can have one or more virtual processors serving it. When there are multiple virtual processors, usually one virtual processor is the main virtual processor and the others are slave virtual processors. Other virtual hardware resources such as virtual memory included in the virtual machine are not shown in Figure 1 It is not shown in Figure 1 . The virtual processor is virtualized through virtualization software, and its operation is actually achieved by the processor or physical core of the host machine reading and running a software program. For example, a physical core reads a software program and runs the software program in a specific mode of hardware-assisted virtualization of the physical core (such as the non-Root mode of x86) to implement a virtual processor. Multiple virtual processors of a virtual machine can be located on different physical cores. It should be noted that the vCPU mentioned in various embodiments of the present application is an optional specific implementation manner of the virtual processor. The "vCPU" mentioned in each embodiment can be replaced by "virtual processor" for understanding.

[0109] Virtual Processor Trap In and Trap Out: The virtualization system includes two modes: host mode and guest mode. Host mode can also be referred to as the privileged level of the host, such as the user state or kernel state of the host. Guest mode can also be referred to as the privileged level of the VM, such as the user state or kernel state of the VM. When a physical processor enters the guest mode, it is called a trap (virtual). The process of the trap can also be understood as the physical processor switching from running the host to running the virtual machine. When the physical processor leaves the guest mode, it is called a trap out (virtual). The process of the trap out can also be understood as the physical processor switching from running the virtual machine to running the host. After the trap out, the physical processor will temporarily not execute the code of the virtual processor. So at this time, it can be understood that the virtual processor is not running. When a virtual machine is running on a physical processor, a virtual processor of the virtual machine will be running. A virtual machine can have multiple virtual processors. A physical processor runs only one virtual processor of the virtual machine at a time. Multiple virtual processors belonging to the same virtual machine can run on this physical processor in a time-sharing multiplexing manner. For example, on physical processor 1, first run vCPU1 of virtual machine 1. After physical processor 1 finishes running vCPU1, it can then run vCPU2 of this virtual machine 1. Multiple vCPUs belonging to the same virtual machine can also run on different physical processors. At a time, different vCPUs can run on different physical processors. For example, run vCPU1 of virtual machine 1 on physical processor 1 and run vCPU2 of virtual machine 1 on physical processor 2. The host layer 109 serves as a management layer to complete the management and allocation of hardware resources and provide various virtual hardware resources for the virtual machine, such as virtual processors (107, 108), virtual memory, virtual disk, virtual network card, etc. It can also implement the scheduling and isolation of the virtual machine, etc. In some implementation manners, the host layer 109 can include the host operating system 111 and a virtual monitoring device, such as the virtual machine monitor 110 (virtual machine monitor, VMM). Among them, the virtual monitor 110 can be deployed within the host operating system 111 or outside the host operating system 111. In other virtualization architectures, the virtual monitoring device can also be called a hypervisor or other types of virtual monitoring devices. The host layer 109 can also be called a virtualization platform. Sometimes the host layer can also be simply referred to as the host. The privileged levels of the host include the user state and the kernel state.

[0110] Hardware Layer 112: The hardware platform on which the virtualization environment runs. Among them, the hardware layer can include various hardware, such as Figure 1As shown, the hardware layer may include a processor system 114 and a memory 113, and may also include a communication interface 115, such as a network interface card (NIC); it may also include an interrupt controller 116, input / output (I / O) devices, etc. The processor system 114 may include one or more processors, such as Figure 1 the processors 1 and 2 listed in

[0111] The processor system 114 may include multiple processors, such as Figure 1 the processors 1 and 2 in Figure 1 The processors 1 and 2 in

[0112] are both physical processors, such as a source physical processor and a target physical processor. Each physical processor can be understood as a physical core. The processor system 114 may specifically be a multi-core processor, which includes a source physical processor and a target physical processor. A virtual processor and a physical core may have a bound relationship, that is, a virtual processor runs fixed on a certain physical core and cannot be scheduled to run on other physical cores, then this virtual processor is a bound core; a virtual processor can be scheduled to run on different physical cores as needed, then this virtual processor is an unbound core.

[0113] An interruption refers to pausing the instructions of the current program and then executing an interrupt service program. Interruptions can include virtual interruptions and physical interruptions. A virtual interruption refers to an interruption notified to a virtual machine (VM) by a hardware device, a host machine, the clock of this virtual machine, or a virtual central processing unit (vCPU) of the virtual machine in a computer device. The hardware device that generates this virtual interruption can be a disk, a network card, a sound card, a mouse, a hard disk, etc. in the computer device. A physical interruption refers to an interruption notified to a physical processor by a hardware device. Physical interruptions are processed by the host machine, while virtual interruptions are processed by the virtual machine.

[0114] An interrupt service routine (ISR), also known as an interrupt handling function, is a program used to handle interrupt requests. When the processor receives an interrupt request, it temporarily halts the execution of the current program and instead executes the interrupt service routine corresponding to that interrupt request.

[0115] The storage space (address space) provided by the memory 113 is divided for use by the virtual machine and the host machine. The host physical address (HPA) refers to the physical address space that the local host (host machine) can use; the host virtual address (HVA) is the virtual address space that the local host (host machine) can use. The guest physical address (GPA) is the physical address space that the guest operating system of the virtual machine can use; the guest virtual address (GVA) is the virtual address space that the guest operating system of the virtual machine can use.

[0116] The computer device 100 can be a physical device, such as a server or a terminal device. The terminal device can be a handheld device with wireless connection capabilities, or other processing devices connected to a wireless modem. For example, it can be a mobile phone, a personal computer (PC), a tablet computer, a personal digital assistant (PDA), a mobile Internet device (MID), a wearable device, and an e-book reader, etc.; it can also be a portable, pocket-sized, handheld, computer-integrated, or in-vehicle mobile device.

[0117] The virtual machine or the host machine in the above computer device 100 can send information for triggering a virtual interrupt, and then the chip system provided by the embodiments of the present application completes the corresponding process of handling the virtual interrupt. The chip system provided by the embodiments of the present application can include the Figure 1 interrupt controller and the processor system mentioned above, or can also include the Figure 1 interrupt controller or the processor system mentioned above.

[0118] Target physical processor Target physical processor In the embodiments of the present application, as Figure 2As shown, virtual interrupts can include virtual local interrupts, virtual software interrupts, virtual device interrupts, and direct peripheral interrupts. Among them, virtual local interrupts refer to interrupts issued by virtual local devices simulated by a virtual machine, such as virtual timers, virtual mice, etc., or interrupts issued by local devices of a certain vCPU of the virtual machine. For example, an interrupt issued by the timer of a certain vCPU of the virtual machine. The interrupt issued by the timer is also called a clock interrupt. A clock interrupt means that the timer, through the method of timing, issues an interrupt when it reaches the time point configured by the virtual machine. A virtual software interrupt refers to an interrupt triggered by software, usually an interrupt sent by a vCPU of a virtual machine to another vCPU of the same virtual machine. For example, the interrupt sent by the first vCPU to the second vCPU that belong to the same virtual machine as shown in Figure 2 in Figure 2 . A virtual machine can have multiple vCPUs. These vCPUs can run on different physical processors at a certain moment to execute different tasks of the virtual machine. When there are dependencies or scheduling requirements between the tasks executed by different vCPUs, a virtual software interrupt will occur. A virtual device interrupt refers to an interrupt triggered by a host computer simulating a hardware device. For example, an interrupt generated by the host computer simulating a virtual machine disk controller or other hardware devices. A direct peripheral interrupt refers to an interrupt triggered by an external device directly connected to the virtual machine. For example, an interrupt generated by a graphics card directly connected to the virtual machine.

[0119] Among the above four types of virtual interrupts, for virtual local interrupts, virtual software interrupts, and virtual device interrupts, the processing process requires the physical processor running the virtual machine to switch from the virtual machine to the host computer, or to switch from the user mode of the host computer to the kernel mode of the host computer, which brings a large switching overhead. Therefore, the embodiments of the present application provide a chip system. During the process of processing virtual interrupts, it is not necessary for the physical processor running the virtual machine to switch from the virtual machine to the host computer, or to switch from the user mode of the host computer to the kernel mode of the host computer, which can save the switching overhead. The chip system provided by the embodiments of the present application will be introduced below with reference to the accompanying drawings.

[0120] As Figure 3As shown in the figure, the chip system provided by the embodiment of the present application includes: a source physical processor, a control device, an intermediate device, a sending device, and a target physical processor. The source physical processor is used to run a host or a virtual machine. The control device includes a register, and the register is used to receive information for triggering a virtual interruption. The information for triggering the virtual interruption can come from the host or the virtual machine. The control device is used to: send the information for triggering the virtual interruption in the register to the intermediate device; The intermediate device is used to: trigger a virtual interruption according to the information for triggering the virtual interruption and send the virtual interruption to the sending device; The sending device is used to: receive the virtual interruption from the intermediate device and send the virtual interruption to the target physical processor.

[0121] This chip system can be applied to the Figure 1 computer device shown above. This chip system can be the Figure 1 interrupt controller or processor system in the above.

[0122] The chip system provided by the embodiment of the present application can be a system on chip (SOC). The source physical processor and the target physical processor can be a processing unit respectively. The source physical processor or the target physical processor can be a physical core and be located in the same processor; The source physical processor and the target physical processor can also be different processors located in the same chip system. The control device, the intermediate device, and the sending device can all be implemented through hardware circuits. The control device and the sending device can be deployed in the multi-core processor and be coupled with the source physical processor and the target physical processor. The intermediate device can be deployed in the multi-core processor or on a peripheral device / peripheral component coupled with the multi-core processor. The system on chip can include a multi-core processor and a peripheral device / peripheral component coupled with the multi-core processor. Any physical processor in the chip system can be used as both the source physical processor and the target physical processor.

[0123] In the present application, the source physical processor and the target physical processor are used. It should be noted that the source physical processor and the target physical processor can be two physical cores in a multi-core processor or two physical cores in different processors. In one implementation, the source physical processor and the target physical processor can be the same physical entity. For example, in the scenario of virtual local interruption, the source physical processor and the target physical processor can be the same physical processor.

[0124] In this application, the control device may include at least one register. Each register may be used to receive a type of information for triggering a virtual interruption. For example, if there are three registers, one register is used to receive information for triggering a virtual local interruption, one register is used to receive information for triggering a virtual software interruption, and one register is used to receive information for triggering a virtual device interruption. Of course, in this control device, only one register may also be configured for virtual interruptions. Since the information for triggering each type of virtual interruption is different, the type of virtual interruption can be identified by the information received by the register.

[0125] There may be one or more intermediate devices. The sending device may be one sending device for each physical processor, or multiple physical processors may share one sending device.

[0126] In the chip system provided by the embodiment of this application, registers dedicated to processing virtual interruptions are set in the control device. In this way, the host machine or virtual machine in the user state can directly write the information for triggering a virtual interruption into this register. The control device can send the information for triggering the virtual interruption to the intermediate device, and the intermediate device triggers the virtual interruption. Moreover, the intermediate device sends the virtual interruption to the sending device, and the sending device sends the virtual interruption to the target physical processor, without the source physical processor performing the switch from the virtual machine to the host machine, or performing the switch from the user state of the host machine to the kernel state of the host machine, thereby reducing the switching overhead generated by processing virtual interruptions and improving the performance of the chip system.

[0127] The above Figure 3 Among them, the intermediate device may be a virtual local interruption generating device or a routing device. If the virtual interruption is a virtual local interruption, this intermediate device may be called a local interruption generating device (such as a timer). If the virtual interruption is a virtual software interruption or a virtual device interruption, this intermediate device may be called a routing device.

[0128] The sending device described above Figure 2 introduced four types of virtual interruptions. Next, taking the control device including register 1, register 2, and register 3 as an example, the process of processing these four types of virtual interruptions will be introduced. Among them, register 1 is used to receive information for triggering a virtual device interruption, register 2 is used to receive information for triggering a virtual software interruption, and register 3 is used to receive information for triggering a virtual local interruption. Figure 4

[0129] Figure 4 ​In the chip system shown, the source physical processor is used to run the host or virtual machine. Both the host and the virtual machine can have privilege level one and privilege level two. Among them, privilege level one can be the user mode, and privilege level two can be the kernel mode. In different virtualization architectures, the states corresponding to privilege level one and privilege level two may be different. In this regard, the embodiments of this application do not make any limitations.

[0130] This application Figure 4 uses four different lines to mark four types of virtual interrupts. Among them, the line marked with the number 1 represents the process of handling virtual local interrupts, the line marked with the number 2 represents the process of handling virtual software interrupts, the line marked with the number 3 represents the process of handling virtual device interrupts, and the line marked with the number 4 represents the process of handling direct-pass peripheral interrupts.

[0131] 1. Virtual local interrupt.

[0132] As Figure 4 shown, in the process of handling virtual local interrupts, the register involved is register 3, and the intermediate device can be called a local interrupt generation device. Since the virtual local interrupt is an in-core interrupt, the target physical processor and the source physical processor are the same physical processor, and the sending device corresponds to the source physical processor.

[0133] The register is used to: receive the information written by the virtual machine for triggering the virtual local interrupt.

[0134] The local interrupt generation device is used to: generate a virtual local interrupt according to the information for triggering the virtual local interrupt.

[0135] The sending device is used to: send the virtual local interrupt to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.

[0136] In the process of handling virtual local interrupts provided by the embodiments of this application, a physical processor will only run one vCPU of one virtual machine at a time. Sending the virtual local interrupt to this vCPU can complete the operation of sending the virtual local interrupt to the virtual machine. The above Figure 4 The local interrupt generation device in can be a timer, and the virtual local interrupt can be a clock interrupt. In the scenario of a clock interrupt, the implementation of this process can be understood by referring to Figure 5 For understanding. As Figure 5 shown, the virtual machine will write the interrupt time into the control device, (this process can be referred to Figure 4(Understand the third register in it), the control device writes the interrupt time into the timer, and the timer starts accordingly. After the preset time is reached, the timer issues a clock interrupt. After the sending device receives the clock interrupt, it determines that the first vCPU of the virtual machine is running, and then sends the clock interrupt to the first vCPU.

[0137] From the above Figure 4 and Figure 5 process, it can be seen that the process of handling this virtual local interrupt does not require the source physical processor to perform a switch from the virtual machine to the host, thereby reducing the switching overhead generated by handling the virtual local interrupt and improving the performance of the chip system.

[0138] 2. Virtual software interrupt.

[0139] As Figure 4 shown, in the process of handling the virtual software interrupt, the register involved is register 2, and the intermediate device can be called a routing device. The first vCPU of the virtual machine runs on the source physical processor, and the second vCPU of the virtual machine runs on the target physical processor.

[0140] The register is used to: receive the identifier of the second vCPU written by the first vCPU.

[0141] The control device is used to: read the identifier of the second vCPU from the register and obtain the identifier of the virtual machine; and send the identifier of the virtual machine and the identifier of the second vCPU to the intermediate device.

[0142] The intermediate device is used to: determine the target physical processor corresponding to the identifier of the virtual machine and the identifier of the second vCPU from the first correspondence; where the first correspondence is used to record the correspondence between the target physical processor, the second vCPU running on the target physical processor, and the virtual machine; send the virtual software interrupt to the sending device corresponding to the target physical processor.

[0143] The sending device is used to: send the virtual software interrupt to the second vCPU running on the target physical processor.

[0144] During the process of handling a virtual software interrupt in an embodiment of the present application, the control device can obtain the identifier of the virtual machine from a register dedicated to storing the identifiers of the virtual machines running on the source physical processor. Since each virtual machine can have multiple vCPUs and the identifiers of the vCPUs of different virtual machines may be the same, the control device needs to send the identifier of the virtual machine and the identifier of the second vCPU to the intermediate device. The above-mentioned first correspondence can be stored on the intermediate device, and the first correspondence can be located in the in-place vCPU identifier group, which records the correspondence between each physical processor in the chip system, each vCPU running on each physical processor, and the virtual machine to which the running vCPU belongs. The present application can target the physical processor by searching the in-place vCPU identifier group. As can be seen from the above description, the process of handling the virtual software interrupt does not require the source physical processor to perform a switch from the virtual machine to the host, thereby reducing the switching overhead generated by handling the virtual software interrupt and improving the performance of the chip system.

[0145] The above-mentioned in-place vCPU identifier group can be referred to Figure 6 for understanding. Figure 6 The meaning represented is: vCPU1 of VM1 is running on physical processor 1, vCPU2 of VM1 is running on physical processor 2, vCPU1 of VM2 is running on physical processor 3, and vCPU2 of VM2 is running on physical processor 4. If the routing device receives the identifier of VM1 and the identifier of vCPU2 from the control device, it can be based on Figure 6 The shown in-place vCPU identifier group can determine that vCPU2 is running on physical processor 2, and the virtual software interrupt can be sent to the sending device corresponding to physical processor 2, and the sending device corresponding to physical processor 2 sends the virtual software interrupt to vCPU2 running on physical processor 2.

[0146] If the second vCPU is not found after searching the above-mentioned in-place vCPU identifier group, it means that the second vCPU is not currently running. Then the routing device can send the virtual software interrupt to the sending device of the source physical processor, and the sending device of the source physical processor sends the virtual software interrupt to the host. After the second vCPU goes online and runs, the host sends the virtual software interrupt to the second vCPU.

[0147] Since a physical processor may run different vCPUs at different times, the correspondence in the in-place vCPU identifier group is changing, and the in-place vCPU identifier group in the above-mentioned routing device can be managed by the host on the source physical processor.

[0148] The process of handling the virtual software interrupt in an embodiment of the present application can be referred to Figure 7Understand. A virtual machine runs on the source physical processor, and the first vCPU of the virtual machine runs on the source physical processor. The second vCPU runs on another physical processor. If the first vCPU of the virtual machine wants to send a virtual software interrupt to the second vCPU, the first vCPU of the virtual machine writes the identifier of the second vCPU to register 2 of the control device. The control device finds the identifier of the virtual machine and then sends the identifier of the virtual machine and the identifier of the second vCPU to the routing device. The routing device looks up the in-place vCPU identifier group shown in, for example Figure 6 and determines that the physical processor corresponding to the identifier of the virtual machine and the identifier of the second vCPU is the target physical processor. Then the routing device sends the virtual software interrupt to the sending device corresponding to the target physical processor, and the sending device corresponding to the target physical processor sends the virtual software interrupt to the second vCPU, that is, sends it to the virtual machine running on the target physical processor.

[0149] From the above Figure 4 、 Figure 6 and Figure 7 process, it can be seen that the processing process of the virtual software interrupt provided by the embodiment of the present application does not require the source physical processor to execute the switch from the virtual machine to the host, thereby reducing the switching overhead generated by processing the virtual software interrupt and improving the performance of the chip system.

[0150] 3. Virtual device interrupt.

[0151] As Figure 4 shown, in the process of processing the virtual device interrupt, the register involved is register 1, and the intermediate device is the routing device. The source physical processor runs the host, and the host is in the user state.

[0152] The register is used to: receive the target interrupt number and the identifier of the virtual machine written by the host, and the target interrupt number is the identifier of the interrupt triggered when the host simulates a hardware device.

[0153] The control device is used to: read the target interrupt number and the identifier of the virtual machine from the register, and send the identifier of the virtual machine and the target interrupt number to the intermediate device.

[0154] The intermediate device is used for: looking up, according to the identifier of the virtual machine and the target interrupt number, the identifier of the first vCPU of the virtual machine corresponding to the identifier of the virtual machine and the target interrupt number in the second corresponding relationship, where the second corresponding relationship is used to record the corresponding relationship between the virtual machine, the target interrupt number, and the first vCPU; determining, according to the identifier of the virtual machine and the identifier of the first vCPU, the target physical processor corresponding to the identifier of the virtual machine and the identifier of the first vCPU from the third corresponding relationship, where the third corresponding relationship is used to record the corresponding relationship between the target physical processor, the first vCPU running on the target physical processor, and the virtual machine; and sending the virtual device interrupt to the sending device corresponding to the target physical processor.

[0155] The sending device is used for: sending the virtual device interrupt to the first vCPU running on the target physical processor.

[0156] In the embodiment of the present application, the virtual device interrupt is an interrupt triggered by the host machine in the user state simulating a hardware device. There can be various types of hardware devices, and the interrupt numbers of each type of hardware device are different. If the host machine simulates a disk, then the target interrupt number is the interrupt number of the disk. Since there can be multiple virtual machines managed by the host machine, the host machine needs to write the identifier of the virtual machine and the target interrupt number into the register. The second corresponding relationship can be located in the interrupt affinity table. This interrupt affinity table can be configured by the virtual machine, so there is an interrupt affinity table for each virtual machine. In this way, the interrupt affinity table of the virtual machine can be found according to the identifier of the virtual machine, and then the corresponding vCPU can be determined from the interrupt affinity table of the virtual machine according to the target interrupt number. If the target interrupt number is 10, and in the interrupt affinity table, the interrupt number 10 corresponds to vCPU ID1, then it can be determined that the vCPU ID corresponding to the target interrupt number is 1. After the routing device determines that the vCPU ID is 1, it can find the physical processor corresponding to the vCPU ID1 according to the in-place vCPU identifier group. The meaning of the in-place vCPU identifier group can be understood by referring to the description of the foregoing virtual software interrupt part, and the third corresponding relationship can also be understood by referring to the foregoing first corresponding relationship.

[0157] The following refers to Table 1 to understand the interrupt affinity table of the virtual machine.

[0158] Table 1: Figure 4 Interrupt affinity table of the virtual machine in

[0159] Interrupt number vCPU ID 10 1 20 2 30 3 40 4

[0160] The above Table 1 is only an example. In fact, it is not limited to the several types listed in Table 1, and there can be other forms of correspondence, and the quantity can also be more. Another column can also be added to Table 1, and the additional column is used to store Figure 4 the identifier of the virtual machine in

[0161] The interrupt affinity table can be stored in the routing device or in the memory. In the routing device, an address register can be provided for each physical processor. The address register can be a base address register, and the base address register can store the address of the interrupt affinity table in the memory and the identifier of the virtual machine. As Figure 8 shown, the base address register 1 on the routing device corresponds to the physical processor 1, the base address register 2 corresponds to the physical processor 2, the base address register 3 corresponds to the physical processor 3, and the base address register 4 corresponds to the physical processor 4. The address in each base address register points to an interrupt affinity table. For example, the base address register 1 points to the interrupt affinity table 1, the base address register 2 points to the interrupt affinity table 2, the base address register 3 points to the interrupt affinity table 3, and the base address register 4 points to the interrupt affinity table 4. If the same virtual machine is running on two physical processors, then the addresses in the base address registers corresponding to the two physical processors can be the same, and the pointed interrupt affinity tables can be the same table.

[0162] In this way, during the process of processing virtual device interrupts, the virtual machine writes the target interrupt number into register 1. The control device reads the identifier of the currently running virtual machine from the register dedicated to storing the virtual machine running on the source physical processor, and then the control device sends the target interrupt number and the identifier of the virtual machine to the routing device. The routing device determines the corresponding interrupt affinity table according to the identifier of the virtual machine, and then uses the target interrupt number to find the identifier of the corresponding vCPU from the interrupt affinity table. If the target interrupt number is 10, the identifier of the corresponding vCPU can be determined to be 1. After the routing device determines that the identifier of the vCPU is 1, it can find the processor corresponding to the vCPU 1 according to Figure 6 the in - place vCPU identifier group shown. The routing device can send the virtual device interrupt to the sending device corresponding to the physical processor 1, and the sending device sends the virtual device interrupt to the first vCPU corresponding to the vCPU1.

[0163] If the first vCPU is not found through the above in - place vCPU identifier group, it means that the first vCPU is not currently running. Then the routing device can send the virtual software interrupt to the sending device of the source physical processor, and the sending device of the source physical processor sends the virtual software interrupt to the host. After the first vCPU goes online and runs, the host sends the virtual software interrupt to the first vCPU.

[0164] From the above Figure 4 , Table 1, Figure 8 and Figure 6As can be seen from the process, the processing process of virtual device interrupt provided by the embodiments of the present application does not require the source physical processor to perform the switch from the user state of the host to the kernel state of the host, thereby reducing the switching overhead generated by processing virtual device interrupts and improving the performance of the chip system.

[0165] 4. Pass-through peripheral interrupt.

[0166] As Figure 4 shown, the pass-through peripheral interrupt is an interrupt triggered by a hardware device directly connected to the virtual machine, such as a graphics card directly connected to the virtual machine. The intermediate device can be called a routing device. This type of interrupt processing process can be completed through the routing device and the sending device, and the process includes:

[0167] The intermediate device is used to: receive the pass-through peripheral interrupt triggered by the hardware device; according to the physical interrupt number of the pass-through peripheral interrupt, look up the corresponding virtual machine identifier and virtual interrupt number in the virtual interrupt table, and the virtual interrupt table records the correspondence between the physical interrupt number and the virtual machine identifier and virtual interrupt number; determine the corresponding interrupt affinity table according to the virtual machine identifier, and determine the identifier of the target virtual processor vCPU corresponding to the virtual machine identifier and virtual interrupt number from the interrupt affinity table. The interrupt affinity table records the correspondence between the virtual interrupt number and the virtual processor; according to the identifier of the target vCPU, determine the target physical processor corresponding to the identifier of the target vCPU from the in-use vCPU identifier group; send the pass-through peripheral interrupt to the sending device corresponding to the target physical processor.

[0168] The sending device is used to: send the pass-through peripheral interrupt to the virtual machine running on the target physical processor.

[0169] In the process of processing the pass-through peripheral interrupt in the embodiments of the present application, the virtual interrupt table, the interrupt affinity table, and the in-use vCPU identifier group will be used in sequence. The interrupt affinity table and the in-use vCPU identifier group can be understood with reference to the previous description. The following introduces the virtual interrupt table.

[0170] The virtual interrupt table maintains the correspondence between the physical interrupt number and the virtual machine identifier and virtual interrupt number. Input a physical interrupt number, and the virtual machine identifier and virtual interrupt number can be output. This virtual interrupt table can be understood with reference to Table 2.

[0171] Table 2: Virtual Interrupt Table

[0172]

[0173]

[0174] As shown in Table 1, when a physical interrupt number 100 is input, the identifier 1 of the virtual machine and the virtual interrupt number 10 can be output. The virtual interrupt table in this application can be stored in a routing device or in memory, and the location of the virtual interrupt table in memory is indicated by another register similar to a base address register.

[0175] During the process of handling the direct-pass peripheral interrupt, as Figure 9 shown, the routing device receives the physical interrupt number sent by the direct-pass peripheral, and looks up the corresponding identifier of the virtual machine and the virtual interrupt number in the virtual interrupt table through this physical interrupt number. For example, when a physical interrupt number 100 is input, the identifier 1 of the virtual machine and the virtual interrupt number 10 can be output. Then, according to the identifier 1 of the virtual machine and the virtual interrupt number 10, look up the interrupt affinity table in Table 1, and find the corresponding identifier of the vCPU. For example, the identifier of the vCPU is found to be 1. Further, according to this vCPU1, look up the corresponding physical processor in the Figure 6 shown in-use vCPU identifier group. For example, if the physical processor 1 is found, the routing device can send the direct-pass peripheral interrupt to the sending device corresponding to the physical processor 1, and the sending device sends the direct-pass peripheral interrupt to the first vCPU corresponding to vCPU1.

[0176] If the first vCPU is not found after looking up the in-use vCPU identifier group above, it means that the first vCPU is not currently running. Then the routing device can send the virtual software interrupt to the sending device of the source physical processor, and the sending device of the source physical processor sends the virtual software interrupt to the host. After the first vCPU goes online and runs, the host sends the virtual software interrupt to the first vCPU.

[0177] From the above Figure 4 、Table 2, Table 1, Figure 6 and Figure 9 process, it can be seen that the process of handling the direct-pass peripheral interrupt provided by the embodiment of this application can complete the sending process through the lookup of three corresponding relationships, improving the flexibility of handling the direct-pass peripheral interrupt.

[0178] During the process of processing the above four types of virtual interrupts, after the sending device receives any one of the above four types of virtual interrupts from the intermediate device, it sends them to the corresponding target physical processor. This sending process can be writing the above several types of virtual interrupts into the pending register, which is used to receive the commands to be executed by the target physical processor next. After writing the virtual interrupt into the pending register, the target physical processor will execute the virtual interrupt next, which can interrupt the currently executing process. If the target vCPU is executing, interrupt the target vCPU and send the interrupt to the target vCPU. If the host is executing, interrupt the host and send the interrupt directly to the running host. After the corresponding target vCPU goes online, the host will then pass the interrupt to the target vCPU. The target vCPU can be the first vCPU or the second vCPU described above. In this way, the solution provided in the embodiment of the present application can shield the action of switching to the host in the existing solution and reduce the switching overhead of the target physical processor from the virtual machine to the host.

[0179] The chip system provided by the embodiment of the present application can be applied to the RISC-V microarchitecture, where RISC is reduced instruction set computing (RISC), such as Figure 10 shown in a schematic structural diagram of the chip system on RISC-V.

[0180] As Figure 10 shown, the chip system includes a control device, a sending device, and an interrupt router for interacting with the physical processor. The interrupt router includes the routing device described in the above embodiment.

[0181] Figure 10Among them, RISC-V-CPU represents the central processing unit in the RISC-V architecture, V = 0 represents the host machine, V = 1 represents the virtual machine, HU-mode represents the user mode of the host machine, HS-mode represents the kernel mode of the host machine, VU-mode represents the user mode of the virtual machine, and VS-mode represents the kernel mode of the virtual machine. The supervisor generate inter-processor interrupt (sgenipi) is used to trigger information for virtual software interrupts, and the supervisor time compare (stimecmp) is a register used to trigger information for virtual local interrupts. When V = 1, that is, when a virtual machine is running on the RISC-V-CPU, information for triggering virtual software interrupts can be sent through sgenipi to the virtual supervisor generate inter-processor interrupt (vsgenipi) register of the control device. The vsgenipi register is the register described in the above embodiments for receiving information for triggering virtual software interrupts, such as: register 2. Information for triggering virtual local interrupts can be sent through stimecmp to the virtual supervisor time compare (vstimecmp) register of the control device. The vstimecmp register is the register described in the above embodiments for receiving information for triggering virtual local interrupts, such as: register 3. The user generate virtual supervisor external interrupt (ugenvsei) register is a register for receiving information for triggering virtual device interrupts, such as register 1 described in the above embodiments. The virtual device emulation logic in the user state of the host machine can directly send information for triggering virtual device interrupts to the ugenvsei register.

[0182] The interrupt router implementation includes registers for a virtual interrupt table (virtual hart shared interrupt mapping, vhsimap), a set of registers for a virtual interrupt affinity table (virtual table base, vtblbase)(1 - n), and a set of interrupt control interface mapping (interface mapping, ifmap) registers. Among them, the vhsimap(1 - n) registers are used to point to the virtual interrupt table stored in memory. Each vtblbase register in the set of vtblbase(1 - n) registers corresponds to a physical processor within the RISC-V system and is used to point to the virtual interrupt affinity table defined by the virtual machine to which the vCPU running on that physical processor belongs. A set of ifmap(1 - n) registers is provided, each corresponding to a physical processor within the system, and is used to record the identifier of the vCPU and the identifier of the virtual machine to which the vCPU running on that physical processor belongs.

[0183] In the above Figure 10 shown RISC-V architecture, the process of handling virtual clock interrupts can be referred to Figure 11 for understanding.

[0184] As Figure 11 shown, the virtual machine uses stimecmp to write the interrupt time to the vstimecmp register, and the control device writes the time when the next virtual clock interrupt is triggered to the clock device dedicated to the virtual machine. When the interrupt time arrives, the clock device dedicated to the virtual machine triggers a virtual clock interrupt. This virtual clock interrupt is sent to the sending device.

[0185] The sending device judges according to the virtualization state V of the current CPU. If V = 1, it directly sends a local interrupt to the virtual machine in VS-mode. If V = 0, it sends it to the host in HS-mode, and the host will handle it on behalf of the virtual machine. That is, after the virtual machine goes online, the host will then pass this virtual clock interrupt to the virtual machine.

[0186] In the above Figure 10 shown RISC-V architecture, the process of handling virtual software interrupts can be referred to Figure 12 for understanding.

[0187] As Figure 12As shown, a vCPU of a virtual machine (which can be referred to as the source vCPU in this scenario) runs on CPU1, and this CPU1 can be the source physical processor in the foregoing embodiments. The source vCPU of the virtual machine writes the identifier of the target vCPU into sgenipi, and through this sgenipi, writes the identifier of the target vCPU into the vsgenipi register in the control device. The control device obtains the identifier of the virtual machine and sends the identifier of the virtual machine and the identifier of the target vCPU (vhartid: the identifier representing the vCPU in RISC-V) to the interrupt router. The interrupt router looks up ifmapx, and the sequence number x of the ifmapx register containing the VMID and vhartid is the identifier of the corresponding physical processor (mhartid: the identifier representing the physical processor in RISC-V). In this scenario, the identifier of this physical processor is Figure 12 CPU2 in, and this CPU2 can also be understood by referring to the target physical processor in the foregoing embodiments. The interrupt router sends a virtual software interrupt to the sending device of the physical processor with the above mhartid. The sending device determines the virtualization state of the current physical processor. If V = 1, the sending device directly sends this virtual software interrupt to the virtual machine. If V = 0, the sending device sends this virtual software interrupt to the host for processing, that is, after the virtual machine is online, the host then sends this virtual software interrupt to the virtual machine.

[0188] In the above Figure 10 shown RISC-V architecture, the process of handling virtual device interrupts can be referred to Figure 13 for understanding.

[0189] As Figure 13 shown, the host in the user state writes the identifier of the virtual machine and the virtual interrupt number into ugenvsei. The control device sends the identifier of the virtual machine and the virtual interrupt number to the interrupt router. The interrupt router looks up the vtblbasex register and finds one of the vtblbasex registers with the identifier of the virtual machine. It looks up the interrupt affinity table saved in the memory pointed to by this register. It obtains the vhartid of the vCPU that processes this interrupt defined by the virtual machine from the interrupt affinity table. The interrupt router looks up ifmapx and finds the sequence number x of the physical processor corresponding to the register with this VMID and vhartid. This x is the mhartid of the target physical processor. The interrupt router sends a virtual device interrupt to the sending device of the physical processor with the above mhartid. The sending device determines the virtualization state of the current CPU. If V = 1, it directly sends a device interrupt to the virtual machine. If V = 0, it sends it to the host for processing, that is, after the virtual machine is online, the host then sends this virtual device interrupt to the virtual machine.

[0190] In the above Figure 10In the RISC-V architecture shown, another process for handling virtual device interrupts can be referred to Figure 14 for understanding.

[0191] As Figure 14 shown, the host writes the identifier of the virtual machine and the virtual interrupt number to ugenvsei. The control device sends the identifier of the virtual machine and the virtual interrupt number to the interrupt router. The interrupt router does not implement vtblbasex and by default sends the virtual interrupt to any vCPU with that virtual machine. Then, the interrupt router looks up ifmapx and finds the serial number x of the physical processor corresponding to the register with the identifier of that virtual machine. This x is the mhartid of the target physical processor. The interrupt router sends the virtual device interrupt to the sending device of the physical processor with the above mhartid. The sending device determines the virtualization state of the current physical processor. If V = 1, it directly sends the virtual device interrupt to the virtual machine. If V = 0, it sends it to the host for proxy processing, that is, after the virtual machine is online, the host sends this virtual device interrupt to the virtual machine again.

[0192] In the above Figure 10 shown RISC-V architecture, the process for handling direct-pass peripheral interrupts can be referred to Figure 15 for understanding.

[0193] As Figure 15 shown, the hardware device directly communicating with the virtual machine triggers a direct-pass peripheral interrupt. The interrupt router looks up the virtual interrupt table pointed to by vhlimap to find the identifier of the virtual machine to which this interrupt is directly passed, and the virtual interrupt number considered within the virtual machine after direct pass. The interrupt router looks up the vtblbasex register and finds one of the vtblbasex registers with that VM ID, and looks up the virtual interrupt affinity table saved in the memory pointed to by this register. The vhartid of the vCPU defined by the virtual machine to handle this interrupt is obtained from the interrupt affinity table. The interrupt router looks up ifmapx and finds the serial number x of the physical processor corresponding to the register with that VMID and vhartid. This x is the mhartid of the target physical processor. The interrupt router sends the direct-pass peripheral interrupt to the sending device of the physical processor with the above mhartid. The sending device determines the virtualization state of the current CPU. If V = 1, it directly sends the direct-pass peripheral interrupt to the virtual machine. If V = 0, it sends it to the host for proxy processing, that is, after the virtual machine is online, the host sends this direct-pass peripheral interrupt to the virtual machine again.

[0194] The above solutions provided by the embodiments of the present application achieve that virtual local interrupts do not trap to the host machine throughout the process from the local interrupt device to the vCPU through the control device, the intermediate device, and the sending device. Virtual software interrupts are realized through the control device, the routing device, and the sending device without the software cooperation between the virtual machine and the host machine, and do not trap to the host machine throughout the process from the sending-end vCPU to the receiving-end vCPU. Virtual device interrupts are realized through the control device, the routing device, and the sending device without switching context / trapping to the host machine throughout the process from the host machine simulation logic to the receiving-end host vCPU. Therefore, the solutions provided by the embodiments of the present application can accelerate the performance of virtual machines in aspects such as I / O, clock, and scheduling. Simulation data shows that when this solution is used to process virtual local interrupts, Redis has an 80% improvement. There is a 6% improvement in processing virtual software interrupts.

[0195] The above describes the process of processing virtual interrupts implemented by means of hardware circuits. The process of processing virtual interrupts provided by the embodiments of the present application can also be implemented by software, and this software implementation process can also be integrated into the above chip system. The chip system includes a source physical processor, a control device, an intermediate device, and a sending device. The control device includes registers; the registers are used to receive information for triggering virtual interrupts. The functions of the control device, the intermediate device, and the sending device can be implemented in the form of software code, which will be introduced below with reference to the accompanying drawings.

[0196] As Figure 16 shown, an embodiment of the method for processing virtual interrupts provided by the embodiments of the present application includes:

[0197] 101. The control device reads the information for triggering virtual interrupts from the register.

[0198] The information for triggering virtual interrupts comes from the host machine or the virtual machine running on the source physical processor.

[0199] 102. The control device sends the information for triggering virtual interrupts to the intermediate device. Correspondingly, the intermediate device receives the information for triggering virtual interrupts.

[0200] 103. The intermediate device triggers a virtual interrupt according to the information for triggering the virtual interrupt.

[0201] 104. The intermediate device sends the virtual interrupt to the sending device. Correspondingly, the sending device receives the virtual interrupt.

[0202] 105. The sending device sends a virtual interrupt to a target physical processor. In the solution provided by the embodiments of the present application, a register dedicated to processing virtual interrupts is set in the control device. In this way, the host machine or virtual machine in the user state can directly write the information for triggering the virtual interrupt into this register. The control device can send the information for triggering the virtual interrupt to the intermediate device, and the intermediate device triggers the virtual interrupt. Moreover, the intermediate device sends the virtual interrupt to the sending device, and the sending device sends the virtual interrupt to the target physical processor. In the solution provided by the present application, both the host machine and the virtual machine can directly access the register and write the information for triggering the virtual interrupt into the register, so as to send out the virtual interrupt. Therefore, compared with the prior art, the solution provided by the present application does not require the source physical processor to perform the switch from the virtual machine to the host machine, or the source physical processor to perform the switch from the user state of the host machine to the kernel state of the host machine, thereby reducing the switching overhead generated by processing virtual interrupts and improving the performance of the chip system.

[0203] When the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor; the register receives the information for triggering the virtual local interrupt written by the virtual machine.

[0204] The intermediate device generates a virtual local interrupt according to the information for triggering the virtual local interrupt.

[0205] The sending device sends the virtual local interrupt to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.

[0206] When the virtual interrupt is a virtual software interrupt, the information for triggering the virtual interrupt read from the register in step 101 includes the identifier of the second vCPU written by the first vCPU of the virtual machine into the register, and the second vCPU is the vCPU of the virtual machine running on the target physical processor.

[0207] Before step 102, the control device obtains the identifier of the virtual machine; then step 103 specifically includes sending the identifier of the virtual machine and the identifier of the second vCPU to the intermediate device.

[0208] Step 103 specifically includes that the intermediate device determines the target physical processor corresponding to the identifier of the virtual machine and the identifier of the second vCPU from the first correspondence relationship; wherein, the first correspondence relationship is used to record the correspondence relationship between the target physical processor, the second vCPU running on the target physical processor, and the virtual machine; trigger the virtual software interrupt.

[0209] Step 104 includes: the intermediate device sends the virtual software interrupt to the sending device corresponding to the target physical processor.

[0210] Step 105 includes: The sending device sends a virtual software interrupt to a second vCPU running on the target physical processor.

[0211] When the virtual interrupt is a virtual device interrupt, the information for triggering the virtual interrupt read from the register in the above step 101 includes the target interrupt number written by the host to the register and the identifier of the virtual machine. The target interrupt number is the identifier of the interrupt triggered when the host simulates a hardware device.

[0212] Step 102 includes: The control device sends the identifier of the virtual machine and the target interrupt number to the intermediate device.

[0213] Step 103 includes: The intermediate device looks up the identifier of the first vCPU of the virtual machine corresponding to the identifier of the virtual machine and the target interrupt number in the second correspondence relationship. The second correspondence relationship is used to record the correspondence relationship between the virtual machine, the target interrupt number, and the first vCPU; determines the target physical processor corresponding to the identifier of the virtual machine and the identifier of the first vCPU from the third correspondence relationship. The third correspondence relationship is used to record the correspondence relationship between the target physical processor, the first vCPU running on the target physical processor, and the virtual machine; generates a virtual device interrupt.

[0214] Step 104 includes: The intermediate device sends the virtual device interrupt to the sending device corresponding to the target physical processor.

[0215] Step 105 includes: The sending device sends the virtual device interrupt to the first vCPU running on the target physical processor.

[0216] Above, the functions of the control device, the intermediate device, and the sending device implemented by software can be understood by referring to the corresponding content in the above Figures 2 to 15 corresponding embodiments, and will not be repeated here.

[0217] The method for processing virtual interrupts implemented by software is introduced above. Next, the device for implementing the method for processing virtual interrupts will be introduced with reference to the accompanying drawings.

[0218] As Figure 17 shown, an embodiment of the control device 20 provided in an embodiment of the present application includes: The control device 20 is applied in a chip system. The chip system further includes a source physical processor, an intermediate device, a sending device, and a target physical processor. The source physical processor is used to run a host or a virtual machine. The control device includes a register. The register is used to receive information for triggering a virtual interrupt. The information for triggering the virtual interrupt comes from the host or the virtual machine. The control device 20 includes:

[0219] A reading unit 201, configured to read information for triggering a virtual interruption from a register.

[0220] A sending unit 202, configured to send the information for triggering a virtual interruption read by the reading unit 201 to an intermediate device. The information for triggering a virtual interruption is used by the intermediate device to trigger a virtual interruption, and the virtual interruption is sent by a sending device to a target physical processor.

[0221] Optionally, the virtual interruption is a virtual local interruption, the target physical processor and the source physical processor are the same physical processor, and the register is used to receive information for triggering a virtual local interruption written by a virtual machine; the information for triggering a virtual local interruption is used to cause the intermediate device to trigger a virtual local interruption, and the virtual local interruption is sent by the sending device to a first virtual central processing unit (vCPU) of the virtual machine, and the first vCPU runs on the source physical processor.

[0222] Optionally, the virtual interruption is a virtual software interruption, and the information for triggering a virtual interruption includes an identifier of a second vCPU written by a first VCPU of a virtual machine to a register. The second vCPU is a vCPU of a virtual machine running on a target physical processor; the control device 20 further includes a processing unit 203.

[0223] A processing unit 203, configured to obtain an identifier of a virtual machine.

[0224] A sending unit 202, configured to send the identifier of the virtual machine to the intermediate device. The identifier of the virtual machine and the identifier of the second vCPU are used by the intermediate device to determine a target physical processor and trigger a virtual software interruption, and the virtual software interruption is sent by the sending device to the second vCPU of the target physical processor.

[0225] Optionally, the virtual interruption is a virtual device interruption, and the information for triggering a virtual interruption includes a target interrupt number written by a host computer to a register and an identifier of a virtual machine. The target interrupt number is an identifier of an interruption triggered when the host computer simulates a hardware device; the identifier of the virtual machine and the target interrupt number are used by the intermediate device to determine a target physical processor and trigger a virtual device interruption, and the virtual device interruption is sent by the sending device to a first vCPU of the target physical processor.

[0226] As Figure 18 shown, an embodiment of an intermediate device 30 provided in an embodiment of the present application includes: The intermediate device 30 is applied to a chip system, and the chip system further includes a source physical processor, a control device, a sending device, and a target physical processor. The source physical processor is used to run a host computer or a virtual machine, and the control device includes a register; the register is used to receive information for triggering a virtual interruption, and the information for triggering a virtual interruption comes from a host computer or a virtual machine. The intermediate device 30 includes:

[0227] A receiving unit 301, configured to receive information for triggering a virtual interrupt from a control device.

[0228] A processing unit 302, configured to trigger a virtual interrupt according to the information for triggering the virtual interrupt.

[0229] A sending unit 303, configured to send the virtual interrupt to a sending device, and the virtual interrupt is sent by the sending device to a target physical processor.

[0230] Optionally, the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, and a register is used to receive information written by a virtual machine for triggering the virtual local interrupt; the information for triggering the virtual local interrupt is used to trigger the virtual local interrupt, and the virtual local interrupt is sent by the sending device to a first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.

[0231] Optionally, the virtual interrupt is a virtual software interrupt, and the information for triggering the virtual interrupt includes an identifier of a second vCPU written by a first vCPU of the virtual machine to a register, and the second vCPU is a vCPU of a virtual machine running on the target physical processor.

[0232] The processing unit 302 is configured to determine, according to the identifier of the virtual machine and the identifier of the second vCPU, a target physical processor corresponding to the identifier of the virtual machine and the identifier of the second vCPU from a first correspondence relationship; wherein, the first correspondence relationship is used to record the correspondence relationship between the target physical processor, the second vCPU running on the target physical processor, and the virtual machine; trigger a virtual software interrupt, and the virtual software interrupt is sent by the sending device to the second vCPU of the target physical processor.

[0233] Optionally, the virtual interrupt is a virtual device interrupt, and the information for triggering the virtual interrupt includes a target interrupt number written by a host to a register and an identifier of a virtual machine, and the target interrupt number is an identifier of an interrupt triggered when the host simulates a hardware device.

[0234] The processing unit 302 is configured to search, according to the identifier of the virtual machine and the target interrupt number, for an identifier of a first vCPU of the virtual machine corresponding to the identifier of the virtual machine and the target interrupt number in a second correspondence relationship, and the second correspondence relationship is used to record the correspondence relationship between the virtual machine, the target interrupt number, and the first vCPU; determine, according to the identifier of the virtual machine and the identifier of the first vCPU, a target physical processor corresponding to the identifier of the virtual machine and the identifier of the first vCPU from a third correspondence relationship; wherein, the third correspondence relationship is used to record the correspondence relationship between the target physical processor, the first vCPU running on the target physical processor, and the virtual machine; trigger a virtual device interrupt, and the virtual device interrupt is sent by the sending device to the first vCPU of the target physical processor.

[0235] Optionally, the processing unit 302 is further configured to find an address register according to the identifier of the virtual machine, and obtain a second correspondence from the memory according to the address in the address register. The address register is used to store the address of the second correspondence in the memory and the identifier of the virtual machine.

[0236] As Figure 19 shown, an embodiment of the sending device 40 provided by the embodiment of the present application includes: The sending device 40 is applied to a chip system, and the chip system further includes a source physical processor, an intermediate device, a control device, and a target physical processor. The source physical processor is used to run a host or a virtual machine. The control device includes a register; the register is used to receive information for triggering a virtual interruption, and the information for triggering the virtual interruption comes from the host or the virtual machine. The sending device 40 includes:

[0237] A receiving unit 401, configured to receive a virtual interruption from the intermediate device.

[0238] A sending unit 402, configured to send the virtual interruption to the target physical processor.

[0239] Optionally, the virtual interruption is a virtual local interruption, and the target physical processor and the source physical processor are the same physical processor; the sending unit 402 is configured to send the virtual local interruption to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.

[0240] Optionally, the virtual interruption is a virtual software interruption, and the information for triggering the virtual interruption includes the identifier of the second vCPU written by the first vCPU of the virtual machine to the register. The second vCPU is the vCPU of the virtual machine running on the target physical processor.

[0241] The sending unit 402 is configured to send the virtual software interruption to the second vCPU running on the target physical processor.

[0242] Optionally, the virtual interruption is a virtual device interruption, and the information for triggering the virtual interruption includes the target interruption number written by the host to the register and the identifier of the virtual machine. The target interruption number is the identifier of the interruption triggered when the host simulates a hardware device.

[0243] The sending unit 402 is configured to send the virtual device interruption to the first vCPU running on the target physical processor.

[0244] Optionally, the sending unit 402 is configured to write the virtual interruption into the pending register of the target physical processor, and the pending register is used to receive commands for the process executed by the target physical processor.

[0245] The above Figures 17 to 19 described solution can be referred to the aboveFigures 2 to 15 For the corresponding content in the corresponding embodiments, refer to the relevant parts for understanding and no repeated description will be given here.

[0246] Figure 20 As shown in the figure, it is a schematic diagram of a possible logical structure of a computer device 50 provided by an embodiment of the present application. The computer device 50 may include the control device, intermediate device or sending device introduced above. The computer device 50 includes: a processor 501, a communication interface 502, a memory 503, and a bus 504. The processor 501, the communication interface 502, and the memory 503 are connected to each other through the bus 504. In the embodiment of the present application, the processor 501 is used to control and manage the actions of the computer device 50. For example, the processor 501 is used to execute Figures 17 to 19 step 101 or step 103 in the method embodiment of. The memory 503 is used to store the program code and data of the computer device 50. The communication interface 502 can be used to execute Figure 16 step 102, step 104 or step 105 in the method embodiment of. Figure 16

[0247] Among them, the processor 501 may be a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. It can implement or execute various exemplary logic blocks, modules and circuits described in combination with the disclosure of the present application. The processor 501 may also be a combination for implementing computing functions, such as a combination including one or more microprocessors, a combination of a digital signal processor and a microprocessor, and so on. The bus 504 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience of representation, Figure 20 only a thick line is used to represent it in the figure, but it does not mean that there is only one bus or one type of bus.

[0248] In another embodiment of the present application, a computer-readable storage medium is further provided. The computer-readable storage medium stores computer-executable instructions. When the processor of the device executes the computer-executable instructions, the device executes the method for processing virtual interrupts performed by the control device, intermediate device or sending device described above. Figure 16

[0249] In another embodiment of the present application, a computer program product is further provided. The computer program product includes computer-executable instructions stored in a computer-readable storage medium. When a processor of a device executes the computer-executable instructions, the device executes the method for processing virtual interruptions performed by the control device, the intermediate device, or the sending device in the above Figure 16 .

[0250] In another embodiment of the present application, a chip system is further provided. The chip system includes a source physical processor, a control device, a sending device, and a target physical processor. The control device is the control device described in the foregoing Figures 2 to 15 embodiment, and the sending device is the sending device described in the foregoing Figures 2 to 15 embodiment.

[0251] In a possible embodiment, the chip system may further include an intermediate device described in the foregoing Figures 2 to 15 embodiment.

[0252] In a possible embodiment, the chip system is a processor. The source physical processor and the target physical processor are physical cores in the processor, and the control device is a component located in the processor and coupled to the source physical processor, and the sending device is a component located in the processor and coupled to the target physical processor. It can be understood that since any physical core in the processor may be a recipient of a virtual interruption, a physical core may act as both the source physical processor and the target physical processor. Correspondingly, what is coupled to this physical core may include both the control device and the sending device.

[0253] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. A professional technician can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the embodiments of the present application.

[0254] Those skilled in the art can clearly understand that for the convenience and conciseness of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments, and will not be elaborated herein.

[0255] In several embodiments provided by the embodiments of the present application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling, direct coupling, or communication connection between each other can be through some interfaces. The indirect coupling or communication connection of devices or units can be in electrical, mechanical, or other forms.

[0256] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place, or they can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0257] In addition, in each embodiment of the embodiments of the present application, each functional unit can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0258] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the embodiments of the present application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in the embodiments of the present application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.

[0259] The above is only the specific implementation manner of the embodiments of the present application, but the protection scope of the embodiments of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed in the embodiments of the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the embodiments of the present application. Therefore, the protection scope of the embodiments of the present application should be subject to the protection scope of the claims.

Claims

1. A chip system, characterized in that, Comprising: A source physical processor, a control device, an intermediate device, a sending device, and a target physical processor. The source physical processor is used to run a host or a virtual machine. The control device includes a register, and the register is used to receive information for triggering a virtual interruption. The information for triggering the virtual interruption comes from the host or the virtual machine; The control device is used to: send the information for triggering the virtual interruption in the register to the intermediate device; The intermediate device is used to: send the virtual interruption to the sending device; The sending device is used to: receive the virtual interruption from the intermediate device and send the virtual interruption to the target physical processor.

2. The chip system according to claim 1, wherein The virtual interruption is a virtual local interruption, and the target physical processor and the source physical processor are the same physical processor; The register is used to: receive the information written by the virtual machine for triggering the virtual local interruption; The sending device is used to: send the virtual local interruption to the first virtual processor of the virtual machine, and the first virtual processor runs on the source physical processor.

3. The chip system according to claim 1, characterized in that The virtual interruption is a virtual software interruption, and the information for triggering the virtual interruption includes the identifier of the second virtual processor written by the first virtual processor of the virtual machine into the register. The second virtual processor is the virtual processor of the virtual machine running on the target physical processor; The control device is used to: read the identifier of the second virtual processor from the register and obtain the identifier of the virtual machine; and send the identifier of the virtual machine and the identifier of the second virtual processor to the intermediate device; The intermediate device is used to: Determine the target physical processor corresponding to the identifier of the virtual machine and the identifier of the second virtual processor from a first correspondence relationship. The first correspondence relationship is used to record the correspondence relationship between the target physical processor, the second virtual processor running on the target physical processor, and the virtual machine; Send the virtual software interruption to the sending device corresponding to the target physical processor; The sending device is used to: send the virtual software interruption to the second virtual processor running on the target physical processor.

4. The chip system according to claim 1, characterized in that, The virtual interruption is a virtual device interruption, and the information for triggering the virtual interruption includes the target interrupt number written by the host into the register and the identifier of the virtual machine. The target interrupt number is the identifier of the interruption triggered when the host simulates a hardware device; The control device is used to: read the target interrupt number and the identifier of the virtual machine from the register and send the identifier of the virtual machine and the target interrupt number to the intermediate device; The intermediate device is used to: Look up the identifier of the first virtual processor of the virtual machine corresponding to the identifier of the virtual machine and the target interrupt number in the second correspondence relationship, where the second correspondence relationship is used to record the correspondence relationship between the virtual machine, the target interrupt number, and the first virtual processor; Determine the target physical processor corresponding to the identifier of the virtual machine and the identifier of the first virtual processor from the third correspondence relationship; where the third correspondence relationship is used to record the correspondence relationship between the target physical processor, the first virtual processor running on the target physical processor, and the virtual machine; Send the virtual device interrupt to the sending device corresponding to the target physical processor; The sending device is used to: send the virtual device interrupt to the first virtual processor running on the target physical processor.

5. The chip system according to claim 4, wherein The intermediate device includes an address register, and the address register is used to store the address of the second correspondence relationship in the memory and the identifier of the virtual machine; The intermediate device is further used to: find the address register according to the identifier of the virtual machine, and obtain the second correspondence relationship from the memory according to the address in the address register.

6. A control device, characterized in that, The control device is applied to a chip system, and the chip system further includes a source physical processor, an intermediate device, a sending device, and a target physical processor. The source physical processor is used to run a host or a virtual machine. The control device includes a register; the register is used to receive information for triggering a virtual interrupt, and the information for triggering the virtual interrupt comes from the host or the virtual machine; The control device is used to: read the information for triggering the virtual interrupt from the register, and send the information for triggering the virtual interrupt to the intermediate device. The information for triggering the virtual interrupt is used to cause the intermediate device to trigger the virtual interrupt, and the virtual interrupt is sent by the sending device to the target physical processor.

7. The control device according to claim 6, characterized in that, The virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, and the register is used to receive the information written by the virtual machine for triggering the virtual local interrupt; The control device is used to: send the information for triggering the virtual local interrupt to the intermediate device. The information for triggering the virtual local interrupt is used to cause the intermediate device to trigger the virtual local interrupt, and the virtual local interrupt is sent by the sending device to the first virtual processor of the virtual machine, and the first virtual processor runs on the source physical processor.

8. The control device according to claim 6, characterized in that The virtual interrupt is a virtual software interrupt, and the information for triggering the virtual interrupt includes the identifier of the second virtual processor written by the first virtual processor of the virtual machine to the register. The second virtual processor is the virtual processor of the virtual machine running on the target physical processor; The control device is configured to: read the identifier of the second virtual processor from the register and obtain the identifier of the virtual machine; and send the identifier of the virtual machine and the identifier of the second virtual processor to the intermediate device, where the identifier of the virtual machine and the identifier of the second virtual processor are used by the intermediate device to determine the target physical processor and trigger the virtual software interrupt, and the virtual software interrupt is sent by the sending device to the second virtual processor of the target physical processor.

9. The control device according to claim 6, characterized in that, The virtual interrupt is a virtual device interrupt, and the information for triggering the virtual interrupt includes the target interrupt number written by the host to the register and the identifier of the virtual machine, where the target interrupt number is the identifier of the interrupt triggered when the host simulates a hardware device; The control device is configured to: read the target interrupt number and the identifier of the virtual machine from the register and send the identifier of the virtual machine and the target interrupt number to the intermediate device, where the identifier of the virtual machine and the target interrupt number are used by the intermediate device to determine the target physical processor and trigger the virtual device interrupt, and the virtual device interrupt is sent by the sending device to the first virtual processor of the virtual machine of the target physical processor.

10. An intermediate device, characterized in that, The intermediate device is applied to a chip system, and the chip system further includes a source physical processor, a control device, a sending device, and a target physical processor. The source physical processor is configured to run a host or a virtual machine, and the control device includes a register; the register is configured to receive the information for triggering a virtual interrupt, and the information for triggering the virtual interrupt comes from the host or the virtual machine; The intermediate device is configured to: receive the information for triggering the virtual interrupt from the control device and send the virtual interrupt to the sending device, and the virtual interrupt is sent by the sending device to the target physical processor.

11. The intermediate device according to claim 10, wherein The virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, and the register is configured to receive the information for triggering the virtual local interrupt written by the virtual machine; The intermediate device is configured to: trigger the virtual local interrupt according to the information for triggering the virtual local interrupt and send the virtual local interrupt to the sending device, and the virtual local interrupt is sent by the sending device to the first virtual processor of the virtual machine, and the first virtual processor runs on the source physical processor.

12. The intermediate device according to claim 10, wherein The virtual interrupt is a virtual software interrupt, and the information for triggering the virtual interrupt includes the identifier of the second virtual processor written by the first virtual processor of the virtual machine to the register, where the second virtual processor is a virtual processor of the virtual machine running on the target physical processor; The intermediate device is configured to: receive the identifier of the virtual machine and the identifier of the second virtual processor from the control device; Determine the target physical processor corresponding to the identifier of the virtual machine and the identifier of the second virtual processor from the first corresponding relationship, where the first corresponding relationship is used to record the corresponding relationship among the target physical processor, the second virtual processor running on the target physical processor, and the virtual machine; Trigger the virtual software interrupt; Send the virtual software interrupt to the sending device corresponding to the target physical processor, and the virtual software interrupt is sent by the sending device to the second virtual processor of the target physical processor.

13. The intermediate device according to claim 10, characterized in that, The virtual interrupt is a virtual device interrupt, and the information for triggering the virtual interrupt includes the target interrupt number written by the host machine to the register and the identifier of the virtual machine, where the target interrupt number is the identifier of the interrupt triggered when the host machine simulates a hardware device; The intermediate device is used for: Receive the identifier of the virtual machine and the target interrupt number from the control device; According to the identifier of the virtual machine and the target interrupt number, search in the second corresponding relationship for the identifier of the first virtual processor of the virtual machine corresponding to the identifier of the virtual machine and the target interrupt number, where the second corresponding relationship is used to record the corresponding relationship among the virtual machine, the target interrupt number, and the first virtual processor; According to the identifier of the virtual machine and the identifier of the first virtual processor, determine the target physical processor corresponding to the identifier of the virtual machine and the identifier of the first virtual processor from the third corresponding relationship, where the third corresponding relationship is used to record the corresponding relationship among the target physical processor, the first virtual processor running on the target physical processor, and the virtual machine; Trigger the virtual device interrupt; Send the virtual device interrupt to the sending device corresponding to the target physical processor, and the virtual device interrupt is sent by the sending device to the first virtual processor of the target physical processor.

14. The intermediate device according to claim 13, characterized in that, The intermediate device includes an address register, and the address register is used to store the address of the second corresponding relationship in the memory and the identifier of the virtual machine; The intermediate device is further used for: finding the address register according to the identifier of the virtual machine, and obtaining the second corresponding relationship from the memory according to the address in the address register.

15. A transmitting device, characterized in that, The sending device is applied to a chip system, and the chip system further includes a source physical processor, an intermediate device, a control device, and a target physical processor. The source physical processor is used to run a host machine or a virtual machine, and the control device includes a register; the register is used to receive the information for triggering the virtual interrupt, and the information for triggering the virtual interrupt comes from the host machine or the virtual machine; The sending device is used for: receiving the virtual interrupt from the intermediate device and sending the virtual interrupt to the target physical processor.

16. The transmitting device according to claim 15, characterized in that, The virtual interrupt is a virtual local interrupt, and the target physical processor and the source physical processor are the same physical processor; The sending device is configured to: receive the virtual local interrupt from the intermediate device, and send the virtual local interrupt to a first virtual processor of the virtual machine, where the first virtual processor runs on the source physical processor.

17. The transmitting device according to claim 15, wherein The virtual interrupt is a virtual software interrupt, and the information for triggering the virtual interrupt includes an identifier of a second virtual processor written by the first virtual processor of the virtual machine to the register, where the second virtual processor is a virtual processor of the virtual machine running on the target physical processor; The sending device is configured to: receive the virtual software interrupt from the intermediate device, and send the virtual software interrupt to the second virtual processor running on the target physical processor.

18. The transmitting device according to claim 15, wherein The virtual interrupt is a virtual device interrupt, and the information for triggering the virtual interrupt includes a target interrupt number written by the host computer to the register and an identifier of the virtual machine, where the target interrupt number is an identifier of an interrupt triggered when the host computer simulates a hardware device; The sending device is configured to: receive the virtual device interrupt from the intermediate device, and send the virtual device interrupt to a first virtual processor running on the target physical processor.

19. The sending device according to any one of claims 15-18, wherein The sending device is configured to: write the virtual interrupt into a pending register of the target physical processor, where the pending register is used to receive commands of a process executed by the target physical processor.

20. A method for processing virtual interrupts, characterized in that, The method is applied to a control device in a chip system, the chip system further includes a source physical processor, an intermediate device, a sending device, and a target physical processor, the source physical processor is used to run a host computer or a virtual machine, the control device includes a register; the register is used to receive information for triggering a virtual interrupt, and the information for triggering the virtual interrupt comes from the host computer or the virtual machine, and the method includes: Read the information for triggering the virtual interrupt from the register; Send the information for triggering the virtual interrupt to the intermediate device, where the information for triggering the virtual interrupt is used to cause the intermediate device to send the virtual interrupt to the sending device, and the virtual interrupt is sent by the sending device to the target physical processor.

21. The method according to claim 20, wherein The virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, and the register is used to receive information for triggering the virtual local interrupt written by the virtual machine; The information for triggering the virtual local interrupt is used for the intermediate device to trigger the virtual local interrupt, and the virtual local interrupt is sent by the sending device to a first virtual processor of the virtual machine, where the first virtual processor runs on the source physical processor.

22. The method according to claim 20, characterized in that, The virtual interrupt is a virtual software interrupt, and the information for triggering the virtual interrupt includes the identifier of a second virtual processor written by a first virtual processor of the virtual machine to the register, where the second virtual processor is a virtual processor of the virtual machine running on the target physical processor; the method further includes: Obtaining the identifier of the virtual machine; Sending the identifier of the virtual machine to the intermediate device, where the identifier of the virtual machine and the identifier of the second virtual processor are used by the intermediate device to determine the target physical processor and trigger the virtual software interrupt, and the virtual software interrupt is sent by the sending device to the second virtual processor of the target physical processor.

23. The method according to claim 20, wherein The virtual interrupt is a virtual device interrupt, and the information for triggering the virtual interrupt includes the target interrupt number written by the host to the register and the identifier of the virtual machine, where the target interrupt number is the identifier of an interrupt triggered when the host simulates a hardware device; the identifier of the virtual machine and the target interrupt number are used by the intermediate device to determine the target physical processor and trigger the virtual device interrupt, and the virtual device interrupt is sent by the sending device to the first virtual processor of the target physical processor.

24. A method for processing virtual interrupts, characterized in that, The method is applied to an intermediate device in a chip system, and the chip system further includes a source physical processor, a control device, a sending device, and a target physical processor. The source physical processor is used to run a host or a virtual machine, and the control device includes a register; the register is used to receive information for triggering a virtual interrupt, and the information for triggering the virtual interrupt comes from the host or the virtual machine. The method includes: Receiving the information for triggering the virtual interrupt from the control device; Sending the virtual interrupt to the sending device, and the virtual interrupt is sent by the sending device to the target physical processor.

25. The method according to claim 24, wherein The virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, and the register is used to receive information written by the virtual machine for triggering the virtual local interrupt; The information for triggering the virtual local interrupt is used to trigger the virtual local interrupt, and the virtual local interrupt is sent by the sending device to the first virtual processor of the virtual machine, and the first virtual processor runs on the source physical processor.

26. The method according to claim 24, characterized in that The virtual interrupt is a virtual software interrupt, and the information for triggering the virtual interrupt includes the identifier of a second virtual processor written by a first virtual processor of the virtual machine to the register, where the second virtual processor is a virtual processor of the virtual machine running on the target physical processor; Triggering the virtual interrupt according to the information for triggering the virtual interrupt includes: Determine the target physical processor corresponding to the identifier of the virtual machine and the identifier of the second virtual processor from a first correspondence relationship, where the first correspondence relationship is used to record the correspondence relationship among the target physical processor, the second virtual processor running on the target physical processor, and the virtual machine; Trigger the virtual software interrupt, where the virtual software interrupt is sent by the sending device to the second virtual processor of the target physical processor.

27. The method according to claim 24, characterized in that, The virtual interrupt is a virtual device interrupt, and the information for triggering the virtual interrupt includes the target interrupt number written by the host to the register and the identifier of the virtual machine, where the target interrupt number is the identifier of the interrupt triggered when the host simulates a hardware device; The triggering of the virtual interrupt according to the information for triggering the virtual interrupt includes: Search for the identifier of the first virtual processor of the virtual machine corresponding to the identifier of the virtual machine and the target interrupt number in a second correspondence relationship, where the second correspondence relationship is used to record the correspondence relationship among the virtual machine, the target interrupt number, and the first virtual processor; Determine the target physical processor corresponding to the identifier of the virtual machine and the identifier of the first virtual processor from a third correspondence relationship, where the third correspondence relationship is used to record the correspondence relationship among the target physical processor, the first virtual processor running on the target physical processor, and the virtual machine; Trigger the virtual device interrupt, where the virtual device interrupt is sent by the sending device to the first virtual processor of the target physical processor.

28. The method according to claim 27, wherein The method further includes: Locate the address register according to the identifier of the virtual machine, and obtain the second correspondence relationship from the memory according to the address in the address register, where the address register is used to store the address of the second correspondence relationship in the memory and the identifier of the virtual machine.

29. A method for handling virtual interrupts, characterized in that, The method is applied to a sending device in a chip system, and the chip system further includes a source physical processor, an intermediate device, a control device, and a target physical processor. The source physical processor is used to run a host or a virtual machine, and the control device includes a register; the register is used to receive the information for triggering a virtual interrupt, and the information for triggering the virtual interrupt comes from the host or the virtual machine. The method includes: Receive the virtual interrupt from the intermediate device; Send the virtual interrupt to the target physical processor.

30. The method according to claim 29, wherein The virtual interrupt is a virtual local interrupt, and the target physical processor and the source physical processor are the same physical processor; The sending of the virtual interrupt to the target physical processor includes: Send the virtual local interrupt to the first virtual processor of the virtual machine, where the first virtual processor runs on the source physical processor.

31. The method according to claim 29, wherein The virtual interrupt is a virtual software interrupt, and the information for triggering the virtual interrupt includes the identifier of a second virtual processor written by a first virtual processor of the virtual machine to the register, where the second virtual processor is a virtual processor of the virtual machine running on the target physical processor; The sending the virtual interrupt to the target physical processor includes: Sending the virtual software interrupt to the second virtual processor running on the target physical processor.

32. The method according to claim 29, wherein The virtual interrupt is a virtual device interrupt, and the information for triggering the virtual interrupt includes the target interrupt number written by the host to the register and the identifier of the virtual machine, where the target interrupt number is the identifier of an interrupt triggered when the host simulates a hardware device; The sending the virtual interrupt to the target physical processor includes: Sending the virtual device interrupt to a first virtual processor running on the target physical processor.

33. The method according to any one of claims 29 to 32, characterized in that, The method further includes: Writing the virtual interrupt into a pending register of the target physical processor, where the pending register is used to receive commands of a process executed by the target physical processor.

34. A chip system, characterized in that, It includes a source physical processor, a control device, a sending device, and a target physical processor, where the control device is the control device according to any one of claims 6-9 above, and the sending device is the sending device according to any one of claims 15-19 above.

35. The chip system according to claim 34, wherein The chip system further includes an intermediate device, where the intermediate device is the intermediate device according to any one of claims 10-14 above.

36. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method according to any one of claims 20-23, or implements the method according to any one of claims 24-28 when executed, or implements the method according to any one of claims 29-33 when executed.

37. A computer device, characterized in that, The computer device includes the chip system according to any one of claims 1-5 above, or includes the chip system according to claim 34 or 35 above.

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