Wafer Pre-alignment Method and Apparatus, Electronic Device, Storage Medium

Abstract

Embodiments of the present disclosure provide a wafer pre-alignment method and apparatus, an electronic device, and a storage medium, relating to the technical field of integrated circuit test equipment. The wafer pre-alignment method includes: obtaining at least two wafer images of a target wafer collected by a planar array camera; performing notch detection processing on the wafer images to obtain notch position information; performing wafer position deviation calculation processing on the wafer images to obtain wafer position deviation information; and performing pre-alignment processing on the target wafer according to the notch position information and the wafer position deviation information. The technical solution provided by the embodiments of the present disclosure can improve the efficiency of wafer testing.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit testing equipment, and particularly to a wafer pre-alignment method and device, an electronic device, and a storage medium. Background Art

[0002] Wafer pre-alignment is one of the important functions of wafer testing equipment. Before the wafer undergoes probe testing or optical inspection, it is necessary to perform pre-alignment to detect the center position and notch direction of the wafer, so as to adjust the position and angle of the wafer, so that the position and angle of the wafer placed on the test station meet the requirements.

[0003] The current pre-alignment method for wafers is to use a line array camera to obtain the entire image of the wafer to achieve pre-alignment. Due to severe image distortion, the alignment accuracy of the pre-alignment process using a line array camera is low, which in turn leads to low wafer testing efficiency. Summary of the Invention

[0004] The main purpose of the embodiments of the present disclosure is to propose a wafer pre-alignment method and device, an electronic device, and a storage medium, which can improve the efficiency of wafer testing.

[0005] To achieve the above object, a first aspect of the embodiments of the present disclosure proposes a wafer pre-alignment method, including:

[0006] Obtain at least two wafer images of a target wafer collected by a area array camera;

[0007] Perform notch detection processing on the wafer image to obtain notch position information;

[0008] Perform wafer position deviation calculation processing on the wafer image to obtain wafer position deviation information;

[0009] Perform pre-alignment processing on the target wafer according to the notch position information and the wafer position deviation information.

[0010] In some embodiments, the performing notch detection processing on the wafer image to obtain notch position information includes:

[0011] Perform notch image recognition processing on the wafer image to obtain a target image;

[0012] Perform notch position calculation processing on the target image to obtain the notch position information.

[0013] In some embodiments, the performing notch image recognition processing on the wafer image to obtain a target image includes:

[0014] Perform notch image recognition processing on the wafer image to obtain the wafer image including the notch contour;

[0015] Use the wafer image including the notch contour as the target image.

[0016] In some embodiments, the calculating the notch position of the target image to obtain the notch position information includes:

[0017] Obtain the first angle information of the target image; the first angle information is the shooting angle of the wafer image including the notch contour;

[0018] Obtain the second angle information of the target image; the second angle information is the angle of the notch contour in the target image;

[0019] Perform comprehensive analysis on the first angle information and the second angle information to obtain the notch position information.

[0020] In some embodiments, the obtaining the first angle information of the target image includes:

[0021] Obtain the number information of the target image;

[0022] Query according to the number information in a preset number-angle comparison table to obtain the first angle information corresponding to the target image.

[0023] In some embodiments, the obtaining the second angle information of the target image includes:

[0024] Obtain the vector change rate of each contour point in the target image;

[0025] Analyze the vector change rate to obtain the second angle information of the target image.

[0026] In some embodiments, the calculating the wafer position deviation of the wafer image to obtain the wafer position deviation information includes:

[0027] Perform center calculation on each wafer image to obtain the center coordinates of each wafer image;

[0028] Perform fitting on the center coordinates to obtain the rotation center coordinates;

[0029] Obtain the wafer position deviation information according to the rotation center coordinates and the center coordinates.

[0030] To achieve the above object, a second aspect of the present disclosure provides a wafer pre-alignment device, including:

[0031] An image acquisition module, configured to acquire at least two wafer images of a target wafer collected by a area array camera;

[0032] A notch detection module for performing notch detection processing on the wafer image to obtain notch position information;

[0033] A wafer position deviation calculation module for performing wafer position deviation calculation processing on the wafer image to obtain wafer position deviation information;

[0034] A pre-alignment module for performing pre-alignment processing on the target wafer according to the notch position information and the wafer position deviation information.

[0035] To achieve the above object, a third aspect of the present disclosure proposes an electronic device, including:

[0036] At least one memory;

[0037] At least one processor;

[0038] At least one program;

[0039] The program is stored in the memory, and the processor executes the at least one program to implement the method described in the first aspect of the present disclosure as above.

[0040] To achieve the above object, a fourth aspect of the present disclosure proposes a storage medium, which is a computer-readable storage medium, and the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to cause a computer to execute:

[0041] The method described in the first aspect as above.

[0042] The wafer pre-alignment method, device, electronic device, and storage medium proposed by the embodiments of the present disclosure collect a wafer image through a area array camera, then perform notch detection processing on the wafer image to obtain notch position information, perform wafer position deviation calculation processing on the wafer image to obtain wafer position deviation information, and finally perform pre-alignment processing on the target wafer according to the notch position information and the wafer position deviation information. Through the technical solution provided by the embodiments of the present disclosure, the alignment accuracy of the pre-alignment process can be improved, and the efficiency of wafer testing can be improved. Description of the Drawings

[0043] Figure 1 Is a flowchart of the wafer pre-alignment method provided by the embodiments of the present disclosure.

[0044] Figure 2 Is Figure 1 The flowchart of step S120 in

[0045] Figure 3 Is Figure 2 The flowchart of step S210 in

[0046] Figure 4 is Figure 2 the flowchart of step S220 in

[0047] Figure 5 is Figure 4 the flowchart of step S410 in

[0048] Figure 6 is Figure 4 the flowchart of step S420 in

[0049] Figure 7 is Figure 1 the flowchart of step S130 in

[0050] Figure 8 is the module block diagram of the wafer pre - alignment device provided by the embodiments of the present disclosure.

[0051] Figure 9 is the schematic diagram of the hardware structure of the electronic device provided by the embodiments of the present disclosure.

[0052] Reference numerals: image acquisition module 810, notch detection module 820, wafer position deviation calculation module 830, pre - alignment module 840, processor 901, memory 902, input / output interface 903, communication interface 904, bus 905. Detailed implementation manners

[0053] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0054] It should be noted that although the functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order from the module division in the device or the order in the flowchart. Terms such as "first" and "second" in the description and claims and the above - mentioned drawings are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used herein are only for the purpose of describing the embodiments of the present invention and are not intended to limit the present invention.

[0056] Wafer pre - alignment is one of the important functions of wafer testing equipment. Before the wafer undergoes probe testing or optical inspection, it is necessary to perform pre - alignment to detect the center position and notch direction of the wafer, so as to adjust the position and angle of the wafer, so that the position and angle of the wafer placed on the test station meet the requirements.

[0057] Currently, the current pre-alignment method for wafers is to use a line array camera to obtain the entire image of the wafer to achieve pre-alignment. The installation conditions of this method are relatively harsh. It requires the camera line scan line to be collinear with the rotation center and has high requirements for the light source. Therefore, the design difficulty and cost are relatively high. The pixels of the image obtained by this method reflect the actual object size and are related to the position of the image to the rotation center. The closer to the rotation center, the smaller the actual object size reflected by a single pixel. The image is not a feature of the accurate wafer edge. Therefore, the image distortion is serious, resulting in poor calculation accuracy of the wafer position deviation and the notch position, and poor ID recognition accuracy, leading to low alignment accuracy in the pre-alignment process, and further resulting in low wafer test efficiency.

[0058] Based on this, the embodiments of the present disclosure provide a wafer pre-alignment method, device, electronic device, and storage medium. The wafer image is collected by a area array camera, and then the notch detection process is performed on the wafer image to obtain the notch position information. The wafer position deviation calculation process is performed on the wafer image to obtain the wafer position deviation information. Finally, the target wafer is pre-aligned according to the notch position information and the wafer position deviation information. Through the technical solution provided by the embodiments of the present disclosure, the requirements for the installation conditions of the device can be reduced, the requirements for the light source can be reduced, the design difficulty and design cost can be reduced, the quality of the image can be improved, the calculation accuracy of the wafer position deviation and the notch position can be improved, the ID recognition accuracy can be improved, and further the alignment accuracy in the pre-alignment process can be improved, and the wafer test efficiency can be improved.

[0059] The embodiments of the present disclosure provide a wafer pre-alignment method, device, electronic device, and storage medium, which will be specifically described through the following embodiments. First, the wafer pre-alignment method in the embodiments of the present disclosure will be described.

[0060] The wafer pre-alignment method provided by the embodiments of the present disclosure relates to the technical field of integrated circuit test equipment. The wafer pre-alignment method provided by the embodiments of the present disclosure can be applied to a terminal, or can be applied to a server, or can also be software running on a terminal or a server. In some embodiments, the terminal can be a smart phone, a tablet computer, a notebook computer, a desktop computer, or a smart watch, etc.; the server can be an independent server, or can be a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, Content Delivery Network (CDN), and big data and artificial intelligence platforms; the software can be an application implementing the wafer pre-alignment method, etc., but is not limited to the above forms.

[0061] This application can be used in numerous general-purpose or special-purpose computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, and so on. This application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. This application can also be practiced in a distributed computing environment where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media including storage devices.

[0062] Embodiments of the present disclosure propose a wafer pre-alignment method, including: acquiring at least two wafer images of a target wafer collected by a area array camera; performing notch detection processing on the wafer images to obtain notch position information; performing wafer position deviation calculation processing on the wafer images to obtain wafer position deviation information; and performing pre-alignment processing on the target wafer according to the notch position information and the wafer position deviation information.

[0063] Figure 1 is an optional flowchart of the wafer pre-alignment method provided by embodiments of the present disclosure, Figure 1 The method in may include but is not limited to steps S110 to S140, specifically including:

[0064] S110, acquiring at least two wafer images of a target wafer collected by a area array camera;

[0065] S120, performing notch detection processing on the wafer images to obtain notch position information;

[0066] S130, performing wafer position deviation calculation processing on the wafer images to obtain wafer position deviation information;

[0067] S140, performing pre-alignment processing on the target wafer according to the notch position information and the wafer position deviation information.

[0068] In step S110, the target wafer is the wafer to be detected. By setting an area array camera in the wafer testing device, wafer images are collected. The wafer images are images of the wafer edge, and the number of wafer images is at least two. The wafer images are used for the subsequent pre-alignment process.

[0069] It should be noted that the wafer pre-alignment method using the embodiments of the present disclosure is different from the pre-alignment method using a line array camera. The wafer image collected by the wafer pre-alignment method of the embodiments of the present disclosure can accurately reflect the wafer edge image, and the wafer image has no distortion.

[0070] It should be noted that when collecting images of the wafer, the shooting methods include, but are not limited to, two methods: keeping the camera stationary and rotating the wafer, and keeping the wafer stationary and rotating the camera.

[0071] It should be noted that the camera shooting frequency and the motor rotation angle are corresponding. After the motor rotates a fixed angle, the camera takes a picture to ensure that the shooting interval of each picture is consistent with the motor rotation angle. By setting the camera shooting frequency and the wafer rotation speed, it is ensured that the wafer rotates one circle to obtain a wafer image that meets the requirements.

[0072] In step S120, the notch position information is the coordinate position of the notch on the wafer. The notch is a positioning mark carried on the wafer at the time of factory for processing or detection. The purpose of notch detection and processing is to determine the position of the notch in the wafer.

[0073] It should be noted that before step S120, that is, before finding the notch contour through an algorithm, it is necessary to preprocess the collected wafer image. The preprocessing includes, but is not limited to, performing binary processing on the image to obtain a wafer edge image.

[0074] In step S130, the wafer position deviation information is the offset between the actual center and the theoretical center of the wafer. After obtaining this offset through wafer position deviation calculation and processing, it is used in the pre-positioning process.

[0075] In step S140, the notch position information and the wafer position deviation information realize the positioning of the actual position of the wafer. Combining with the offset obtained in step S130, the operating device in the integrated circuit testing equipment can align the target wafer to the theoretical position by moving, rotating, etc. according to the offset, thereby realizing the pre-alignment of the target wafer.

[0076] The wafer pre-alignment method proposed by the embodiments of the present disclosure collects wafer images through a area array camera, then performs notch detection and processing on the wafer images to obtain notch position information, performs wafer position deviation calculation and processing on the wafer images to obtain wafer position deviation information, and finally performs pre-alignment processing on the target wafer according to the notch position information and the wafer position deviation information. Through the technical solution provided by the embodiments of the present disclosure, the requirements for installation conditions of the equipment can be reduced, the requirements for the light source can be reduced, the design difficulty and design cost can be reduced, the quality of the image can be improved, the accuracy of wafer position deviation and notch position calculation can be improved, the accuracy of ID recognition can be improved, and thus the alignment accuracy of the pre-alignment process can be improved, and the efficiency of wafer testing can be improved.

[0077] In some embodiments, notch detection processing is performed on the wafer image to obtain notch position information, including: performing notch image recognition processing on the wafer image to obtain a target image; and performing notch position calculation processing on the target image to obtain notch position information.

[0078] Figure 2 is a flowchart of step S120 in some embodiments, Figure 2 The illustrated step S120 includes but is not limited to steps S210 to S220:

[0079] S210, performing notch image recognition processing on the wafer image to obtain a target image;

[0080] S220, performing notch position calculation processing on the target image to obtain notch position information.

[0081] In a specific embodiment, the notch detection processing in step S120 includes but is not limited to notch image recognition processing and notch position calculation processing.

[0082] In step S210, the notch image recognition processing is: identifying which one of multiple wafer images is the target image with a notch contour.

[0083] It should be noted that the number of target images is at least one. When there is only one target image and the notch contour is completely displayed, the center point coordinates of the notch contour are the notch position information; when there are two or more target images, at this time the notch contours are distributed on multiple target images, then calculate the positions of the notches in each picture respectively, and then take the average value to obtain the notch position information.

[0084] In step S220, the notch position calculation processing is to calculate the notch position after identifying the target image and use the calculation result as the notch position information.

[0085] In some embodiments, performing notch image recognition processing on the wafer image to obtain a target image includes: performing notch image recognition processing on the wafer image to obtain a wafer image containing a notch contour; and using the wafer image containing the notch contour as the target image.

[0086] Figure 3 is a flowchart of step S210 in some embodiments, Figure 3 The illustrated step S210 includes but is not limited to steps S310 to S320:

[0087] S310, performing notch image recognition processing on the wafer image to obtain a wafer image containing a notch contour;

[0088] S320, using the wafer image containing the notch contour as the target image.

[0089] In a specific embodiment, an image of a wafer image including a notch profile is used as a target image for subsequent pre-positioning processes.

[0090] In some embodiments, the notch position calculation process is performed on the target image to obtain notch position information, including: obtaining the first angle information of the target image; the first angle information is the shooting angle of the wafer image including the notch profile; obtaining the second angle information of the target image; the second angle information is the angle of the notch profile in the target image; and comprehensively analyzing and processing the first angle information and the second angle information to obtain the notch position information.

[0091] Figure 4 is a flowchart of step S220 in some embodiments. Figure 4 The schematic step S220 includes but is not limited to steps S410 to S430:

[0092] S410, obtaining the first angle information of the target image;

[0093] S420, obtaining the second angle information of the target image;

[0094] S430, comprehensively analyzing and processing the first angle information and the second angle information to obtain the notch position information.

[0095] In step S410, the first angle information is the shooting angle of the wafer image including the notch profile. In a specific embodiment, before shooting the wafer, it is necessary to set the position of the initial 0 angle as the starting position. Each wafer image captures a part of the wafer profile, and each wafer image corresponds to a certain angle value, which is the first angle information of the target image.

[0096] In step S420, the second angle information is the angle of the notch profile in the target image. In a specific embodiment, each wafer image captures a part of the wafer profile. If the wafer image is the target image, then in this target image, the relative position of the notch profile in the target image is the second angle information of the target image.

[0097] In step S430, the comprehensive analysis and processing specifically include: adding the first angle information and the second angle to obtain the notch position information. For example, if it is known in which photo the notch appears and the position of the notch in this photo, the specific position of the notch can be determined.

[0098] In some embodiments, obtaining the first angle information of the target image includes: obtaining the number information of the target image; and querying and processing in a preset number-angle comparison table according to the number information to obtain the first angle information corresponding to the target image.

[0099] Figure 5 is a flowchart of step S410 in some embodiments, Figure 5 The illustrated step S410 includes but is not limited to steps S510 to S520:

[0100] S510, obtain the number information of the target image;

[0101] S520, perform a query process in a preset number-angle comparison table according to the number information to obtain the first angle information corresponding to the target image.

[0102] In step S510, the number information is the number of the target image in the wafer image, such as image No. 1, image No. 2, etc.

[0103] In step S520, the number-angle comparison table stores the corresponding relationship between the number information and the angle corresponding to the target image. After learning the number information of the target image, a query is performed in the table to obtain the first angle information, and the first angle information is used for the calculation of the notch position.

[0104] In some embodiments, obtaining the second angle information of the target image includes: obtaining the vector change rate of each contour point in the target image; analyzing the vector change rate to obtain the second angle information of the target image.

[0105] Figure 6 is a flowchart of step S420 in some embodiments, Figure 6 The illustrated step S420 includes but is not limited to steps S610 to S620:

[0106] S610, obtain the vector change rate of each contour point in the target image;

[0107] S620, analyze the vector change rate to obtain the second angle information of the target image.

[0108] It should be noted that, Figure 6 a specific embodiment of one method for obtaining the second angle information shown does not constitute a limitation on the position calculation process.

[0109] In step S610, after obtaining the target image, the coordinates of each point on the contour line of the wafer edge are obtained, that is, the coordinates of the contour points are obtained, and then the vector change rate of each contour point is calculated for subsequent analysis.

[0110] In step S620, if the values of the vector change rate are relatively uniform, it indicates that the contour line is relatively smooth, and thus the notch is not at the corresponding position; if the values of the vector change rate undergo a mutation, the position where the vector change rate mutates is the position where the notch exists. Therefore, the angle of the midpoint of the angular region where the mutation occurs is used as the second angular information of the target image.

[0111] In some embodiments, wafer position deviation calculation processing is performed on the wafer images to obtain wafer position deviation information, including: performing center calculation processing on each wafer image to obtain the center coordinates of each wafer image; performing fitting processing on the center coordinates to obtain the rotation center coordinates; and obtaining the wafer position deviation information based on the rotation center coordinates and the center coordinates.

[0112] Figure 7 It is a flowchart of step S130 in some embodiments. Figure 7 The schematic step S130 includes but is not limited to steps S710 to S730:

[0113] S710, perform center calculation processing on each wafer image to obtain the center coordinates of each wafer image.

[0114] S720, perform fitting processing on the center coordinates to obtain the rotation center coordinates;

[0115] S730, obtain the wafer position deviation information based on the rotation center coordinates and the center coordinates.

[0116] In step S710, each wafer image has a wafer contour line in the shape of an arc, and the center coordinates of the arc can be calculated based on the arc, which are the center coordinates of each wafer image; specifically, using two points on the arc and the known wafer radius, the center coordinates of each wafer image can be calculated relatively accurately.

[0117] In step S720, after obtaining the center coordinates of each wafer image, fitting processing is performed on multiple center coordinates. Among them, the fitting processing includes but is not limited to obtaining the average value of each center coordinate to obtain the rotation center coordinates, and the obtained rotation center coordinates are the theoretical coordinates of the rotation center during image capture.

[0118] It should be noted that the center calculation method using a line array camera requires the rotation center and the line scan line to be collinear in order to obtain the rotation center from the image. Therefore, it has relatively high requirements for installation and debugging, which will bring additional costs. At the same time, due to image distortion and installation accuracy, the error of the center calculation method using a line array camera is relatively large. However, the wafer pre-alignment method provided by the embodiments of the present disclosure can achieve accurate center calculation, thereby improving the accuracy of pre-alignment.

[0119] In step S730, the center coordinates include, but are not limited to, the center coordinates of any wafer image. The wafer position deviation information is the offset between the rotation center of the wafer and the center of the selected wafer image, which characterizes the deviation between the center coordinates of a single wafer image before fitting and the theoretical coordinates after fitting. The wafer position deviation information enables the operating device in the integrated circuit test equipment to align the target wafer to the theoretical position through means such as movement and rotation, thereby achieving pre-alignment of the target wafer.

[0120] It should be noted that in a specific embodiment, any wafer image can be a wafer image with a notch contour, or any other wafer image with a special position (such as a wafer image that is 90 degrees different from the wafer image with a notch contour); the center coordinates of this wafer image are selected and used for calculating the wafer position deviation. The ultimate goal is to align the wafer to a specific position. Therefore, any wafer image will preferably be a wafer image that is convenient for wafer alignment.

[0121] An embodiment of the present disclosure provides a wafer pre-alignment device, including: an image acquisition module for acquiring at least two wafer images of a target wafer collected by a area array camera; a notch detection module for performing notch detection processing on the wafer images to obtain notch position information; a wafer position deviation calculation module for performing wafer position deviation calculation processing on the wafer images to obtain wafer position deviation information; and a pre-alignment module for performing pre-alignment processing on the target wafer according to the notch position information and the wafer position deviation information.

[0122] Please refer to Figure 8 , Figure 8 FIG. schematically shows a wafer pre-alignment device according to an embodiment. The wafer pre-alignment device includes: an image acquisition module 810, a notch detection module 820, a wafer position deviation calculation module 830, and a pre-alignment module 840. The image acquisition module 810 is connected to the notch detection module 820, the notch detection module 820 is connected to the wafer position deviation calculation module 830, and the wafer position deviation calculation module 830 is connected to the pre-alignment module 840.

[0123] Among them, the image acquisition module 810 is used to acquire at least two wafer images of a target wafer collected by a area array camera; the notch detection module 820 is used to perform notch detection processing on the wafer images to obtain notch position information; the wafer position deviation calculation module 830 is used to perform wafer position deviation calculation processing on the wafer images to obtain wafer position deviation information; and the pre-alignment module 840 is used to perform pre-alignment processing on the target wafer according to the notch position information and the wafer position deviation information.

[0124] The specific implementation of the wafer pre-alignment device in this embodiment is basically the same as that of the above-mentioned wafer pre-alignment method, belonging to the same inventive concept, and will not be elaborated here.

[0125] This disclosure embodiment also provides an electronic device, including:

[0126] At least one memory;

[0127] At least one processor;

[0128] At least one program;

[0129] The program is stored in the memory, and the processor executes the at least one program to implement the wafer pre-alignment method described above in this disclosure. This electronic device can be any intelligent terminal including a mobile phone, a tablet computer, a personal digital assistant (PDA for short), an in-vehicle computer, etc.

[0130] Please refer to Figure 9 , Figure 9 which schematically shows the hardware structure of an electronic device in another embodiment. The electronic device includes:

[0131] A processor 901, which can be implemented in ways such as a general-purpose CPU (Central Processing Unit, central processor), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided by this disclosure embodiment;

[0132] A memory 902, which can be implemented in forms such as a ROM (Read Only Memory, read-only memory), a static storage device, a dynamic storage device, or a RAM (Random Access Memory, random access memory). The memory 902 can store an operating system and other application programs. When implementing the technical solutions provided by this specification embodiment through software or firmware, the relevant program codes are stored in the memory 902, and the processor 901 is called to execute the wafer pre-alignment method of this disclosure embodiment;

[0133] An input / output interface 903, which is used to implement information input and output;

[0134] A communication interface 904, which is used to implement communication interaction between this device and other devices, and can implement communication through a wired method (such as USB, network cable, etc.) or through a wireless method (such as a mobile network, WIFI, Bluetooth, etc.); and

[0135] A bus 905 transmits information between various components of the device (such as a processor 901, a memory 902, an input / output interface 903, and a communication interface 904).

[0136] Among them, the processor 901, the memory 902, the input / output interface 903, and the communication interface 904 achieve communication connections with each other inside the device through the bus 905.

[0137] An embodiment of the present disclosure also provides a storage medium, which is a computer-readable storage medium. The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to cause a computer to execute the above-mentioned wafer pre-alignment method.

[0138] The wafer pre-alignment method and device, electronic device, and storage medium proposed in the embodiments of the present disclosure collect a wafer image through a planar array camera, then perform notch detection processing on the wafer image to obtain notch position information, perform wafer position deviation calculation processing on the wafer image to obtain wafer position deviation information, and finally perform pre-alignment processing on the target wafer according to the notch position information and the wafer position deviation information. Through the technical solution provided by the embodiments of the present disclosure, the requirements for installation conditions of the device can be reduced, the requirements for the light source can be reduced, the design difficulty and design cost can be reduced, the quality of the image can be improved, the accuracy of the wafer position deviation and the notch position calculation can be improved, the accuracy of ID recognition can be improved, and thus the alignment accuracy of the pre-alignment process can be improved, and the efficiency of wafer testing can be improved.

[0139] As a non-transitory computer-readable storage medium, the memory can be used to store non-transitory software programs and non-transitory computer-executable programs. In addition, the memory can include a high-speed random access memory, and can also include non-transitory memory, such as at least one disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories can be connected to the processor through a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0140] The embodiments described in the embodiments of the present disclosure are for more clearly illustrating the technical solutions of the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions provided by the embodiments of the present disclosure. Those skilled in the art know that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of the present disclosure are equally applicable to similar technical problems.

[0141] Those skilled in the art can understand that Figure 1-7 the technical solutions shown do not constitute a limitation on the embodiments of the present disclosure, and may include more or fewer steps than those shown, or combine some steps, or different steps.

[0142] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0143] Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, and their appropriate combinations.

[0144] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of this application and the above-mentioned drawings are used to distinguish similar objects and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of this application described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that comprises a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0145] It should be understood that in this application, "at least one (item)" means one or more, and "a plurality" means two or more. "And / or" is used to describe the association relationship of associated objects and indicates that three relationships can exist. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist at the same time. Among them, A and B can be singular or plural. The character " / " generally means that the associated objects before and after are in an "or" relationship. "At least one (one) of the following" or its similar expression refers to any combination of these items, including any combination of single item (one) or plural items (ones). For example, at least one (one) of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0146] In several embodiments provided by the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, mechanical or other forms.

[0147] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place, or can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0148] In addition, in each embodiment of the present application, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0149] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment of the present application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store programs.

[0150] The preferred embodiments of the present disclosure have been described above with reference to the accompanying drawings, and thus do not limit the scope of rights of the present disclosure. Any modifications, equivalent replacements, and improvements made by those skilled in the art without departing from the scope and essence of the present disclosure shall be within the scope of rights of the present disclosure.

Claims

1. A wafer pre-alignment method, characterized in that, Including: Obtaining at least two wafer images of a target wafer collected by an area array camera; Performing notch detection processing on the wafer images to obtain notch position information; Performing wafer position deviation calculation processing on the wafer images to obtain wafer position deviation information; Performing pre-alignment processing on the target wafer according to the notch position information and the wafer position deviation information; The performing notch detection processing on the wafer images to obtain notch position information includes: performing notch image recognition processing on the wafer images to obtain target images; performing notch position calculation processing on the target images to obtain the notch position information; wherein, the number of the target images is at least one. When there is only one target image, the center point coordinates of the notch contour are the notch position information. When there are two or more target images, the positions of the notches in each target image are calculated respectively, and then the average value is obtained to obtain the notch position information; The performing notch image recognition processing on the wafer images to obtain target images includes: performing notch image recognition processing on the wafer images to obtain the wafer images including the notch contour; using the wafer images including the notch contour as the target images; The performing notch position calculation processing on the target images to obtain the notch position information includes: obtaining first angle information of the target images; the first angle information is the shooting angle of the wafer image including the notch contour, and each wafer image corresponds to one shooting angle; obtaining second angle information of the target images; the second angle information is the angle of the notch contour in the target image; performing comprehensive analysis processing on the first angle information and the second angle information to obtain the notch position information; The obtaining first angle information of the target images includes: obtaining the number information of the target images; performing query processing in a preset number-angle comparison table according to the number information to obtain the first angle information corresponding to the target images; The performing comprehensive analysis processing on the first angle information and the second angle information to obtain the notch position information includes: obtaining the notch position information by adding the first angle information and the second angle; The performing wafer position deviation calculation processing on the wafer images to obtain wafer position deviation information includes: performing center calculation processing on each wafer image to obtain the center coordinates of each wafer image; performing fitting processing on the center coordinates to obtain the rotation center coordinates; obtaining the wafer position deviation information according to the rotation center coordinates and the center coordinates; The performing center calculation processing on each wafer image to obtain the center coordinates of each wafer image includes: for each wafer image, using two points on the arc of the wafer image and the known wafer radius to calculate the center coordinates of each wafer image; Performing fitting processing on the center coordinates to obtain the rotation center coordinates includes: obtaining the average value of each of the center coordinates to obtain the rotation center coordinates.

2. The method according to claim 1, characterized in that, Obtaining the second angle information of the target image includes: Obtaining the vector change rate of each contour point in the target image; Analyzing the vector change rate to obtain the second angle information of the target image.

3. A wafer pre-alignment device, characterized in that, Including: An image acquisition module for obtaining at least two wafer images of a target wafer collected by an area array camera; A notch detection module for performing notch detection processing on the wafer images to obtain notch position information; performing notch detection processing on the wafer images to obtain notch position information includes: performing notch image recognition processing on the wafer images to obtain a target image; performing notch position calculation processing on the target image to obtain the notch position information; where the number of the target images is at least one, when there is only one target image, the center point coordinates of the notch contour are the notch position information, when there are two or more target images, the positions of the notches in each target image are calculated respectively, and then the average value is obtained to obtain the notch position information; Performing notch image recognition processing on the wafer images to obtain a target image includes: performing notch image recognition processing on the wafer images to obtain the wafer image including the notch contour; using the wafer image including the notch contour as the target image; Performing notch position calculation processing on the target image to obtain the notch position information includes: obtaining the first angle information of the target image; the first angle information is the shooting angle of the wafer image including the notch contour, and each wafer image corresponds to one shooting angle; obtaining the second angle information of the target image; the second angle information is the angle of the notch contour in the target image; comprehensively analyzing and processing the first angle information and the second angle information to obtain the notch position information; Obtaining the first angle information of the target image includes: obtaining the number information of the target image; performing query processing in a preset number-angle comparison table according to the number information to obtain the first angle information corresponding to the target image; Comprehensively analyzing and processing the first angle information and the second angle information to obtain the notch position information includes: adding the first angle information and the second angle to obtain the notch position information; A wafer position deviation calculation module for performing wafer position deviation calculation processing on the wafer images to obtain wafer position deviation information; performing wafer position deviation calculation processing on the wafer images to obtain wafer position deviation information includes: performing center calculation processing on each wafer image to obtain the center coordinates of each wafer image; performing fitting processing on the center coordinates to obtain the rotation center coordinates; obtaining the wafer position deviation information according to the rotation center coordinates and the center coordinates; Calculating the center coordinates of each of the wafer images, including: for each of the wafer images, using two points on the arc of the wafer image and the known wafer radius to calculate the center coordinates of each of the wafer images; Performing a fitting process on the center coordinates to obtain the rotation center coordinates, including: obtaining the average value of each of the center coordinates to obtain the rotation center coordinates; A pre-alignment module for pre-aligning the target wafer according to the notch position information and the wafer position deviation information.

4. An electronic device, characterized in that, Including: At least one memory; At least one processor; At least one program; The program is stored in the memory, and the processor executes the at least one program to implement: The method according to claim 1 or 2.

5. A storage medium, the storage medium being a computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions for causing a computer to execute: The method according to claim 1 or 2.

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