A memory system and a controller

Abstract

The present application discloses a memory system. The memory system includes: a non-volatile memory device; a processor configured to generate a first mapped chunk, the first mapped chunk including mapping information for accessing the non-volatile memory device; a first error correction code (ECC) component configured to generate a first mapped codeword by adding first parity bits to the first mapped chunk; a volatile memory configured to store the first mapped codeword; a second ECC component configured to generate first mapped data by performing decoding on the first mapped codeword output from the volatile memory and, when the memory system is powered off, bypass the first ECC component; and a direct memory access (DMA) component configured to provide the first mapped data to the non-volatile memory device.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2020 - 0133494, filed on October 15, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments relate to a memory system including a non - volatile memory device and a controller controlling the non - volatile memory device. Background Art

[0004] The paradigm of the computer environment has shifted to ubiquitous computing that enables the use of a computing system anytime and anywhere. Accordingly, the use of portable electronic devices such as mobile phones, digital cameras, and laptop computers has increased rapidly. These portable electronic devices generally use a memory system having one or more memory devices for storing data. The memory system may be used as a main memory device or an auxiliary memory device of the portable electronic device.

[0005] Since a memory system using a non - volatile memory device does not have mechanical driving parts, a memory system using a non - volatile memory device provides advantages such as excellent stability and durability, high information access speed, and low power consumption. Examples of memory systems having these advantages include a Universal Serial Bus (USB) memory device, a memory card having various interfaces, and a Solid State Drive (SSD). Summary of the Invention

[0006] Various embodiments are directed to a controller and a memory system capable of shortening the time to flush data protected by ECC encoding among data stored in a volatile memory to a non - volatile memory device.

[0007] Various embodiments relate to a controller and a memory system capable of shortening a power - off time by quickly flushing a large amount of mapping data stored in a volatile memory to a memory device when the memory system is powered off.

[0008] The technical problems to be solved by the present embodiments are not limited to the above - mentioned technical problems, and other technical problems may also be inferred from the following embodiments.

[0009] According to an embodiment, a memory system includes: a non-volatile memory device; a processor configured to generate a first mapped chunk including mapping information for accessing the non-volatile memory device; a first error correction code (ECC) component configured to generate a first mapped codeword by adding a first parity bit to the first mapped chunk; a volatile memory configured to store the first mapped codeword; a second ECC component configured to generate first mapped data by decoding the first mapped codeword output from the volatile memory and, when the memory system is powered off, bypass the first ECC component; and a direct memory access (DMA) component configured to provide the first mapped data to the non-volatile memory device.

[0010] The first ECC component may have a lower latency than the second ECC component, and the second ECC component may have a higher throughput than the first ECC component.

[0011] The memory system may further include: a third ECC component configured to generate first mapped data by decoding the first mapped codeword in parallel with the second ECC component when the memory system is powered off.

[0012] In a first mode, the first mapped data may be the first mapped chunk from which the first parity bit has been removed from the decoded first mapped codeword, and in a second mode, the first mapped data may be the first mapped codeword in which the first parity bit of the decoded first mapped codeword is retained.

[0013] In the first mode, when the memory system is powered on, the DMA component may further provide the first mapped chunk obtained from the non-volatile memory device to the first ECC component, and in the second mode, when the memory system is powered on, the DMA component may further provide the first mapped codeword obtained from the non-volatile memory device to the volatile memory by bypassing the first ECC component.

[0014] The volatile memory may further store a second mapped codeword including a second mapped chunk generated by the processor and a second parity bit added by the first ECC component. When the memory system is powered off, the first ECC component may generate the second mapped chunk by decoding the second mapped codeword and removing the second parity bit therefrom, and the DMA component may further provide the second mapped chunk to the non-volatile memory device.

[0015] The first mapped codeword may be a mapped codeword adjusted to have a size that is a power of 2, and the second mapped codeword may be an unadjusted codeword that does not have a size that is a power of 2.

[0016] The adjusted codeword may include a logical-to-virtual (L2V) mapping codeword, and the unadjusted codeword may include a valid page table (VPT) codeword.

[0017] In the first mode, the first mapped data may be a first mapped chunk from which the first parity bit has been removed from the decoded first mapped codeword, and in the second mode, the first mapped data may be the first mapped codeword in which the first parity bit of the decoded first mapped codeword is retained.

[0018] In the first mode, when the memory system is powered on, the DMA component may further provide a first mapped chunk obtained from the non-volatile memory device to the first ECC component, and in the second mode, when the memory system is powered on, the DMA component may further provide the first mapped codeword obtained from the non-volatile memory device to the volatile memory by bypassing the first ECC component.

[0019] When the memory system is powered on, the DMA component may further provide second mapped data obtained from the non-volatile memory device to the first ECC component, and the first ECC component may generate a second mapped codeword by adding a parity bit to the second mapped chunk, and further provide the second mapped codeword to the volatile memory.

[0020] The memory system may further include: a fourth ECC component configured to perform encoding to store the first mapped data and the second mapped chunk in the non-volatile memory device, and perform error correction decoding on data obtained from the non-volatile memory device.

[0021] According to an embodiment, a controller for controlling a non-volatile memory device includes: a processor configured to generate a first mapped chunk including mapping information for accessing the non-volatile memory device; a first error correction code (ECC) component configured to generate a first mapped codeword by adding a first parity bit to the first mapped chunk generated by the processor; a volatile memory configured to store the first mapped codeword; a second ECC component configured to generate first mapped data by performing error correction decoding on the first mapped codeword output from the volatile memory, and bypass the first ECC component when the memory system is powered off; and a direct memory access (DMA) component configured to provide the first mapped data to the non-volatile memory device.

[0022] According to an embodiment, a memory system includes: a non-volatile memory device; and a controller coupled to the non-volatile memory device and including: a volatile memory; a processor configured to generate a mapping chunk including mapping information for accessing the non-volatile memory device; a first error correction code (ECC) component configured to encode the mapping chunk to generate a mapping codeword and provide the mapping codeword to the volatile memory such that the mapping codeword is stored in the volatile memory, the mapping codeword including the mapping chunk and parity bits; and a memory interface coupled between the volatile memory and the non-volatile memory device and between the first ECC component and the non-volatile memory device, wherein the memory interface includes: a second ECC component configured to receive the mapping codeword from the volatile memory when the memory system is powered off and decode the received mapping codeword to generate mapping data, the second ECC component having a higher throughput than the first ECC component; and a direct memory access (DMA) component configured to receive the mapping data and provide the mapping data to the non-volatile memory device.

[0023] According to the present disclosure, a controller and a memory system can be provided that are capable of shortening the time for clearing data protected by ECC coding among the data stored in the volatile memory to the non-volatile memory device.

[0024] According to the present disclosure, a controller and a memory system can be provided that are capable of shortening the power-off time by quickly clearing a large amount of mapping data stored in the volatile memory to the memory device when the memory system is powered off.

[0025] The effects achievable in the present disclosure are not limited to the above effects, and those skilled in the art will clearly understand other unmentioned effects from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a diagram schematically showing a data processing system including a memory system according to an embodiment of the present disclosure.

[0027] Figure 2 is a diagram showing a memory system according to an embodiment of the present disclosure.

[0028] Figure 3 is a diagram showing a power-off operation of a memory system according to an embodiment of the present disclosure.

[0029] Figure 4 is a diagram showing a start-up operation of a memory system according to a first mode.

[0030] Figure 5 is a diagram showing a start-up operation of a memory system according to a second mode.

[0031] Figures 6A to 6C is a diagram showing the type of mapped data.

[0032] Figure 7 is a diagram showing a mapped ECC component according to an embodiment of the present disclosure.

[0033] Figure 8A and Figure 8B is a diagram showing the chunk splitting operation of a mapped chunk splitter.

[0034] Figure 9 is a diagram showing the power-off operation of a memory system according to an embodiment of the present disclosure.

[0035] Figure 10 is a diagram showing the startup operation of a memory system according to a first mode.

[0036] Figure 11 is a diagram showing the startup operation of a memory system according to a second mode. Detailed Description

[0037] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below, but may be configured in various different forms. The various embodiments of the present disclosure are provided as examples to strengthen the present disclosure and help those skilled in the art better understand the scope of the present disclosure.

[0038] Figure 1 is a block diagram showing a data processing system 100 according to an embodiment of the present invention.

[0039] Referring to Figure 1 , the data processing system 100 may include a host 102 operatively coupled to a memory system 110. The host 102 may include any one of various portable electronic devices such as a mobile phone, an MP3 player, and a laptop computer, or any one of various non-portable electronic devices such as a desktop computer, a game console, a television (TV), and a projector.

[0040] The host 102 may include at least one operating system (OS), which may manage and control the overall functions and operations of the host 102, and provide operations between the host 102 and a user using the data processing system 100 or the memory system 110. The OS may support functions and operations corresponding to the usage purpose and use of the user. For example, according to the mobility of the host 102, the OS may be divided into a general OS and a mobile OS. According to the user's environment, the general OS may be divided into a personal OS and an enterprise OS.

[0041] The memory system 110 is operable to store data for the host 102 in response to requests from the host 102. Non-limiting examples of the memory system 110 may include a solid state drive (SSD), a multimedia card (MMC), a secure digital (SD) card, a universal serial bus (USB) device, a universal flash storage (UFS) device, a compact flash (CF) card, a smart media card (SMC), a personal computer memory card international association (PCMCIA) card, and a memory stick. The MMC may include an embedded MMC (eMMC), a reduced size MMC (RS-MMC), and a micro MMC, etc. The SD card may include a mini SD card and a micro SD card.

[0042] The memory system 110 may be implemented by various types of storage devices. Examples of such storage devices may include, but are not limited to, volatile memory devices such as dynamic random access memory (DRAM) and static RAM (SRAM), and non-volatile memory devices such as read only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric RAM (FRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM or ReRAM), and flash memory. The flash memory may have a three-dimensional (3D) stacked structure.

[0043] The memory system 110 may include a controller 130 and a non-volatile memory device (NVM) 150. The NVM 150 may store data for the host 102. The controller 130 may control the storage of data into the NVM 150.

[0044] The controller 130 and the NVM 150 may be integrated into a single semiconductor device. For example, the controller 130 and the NVM 150 may be integrated as one semiconductor device to form a solid state drive (SSD). When the memory system 110 is used as an SSD, the operating speed of the host 102 connected to the memory system 110 may be increased. Additionally, the controller 130 and the NVM 150 may be integrated as one semiconductor device to form a memory card. For example, the controller 130 and the NVM 150 may form a memory card such as a personal computer memory card international association (PCMCIA) card, a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC) including a reduced size MMC (RS-MMC) and a micro MMC, a secure digital (SD) card including a mini SD card, a micro SD card, and an SDHC card, or a universal flash storage (UFS) device.

[0045] Non-limiting application examples of the memory system 110 may include a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a network tablet, a tablet computer, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation system, a black box, a digital camera, a digital multimedia broadcast (DMB) player, a 3D TV, a smart TV, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device constituting a data center, a device capable of transmitting / receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, a radio frequency identification (RFID) device, or one of various components constituting a computing system.

[0046] Even without power being supplied, the NVM 150 may retain data stored therein. The NVM 150 may store data provided from the host 102 through a programming operation and provide the data stored therein to the host 102 through a read operation. The NVM 150 may include a plurality of memory blocks, each memory block may include a plurality of pages, and each page may include a plurality of memory cells coupled to a word line.

[0047] In an embodiment, the NVM 150 may include a flash memory device. The flash memory device may have a three-dimensional (3D) stacked structure. The flash memory device may store data in a memory cell array including memory cell transistors. The flash memory device may have a hierarchical structure of a memory die, a plane, a memory block, and a page. One memory die may receive one command at a time. The flash memory device may include a plurality of memory dies. One memory die may include a plurality of planes, and the plurality of planes may process commands received by the memory die in parallel. Each of the planes may include a plurality of memory blocks. Each memory block may correspond to a minimum unit of an erase operation. One memory block may include a plurality of pages. A page may correspond to a minimum unit of a programming operation.

[0048] The controller 130 may control the NVM 150 in response to a request from the host 102. For example, the controller 130 may provide data read from the NVM 150 to the host 102 and store data provided from the host 102 in the NVM 150. For this operation, the controller 130 may control read operations, programming operations, and erase operations of the NVM 150.

[0049] The controller 130 may include a host interface (I / F) 132, a processor 134, a memory I / F 142, a volatile memory (VM) 144, and a VM error correction code ECC component 146, all of which are operably coupled via an internal bus.

[0050] The host I / F 132 may be configured to process commands and data from the host 102 and communicate with the host 102 through one or more of various interface protocols such as: Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed Peripheral Component Interconnect (PCI-e or PCIe), Small Computer System Interface (SCSI), Serial SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0051] The host I / F 132 may be driven by firmware called the host interface layer (HIL) to exchange data with the host 102.

[0052] The memory I / F 142 may serve as a memory / storage device interface to interface the controller 130 and the NVM 150, such that the controller 130 controls the NVM 150 in response to requests from the host 102. When the NVM 150 is a flash memory, such as a NAND flash memory, the memory I / F 142 may generate control signals for the NVM 150 and process data to be provided to the NVM 150 under the control of the processor 134. The memory I / F 142 may operate as an interface (e.g., a NAND flash interface) for processing commands and data between the controller 130 and the NVM 150. Specifically, the memory I / F 142 may support data transfer between the controller 130 and the NVM 150.

[0053] The memory I / F 142 may be driven by firmware called the flash interface layer (FIL) to exchange data with the NVM 150.

[0054] The memory I / F 142 may include an NVM ECC (not shown) component to detect and correct errors included in data read from the NVM 150. The NVM ECC component may include an NVM ECC encoder and an NVM ECC decoder. The NVM ECC encoder may perform error correction encoding on data to be programmed into the NVM 150 and generate data with parity bits added. The data with parity bits added may be stored in the NVM 150. The NVM ECC decoder may detect and correct errors included in data output from the NVM 150. The NVM ECC component may perform error correction by using an encoding modulation such as a low density parity check (LDPC) code. The NVM ECC component is not limited to a specific structure. The NVM ECC component may include all circuits, modules, systems, and devices for error correction.

[0055] The processor 134 may control the overall operation of the memory system 110. The processor 134 may be implemented as a microprocessor or a central processing unit (CPU).

[0056] The processor 134 may drive the FTL and perform foreground operations corresponding to requests received from the host 102. For example, the processor 134 may control the write operation of the NVM 150 in response to a write request from the host 102 and control the read operation of the NVM 150 in response to a read request from the host 102. For example, the processor 134 may perform mapping between the logical address used in the file system of the host 102 and the physical address used in the NVM 150.

[0057] The controller 130 may perform background operations on the NVM 150 through the processor 134. For example, the background operations may include a garbage collection (GC) operation, a wear leveling (WL) operation, a mapping erase operation, or a bad block management operation.

[0058] The processor 134 may run firmware (FW) called a flash translation layer (FTL) to perform foreground operations and background operations.

[0059] The VM 144 may store mapping data including address mapping information between a logical address and a physical address. The mapping data may be stored in the NVM 150 and may be loaded into the VM 144 when the memory system 110 is powered on. Due to various factors, errors may occur in the mapping data loaded into the VM 144. In order for the memory system 110 to accurately access data requested by the host 102, error correction of the mapping data stored in the VM 144 is required.

[0060] The VM ECC component 146 can detect and correct errors in the mapped data stored in the VM 144. For example, the VM ECC component 146 can perform error correction encoding on the mapped chunks generated by the processor 134 and generate a mapped codeword with parity bits added. The smallest unit of the mapped data can be referred to as a map piece. For example, a map piece can include a logical-to-physical (L2P) segment indicating the mapping relationship between a logical address and a physical address. A mapped chunk can include a predetermined number of map pieces. A mapped chunk refers to the unit of the mapped data on which the VM ECC component 146 performs an error correction operation at one time. The mapped codeword can be stored in the VM 144. When there is a request for a mapped chunk from the processor 134, the VM ECC component 146 can detect and correct the error corresponding to the mapped chunk in the mapped codeword, remove the parity bits from the error-corrected mapped codeword to generate the mapped chunk, and provide the mapped chunk to the processor 134.

[0061] In an embodiment, the VM ECC component 146 can perform error correction by using an encoding modulation such as Bose-Chaudhuri-Hocquenghem (BCH) code. The VM ECC component 146 is not limited to a specific structure. The VM ECC component 146 can include all circuits, modules, systems, and devices for error correction.

[0062] Hereinafter, the parity bits added by the VM ECC component 146 are referred to as VM parity bits, and the parity bits added by the NVMECC component are referred to as NVM parity bits.

[0063] To quickly process commands from the host 102, the processor 134 needs to quickly convert the logical address in the command into a physical address. To quickly convert the logical address into a physical address, the processor 134 needs to quickly obtain from the VM 144 a mapped chunk including the logical address. To quickly provide an error-free mapped chunk to the processor 134, the VM ECC component 146 can be designed to have a short latency. For example, the VM ECC component 146 can have complex functions in addition to the error correction function, such as a cache for caching the mapped chunks referenced by the processor 134 to accelerate the processing of the mapped chunks. The VM ECC component 146 with complex functions can be implemented by a plurality of logic gates, for example, about two million logic gates, and can occupy a relatively wide area in the circuit of the memory system 110.

[0064] Generally, when designing the VM ECC component 146, throughput can be considered less than latency. This is because, in many cases, the processor 134 requests a small number of mapped chunks required to process requests from the host 102, rather than requesting multiple mapped chunks at one time.

[0065] When the memory system 110 is powered off, the processor 134 may control the memory I / F 142 to store the mapped chunk in the NVM 150, and the mapped chunk includes a plurality of mapped codewords stored in the VM 144. To ensure the reliability of the memory system 110, it is necessary to detect and correct errors in the mapped codewords including the mapped chunk before storing the mapped chunk in the NVM 150.

[0066] Since less consideration is given to throughput when designing the VM ECC component 146, the VM ECC component 146 may have a lower throughput than the memory I / F 142. When the memory system 110 is powered off, if the VM ECC component 146 needs to detect and correct errors in a plurality of mapped codewords of the VM 144 to generate an error-corrected mapped chunk, and then the memory I / F 142 needs to store the mapped chunk in the NVM 150, a bottleneck may occur in the VM ECC component 146. When a bottleneck occurs in the VM ECC component 146, the power-off time of the memory system 110 may be delayed. When the power-off time of the memory system 110 is delayed, it is difficult to meet the requirements for the power-off time of the memory system 110, and it is difficult to ensure the reliability of the memory system 110 in the case of a sudden power-off.

[0067] On the other hand, considering both the latency and throughput of the VM ECC component 146 to substantially prevent a bottleneck, the method of designing the VM ECC component 146 may increase the area occupied by the VM ECC component 146 in the circuit of the memory system 110 and increase the power consumed by the VM ECC component 146. For example, when the number of VM ECC components 146 is increased and the VM ECC components 146 are arranged in parallel to improve throughput, the circuit area may expand due to the increase in the number of VM ECC components 146, and the power consumption may increase.

[0068] According to an embodiment of the present disclosure, the memory I / F 142 may include a mapped ECC component 214 for performing error-correction decoding on the mapped codewords with high throughput when the memory system 110 is powered off. The mapped ECC component 214 may be designed considering throughput rather than latency. A plurality of mapped ECC components 214 may be included to improve throughput, but additional functions such as a cache function may be excluded. For example, the mapped ECC component 214 from which additional functions have been excluded may be implemented using approximately 50,000 logic gates. For example, when four mapped ECC components 214 are included in the memory I / F 142, the mapped ECC component 214 may be implemented using approximately 200,000 logic gates.

[0069] When memory system 110 is powered off, multiple mapping codewords stored in VM 144 can bypass VM ECC component 146. Memory I / F 142 can detect and correct errors in mapping codewords by using mapping ECC 214 component and provide error-corrected mapping codewords or mapping chunks to NVM 150.

[0070] According to embodiments of the present disclosure, a bottleneck caused by low throughput of the VM ECC component 146 may be substantially prevented, and the power-off time of the memory system 110 may be shortened.

[0071] Figure 2 is a diagram illustrating a memory system 110 according to an embodiment of the present disclosure.

[0072] Figure 2 Shown only for reference Figure 1 Among the components of memory system 110 depicted are processor 134 , memory I / F 142 , VM 144 , VM ECC component 146 , and NVM 150 . Figure 2 Components of the memory system 110 other than those used to explain the embodiments of the present disclosure are not shown.

[0073] The memory I / F 142 may include a write path (WRP) 210 , a channel direct memory access (CH-DMA) component 230 , and a read path (RDP) 250 .

[0074] The CH-DMA component 230 may perform data input / output operations between the VM 144 and the NVM 150. When the processor 134 provides a request to the memory I / F 142 to perform data input / output, the CH-DMA component 230 may perform the data input / output operation in response to the request without intervention of the processor 134.

[0075] Data output from VM 144 may pass through WRP 210 before being programmed into NVM 150 through CH-DMA component 230. In some embodiments, WRP 210 may include a read DMA (RDMA) component 212, a mapping ECC component 214, and a data path 216.

[0076] RDMA component 212 may obtain data from VM 144 to be programmed into NVM 150 without intervention by processor 134 .

[0077] When the memory system 110 is powered off, the mapping ECC component 214 may perform error correction decoding on the plurality of mapping codewords stored in the VM 144 .

[0078] The mapping ECC component 214 can perform error correction decoding by using substantially the same encoding modulation as the VM ECC component 146. For example, when the VM ECC component 146 performs error correction encoding and decoding by using a BCH code, the mapping ECC component 214 can also perform error correction decoding by using a BCH code.

[0079] Data to be programmed from the VM 144 to the NVM 150 can pass through the data path 216. The data path 216 can include an NVM ECC encoder (not shown). The data to be programmed can be encoded by the NVM ECC encoder, and NVM parity bits can be added thereto.

[0080] Data output from the NVM 150 can be stored in the VM 144 via the CH-DMA component 230 and the RDP 250. The RDP 250 can include an NVM ECC decoder (not shown). The data output from the NVM 150 can include NVM parity bits and can be decoded by the NVM ECC decoder.

[0081] The NVM 150 can include a plurality of memory dies (not shown). To improve the throughput of the NVM 150, the memory I / F 142 can include a plurality of WRPs 210, CH-DMA components 230, and RDPs 250. The memory I / F 142 can simultaneously control a plurality of memory dies by using the plurality of WRPs 210, CH-DMA components 230, and RDPs 250. When the memory I / F 142 includes a plurality of WRPs 210, a plurality of mapping ECC components 214 can also be included, and the plurality of mapping ECC components 214 can simultaneously detect and correct errors in a plurality of mapped codewords.

[0082] According to an embodiment of the present disclosure, the mapping ECC component 214 can selectively remove the VM parity bits in the decoded mapped codeword, or can substantially maintain the mapped codeword including the VM parity bits. That is, the mapped codeword decoded by the mapping ECC 214 can also pass through the data path 216 as a mapped chunk, or can be stored in the NVM 150 as a mapped codeword via the data path 216.

[0083] Reference Figures 3 to 5 Describe embodiments of the present disclosure in detail. Figures 3 to 5 Schematically show reference Figure 1 and Figure 2 The memory I / F 142, VM 144, VM ECC component 146, and NVM 150 described.

[0084] Figure 3It is a diagram showing the power-off operation of the memory system 110 according to an embodiment of the present disclosure.

[0085] Refer to Figure 3 , as referred to in Figure 1 During the operation of the memory system 110, the VM 144 may store a plurality of mapped codewords including mapped chunks and VM parity bits. In response to a power-off signal of the memory system 110, the processor 134 may control the memory I / F 142 to program the plurality of mapped codewords in the VM 144 into the NVM 150. The operation of the memory I / F 142 programming the plurality of mapped codewords into the NVM 150 is described in detail.

[0086] In operation S302, the mapped ECC component 214 may receive a plurality of mapped codewords from the VM 144 and perform error correction decoding on the received mapped codewords.

[0087] In operation S304, the mapped ECC component 214 may provide the mapped data generated by the error correction decoding to the data path 216. According to an embodiment of the present disclosure, the mapped ECC component 214 may selectively remove the VM parity bits from the plurality of mapped codewords according to a mode and provide the mapped codewords without the VM parity bits to the data path 216.

[0088] In Figure 3 In the example shown, when the first mode (i.e., MODE1) is selected in the memory system 110, the mapped ECC component 214 may remove the VM parity bits from the mapped codewords to generate mapped chunks and provide the mapped chunks to the data path 216. When the second mode (i.e., MODE2) is selected in the memory system 110, the mapped ECC component 214 may provide the mapped codewords without the VM parity bits removed therefrom to the data path 216. The first mode and the second mode may be determined when implementing the memory system 110 or may be selected by a user. The data path 216 may perform error correction encoding on the mapped chunks or the mapped codewords by using an internal NVM ECC encoder (not shown) to generate mapped data to which NVM parity bits have been added.

[0089] In operation S306, the data path 216 may provide the mapped data to which NVM parity bits have been added to the NVM 150 through the CH-DMA component 230. The NVM 150 may program the mapped data to which NVM parity bits have been added. Then, the memory system 110 may be powered off.

[0090] The method of loading the mapped data from the NVM 150 to the VM 144 during startup may vary according to the operation mode of the memory system 110. Refer to Figure 4 AndFigure 5 Describe a method for loading mapping data according to each mode.

[0091] Figure 4 FIG. is a diagram showing a startup operation of the memory system 110 according to the first mode.

[0092] Refer to Figure 4 After the memory system 110 is powered on, in operation S402, the processor 134 may control the memory I / F 142 to read mapping data from the NVM 150.

[0093] The NVM 150 may output mapping data under the control of the memory I / F 142. The NVM ECC decoder (not shown) in the RDP 250 may perform error correction decoding on the output mapping data. When a power-off operation has been performed in the first mode, the mapping data stored in the NVM 150 may include a plurality of mapped chunks to which NVM parity bits have been added.

[0094] The plurality of mapped chunks need to be protected from errors when being stored in the VM 144. In operation S404, the memory I / F 142 may provide a plurality of error-corrected mapped chunks to the VM ECC component 146. The VM ECC component 146 may perform error correction encoding on the mapped chunks to add VM parity bits thereto, thereby generating mapped codewords.

[0095] In operation S406, the VM ECC component 146 may store the mapped codewords in the VM 144 and complete startup.

[0096] Figure 5 FIG. is a diagram showing a startup operation of the memory system 110 according to the second mode.

[0097] Refer to Figure 5 In operation S502, after the memory system 110 is powered on, the processor 134 may control the memory I / F 142 such that the NVM 150 outputs mapping data. When a power-off operation has been performed in the second mode, the mapping data stored in the NVM 150 may include mapped codewords and NVM parity bits.

[0098] Under the control of the memory I / F 142, the NVM 150 may output a plurality of mapped codewords to which NVM parity bits have been added. The NVM ECC decoder (not shown) in the RDP 250 may perform error correction decoding on the output mapped codewords by using the NVM parity bits.

[0099] The mapped codewords whose errors have been corrected by the NVM ECC decoder may include mapped chunks and VM parity bits. The mapped codewords can be protected from errors when stored in the VM 144 because they include VM parity bits.

[0100] In operation S504, the memory I / F 142 may store the mapped codewords directly in the VM 144 by bypassing the VM ECC component 146. When there is a request for a mapped chunk from the processor 134, the VM ECC component 146 may perform error correction decoding on the mapped codeword including the mapped chunk and provide the error-corrected mapped chunk to the processor 134. When the memory system 110 operates in the second mode, the bottleneck caused by the VM ECC component 146 during the startup of the memory system 110 can be resolved.

[0101] According to the reference Figures 3 to 5 described embodiments of the present disclosure, in order to store the mapped codewords stored in the VM 144 in the NVM 150, the processor 134 may control the memory I / F 142 such that the mapping ECC component 214 having a throughput higher than that of the VM ECC component 146 detects and corrects errors in the mapped codewords. Therefore, the power-off time of the memory system 110 can be shortened.

[0102] According to embodiments of the present disclosure, in order to store the mapped codewords stored in the VM 144 in the NVM 150, the processor 134 may control the VM ECC component 146 and the mapping ECC component 214 such that the VM ECC component 146 or the mapping ECC component 214 can selectively detect and correct the mapped codewords according to the type of the mapped codewords. Reference Figures 6A to 6C 、 Figure 7 、 Figure 8A 、 Figure 8B 、 Figure 9 and Figure 10 describe embodiments of the present disclosure in detail.

[0103] Figures 6A to 6C is a diagram showing the types of mapped data.

[0104] Figure 6A is a diagram showing the mapped data stored in the VM 144.

[0105] As described in reference Figure 1 the VM 144 may store mapped codewords including mapped chunks and VM parity bits.

[0106] In the memory system 110, data can be mainly processed in units of powers of two bits. For example, the processor 134 can process data in units of powers of two bits, and the VM 144 and the NVM 150 can store data in units of powers of two bits.

[0107] In an example where the processor 134 processes 32-bit data per cycle, the mapping segment can consist of up to 3,2-bit data. The mapping chunks can include mapping chunks corresponding to powers of two. When a mapping chunk consists of 32-bit data, the size of the mapping chunk can also have a size corresponding to powers of two bits.

[0108] The VM 144 can store mapping codewords in which VM parity bits have been added to the mapping chunks. When the mapping chunks correspond to powers of two bits, the mapping codewords to which VM parity bits have been added to the mapping chunks may not be powers of two.

[0109] Since the VM 144 addresses in units of powers of two, mapping data with non-powers-of-two bits to the address of the VM 144 may require a larger number of operations than mapping data with powers of two bits to the address of the VM 144.

[0110] To reduce the amount of operations required when mapping the mapping codewords to the address of the VM 144 and the capacity occupied by the mapping codewords in the VM 144, the size of the mapping codewords can be adjusted to powers of two bits when the memory system 110 is designed.

[0111] Figure 6A Adjusted codewords and unadjusted codewords are shown. Examples of mapping codewords whose size is adjusted to powers of two bits include logical-to-virtual (L2V) codewords. Figure 6A An adjusted codeword including an L2V chunk and a VM parity bit P is shown respectively.

[0112] Examples of mapping codewords whose size is not adjusted include valid page table (VPT) codewords. Figure 6A An unadjusted codeword including a VPT chunk and a VM parity bit P is shown respectively. Refer to Figure 6B For a detailed description of the L2V codeword, refer to Figure 6C For a detailed description of the VPT codeword.

[0113] Figure 6B Is a diagram showing an example of the L2V codeword as an adjusted codeword.

[0114] The L2V codeword is a kind of mapped data and can occupy most of the mapped data stored in the VM 144, such as about 95% of the mapped data. An L2V segment can indicate the mapping between a logical address and the corresponding virtual address. The virtual address can be an address used to indicate the defect-free space among the physical memory spaces of the NVM 150 and can be mapped to the physical address of the normal storage block of the NVM 150. Depending on the implementation, data less than 32 bits can indicate the mapping between a logical address and a virtual address. Figure 6B Shows an L2V segment adjusted to a 31-bit size.

[0115] To store multiple L2V segments in the VM 144, the VM ECC component 146 can perform error correction coding on an L2V chunk including a predetermined number of L2V segments and generate an L2V codeword to which VM parity bits have been added to the L2V chunk. In Figure 6B the example of, the VM ECC component 146 can add 16-bit VM parity bits to a 62-byte L2V chunk including 16 L2V segments, thereby generating a 64-byte adjusted L2V codeword.

[0116] When the processor 134 requests an L2V segment stored in the VM 144, the VM ECC component 146 can perform error correction decoding on the L2V codeword including the L2V segment, extract the error-corrected L2V segment, and provide 32-bit data to the processor 134, where 1-bit virtual data has been added to the extracted L2V segment.

[0117] As an example, Figure 6B shows a 31-bit L2V segment and a 64-byte L2V codeword; however, the present disclosure is not limited thereto. For example, the VM ECC component 146 can add 16-bit VM parity bits to a 30-byte L2V chunk including eight 30-bit L2V segments, thereby generating a 32-byte adjusted L2V codeword.

[0118] Figure 6C Is a diagram showing a valid page table (VPT) codeword as an example of an unadjusted codeword.

[0119] The VPT can indicate whether valid data has been stored in each page of the NVM 150. The VPT codeword is a kind of mapped data and can occupy a part of the mapped data stored in the VM 144, for example, about 5% or less of the mapped data. Depending on the implementation, when 32-bit data is required to represent the minimum information of the VPT, the size of the VPT segment may not be adjusted to less than 32 bits. As an example, Figure 6C shows a VPT segment composed of 32-bit data.

[0120] To store multiple VPT segments in VM 144, the VM ECC component 146 can perform error correction encoding on a VPT chunk including a predetermined number of L2V segments and generate a VPT codeword to which VM parity bits have been added to the VPT chunk. In Figure 6C the example of

[0121] as referenced Figures 6A to 6C above, most of the mapping data stored in VM 144 is an adjusted codeword, and the unadjusted codeword can occupy a part of the mapping data.

[0122] According to an embodiment of the present disclosure, when the memory system 110 is powered off, the memory I / F 142 can control the mapping ECC 214 to perform error correction decoding on the adjusted codeword by bypassing the VMECC component 146, and control the VM ECC component 146 to perform error correction decoding on the unadjusted codeword.

[0123] In an embodiment of the present disclosure, the VM ECC component 146 can be implemented to perform error correction decoding on both the adjusted codeword and the unadjusted codeword. In some embodiments, the mapping ECC component 214 can be implemented to only process the adjusted codeword. When the mapping ECC component 214 can only process the adjusted codeword, the mapping ECC component 214 can be simply implemented. Therefore, the area occupied by the mapping ECC component 214 in the circuit of the memory system 110 can be reduced.

[0124] Since most of the mapping data stored in VM 144 is an adjusted codeword, even if the mapping ECC component 214 only processes the adjusted codeword with increased throughput, the throughput of the entire mapping codeword can be similar to the throughput of the mapping ECC component 214. Therefore, when the memory system 110 is powered off, the mapping data stored in VM 144 can be quickly stored in the NVM 150.

[0125] Figure 7 is a diagram showing the mapping ECC component 214 according to an embodiment of the present disclosure.

[0126] Referring to Figure 7 , the mapping ECC component 214 can include a mapping ECC decoder 302 and a mapping chunk splitter 304.

[0127] The mapping ECC decoder 302 can perform error correction decoding on the adjusted codeword.

[0128] The mapping chunk splitter 304 can perform a chunk splitting operation that removes the VM parity bits from the error-corrected adjusted codeword and allows the mapping chunks to have a power-of-two number of bits.

[0129] Figure 8A and Figure 8B is a diagram showing the chunk splitting operation of the mapping chunk splitter 304.

[0130] Figure 8A Shows the adjusted codeword before performing the chunk splitting operation.

[0131] Figure 8A The adjusted codeword in Figure 6B can be substantially the same as or similar to the L2V codeword described in the reference

[0132] Figure 8B Shows the mapping chunk for which the chunk splitting operation has been completed.

[0133] The mapping chunk splitter 304 can remove the VM parity bits and add virtual data having the same size as the VM parity bits so that the mapping chunk can have a power-of-two number of bits. Specifically, the mapping chunk splitter 304 adds 1-bit virtual data to each adjusted mapping segment so that the adjusted mapping segments in the mapping chunk can be non-consecutive and can be split.

[0134] When virtual data is added to each adjusted mapping segment, each adjusted mapping segment can have a power-of-two number of bits. The adjusted mapping chunk including the adjusted mapping segments with the virtual data added thereto can also have a power-of-two number of bits. Thus, the processor 134 may not perform complex mapping operations to store the mapping chunk in the NVM 150.

[0135] The mapping chunk splitter 304 can be selectively activated according to the mode of the memory system 110. For example, when the memory system 110 operates in a first mode, the mapping chunk splitter 304 can be activated. When the memory system 110 operates in a second mode, the mapping chunk splitter 304 can be deactivated.

[0136] Hereinafter, operations according to the present disclosure are described with reference to Figures 9 to 11 the reference. Figures 9 to 11 is schematically shown with reference to Figure 1 andFigure 2 The described memory I / F 142, VM 144, VM ECC component 146, and NVM 150.

[0137] Figure 9 is a diagram illustrating a power-off operation of a memory system 110 according to an embodiment of the present disclosure.

[0138] In response to a power-off signal of the memory system 110, the processor 134 may control the memory I / F 142 to program a plurality of mapped codewords in the VM 144 into the NVM 150. The operation of the memory I / F 142 programming the plurality of mapped codewords into the NVM 150 is described in detail.

[0139] In operation S902, the mapping ECC component 214 may obtain a plurality of adjusted codewords from the VM 144 and perform error correction decoding on the adjusted codewords.

[0140] In operation S904, the mapping ECC component 214 may provide the error-corrected adjusted mapped data to the data path 216.

[0141] When a first mode is selected in the memory system 110, the mapping block splitter 304 may be activated. The mapping ECC component 214 may remove the VM parity bits from the error-corrected adjusted codewords by using the mapping block splitter 304 and perform the block splitting operation described in Figure 8B reference. In the Figure 9 illustrated example, when the first mode is selected, the adjusted mapped data may include adjusted mapped blocks.

[0142] When a second mode is selected in the memory system 110, the mapping block splitter 304 may be deactivated. The mapping ECC component 214 may provide the mapped codewords to the data path 216, from which the VM parity bits have not been removed. In the Figure 9 illustrated example, when the second mode is selected, the adjusted mapped data may include adjusted codewords.

[0143] The data path 216 may perform error correction encoding on the adjusted mapped data by using an internal NVM ECC encoder to generate mapped data to which NVM parity bits have been added.

[0144] In operation S906, in response to the power-off signal, the VM ECC component 146 may receive unadjusted codewords from the VM 144, perform error correction decoding on the unadjusted codewords, and remove the VM parity bits from the error-corrected mapped codewords to generate unadjusted mapped blocks. As described in reference Figure 6CAs described above, the unadjusted mapping chunks can have a power of two number of bits. Thus, the processor 134 may not perform complex mapping operations to store the unadjusted mapping chunks in the NVM 150.

[0145] In operation S908, the VM ECC component 146 may provide the generated mapping chunks to the data path 216. The data path 216 may perform error correction encoding on the unadjusted mapping chunks by using an internal NVM ECC encoder to generate mapping data to which NVM parity bits have been added.

[0146] The operations on the adjusted codewords in S902 and S904 and the operations on the unadjusted codewords in S906 and S908 may be performed in parallel.

[0147] In operation S910, the data path 216 may provide the data to which NVM parity bits have been added in the operations of S904 and S908 to the NVM 150 through the CH-DMA component 230. The NVM 150 may program the data to which NVM parity bits have been added. Then, the memory system 110 may be powered off.

[0148] In some embodiments, the method of loading mapping data from the NVM 150 to the VM 144 during startup of the memory system 110 may be changed according to the operation mode of the memory system 110. Refer to Figure 10 and Figure 11 for a description of the method of loading mapping data according to each mode.

[0149] Figure 10 is a diagram illustrating the startup operation of the memory system 110 according to the first mode.

[0150] Refer to Figure 10 After the memory system 110 is powered on, in operation S1002, the processor 134 may control the memory I / F 142 to read mapping data from the NVM 150.

[0151] The NVM 150 may output the mapping data under the control of the memory I / F 142. An NVMECC decoder (not shown) included in the RDP 250 may perform error correction decoding on the output mapping data.

[0152] When a power-off operation has been performed in the first mode, the mapping data stored in the NVM 150 may include adjusted mapping chunks, unadjusted mapping chunks, and NVM parity bits added to the mapping chunks.

[0153] In operation S1004, the memory I / F 142 may provide the error-corrected map chunks to the VM ECC component 146. The map chunks may include adjusted map chunks and unadjusted map chunks. The VM ECC component 146 may perform error correction encoding on the map chunks, thereby generating map codewords.

[0154] In operation S1006 , the VM ECC component 146 may store the mapped codeword in the VM 144 and complete the boot.

[0155] According to an embodiment of the present disclosure, when the memory system 110 operates in the first mode, the mapping chunks can be simultaneously error-corrected and decoded by the VM ECC component 146 without distinguishing between adjusted mapping chunks and unadjusted mapping chunks. Therefore, the operation of distinguishing between adjusted mapping chunks and unadjusted mapping chunks during the boot operation can be omitted.

[0156] Figure 11 is a diagram illustrating a startup operation of the memory system 110 according to the second mode.

[0157] After the memory system 110 is powered on, in operation S1102, the processor 134 may control the memory I / F 142 so that the NVM 150 outputs mapping data. When the power-off operation has been performed in the second mode, the mapping data may include adjusted codewords to which NVM parity bits have been added and unadjusted mapping chunks.

[0158] The NVM ECC decoder in RDP 250 may perform error correction decoding on the output adjusted codewords and unadjusted mapped chunks by using the NVM parity bits.

[0159] In operation S1104, memory I / F 142 may directly store the adjusted codeword in VM 144 by bypassing VM ECC component 146. Since the adjusted codeword occupies most of the mapped codewords, when memory system 110 operates in the second mode, a bottleneck caused by VM ECC component 146 during startup of memory system 110 may be resolved.

[0160] In operation S1106 , the memory I / F 142 may provide the unadjusted mapped chunks to the VM ECC component 146 .

[0161] In operation S1108 , the VM ECC component 146 may add VM parity bits to the unaligned mapped chunks, thereby generating unaligned codewords. The VM ECC component 146 may provide the unaligned codewords to the VM 144 .

[0162] After storing the adjusted codewords and the unadjusted codewords in the VM 144, the startup of the memory system 110 can be completed.

[0163] In some embodiments, to perform operations 1104, 1106, and 1108, it is necessary to distinguish between the adjusted codewords and the unadjusted mapped chunks. When the memory system 110 is powered off, the processor 134 can distinguish the adjusted codewords from the unadjusted mapped chunks by referring to the data logged in the NVM 150.

[0164] According to the reference Figures 6A to 6C , Figure 7 , Figure 8A and Figure 8B , Figure 9 , Figure 10 and Figure 11 In the embodiments of the present disclosure described above, in order to store the mapped codewords stored in the VM 144 in the NVM 150, the mapped ECC component 214 of the memory I / F 142 can perform error correction decoding on the adjusted codewords, and the VM ECC component 146 can perform error correction decoding on the unadjusted codewords. Since the mapped ECC component 214 is only implemented to be able to perform error correction decoding on the adjusted codewords, the mapped ECC component 214 can occupy a smaller area in the memory system 110. In addition, the adjusted codewords that occupy most of the mapped codewords are decoded by the mapped ECC component 214, thereby shortening the power-off time of the memory system 110.

[0165] According to various embodiments of the present disclosure, it has been described that when the memory system 110 is powered off, the memory I / F 142 performs error correction decoding on at least a part of the mapped data stored in the VM 144 by using the mapped ECC component 214, and stores the error-correction decoded mapped data in the NVM 150; however, the present disclosure is not limited thereto. For example, the VM 144 can store metadata for the operation of the memory system 110. In addition to the mapped data, the metadata can also include block management data. The memory I / F 142 can perform error correction decoding on the metadata stored in the VM 144 by using the mapped ECC component 214, and store the error-correction decoded metadata in the NVM 150.

[0166] The above-described content of the present disclosure is not limited by the above embodiments and the drawings, and it is obvious to those skilled in the art to which the present disclosure pertains that various substitutions, modifications, and changes can be made without departing from the technical idea of the present disclosure.

Claims

1. A memory system, comprising: A non-volatile memory device; A processor that generates a first mapped chunk, the first mapped chunk including mapping information for accessing the non-volatile memory device; A first error correction code component, i.e., a first ECC component, that generates a first mapped codeword by adding a first parity bit to the first mapped chunk; A volatile memory that stores the first mapped codeword; A second ECC component that, when performing a power-down operation of the memory system, generates first mapped data by decoding the first mapped codeword output from the volatile memory and bypassing the first ECC component; and A direct memory access component, i.e., a DMA component, that provides the first mapped data to the non-volatile memory device.

2. The memory system according to claim 1, wherein the first ECC component has a lower latency than the second ECC component, and The second ECC component has a higher throughput than the first ECC component.

3. The memory system according to claim 2, further comprising: A third ECC component that, when performing a power-down operation of the memory system, generates the first mapped data by decoding the first mapped codeword in parallel with the second ECC component.

4. The memory system according to claim 1, wherein in a first mode, the first mapped data is the first mapped chunk from which the first parity bit has been removed from the decoded first mapped codeword, and In a second mode, the first mapped data is the first mapped codeword in which the first parity bit of the decoded first mapped codeword is retained.

5. The memory system according to claim 4, wherein in the first mode, when the memory system is started, the DMA component further provides the first mapped chunk obtained from the non-volatile memory device to the first ECC component, and In the second mode, when the memory system is started, the DMA component further provides the first mapped codeword obtained from the non-volatile memory device to the volatile memory by bypassing the first ECC component.

6. The memory system according to claim 1, wherein the volatile memory further stores a second mapped codeword, the second mapped codeword including a second mapped chunk generated by the processor and a second parity bit added by the first ECC component, When performing a power-down operation of the memory system, the first ECC component generates a second mapped chunk by decoding the second mapped codeword and removing the second parity bit therefrom, and The DMA component further provides the second mapped chunk to the non-volatile memory device.

7. The memory system according to claim 6, wherein the first mapped codeword is a mapped codeword adjusted to have a size that is a power of 2, and The second mapped codeword is an unadjusted codeword that does not have a size that is a power of 2.

8. The memory system according to claim 7, wherein the adjusted codeword includes a logical-to-virtual mapping codeword, i.e., an L2V mapping codeword, and the unadjusted codeword includes a valid page table codeword, i.e., a VPT codeword.

9. The memory system according to claim 7, wherein in the first mode, the first mapped data is a first mapped chunk from which the first parity bit has been removed from the decoded first mapped codeword, and in the second mode, the first mapped data is the first mapped codeword in which the first parity bit of the decoded first mapped codeword is retained.

10. The memory system according to claim 9, wherein in the first mode, when the memory system is started, the DMA component further provides the first mapped chunk obtained from the non-volatile memory device to the first ECC component, and in the second mode, when the memory system is started, the DMA component further provides the first mapped codeword obtained from the non-volatile memory device to the volatile memory by bypassing the first ECC component.

11. The memory system according to claim 9, wherein when the memory system is started, the DMA component further provides second mapped data obtained from the non-volatile memory device to the first ECC component, and the first ECC component generates a second mapped codeword by adding a parity bit to the second mapped chunk and further provides the second mapped codeword to the volatile memory.

12. The memory system according to claim 7, further comprising: a fourth ECC component that performs encoding to store the first mapped data and the second mapped chunk in the non-volatile memory device and performs error correction decoding on data obtained from the non-volatile memory device.

13. A controller for controlling a non-volatile memory device, comprising: a processor that generates a first mapped chunk including mapping information for accessing the non-volatile memory device; a first error correction code component, i.e., a first ECC component, that generates a first mapped codeword by adding a first parity bit to the first mapped chunk; a volatile memory that stores the first mapped codeword; a second ECC component that generates first mapped data by decoding the first mapped codeword output from the volatile memory and bypasses the first ECC component when performing a power-off operation of a memory system including the non-volatile memory device and the controller; and a direct memory access component, i.e., a DMA component, that provides the first mapped data to the non-volatile memory device.

14. The controller according to claim 13, wherein the first ECC component has a lower latency than the second ECC component, and the second ECC component has a higher throughput than the first ECC component.

15. The controller according to claim 13, wherein in the first mode, the first mapped data is a first mapped chunk from which the first parity bit has been removed from the decoded first mapped codeword, and in the second mode, the first mapped data is the first mapped codeword in which the first parity bit of the decoded first mapped codeword is maintained.

16. The controller according to claim 15, wherein in the first mode, when the memory system is started, the DMA component further provides the first mapped chunk obtained from the non-volatile memory device to the first ECC component, and in the second mode, when the memory system is started, the DMA component further provides the first mapped codeword obtained from the non-volatile memory device to the volatile memory by bypassing the first ECC component.

17. The controller according to claim 13, wherein the volatile memory further stores a second mapped codeword, the second mapped codeword including a second mapped chunk generated by the processor and a second parity bit added by the first ECC component, when performing a power-off operation of the memory system, the first ECC component generates a second mapped chunk by decoding the second mapped codeword and removing the second parity bit therefrom, and the DMA component further provides the second mapped chunk to the non-volatile memory device.

18. The controller according to claim 17, wherein the first mapped codeword is a mapped codeword adjusted to have a size that is a power of 2, and the second mapped codeword is an unadjusted codeword that does not have a size that is a power of 2.

19. The controller according to claim 18, wherein in the first mode, the first mapped data is a first mapped chunk from which the first parity bit has been removed from the decoded first mapped codeword, and in the second mode, the first mapped data is the first mapped codeword in which the first parity bit of the decoded first mapped codeword is maintained.

20. A memory system, comprising: a non-volatile memory device; and a controller coupled to the non-volatile memory device and including: a volatile memory; a processor that generates a mapped chunk including mapping information for accessing the non-volatile memory device; a first error correction code component, i.e., a first ECC component, that encodes the mapped chunk to generate a mapped codeword and provides the mapped codeword to the volatile memory such that the mapped codeword is stored in the volatile memory, the mapped codeword including the mapped chunk and a parity bit; and a memory interface coupled between the volatile memory and the non-volatile memory device and between the first ECC component and the non-volatile memory device, wherein the memory interface includes: A second ECC component that receives the mapped codeword from the volatile memory when performing a power-down operation of the memory system, and decodes the received mapped codeword to generate mapped data, the second ECC component having a higher throughput than the first ECC component; and A direct memory access component, namely a DMA component, that receives the mapped data and provides the mapped data to the non-volatile memory device.

Images