Memory device

Abstract

The present technology includes a memory device. The memory device includes: a stacked structure including word lines and selection lines; a vertical hole vertically penetrating the stacked structure; and a memory layer, a channel layer, and a plug formed sequentially along an inner surface of the vertical hole. The plug includes a material layer having a fixed negative charge.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0134633, filed with the Korean Intellectual Property Office on October 16, 2020, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to a memory device, and more particularly, to a three-dimensional memory device. Background Art

[0004] A memory device may store data or output stored data. For example, the memory device may be configured as a volatile memory device that loses stored data when power supply is interrupted, or may be configured as a non-volatile memory device that retains stored data even when power supply is interrupted. The memory device may include: a memory cell array in which data is stored; a peripheral circuit capable of performing programming, reading, or erasing operations; and a logic circuit capable of controlling the peripheral circuit.

[0005] The memory cell array may include a plurality of memory blocks, and each of the plurality of memory blocks may include a plurality of memory cells. The memory cells may be connected in series with each other between a bit line and a source line to form a string. Memory cells included in different strings and connected to the same word line may form a page. Programming operations and reading operations may be performed in units of pages, and erasing operations may be performed in units of blocks. Summary of the Invention

[0006] According to an aspect of the present disclosure, there may be provided a memory device including: a stacked structure including a word line and a selection line; a vertical hole vertically penetrating the stacked structure; and a memory layer, a channel layer, and a plug sequentially formed along an inner surface of the vertical hole, wherein the plug includes a material layer having a fixed negative charge.

[0007] According to another aspect of the present disclosure, there may be provided a memory device including: a stacked structure including a word line and a plurality of selection lines; a vertical hole vertically penetrating the stacked structure; and a memory layer, a channel layer, and a plug sequentially formed along an inner surface of the vertical hole, wherein the plug includes a material layer having a fixed negative charge. Brief Description of the Drawings

[0008] Examples of embodiments will now be described below with reference to the accompanying drawings; however, these examples may be embodied in different forms and should not be construed as limited to the embodiments set forth herein.

[0009] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It should be understood that when an element is referred to as being “between” two elements, the element may be the only element between the two elements, or there may also be one or more intervening elements. Like reference numerals always refer to like elements.

[0010] Figure 1 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0011] Figure 2 is a diagram illustrating Figure 1 the memory cell array shown in

[0012] Figure 3 is a diagram illustrating the i-th memory block according to an embodiment of the present disclosure.

[0013] Figure 4 is a view illustrating the final structure of a memory device according to a first embodiment of the present disclosure.

[0014] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15 is a view illustrating a memory device and a method of manufacturing the memory device according to a first embodiment of the present disclosure.

[0015] Figure 16 is a view illustrating the effects according to the present disclosure.

[0016] Figure 17 is a view illustrating a memory device according to a second embodiment of the present disclosure.

[0017] Figure 18 is a view illustrating a memory device according to a third embodiment of the present disclosure.

[0018] Figure 19 is a view illustrating a memory device according to a fourth embodiment of the present disclosure.

[0019] Figure 20 is a view illustrating a memory device according to a fifth embodiment of the present disclosure.

[0020] Figure 21 FIG. 66 is a view illustrating a memory device according to a sixth embodiment of the present disclosure.

[0021] Figure 22 FIG. 67 is a diagram illustrating a memory card system to which the memory device of the present disclosure is applied.

[0022] Figure 23 FIG. 68 is a diagram illustrating a solid state drive (SSD) system to which the memory device of the present disclosure is applied. DETAILED DESCRIPTION

[0023] The specific structures or functions disclosed herein are merely illustrative for the purpose of describing embodiments of the concepts according to the present disclosure. Embodiments according to the concepts of the present disclosure may be implemented in various forms and cannot be construed as limited to the embodiments set forth herein.

[0024] It will be understood that although terms such as "first" and "second" may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, the "first" element discussed below may also be referred to as the "second" element without departing from the teachings of the present disclosure.

[0025] An embodiment may provide a memory device capable of improving an erase operation.

[0026] Figure 1 FIG. 84 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0027] Referring to Figure 1 , the memory device 1100 may include: a memory cell array 110 in which data is stored; peripheral circuits 120, 130, 140, 150, and 160 that perform programming, reading, and erasing operations; and a logic circuit 170 that controls the peripheral circuits 120, 130, 140, 150, and 160. The peripheral circuits 120 to 160 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, and an input / output circuit 160.

[0028] The memory cell array 110 may include a plurality of memory blocks, and each of the memory blocks may include a plurality of memory cells. The memory blocks may be connected to the row decoder 130 through a plurality of local lines LL and to the page buffer group 140 through a plurality of bit lines BL.

[0029] The voltage generator 120 can generate the operation voltages required for programming, reading, or erasing operations in response to the operation code Cop. For example, the voltage generator 120 can generate operation voltages such as a programming voltage, a reading voltage, an erasing voltage, a pass voltage, a turn-off voltage, and a verification voltage. The operation voltages generated by the voltage generator 120 can be transferred to the row decoder 130 through the global line GL.

[0030] The row decoder 130 can select the memory blocks included in the memory cell array 110 in response to the row address ADDR, and transfer the operation voltages received through the global line GL to the selected memory blocks through the local lines LL. The local lines LL can include a plurality of word lines, drain select lines, source select lines, and source lines.

[0031] The page buffer group 140 can temporarily store the data received from the outside during a programming operation, and temporarily store the data sensed from the memory cells during a verification or reading operation. The page buffer group 140 can temporarily store data or pre-charge the bit lines BL in response to the page buffer signals PBSIGS, and sense the voltage or current of the bit lines BL. For example, the page buffer group 140 can sense the current or voltage passing through the string of the bit lines BL during an erase verification operation.

[0032] The column decoder 150 can transfer data between the input / output circuit 160 and the page buffer group 140 in response to the column address ADDC.

[0033] The input / output circuit 160 can receive a command CMD and an address ADD from an external device (e.g., a controller) through the input / output lines IO, and input or output data. During a programming operation, the input / output circuit 160 can transfer the command CMD and the address ADD input through the input / output lines IO to the logic circuit 170, and transfer the data to the page buffer group 140. During a reading operation, the input / output circuit 160 can output the data read from the page buffer group 140 to an external device.

[0034] The logic circuit 170 can be configured with software and hardware that can control the peripheral circuits in response to the command CMD and the address ADD. The logic circuit 170 can output the operation code Cop, the page buffer signals PBSIGS, the row address ADDR, and the column address ADDC in response to the command CMD and the address ADD.

[0035] Figure 2 is a diagram showing Figure 1 a diagram of the memory cell array shown in

[0036] Refer to Figure 2, the memory cell array 110 may include a first memory block BLK1 to an i-th memory block BLKi. In a single-plane structure, the first memory block BLK1 to the i-th memory block BLKi may constitute the memory cell array 110. In a multi-plane structure, the first memory block BLK1 to the i-th memory block BLKi may constitute one plane, and multiple planes may be included in the memory cell array 110. The first memory block BLK1 to the i-th memory block BLKi may be configured identically to each other, and the i-th memory block BLKi among the first memory block BLK1 to the i-th memory block BLKi will be described in detail below.

[0037] Figure 3 is a diagram illustrating the i-th memory block according to an embodiment of the present disclosure.

[0038] Referring to Figure 3 , the i-th memory block BLKi may include a plurality of memory strings ST, which are connected between a first bit line BL1 to a j-th bit line BLj and a source line SL. Each memory string ST in the memory strings ST may extend along the Z direction. The Z direction may be the direction in which the memory cells C1 to Cn are stacked, and may be a direction orthogonal to the substrate.

[0039] Each memory string ST in the memory strings ST may include a source select transistor SST, memory cells C1 to Cn, and a first drain select transistor DST1 connected in series with each other.

[0040] The source select transistor SST included in one memory string ST may be connected between the first memory cell C1 and the source line SL. The gate electrodes of the source select transistors SST included in different memory strings ST may be connected to the source select line SSL. In addition, the source select transistors SST located in the same layer may be connected to the same source select line SSL.

[0041] The first memory cells C1 to the n-th memory cells Cn included in one memory string ST may be connected in series between the source select transistor SST and the first drain select transistor DST1. The gate electrodes of the first memory cells C1 to the n-th memory cells Cn may be respectively connected to the first word line WL1 to the n-th word line WLn. The operating voltages required for driving (such as programming voltage, pass voltage, read voltage, ground voltage, etc.) may be applied to the first word line WL1 to the n-th word line WLn. A group of memory cells connected to each word line among the first word line WL1 to the n-th word line WLn becomes a page. For example, a group of first memory cells C1 connected to the first word line WL1 may constitute a page. The programming or reading operation of the i-th memory block BLKi may be performed in units of pages PG.

[0042] The first drain select transistor DST1 included in a memory string ST may be connected between any one of the first bit line BL1 to the j-th bit line BLj and the memory cell Cn. For example, the first drain select transistor DST1 included in the i-th memory block BLKi may be connected between the first bit line BL1 to the j-th bit line BLj and the n-th memory cell Cn. The gates of the first drain select transistors DST1 included in different memory strings ST may be connected to the first drain select line DSL1.

[0043] Figure 4 is a view illustrating the final structure of a memory device according to a first embodiment of the present disclosure. Figure 4 Illustrated in Figure 3 is a cross-sectional view taken along the direction I-I’ shown in.

[0044] Referring to Figure 4 , the first insulating layer 40 may be formed on the lower structure STRun, and the first conductive layer 41 may be formed on the first insulating layer 40. The lower structure STRun may include a substrate and include peripheral circuits formed on the substrate. The first insulating layer 40 is a layer for electrically insulating the lower structure STRun and the first conductive layer 41 from each other, and may be formed as an oxide layer. The first conductive layer 41 may be used as the source line SL. A ground voltage or an erase voltage may be applied to the source line SL.

[0045] A stacked structure STK in which the second insulating layer 51 and the second conductive layer 82 are alternately stacked may be formed on the first conductive layer 41. For example, the second insulating layer 51 may be formed as an oxide layer, and the second conductive layer 82 may be formed as a tungsten layer. Depending on the position of the second conductive layer 82, the second conductive layer 82 may be used as the source select line SSL, the word line WLn, or the first drain select line DSL1. For example, the conductive layer located at the lowermost end in the second conductive layer 82 may become the source select line SSL, the conductive layer located at the uppermost end in the second conductive layer 82 may become the first drain select line DSL1, and the conductive layer located between the source select line SSL and the first drain select line DSL1 in the second conductive layer 82 may become the word line WLn. The third insulating layer 53 may be formed on the stacked structure STK.

[0046] A vertical hole VH may be formed that vertically penetrates the third insulating layer 53 and the stacked structure STK, and a plug PL having a cylindrical shape and a cylindrical channel layer 64 and a cylindrical memory layer ML may be formed inside the vertical hole VH, with the cylindrical channel layer 64 and the cylindrical memory layer ML surrounding the periphery of the plug PL.

[0047] The plug PL may include a fourth insulating layer 65, a second material layer 70, and a capping pattern 71. The fourth insulating layer 65 may be formed as an oxide layer, and may be formed as, for example, a silicon dioxide (SiO2) layer. The second material layer 70 may be formed of a fixed negative electrode material. The fixed negative electrode material is a material having a high density of negative charges due to the crystal structure of the film, and may include, for example, aluminum oxide (Al2O3). The capping pattern 71 may be configured as a doped semiconductor layer. For example, the capping pattern 71 may include doped silicon doped with an n-type impurity.

[0048] The channel layer 64 is a layer in which charges can move, and may be formed as, for example, an undoped semiconductor layer. In an embodiment, the undoped semiconductor layer may include an undoped silicon layer. A junction region JC to which a voltage is applied may be formed in the channel layer 64.

[0049] The memory layer ML may include a blocking layer 61, a charge trapping layer 62, and a tunnel isolation layer 63. The blocking layer 61 may be formed of an insulating material, and may be formed as, for example, an oxide layer. The charge trapping layer 62 is a layer for storing data, and may be formed as a nitride layer. For example, in a programming operation, electrons having negative charges may be stored in the charge trapping layer 62 through a programming voltage. In an erase operation, the electrons stored in the charge trapping layer 62 may be discharged to the outside through an erase voltage. The tunnel isolation layer 63 is a layer for isolating the charge trapping layer 62 from the channel layer 64, and may be formed as an oxide layer. The tunnel isolation layer 63 may be located between the charge trapping layer 62 and the channel layer 64. For example, in a programming operation, electrons may be moved to the charge trapping layer 62 when passing through the tunnel isolation layer 63 from the channel layer 64. In an erase operation, electrons may be moved from the charge trapping layer 62 to the channel layer 64.

[0050] A fifth insulating layer 76 may be formed over the third insulating layer 53 and the memory layer ML, and a bit line contact BLC may be formed on the channel layer 64 and the plug PL. The fifth insulating layer 76 may be formed as an oxide layer, and the bit line contact BLC may be formed as a conductive layer.

[0051] The bit line BL may be formed on a part of the fifth insulating layer 76 and over the bit line contact BLC. According to this embodiment, the second material layer 70 having fixed negative charges is included in the plug PL, such that positive charges moving in the channel layer 64 may move adjacent to the memory layer ML. Therefore, in an erase operation, the electrons trapped in the charge trapping layer 62 may be easily discharged.

[0052] Figures 5 to 15 is a view illustrating a memory device and a method of manufacturing the memory device according to a first embodiment of the present disclosure.

[0053] Referring to Figure 5 , the first insulating layer 40 and the first conductive layer 41 may be formed on the lower structure STRun. The lower structure STRun may include a substrate and also include peripheral circuits formed on the substrate. The first insulating layer 40 is a layer for electrically insulating the lower structure STRun and the first conductive layer 41 from each other and may be formed as an oxide layer. The first conductive layer 41 may be used as a source line SL. A ground voltage or an erase voltage may be applied to the source line SL.

[0054] A stacked structure STK in which the second insulating layer 51 and the first material layer 52 are alternately stacked may be formed on the first conductive layer 41. The second insulating layer 51 may be formed as an oxide layer, and the first material layer 52 may be formed of a material that is removed in a subsequent process and has an etching selectivity with respect to the second insulating layer 51. For example, the first material layer 52 may be formed as a nitride layer. The third insulating layer 53 may be formed on the stacked structure STK. The third insulating layer 53 may be formed as an oxide layer. The third insulating layer 53 may be formed thicker than the second insulating layer 51 included in the stacked structure STK in order to suppress an interference phenomenon between bit lines and drain selection lines formed in a subsequent process.

[0055] Referring to Figure 6 , a vertical hole VH may be formed in the third insulating layer 53 and the stacked structure STK. For example, by forming a mask pattern (not shown) including an opening on the third insulating layer 53 and etching the third insulating layer 53 and the stacked structure STK exposed through the opening, a vertical hole VH having a cylindrical shape may be formed. The first conductive layer 41 may be exposed through the bottom surface of the vertical hole VH.

[0056] Referring to Figure 7, the memory layer ML and the channel layer 64 may be formed on the side surfaces of the vertical holes VH. The memory layer ML may include a blocking layer 61, a charge trapping layer 62, and a tunneling isolation layer 63. The blocking layer 61 may be formed of an insulating material and formed as, for example, an oxide layer. The charge trapping layer 62 is a layer for storing data and may be formed as a nitride layer. For example, in a programming operation, electrons having a negative charge may be stored in the charge trapping layer 62 through a programming voltage. In an erase operation, the electrons stored in the charge trapping layer 62 may be discharged to the outside through an erase voltage. The tunneling isolation layer 63 is a layer for isolating between the charge trapping layer 62 and the channel layer 64 and may be formed as an oxide layer. For example, in a programming operation, electrons may move to the charge trapping layer 62 when passing through the tunneling isolation layer 63 from the channel layer 64. In an erase operation, electrons may move from the charge trapping layer 62 to the channel layer 64. The channel layer 64 is a layer through which charges may move and may be formed as, for example, an undoped semiconductor layer. In an embodiment, the undoped semiconductor layer may include an undoped silicon layer.

[0057] Referring to Figure 8 , a fourth insulating layer 65 may be formed over the entire structure to fill the interior of the vertical holes VH. For example, the fourth insulating layer 65 may be formed as a silicon oxide layer SiO2. The fourth insulating layer 65 may be formed such that the third insulating layer 53 is completely covered to sufficiently fill the interior of the vertical holes VH.

[0058] Referring to Figure 9 , a planarization process may be performed such that the top surface of the third insulating layer 53 is exposed. After the planarization process, portions of the third insulating layer 53, the blocking layer 61, the charge trapping layer 62, the tunneling isolation layer 63, the channel layer 64, and the fourth insulating layer 65 may be exposed over the entire structure.

[0059] Referring to Figure 10 , an etching process for reducing the height of the fourth insulating layer 65 may be performed. For example, the etching process may be performed as a dry etching process for selectively etching only the fourth insulating layer 65. The etching process may be performed such that the height of the fourth insulating layer 65 is lower than a second height H2 and higher than a fifth height H5. The second height H2 may be the height from the bottom surface of the stacked structure STK to the position where a channel may be formed in the channel layer 64, and the fifth height H5 may be the height from the bottom surface of the stacked structure STK to the bottom surface of the topmost first material layer 52 in the first material layer 52. That is, a third height H3 may be determined between the fifth height H5 and the second height H2.

[0060] Referring to Figure 11, a second material layer 70 may be formed over the entire structure to fill an upper region of the fourth insulating layer 65. The second material layer 70 may be formed of a material for increasing the amount of current in the channel layer 64 during an erase operation. For example, the second material layer 70 may be formed of a material having a fixed negative charge. For example, the second material layer 70 may be formed as an Al2O3 layer having a fixed negative charge. The second material layer 70 may be formed such that the entire structure is completely covered to sufficiently fill the region above the vertical hole VH in the fourth insulating layer 65.

[0061] Referring Figure 12 , an etching process for adjusting the thickness of the second material layer 70 may be performed. For example, the etching process may be performed as a dry etching process for selectively etching the second material layer 70. The etching process may be performed such that a top surface of the second material layer 70 has a fourth height H4 higher than a first height H1. In an embodiment, the fourth height H4 may be a height from the top surface of the second material layer 70 to the top surface of the first conductive layer 41. The first height H1 may be a height from the bottom surface of the stacked structure STK to the top surface of the first material layer 52. Thus, the thickness of the second material layer 70 remaining after the etching process may be a height obtained by subtracting a third height H3 from the fourth height H4. In an embodiment, the third height H3 may be a height from the bottom surface of the second material layer 70 to the top surface of the first conductive layer 41.

[0062] Referring Figure 13 , a capping pattern 71 for filling an upper region of the second material layer 70 may be formed. The capping pattern 71 may be configured as a doped semiconductor layer. For example, the capping pattern 71 may include doped silicon doped with an n-type impurity. For example, the capping pattern 71 may be formed such that the top surface of the entire structure is completely covered to sufficiently fill the upper region of the second material layer 70. After forming the capping pattern 71, a planarization process may be performed until the top surface of the third insulating layer 53 is exposed. Thus, a plug PL may be formed, which includes the fourth insulating layer 65, the second material layer 70, and the capping pattern 71. That is, the plug PL may be formed in a cylindrical shape, and the channel layer 64, the tunnel isolation layer 63, the charge trapping layer 62, and the blocking layer 61 may be formed in a cylindrical shape to sequentially surround the plug PL.

[0063] Referring Figure 14 , an etching process for removing the first material layer ( Figure 13 52 shown in) may be performed. The etching process may be performed as a wet etching process for removing all of the first material layers 52 formed between the second insulating layers 51. Each of the spaces in which the first material layer 52 is removed between the second insulating layers 51 may be defined as a notch RC.

[0064] Reference Figure 15 As shown in Figure 15 , the second conductive layer 82 can be formed in each of the recesses RC. For example, the second conductive layer 82 can be formed of tungsten. Although not shown in the drawings, a barrier layer can be further formed along the inner surface of the recess RC before forming the second conductive layer 82.

[0065] At least one of the second conductive layers in the second conductive layer 82 can be used as the first drain select line DSL1, some of the second conductive layers in the second conductive layer 82 can be used as the word line WLn, and at least one of the second conductive layers in the second conductive layer 82 can be used as the source select line. For example, the conductive layer at the uppermost end in the second conductive layer 82 can become the first drain select line DSL1, and the conductive layer below the first drain select line DSL1 can be used as the word line WLn. The conductive layer at the lowermost end in the second conductive layer 82 can be used as the source select line.

[0066] The fifth insulating layer 76 for the interlayer insulating layer can be formed over the third insulating layer 53 and the memory layer ML, and the bit line contact BLC can be formed over the channel layer 64 and the plug PL. The fifth insulating layer 76 can be formed as an oxide layer, and the bit line contact BLC can be formed as a conductive layer.

[0067] The bit line BL can be formed over a part of the fifth insulating layer 76 and over the bit line contact BLC. The bit line contact BLC can electrically connect the bit line BL and the channel layer 64.

[0068] Figure 16 is a view illustrating the effects according to the present disclosure.

[0069] Reference Figure 16, when the conductive layer at the uppermost position in the second conductive layer 82 is used as the first drain select line DSL1, the memory layer ML connected to the first drain select line DSL1 becomes the first drain select transistor DST1. Thus, the junction region JC can be formed in the region of the channel layer 64 that partially overlaps with the upper portion of the first drain select transistor DST1. The junction region JC can be a region to which a voltage is applied. The erase operation will be described as an example. In the erase operation, an erase voltage Vera having a high positive voltage can be applied to the channel layer 64. After the positive voltage is applied to the first drain select line DSL1 for a certain period of time, the first drain select line DSL1 can be floated. Due to the voltage difference between the erase voltage Vera applied to the channel layer 64 and the voltage of the first drain select line DSL1, current can flow through the channel layer 64, and the positive charges (+) generated in the channel layer 64 can be moved away from the plug PL due to the second material layer 70 having fixed negative charges (-). That is, the positive charges (+) generated in the channel layer 64 can be moved adjacent to the memory layer ML by the second material layer 70. Thus, the electrons (-) trapped in the charge trapping layer 62 of the memory layer ML can be easily discharged through the positive charges (+). Therefore, the erase operation of the memory device can be easily performed through the second material layer 70 having fixed negative charges (-).

[0070] Based on the first embodiment described above, the second material layer 70 can be formed in various structures. Various embodiments associated therewith will be described as follows.

[0071] Figure 17 is a view illustrating a memory device according to a second embodiment of the present disclosure.

[0072] Refer to Figure 17 , in the memory device according to the second embodiment of the present disclosure, other structures except for the plug PL are the same as the final structure of the first embodiment shown in Figure 15 , so the description of other structures except for the plug PL will be omitted. In the second embodiment, the plug PL can include a fourth insulating layer 65, a second material layer 70, and a sixth insulating layer 77. For example, the plug PL can be formed into the following structure: in this structure, the second material layer 70 is formed on the fourth insulating layer 65, and the sixth insulating layer 77 is formed on the second material layer 70. The sixth insulating layer 77 can be formed as an oxide layer and can be formed as, for example, a SiO2 layer. A fifth insulating layer 76 can be formed on the third insulating layer 53 and the memory layer ML, and a bit line contact BLC can be formed on the channel layer 64 and the plug PL. The bit line BL can be formed on a part of the fifth insulating layer 76 and on the bit line contact BLC.

[0073] Figure 18 FIG. is a view illustrating a memory device according to a third embodiment of the present disclosure.

[0074] Referring to Figure 18 , in the memory device according to the third embodiment of the present disclosure, structures other than the plug PL are the same as the final structure of the first embodiment shown in Figure 15 , and thus, descriptions of structures other than the plug PL will be omitted. In the third embodiment, the plug PL does not include a capping pattern ( Figure 15 71 shown in ), and may be configured with a fourth insulating layer 65 and a second material layer 70. For example, the plug PL may be formed in a structure in which the second material layer 70 is formed on the fourth insulating layer 65. The height of the bottom surface Lb of the second material layer 70 may be located between the bottom surface and the top surface of the first drain selection line DSL1. A fifth insulating layer 76 may be formed on the third insulating layer 53 and the memory layer ML, and a bit line contact BCL may be formed on the channel layer 64 and the plug PL. A bit line BL may be formed on a part of the fifth insulating layer 76 and on the bit line contact BCL.

[0075] Figure 19 FIG. is a view illustrating a memory device according to a fourth embodiment of the present disclosure.

[0076] Referring to Figure 19 , in the memory device according to the fourth embodiment of the present disclosure, structures other than the drain selection lines DSL1 to DSLk and the plug PL are the same as the final structure of the first embodiment shown in Figure 15 , and thus, descriptions of structures other than the drain selection lines DSL1 to DSLk and the plug PL will be omitted. In the fourth embodiment, different from the first embodiment, a plurality of drain selection lines DSL1 to DSLk may be included in the memory device. For example, the first drain selection line DSL1 to the k-th drain selection line DSLk may be sequentially disposed in an upper region of the word line WLn. The first drain selection line DSL1 to the k-th drain selection line DSLk may become a drain selection line group DSL_GR. The first drain selection line DSL1 may be disposed at the lowermost end, and the k-th drain selection line DSLk may be disposed at the uppermost end.

[0077] The plug PL may include a fourth insulating layer 65, a second material layer 70, and a capping pattern 71. That is, since the second material layer 70 is disposed between the fourth insulating layer 65 and the capping pattern 71, in the fourth embodiment, the position of the second material layer 70 may be changed according to the positions of the first drain selection line DSL1 to the k-th drain selection line DSLk. For example, the height of the bottom surface Lb of the second material layer 70 may be located in the space D1 between the bottom surface of the first drain selection line DSL1 and the top surface of the k-th drain selection line DSLk, and the height of the top surface Lt of the second material layer 70 may be located in the upper region of the k-th drain selection line DSLk.

[0078] Figure 20 is a view illustrating a memory device according to a fifth embodiment of the present disclosure.

[0079] Referring to Figure 20 , in the memory device according to the fifth embodiment of the present disclosure, structures other than the plug PL are the same as the final structure of the fourth embodiment shown in Figure 19 , and thus, descriptions of structures other than the plug PL will be omitted. In the fifth embodiment, different from the fourth embodiment, a sixth insulating layer 77 instead of the capping pattern ( Figure 19 shown as 71) may be included in the plug PL. That is, since the second material layer 70 is disposed between the fourth insulating layer 65 and the sixth insulating layer 77, in the fifth embodiment, the position of the second material layer 70 may be changed according to the positions of the first drain selection line DSL1 to the k-th drain selection line DSLk. For example, the bottom surface Lb of the second material layer 70 may be located between the bottom surface of the first drain selection line DSL1 and the top surface of the k-th drain selection line DSLk, and the top surface Lt of the second material layer 70 may be located in the upper region of the k-th drain selection line DSLk.

[0080] Figure 21 is a view illustrating a memory device according to a sixth embodiment of the present disclosure.

[0081] Referring to Figure 21 , in the memory device according to the sixth embodiment of the present disclosure, structures other than the plug PL are the same as the final structure of the fifth embodiment shown in Figure 20 , and thus, descriptions of structures other than the plug PL will be omitted. In the sixth embodiment, the plug PL does not include the sixth insulating layer ( Figure 20as shown in 77), and may include a fourth insulating layer 65 and a second material layer 70. For example, the plug PL may be formed in a structure in which the second material layer 70 is formed on the fourth insulating layer 65. In this structure, the bottom surface Lb of the second material layer 70 may be located in the space D1 between the bottom surface of the first drain selection line DSL1 and the top surface of the k-th drain selection line DSLk.

[0082] Figure 22 is a diagram illustrating a memory card system to which the memory device of the present disclosure is applied.

[0083] Referring to Figure 22 , the memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

[0084] The memory controller 2100 is connected to the memory device 2200. The memory controller 2100 can access the memory device 2200. For example, the memory controller 2100 can control programming, reading, or erasing operations of the memory device 2200, or control the background of the memory device 2200. The memory controller 2100 provides an interface between the memory device 2200 and the host Host. The memory controller 2100 drives firmware for controlling the memory device 2200. The memory device 2200 may be configured in the same manner as the memory device 1100 described with reference to Figure 1 above.

[0085] The memory controller 2100 can communicate with an external device through the connector 2300. The memory controller 2100 can communicate with an external device (such as a host) according to a specific communication protocol. Exemplarily, the memory controller 2100 can communicate with an external device through at least one of various communication protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe. Exemplarily, the connector 2300 can be defined by at least one of the various communication protocols described above.

[0086] For example, the memory device 2200 can be implemented with various non-volatile memory devices such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin torque transfer magnetic RAM (STT-MRAM).

[0087] The memory controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and the memory device 2200 can form a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a CompactFlash (CF) card, a SmartMedia card (SM and SMC), a Memory Stick, a Multimedia card (MMC, RS-MMC, MMCmicro, and eMMC), an SD card (SD, miniSD, microSD, and SDHC), and a Universal Flash Storage (UFS).

[0088] Figure 23 FIG. is a diagram illustrating a solid state drive (SSD) system to which the memory device of the present disclosure is applied.

[0089] Referring to Figure 23 , the SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals with the host 3100 through a signal connector 3001 and receives a power supply voltage through a power connector 3002. The SSD 3200 includes an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0090] According to an embodiment of the present disclosure, the flash memories 3221 to 322n can be configured in the same manner as the memory device 1100 described with reference to Figure 1 .

[0091] The SSD controller 3210 can control multiple flash memories 3221 to 322n in response to signals received from the host 3100. Exemplarily, the signals can be signals based on the interface between the host 3100 and the SSD 3200. For example, the signals can be signals defined by at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), WI-FI, Bluetooth, and NVMe.

[0092] The auxiliary power supply 3230 is connected to the host 3100 through the power connector 3002. The auxiliary power supply 3230 can receive the power input from the host 3100 and charge the power. When the power supply from the host 3100 is unstable, the auxiliary power supply 3230 can provide power for the SSD 3200. Exemplarily, the auxiliary power supply 3230 can be located inside the SSD 3200 or outside the SSD 3200. For example, the auxiliary power supply 3230 can be located on the motherboard and provide auxiliary power to the SSD 3200.

[0093] The buffer memory 3240 operates as the buffer memory of the SSD 3200. For example, the buffer memory 3240 can temporarily store the data received from the host 3100 or the data received from the multiple flash memories 3221 to 322n, or temporarily store the metadata (such as the mapping table) of the flash memories 3221 to 322n. The buffer memory 3240 can include volatile memories (such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM) or non-volatile memories (such as FRAM, ReRAM, STT-MRAM, and PRAM).

[0094] According to the present disclosure, the material constituting the plug is changed so that the erase operation of the memory device can be improved.

[0095] Examples of embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, these are only for explaining the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the embodiments described above, and many variations are possible within the spirit and scope of the present disclosure. It should be obvious to those skilled in the art that various modifications can be made based on the technical scope of the present disclosure in addition to the embodiments disclosed herein.

[0096] Unless otherwise defined, all terms (including technical and scientific terms) used herein shall have the meanings commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should be understood that terms having definitions as defined in a dictionary shall have meanings consistent with the context of the relevant art. Unless explicitly defined in this application, terms should not be construed in an idealized or overly formal manner.

Claims

1. A memory device, comprising: A stacked structure including word lines and select lines; Vertical holes vertically penetrating the stacked structure; And A memory layer, a channel layer, and plugs sequentially formed along an inner surface of the vertical holes, Wherein the plugs include a material layer having a fixed negative charge, Wherein a bottom surface of the material layer is located between a bottom surface and a top surface of the select line.

2. The memory device according to claim 1, wherein the material layer includes an Al2O3 layer.

3. The memory device according to claim 1, wherein the plugs include: A first insulating layer; The material layer formed on the first insulating layer; And A capping pattern formed on the material layer.

4. The memory device according to claim 3, wherein the first insulating layer includes an oxide layer, and The capping pattern includes doped silicon.

5. The memory device according to claim 3, wherein the material layer is formed at a position adjacent to the select line in the plugs.

6. The memory device according to claim 5, wherein a top surface of the material layer is located in a region higher than the top surface of the select line.

7. The memory device according to claim 1, wherein the plugs include a first insulating layer, the material layer, and a second insulating layer, and Wherein the material layer is disposed between the first insulating layer and the second insulating layer.

8. The memory device according to claim 7, wherein a top surface of the material layer is located at a height higher than a height at which the top surface of the select line is located.

9. The memory device according to claim 1, wherein the plugs include a first insulating layer and the material layer, and Wherein a position of a top surface of the material layer is equal to a position of a top surface of the plugs.

10. A memory device, comprising: A stacked structure including at least one first select line adjacent to a bit line, at least one second select line adjacent to a source line, and word lines between the at least one first select line and the at least one second select line; Vertical holes vertically penetrating the stacked structure; And A memory layer, a channel layer, and plugs sequentially formed along an inner surface of the vertical holes, Wherein the plugs include a material layer having a fixed negative charge, and Wherein a bottom surface of the material layer is located between a bottom surface of a lowermost first select line among the at least one first select lines and a top surface of an uppermost first select line among the at least one first select lines.

11. The memory device according to claim 10, wherein the material layer includes an Al2O3 layer.

12. The memory device according to claim 10, wherein the plugs include: A first insulating layer; The material layer formed on the first insulating layer; And A capping pattern formed on the material layer.

13. The memory device according to claim 12, wherein the capping pattern includes doped silicon.

14. The memory device according to claim 10, wherein the plugs include a first insulating layer, the material layer, and a second insulating layer, and Wherein the material layer is disposed between the first insulating layer and the second insulating layer.

15. The memory device according to claim 14, wherein a top surface of the material layer is above a top surface of the uppermost one of the at least one first select line.

16. The memory device according to claim 10, wherein the plug includes a first insulating layer and the material layer, and wherein a position of the top surface of the material layer is equal to a position of the top surface of the plug.

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