3D memory device and method of manufacturing the same

Abstract

The application discloses a 3D memory device and a manufacturing method thereof. The method comprises: forming an insulating stack on a substrate, the insulating stack comprising a plurality of sacrificial layers and a plurality of interlayer insulating layers alternately stacked; removing the plurality of sacrificial layers to form sacrificial gaps; replacing the plurality of interlayer insulating layers with a plurality of insulating stress layers; and forming a gate conductor layer in the sacrificial gaps, the stress of the insulating stress layers being less than that of the interlayer insulating layers. By performing steam annealing treatment on the interlayer insulating layers to obtain the insulating stress layers with less stress and replacing the interlayer insulating layers, the warping of the wafer along a first direction (for example, the X direction) can be adjusted, so that the warping of the 3D memory device in the intermediate device at each stage does not exceed the limit value of the machine.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor device manufacturing, and more particularly, to a 3D memory device and a manufacturing method thereof. BACKGROUND

[0002] The improvement of the storage density of a memory device is closely related to the progress of semiconductor manufacturing process. As the feature size of the semiconductor manufacturing process becomes smaller and smaller, the storage density of the memory device becomes higher and higher. In order to further improve the storage density, a memory device of three-dimensional structure (i.e., 3D memory device) has been developed. The 3D memory device includes a plurality of memory cells stacked along a vertical direction, which can multiply the integration in a unit area of wafer and can reduce the cost.

[0003] With the increase of the number of stacked layers, the flatness of the wafer increases in the preparation process of the 3D memory device. When the bow value of the wafer exceeds the bow limit value of the machine used in a certain process, the intermediate device in the current process will be damaged, thereby increasing the cost of preparing the memory device.

[0004] It is desirable to further improve the structure of the 3D memory device and the manufacturing method thereof to reduce the probability of damage of the memory device in the process. SUMMARY

[0005] The purpose of the present application is to provide an improved 3D memory device and a manufacturing method thereof, in which the curvature of the wafer is flexibly adjusted by reducing the stress of the interlayer insulating layer to reduce the probability of damage of the intermediate device in the preparation process of the memory device.

[0006] According to an aspect of the present application, a manufacturing method of a 3D memory device is provided, comprising: forming an insulating stack on a substrate, the insulating stack comprising a plurality of sacrificial layers and a plurality of interlayer insulating layers alternately stacked;

[0007] removing the plurality of sacrificial layers to form sacrificial gaps;

[0008] replacing the plurality of interlayer insulating layers with a plurality of insulating stress layers;

[0009] forming a plurality of gate conductor layers in the sacrificial gaps,

[0010] wherein the stress of the insulating stress layer is smaller than the stress of the interlayer insulating layer.

[0011] Optionally, the step of replacing the plurality of interlayer insulating layers with a plurality of insulating stress layers comprises:

[0012] passing hydrogen and oxygen into the sacrificial gaps and performing a steam annealing treatment to combine the ions diffused into the interlayer insulating layer with the dangling bonds in the interlayer insulating layer to form silicon-oxygen bonds or hydrogen-oxygen-silicon bonds.

[0013] Optionally, the step of performing the steam annealing treatment with hydrogen and oxygen comprises:

[0014] continuously supplying the preset proportion of hydrogen and oxygen for a first preset time to perform the steam annealing treatment when heated to a first preset temperature.

[0015] Optionally, the step of performing the steam annealing treatment with hydrogen and oxygen comprises:

[0016] continuously supplying the preset proportion of hydrogen and oxygen for a second preset time to perform the steam annealing treatment when heated to a second preset temperature; and

[0017] continuously supplying the preset proportion of hydrogen and oxygen for a third preset time to perform the steam annealing treatment when heated to a third preset temperature,

[0018] wherein the third preset temperature is higher than the second preset temperature.

[0019] Optionally, the step of performing the steam annealing treatment with hydrogen and oxygen comprises:

[0020] continuously supplying the preset proportion of hydrogen and oxygen to perform the steam annealing treatment during a process in which a fourth preset temperature decreases to a fifth preset temperature.

[0021] Optionally, the steam annealing treatment is repeated at least twice.

[0022] Optionally, the step of removing the plurality of sacrificial layers to form the sacrificial gaps comprises:

[0023] forming gate line gaps through the insulating stack structure to reach the substrate; and

[0024] removing the plurality of sacrificial layers along the gate line gaps to form sacrificial gaps in communication with the gate line gaps.

[0025] Optionally, the step of forming the gate conductor layer in the sacrificial gaps further comprises:

[0026] forming a barrier layer on the exposed surface of the interlayer insulating layer and the exposed substrate surface; and

[0027] forming an adhesion layer on the surface of the barrier layer in the sacrificial gaps.

[0028] Optionally, the barrier layer is a high-dielectric aluminum trioxide layer, and / or the adhesion layer is a titanium silicide layer or a titanium nitride layer.

[0029] According to another aspect of the present application, a 3D memory device is provided, comprising:

[0030] a substrate;

[0031] a gate stack on the substrate surface, comprising a plurality of insulating stress layers and a plurality of gate conductor layers stacked alternately.

[0032] The manufacturing method of the 3D memory device provided by the embodiment of the present application replaces the interlayer insulating layer with an insulating stress layer with less stress by performing steam annealing on the interlayer insulating layer, and then adjusts the bow of the wafer along the first direction (for example, the X direction) so that the bow of the intermediate device at each stage does not exceed the bow limit value of the machine used at the current stage.

[0033] Further, hydrogen and oxygen are introduced into the sacrificial gap and steam annealing is performed so that the ions diffused into the interlayer insulating layer combine with the dangling bonds in the interlayer insulating layer to form silicon-oxygen bonds or hydrogen-oxygen-silicon bonds, and the number of disordered atoms in the interlayer insulating layer is increased, so that the bow value of the wafer is adjusted to be within the limit value of the bow of the machine. Further, the bow value of the wafer is flexibly adjusted, and the probability of damage to the intermediate device of the memory device during preparation is reduced. Moreover, the wafer after adjustment has a larger window in subsequent processes. BRIEF DESCRIPTION OF DRAWINGS

[0034] The above and other objects, features and advantages of the present application will become more apparent from the following description of the embodiments of the present application taken with reference to the accompanying drawings.

[0035] Figure 1 A flowchart of a manufacturing method of a 3D memory device according to an embodiment of the present application is shown.

[0036] Figures 2a to 2g Cross-sectional views of various stages of a manufacturing method of a 3D memory device according to an embodiment of the present application are shown.

[0037] Figure 3a A flowchart of a manufacturing method of a 3D memory device according to an embodiment of the present application is shown. Figure 2e A schematic diagram of a flowchart of preparation; Figure 3b A schematic diagram of a flowchart of preparation; Figure 2e Another schematic diagram of a flowchart of preparation; Figure 3c A schematic diagram of a flowchart of preparation; Figure 2e Still another schematic diagram of a flowchart of preparation.

[0038] Figure 4 A waveform diagram of the X-bow of various stages of a manufacturing method of a 3D memory device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0039] The present application will be described in more detail with reference to the drawings. Like elements in the various drawings are denoted by like reference numerals. Each portion in the drawings is not drawn to scale for the sake of clarity. Further, certain known elements can not be shown. For the sake of simplicity, a semiconductor structure obtained after several steps can be described in one figure.

[0040] It should be understood that when a layer, a region is referred to as being "on" or "above" another layer, another region, it can be directly on the other layer, the other region or intervening layers or regions can also be present. Also, the layer, the region can be "under" or "below" the other layer, the other region if the device is turned over.

[0041] Many specific details of the application are described below in order to provide a thorough understanding of the present application. However, as will be understood by one skilled in the art, the present application can be practiced without incorporating these specific details.

[0042] The 3D memory device and the manufacturing method thereof provided in the present application are 3D NAND, and mainly a 3D NAND semiconductor device is prepared. In order to avoid confusion, the intermediate structure formed at each stage in the process of preparing the final product is referred to as "intermediate device". The term "intermediate device" refers to the collective term of the entire semiconductor structure formed at each stage in the manufacture of the memory device, including all layers or regions that have been formed.

[0043] The preparation of the 3D memory device requires the combination of multiple step processes. In the actual preparation process, as the number of stacked layers increases, the bow value of the wafer continuously increases. Among them, in the process of replacing the insulating layer stack in the intermediate device with a gate stack, the bow value of the intermediate structure obtained after each process step is likely to exceed the limit value of the machine used in the next process step. Therefore, the inventors propose the manufacturing method of the 3D memory device of the present application, so that the curvature of the intermediate device at each stage of the 3D memory device does not exceed the limit value of the machine used in the process flow.

[0044] The inventors of the present application have noticed the above-mentioned problems affecting the yield of the 3D memory device, and therefore propose a further improved 3D memory device and a manufacturing method thereof.

[0045] The present application can be presented in various forms, some examples of which will be described below.

[0046] Figure 1 A flowchart showing the manufacturing method of a 3D memory device according to an embodiment of the present application is shown. Figures 2a to 2gCross-sectional views are shown of various stages of a 3D storage device manufacturing method according to an embodiment of the present invention. Figure 3a Show Figure 2e A schematic diagram of a process preparation. Figure 3b Show Figure 2e Another schematic diagram of the intermediate process preparation. Figure 3c Show Figure 2e Another schematic diagram of the process preparation.

[0047] like Figure 1 As shown, the 3D storage device manufacturing method includes the following steps:

[0048] Step S100: An insulating stack comprising alternatingly stacked sacrificial layers and multiple interlayer insulating layers is formed on the substrate. Specifically, as shown in Figure S100... Figure 2a As shown, an insulating stack structure 110 is formed on a substrate 101 by alternating stacks of interlayer insulating layers 111 and sacrificial layers 112, and a channel pillar 120 is formed through the insulating stack structure 110. The sacrificial layer 112 is replaced with a conductive layer in a subsequent step to form a gate stack. In this embodiment, the substrate 101 is, for example, a single-crystal silicon substrate, the interlayer insulating layer 111 is, for example, an oxide film layer, and the sacrificial layer 112 is, for example, a nitride film layer. Further, the interlayer insulating layer 111 is a silicon oxide layer, and the sacrificial layer 112 is a silicon nitride layer. The above insulating stack is a nitrogen-oxygen stack, but the sacrificial layer 112 and the interlayer insulating layer 111 in this application can be formed from other material layers. For clarity, Figure 2a The internal structure of the channel post 110 is not shown. In the middle portion of the channel post 110, the channel post 110 includes, for example, a channel layer, a tunneling dielectric layer, a charge storage layer, and a barrier dielectric layer stacked sequentially. At both ends of the channel post 110, the channel post 110 includes, for example, a channel layer and a barrier dielectric layer stacked sequentially.

[0049] Step S200: Remove multiple sacrificial layers to form sacrificial slots. Further, the step of forming sacrificial slots 132 includes: forming gate line slots 131 through the insulating stack 110 to reach the substrate 101; and removing multiple sacrificial layers along the gate line slots 131 to form multiple sacrificial slots 132 communicating with the gate line slots 131. Specifically, as... Figure 2b As shown, for example, Figure 2aAnisotropic etching is performed to form gate line trenches 131 in the insulating stack 110. In one embodiment, the anisotropic etching is controlled to stop near the surface of the substrate 101. In other embodiments, ion implantation is performed through the gate line trenches 131 to form N-type (using N-type dopants such as P, As) or P-type (using P-type dopants such as B) doped regions (not shown) in the substrate 101. The doped regions act as contact regions for the subsequently formed conductive channels (formed by filling the gate line trenches 131 with a conductive layer) to the substrate 101 to reduce contact resistance. Further, the gate line trenches 131 can be used to divide the gate conductor into multiple gate lines and to form conductive channels to the source. Further, the gate line trenches 131 extend through the insulating stack 110 to the doped regions in the semiconductor substrate 101. Figure 2b Only one gate line trench 131 is shown by way of example, but embodiments of the application are not limited in this regard. Further, the process can include, for example, an anneal of the gate line trenches 131 prior to forming the sacrificial trenches 132. Next, as shown in FIG. 2B, the sacrificial layer 112 in the insulating stack 110 is removed along the gate line trenches 131 to form sacrificial trenches 132 in communication with the gate line trenches 131. In one embodiment, the sacrificial layer 112 is removed by isotropic etching. In other embodiments, the sacrificial layer 112 is removed by selective wet etching or vapor phase etching. In wet etching, an etching solution is used as the etchant, in which the intermediate structure shown in FIG. 2A is immersed. In vapor phase etching, an etching gas is used as the etchant, in which the intermediate structure shown in FIG. 2A is exposed to the etching gas. Figure 2c In one embodiment, the sacrificial layer 112 is removed by isotropic etching. In other embodiments, the sacrificial layer 112 is removed by selective wet etching or vapor phase etching. In wet etching, an etching solution is used as the etchant, in which the intermediate structure shown in FIG. 2A is immersed. In vapor phase etching, an etching gas is used as the etchant, in which the intermediate structure shown in FIG. 2A is exposed to the etching gas. Figure 2b In one embodiment, the sacrificial layer 112 is removed by isotropic etching. In other embodiments, the sacrificial layer 112 is removed by selective wet etching or vapor phase etching. In wet etching, an etching solution is used as the etchant, in which the intermediate structure shown in FIG. 2A is immersed. In vapor phase etching, an etching gas is used as the etchant, in which the intermediate structure shown in FIG. 2A is exposed to the etching gas. Figure 2b In one embodiment, the sacrificial layer 112 is removed by isotropic etching. In other embodiments, the sacrificial layer 112 is removed by selective wet etching or vapor phase etching. In wet etching, an etching solution is used as the etchant, in which the intermediate structure shown in FIG. 2A is immersed. In vapor phase etching, an etching gas is used as the etchant, in which the intermediate structure shown in FIG. 2A is exposed to the etching gas.

[0050] Step S300: Replace multiple interlayer insulating layers with insulating stress layers. This step reduces the stress of the interlayer insulating layers 111 in the insulating stack 110 to obtain an insulating stress layer 151, thereby adjusting the wafer curvature value of the intermediate device. Further, this step involves introducing hydrogen and oxygen into the sacrificial gap 132 and performing steam annealing to allow oxygen and hydroxide ions diffusing into the interlayer insulating layer 111 to combine with dangling bonds in the interlayer insulating layer 111 to form silicon-oxygen bonds or hydroxy-silicon bonds, thereby reducing the stress of the interlayer insulating layer 111.

[0051] Furthermore, since the change in the curvature value of the intermediate device wafer along the Y direction is within approximately 50 micrometers during the process from the formation of the sacrificial gap 132 to the formation of the gate stack 160, while the change in the curvature value along the X direction is larger and may exceed the limit of the curvature value acceptable to the equipment in a certain process stage, it can be determined whether to adjust the current curvature value of the intermediate device by introducing hydrogen and oxygen into the sacrificial gap 132 and performing steam annealing before proceeding to the next process flow, based on the current curvature value of the intermediate device. This allows the intermediate device to be placed in the equipment in the next process without damage to perform the corresponding process steps.

[0052] Specifically, such as Figure 2d As shown, for example, atomic layer deposition (ALD) is used to form a barrier layer 141 on the exposed surface of the interlayer insulating layer 111, on the exposed surface of the substrate 101 via the sacrificial gap 131, and on the surface of the interlayer insulating layer 111 on top of the insulating stack. Further, the barrier layer 141 is made of a high-dielectric metal compound, such as an aluminum oxide layer. In other embodiments, the film thickness of the barrier layer 141 is, for example, less than or equal to 2.7 nm.

[0053] Then as Figure 2e As shown, towards Figure 2d Hydrogen and oxygen are introduced into the surface of the intermediate device for steam annealing. The hydrogen and oxygen diffuse through the gate gap 131 and the sacrificial gap 132 connected thereto into the interlayer insulating layer 111. This causes the ions diffused into the interlayer insulating layer 111 to combine with the dangling bonds in the interlayer insulating layer 111 to form silicon-oxygen bonds or hydrogen-oxygen-silicon bonds, increasing the number of disordered atoms in the interlayer insulating layer 111. After this process, the stress in the interlayer insulating layer decreases to form an insulating stress layer 151. This, in turn, allows the wafer curvature value to be controlled within the limits of the equipment. Furthermore, as... Figure 3a As shown, for example, when the temperature of the reaction environment is heated to a first preset temperature T1, hydrogen and oxygen in a preset ratio are continuously introduced within a first preset time t1 to react with the above-mentioned... Figure 2dThe intermediate device shown is subjected to a vapor annealing process. In this embodiment, the first preset temperature T1 is about 750 °C, for example, the first preset time t1 is about 30 minutes, and the preset ratio of hydrogen and oxygen is 5:7, for example. In other embodiments, as shown in Figure 3b As shown, for example, when the temperature of the reaction environment is heated to the second preset temperature T2, the preset ratio of hydrogen and oxygen is continuously introduced for the second preset time t2 to continue the vapor annealing process of the above-mentioned Figure 2d The intermediate device shown is subjected to a vapor annealing process. Then, when the temperature of the reaction environment is heated to the third preset temperature T3, the preset ratio of hydrogen and oxygen is continuously introduced for the third preset time t3 to continue the vapor annealing process of the above-mentioned intermediate device. In this embodiment, the third preset temperature T3 is higher than the second preset temperature T2. Further, the second preset temperature T2 is about 700 °C, for example, the third preset temperature T3 is about 750 °C, for example, the second preset time t2 and the third preset time t3 are both about 20 minutes, for example, and the preset ratio of hydrogen and oxygen is 5:7, for example. In other embodiments, as shown in Figure 3c As shown, during the process of reducing the temperature of the reaction environment from the fourth preset temperature T4 to the fifth preset temperature T5, the preset ratio of hydrogen and oxygen is continuously introduced to continue the vapor annealing process of the above-mentioned Figure 2d The intermediate device shown is subjected to a vapor annealing process. Further, the above-mentioned vapor annealing process is repeated at least twice. In this embodiment, the above-mentioned vapor annealing process is repeated three times, for example, wherein the fourth preset temperature T4 is about 800 °C, for example, the fifth preset temperature T5 is about 750 °C, for example, and the preset ratio of hydrogen and oxygen is 5:7, for example. The vapor annealing process in the cooling stage can make the surface of the intermediate device more uniform in heating.

[0054] Then, as shown in Figure 2f As shown, for example, an adhesion layer 142 is formed on the exposed surface of the partial barrier layer 141 by using an atomic layer deposition (ALD) process. Further, the adhesion layer 142 is a titanium silicide layer or a titanium nitride layer, for example.

[0055] Step S400: Forming a plurality of gate conductor layers in the sacrificial gap. Specifically, as shown in Figure 2gAs shown, a metal layer is filled in the gate line slit 131 and the sacrificial slit 132 via the gate line slit 131 and the sacrificial slit 132 as a deposition passage by an atomic layer deposition (ALD) process. Further, the metal layer is composed of, for example, tungsten. A precursor gas used in the atomic layer deposition is, for example, tungsten hexafluoride WF6, and a reducing gas is, for example, silane SiH4or diborane B2H6. In the above-mentioned atomic layer deposition step, the deposition process is achieved by using the chemical adsorption of the reaction product of tungsten hexafluoride WF6and silane SiH4. Next, a photoresist mask is formed on the surface of the above-mentioned intermediate device, and then an etchback is performed using fluorinated sulfur, nitrogen and chlorine as etchants to remove the tungsten material in the gate line slit 131. Further, the metal layer remaining in the sacrificial slit 132 serves as a gate conductor layer 143 of a different level. Where the gate conductor layer 143 is formed on the surface of the adhesion layer 142, the chemical adsorption property of the precursor gas on the surface during the atomic layer deposition can be improved, and the adhesion strength of the gate conductor layer 143 on the insulating stress layer 151 can be improved.

[0056] It should be noted that in the present embodiment, the above-mentioned steam annealing treatment is performed on the intermediate device after the formation of the barrier layer 141, for example, to reduce the stress of the interlayer insulating layer and to adjust the bending value of the intermediate device. However, the implementation of the present application is not limited thereto, and whether to perform the above-mentioned steam annealing treatment at the moment can be determined based on the bending value of the intermediate device in actual application. That is, the sequential steam annealing treatment can be performed, for example, without being limited to before the formation of the gate stack.

[0057] Figure 4 A waveform diagram of X-bow showing each stage of the method for manufacturing a 3D memory device according to an embodiment of the present application.

[0058] As Figure 4As shown, the waveform L1 shows the first limit threshold of the X-bow value of the X direction of the intermediate device at each step of the process steps S1-Sn for preparing the 3D memory device, and the waveform L2 shows the second limit threshold of the X-bow value of the X direction of the intermediate device at each step of the process steps S1-Sn for preparing the 3D memory device. The waveform L3 is the X-bow value of the X direction of the intermediate device at the process steps S1-Sn when the 3D memory device is prepared by using the prior art, and it can be seen that the X-bow value of the X direction of the wafer in the prior art exceeds the limit threshold interval at some process stages, and the wafer can be damaged in the preparation process. The waveform L4 is the X-bow value of the X direction of the intermediate device at the process steps S1-Sn when the 3D memory device is prepared by using the manufacturing method provided in the present application, and by flexibly controlling the bow value of the wafer, the probability of damage of the intermediate device of the 3D memory device in the preparation process is reduced. And the wafer after regulation has a larger window in the subsequent process.

[0059] The present application also provides a 3D memory device, comprising a substrate and a gate stack, the gate stack is located on the surface of the substrate and comprises a plurality of insulating stress layers and a plurality of gate conductor layers which are alternately stacked. The 3D memory device is prepared by using the manufacturing method described above, for example.

[0060] In the above description, the patterning, etching and other technical details of each layer are not described in detail. However, those skilled in the art should understand that the layers, regions and the like with the required shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0061] The embodiments of the present application are described above. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present application. The scope of the present application is defined by the appended claims and their equivalents. Without departing from the scope of the present application, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present application.

Claims

1. A method for manufacturing a 3D storage device, wherein, include: An insulating stack is formed on a substrate, the insulating stack comprising a plurality of sacrificial layers and a plurality of interlayer insulating layers stacked alternately; Remove the plurality of sacrificial layers to form sacrificial gaps; The plurality of interlayer insulation layers are replaced with a plurality of insulating stress layers; Multiple gate conductor layers are formed in the sacrificial gap. Wherein, the stress of the insulating stress layer is less than the stress of the interlayer insulating layer, and the step of replacing the plurality of interlayer insulating layers with the plurality of insulating stress layers includes: Hydrogen and oxygen are introduced into the sacrificial gap and steam annealing is performed to allow ions that diffuse into the interlayer insulation layer to combine with the dangling bonds in the interlayer insulation layer to form silicon-oxygen bonds or hydrogen-oxygen-silicon bonds.

2. The method for manufacturing a 3D storage device according to claim 1, wherein, The steps for steam annealing with hydrogen and oxygen include: When heated to a first preset temperature, hydrogen and oxygen in a preset ratio are continuously introduced for a first preset time to perform steam annealing.

3. The method for manufacturing a 3D storage device according to claim 1, wherein, The steps for steam annealing with hydrogen and oxygen include: While heating to a second preset temperature, a preset ratio of hydrogen and oxygen is continuously introduced for a second preset time to perform steam annealing; and When heated to a third preset temperature, hydrogen and oxygen in a preset ratio are continuously introduced for a third preset time to perform steam annealing. The third preset temperature is higher than the second preset temperature.

4. The method for manufacturing a 3D storage device according to claim 1, wherein, The steps for steam annealing with hydrogen and oxygen include: During the process of cooling from the fourth preset temperature to the fifth preset temperature, hydrogen and oxygen in a preset ratio are continuously introduced to perform steam annealing.

5. The method for manufacturing a 3D storage device according to claim 4, wherein, The steam annealing process shall be repeated at least twice.

6. The method for manufacturing a 3D storage device according to claim 1, wherein, The step of removing the plurality of sacrificial layers to form sacrificial gaps includes: Forming gate line gaps that penetrate the insulating stack structure to reach the substrate; and The plurality of sacrificial layers are removed along the grid line gaps to form sacrificial gaps that communicate with the grid line gaps.

7. The method for manufacturing a 3D storage device according to claim 1, wherein, The method further includes, prior to the step of forming the gate conductor layer in the sacrificial gap: A barrier layer is formed on the exposed surface of the interlayer insulating layer and on the exposed surface of the substrate; and An adhesive layer is formed on the surface of the barrier layer in the sacrificial gap.

8. The method for manufacturing a 3D storage device according to claim 7, wherein, The barrier layer is a high-dielectric aluminum oxide layer, and / or the adhesion layer is a titanium silicide layer or a titanium nitride layer.

9. A 3D storage device, wherein, Prepared using the manufacturing method of any one of claims 1-8, comprising: Substrate; A gate stack, located on the surface of the substrate, comprises multiple alternately stacked insulating stress layers and multiple gate conductor layers.

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