Perovskite / silicon tandem solar cell and preparation method thereof

Abstract

This invention relates to a method for fabricating a perovskite / silicon tandem solar cell. The method involves stacking perovskite cells in series on top of silicon cells via an intermediate connecting structure. Based on the current of the perovskite cells or the current of the silicon cells without backscattered light, the current of either the silicon cells without backscattered light or the perovskite cells is adjusted so that the current of the perovskite cells is greater than the current of the silicon cells without backscattered light. The objective of this invention is to provide a perovskite / silicon tandem solar cell and its fabrication method. By adjusting the currents of the perovskite and silicon cells, the current of the perovskite cells is made higher than the current of the silicon cells, thereby utilizing the efficiency gain of bifacial power generation from the bottom cells to improve the conversion efficiency and actual power generation of the tandem solar cell.

Description

Technical Field

[0001] This invention belongs to the field of solar cells, specifically relating to a perovskite / silicon tandem solar cell and its preparation method. Background Technology

[0002] Because the solar spectrum has a wide energy distribution, existing single-junction solar cells are limited by the band gap of their absorber layer materials, allowing them to absorb only a portion of solar photons and thus failing to maximize the utilization of the solar spectrum. The absorbed sunlight is converted into electrical energy through the photovoltaic effect, while sunlight outside the band gap of the absorber layer material is absorbed by the back electrode metal and converted into heat energy or causes the material itself to heat up, failing to become effective electrical energy. Therefore, the theoretical conversion efficiency of single-junction solar cells is generally low, and existing single-junction photovoltaic technology is reaching its limit, struggling to overcome the 28% conversion efficiency threshold. Further breakthroughs require the use of double- or even triple-layer structures.

[0003] The solar spectrum can be divided into several continuous parts. Cells made of materials with band widths that are optimally matched to these parts are stacked from the outside in in order of decreasing band gap. This allows the shortest wavelength light to be utilized by the outermost wide-bandgap material of the top cell, while longer wavelength light can be transmitted to the bottom cell with narrower band gap materials. This maximizes the conversion of light energy into electrical energy. Such a cell structure is called a stacked cell, which can greatly improve performance and stability. Summary of the Invention

[0004] The purpose of this invention is to provide a perovskite / silicon tandem solar cell and its preparation method. By adjusting the current of the perovskite cell and the silicon cell, the current of the perovskite cell is made higher than that of the silicon cell, thereby utilizing the efficiency gain of bifacial power generation of the bottom cell to improve the conversion efficiency and actual power generation of the tandem cell.

[0005] The objective of this invention is achieved through the following technical solution:

[0006] A perovskite / silicon tandem solar cell includes a silicon cell, a perovskite cell disposed above the silicon cell and having a current greater than the silicon cell's backscattered light current, and an intermediate connection structure connecting the perovskite cell and the silicon cell.

[0007] A method for fabricating a perovskite / silicon tandem solar cell involves stacking perovskite cells in series above a silicon cell via an intermediate connecting structure; adjusting the current of the silicon cell without backscattered light or the current of the perovskite cell without backscattered light, based on the current of the perovskite cell or the current of the silicon cell without backscattered light, so that the current of the perovskite cell is greater than the current of the silicon cell without backscattered light.

[0008] Compared with the prior art, the advantages of the present invention are as follows:

[0009] 1. This invention, based on the additive effect of back-reflected light on current in silicon cells, improves the actual photoelectric conversion efficiency by adjusting the current of perovskite cells and silicon cells so that the current of perovskite cells is higher than that of silicon cells.

[0010] 2. By using a current regulation design for both perovskite and silicon cells, current from the silicon cell is prevented from being injected into the perovskite cell, thus avoiding the stability degradation of the perovskite cell caused by high current and improving the stability of the tandem cell. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of an embodiment of a stacked solar cell of the present invention.

[0012] Figure 2 This is a schematic diagram of an embodiment of a stacked solar cell of the present invention.

[0013] Figure 3 This is a schematic diagram of an embodiment of a stacked solar cell of the present invention.

[0014] Figure 4 This is a schematic diagram of an embodiment of a stacked solar cell of the present invention.

[0015] Figure 5 This is a schematic diagram of an embodiment of a stacked solar cell of the present invention. Detailed Implementation

[0016] A perovskite / silicon tandem solar cell includes a silicon cell, a perovskite cell disposed above the silicon cell and having a current greater than the silicon cell's backscattered light current, and an intermediate connection structure connecting the perovskite cell and the silicon cell.

[0017] The intermediate connection structure is a transparent conductive film layer, a microcrystalline silicon thin film layer, or a polycrystalline silicon thin film layer. The intermediate connection structure can be an ITO layer, a NiO layer, an N-type hydrogenated oxygen-containing microcrystalline silicon (μc-SiOx:H) layer, or a P-type hydrogenated oxygen-containing microcrystalline silicon (μc-SiOx:H) layer.

[0018] The silicon cell is a bifacial silicon cell, which is a structure that combines one or more of the following: silicon heterojunction cell, TOPCon cell, and PERC cell.

[0019] The silicon heterojunction solar cell comprises, from top to bottom, a P-type or N-type doped silicon-based thin film, an intrinsic amorphous silicon thin film, a silicon wafer, an intrinsic amorphous silicon thin film, a P-type doped amorphous silicon thin film, a transparent conductive thin film, and a metal electrode; or, the silicon heterojunction solar cell comprises, from top to bottom, a transparent conductive layer, an N-type doped silicon-based thin film, an intrinsic amorphous silicon thin film, a silicon wafer, an intrinsic amorphous silicon thin film, a P-type doped amorphous silicon thin film, a transparent conductive thin film, and a metal electrode.

[0020] The TOPCon cell comprises, from top to bottom, a P-type polycrystalline silicon thin film layer, an N-type polycrystalline silicon thin film layer, a silicon oxide passivation layer, a monocrystalline silicon wafer, a silicon oxide passivation layer, a P-type polycrystalline silicon thin film layer, a SiNx passivation layer, and a metal electrode, stacked sequentially; or, the TOPCon cell comprises, from top to bottom, a transparent conductive layer, an N-type polycrystalline silicon thin film layer, a silicon oxide passivation layer, a monocrystalline silicon wafer, a silicon oxide passivation layer, a P-type polycrystalline silicon thin film layer, a SiNx passivation layer, and a metal electrode, stacked sequentially; or, the TOPCon cell comprises, from top to bottom, a P-type polycrystalline silicon thin film layer, an N-type polycrystalline silicon thin film layer, a silicon oxide passivation layer, a monocrystalline silicon wafer, an aluminum oxide passivation layer, a SiNx passivation layer, and a metal electrode, stacked sequentially; or, the TOPCon cell comprises, from top to bottom, a transparent conductive layer, an N-type polycrystalline silicon thin film layer, a silicon oxide passivation layer, a monocrystalline silicon wafer, an aluminum oxide passivation layer, a SiNx passivation layer, and a metal electrode, stacked sequentially.

[0021] The PERC cell comprises, from top to bottom, a transparent conductive layer, an N-type emitter junction layer, a P-type monocrystalline silicon wafer, an aluminum oxide passivation layer, a SiNx passivation layer, and a metal electrode; or, the PERC cell comprises, from top to bottom, a P-type polycrystalline silicon layer, an N-type emitter junction layer, a P-type monocrystalline silicon wafer, an aluminum oxide passivation layer, a SiNx passivation layer, and a metal electrode.

[0022] The PERC and TOPCon fused solar cell includes, from top to bottom, an N-type emitter junction layer, a monocrystalline silicon wafer, a silicon oxide passivation layer, a P-type polycrystalline silicon thin film layer, a SiNx passivation layer, and a metal electrode; or, the PERC and TOPCon fused solar cell includes, from top to bottom, a P-type polycrystalline silicon layer, an N-type emitter junction layer, a monocrystalline silicon wafer, a silicon oxide passivation layer, a P-type polycrystalline silicon thin film layer, a SiNx passivation layer, and a metal electrode.

[0023] The perovskite solar cell is a perovskite solar cell whose current is no more than 20% higher than that of a silicon solar cell without backscattering light current.

[0024] The perovskite solar cell includes a perovskite absorber layer with an optical bandgap of 1.60 eV-1.80 eV.

[0025] The thickness of the perovskite absorber layer is 300-1000 nm, and its composition is MA. (1-x-y) FA x Cs y PbI (3-3x) Br 3y (0≤x,y≤1) perovskite layer.

[0026] The perovskite solar cell adopts a PIN structure, which includes a metal electrode, a transparent conductive layer, an electron transport layer, a perovskite absorption layer, and a hole transport layer stacked from top to bottom.

[0027] A method for fabricating a perovskite / silicon tandem solar cell involves stacking perovskite cells in series above a silicon cell via an intermediate connecting structure; adjusting the current of the silicon cell without backscattered light or the current of the perovskite cell without backscattered light, based on the current of the perovskite cell or the current of the silicon cell without backscattered light, so that the current of the perovskite cell is greater than the current of the silicon cell without backscattered light.

[0028] The current of the perovskite solar cell is no more than 20% higher than that of the silicon solar cell without backscattering.

[0029] The fabrication of the perovskite solar cell includes the fabrication of a perovskite absorber layer, the composition of which is MA. (1-x-y) FA x Cs y PbI (3-3x) Br 3y (0≤x,y≤1), by adjusting the composition ratio of MA, FA and Cs, and the composition ratio of I and Br, the optical band gap of the perovskite layer is changed to 1.60eV-1.80eV.

[0030] The fabrication process of the perovskite absorber layer is as follows: a perovskite layer is coated on the surface of the perovskite absorber layer to be fabricated using slit coating technology, and then annealed and dried at 100-200℃ for 10-60 minutes to form a perovskite layer with a thickness of 300-1000nm; or, a perovskite layer is fabricated on the surface of the perovskite absorber layer to be fabricated using a combination of vacuum evaporation and slit coating, and then annealed and crystallized at 100-200℃ for 10-60 minutes to form a perovskite layer with a thickness of 300-1000nm.

[0031] like Figure 1 The perovskite / silicon tandem solar cell shown comprises, from bottom to top, a metal grid electrode 106, an ITO transparent conductive film layer 006, a P-type amorphous silicon layer 005, an intrinsic amorphous silicon layer 004, an N-type monocrystalline silicon wafer 001, an intrinsic amorphous silicon layer 002, an N-type microcrystalline silicon oxide layer 003, a P-type microcrystalline silicon oxide layer 007, a hole transport layer 101, a perovskite absorber layer 102, an electron transport layer 103, a transparent conductive film layer 104, and a metal grid electrode 105. The specific steps of its fabrication method include:

[0032] a. The silicon heterojunction solar cell uses an N-type monocrystalline silicon wafer 001, and a double-sided texturing structure is formed on the surface of the N-type monocrystalline silicon wafer 001 after texturing and cleaning.

[0033] b. After the treatment in step a, an intrinsic amorphous silicon layer 002, an N-type microcrystalline silicon oxide layer 003 and a P-type microcrystalline silicon oxide layer 007 are sequentially deposited on the front side of an N-type monocrystalline silicon wafer 001 using PECVD.

[0034] c. After step b, an intrinsic amorphous silicon layer 004 and a P-type amorphous silicon layer 005 are sequentially deposited on the back side of the N-type monocrystalline silicon wafer 001.

[0035] d. After step c, an ITO transparent conductive film layer 006 is deposited on the back side of the P-type amorphous silicon layer 005 by magnetron sputtering;

[0036] e. After step d, an organic hole transport layer 101 is prepared on the P-type microcrystalline silicon oxide layer 007 by vacuum evaporation; or, after step d, an inorganic hole transport layer 101 is prepared on the P-type microcrystalline silicon oxide layer by physical deposition.

[0037] f. After step d, a perovskite absorption layer 102 is formed on the surface of hole transport layer 101 using slit coating technology, and then a perovskite film is formed by thermal annealing and crystallization; or, after step d, a perovskite absorption layer 102 is formed on the surface of hole transport layer 101 using a combination of vacuum evaporation and slit coating, and then a perovskite film is formed by annealing and crystallization.

[0038] g. After step f, an electron transport layer 103 is prepared on the perovskite absorber layer 102 using vapor deposition technology;

[0039] h. After step g, an ITO transparent conductive film layer 104 is prepared on the surface of the electron transport layer 103 using magnetron sputtering; or, after step g, a transparent conductive film layer 104 is prepared on the surface of the electron transport layer 103 using atomic layer deposition and magnetron sputtering; or, after step g, a transparent conductive film layer 104 is prepared on the surface of the electron transport layer 103 using reactive ion deposition.

[0040] i. After step h, low-temperature silver paste is printed on the surface of the transparent conductive film layer 104 to form metal grid electrodes 105 by screen printing technology. After drying, low-temperature silver paste is printed on the back of the battery to form metal grid electrodes 106, and then cured.

[0041] The intrinsic amorphous silicon layer 002, N-type amorphous silicon oxide layer 003, intrinsic amorphous silicon layer 004, and P-type amorphous silicon layer 005 have a thickness of 5-10 nm; the electron transport layer 103 has a thickness of 5-10 nm; the P-type microcrystalline silicon oxide layer 007 has a thickness of 10-30 nm; the ITO transparent conductive film layer 104 has a thickness of 80-120 nm; the organic hole transport layer 101 is Spiro-TTB with a thickness of 5-20 nm; the inorganic hole transport layer 101 is NiO with a thickness of 5-20 nm. The electron transport layer has a thickness of 5-50 nm. The electron transport layer 103 is a C60 or C60 derivative film.

[0042] like Figure 2 The perovskite / silicon tandem solar cell shown comprises, from bottom to top, a metal grid electrode 106, a SiNx passivation layer 206, a P-type doped polycrystalline silicon thin film 205, a silicon oxide passivation layer 204, an N-type or P-type monocrystalline silicon wafer 201, a silicon oxide passivation layer 202, an N-type doped polycrystalline silicon thin film 203, a transparent conductive ITO film or an N-type doped polycrystalline silicon thin film 207, a hole transport layer 101, a perovskite absorber layer 102, an electron transport layer 103, a transparent conductive film 104, and a metal grid electrode 105. The specific steps of its fabrication method include:

[0043] a. The TOPCon cell uses an N-type monocrystalline silicon wafer or a P-type monocrystalline silicon wafer 201, and a double-sided texturing structure is formed on the surface of the N-type monocrystalline silicon wafer or the P-type monocrystalline silicon wafer 201 after texturing and cleaning.

[0044] b. After the treatment in step a, silicon oxide passivation layers 202 and 204 are deposited on both sides of the N-type or P-type single crystal silicon wafer 201 by thermal oxidation.

[0045] c. After the treatment in step b, an N-type doped polycrystalline silicon thin film 203 is deposited on the silicon oxide passivation layer 202 and a P-type doped polycrystalline silicon thin film 205 is deposited on the silicon oxide passivation layer 204 using the LPCVD method.

[0046] d. After step c, SiNx passivation layer 206 is deposited on the P-type doped polycrystalline silicon thin film 205 by PECVD.

[0047] e. After step d, a transparent conductive ITO film 207 is deposited on the surface of the N-type doped polysilicon layer 203 by magnetron sputtering; or, after step d, an N-type doped polysilicon thin film 207 is deposited on the surface of the N-type doped polysilicon layer 203 by LPCVD.

[0048] f. After step e, NiOx hole transport layer 101 is prepared on transparent conductive ITO film layer or N-type doped polycrystalline silicon thin film 207 by magnetron sputtering; or, after step e, organic hole transport layer 101 is prepared on transparent conductive ITO film layer or N-type doped polycrystalline silicon thin film 207 by vacuum evaporation.

[0049] g. After step f, a perovskite absorption layer 102 is formed on the surface of hole transport layer 101 using slot coating technology, and then annealed and dried at 150°C for 15 minutes; or, after step f, a perovskite absorption layer 102 is formed on the surface of hole transport layer 101 using a combination of vacuum evaporation and slot coating, and then annealed and crystallized to form a perovskite thin film.

[0050] h. After step g, an electron transport layer 103 is prepared on the perovskite absorber layer 102 using vapor deposition technology;

[0051] i. After step h, an ITO transparent conductive film layer 104 is prepared on the surface of the electron transport layer 103 using magnetron sputtering; or, after step h, a transparent conductive film layer 104 is prepared on the surface of the electron transport layer 103 using atomic layer deposition and magnetron sputtering; or, after step h, a transparent conductive film layer 104 is prepared on the surface of the electron transport layer 103 using reactive ion deposition.

[0052] j. After step i, low-temperature silver paste is printed on the surface of the transparent conductive film layer 104 to form a metal grid electrode 105. After drying, low-temperature silver paste is printed on the back of the battery to form a metal grid electrode 106, which is then cured.

[0053] The thickness of the silicon oxide passivation layers 202 and 204 is 1-2 nm. The thickness of the P-type doped polycrystalline silicon thin film and the N-type doped polycrystalline silicon thin film is 100-300 nm. The thickness of the SiNx hole transport layer is 70-100 nm. The thickness of the NiOx hole transport layer 101 is 10-20 nm. The thickness of the organic hole transport layer 101 is 10-20 nm. The thickness of the ITO transparent conductive film layer 104 is 80-120 nm. The thickness of the electron transport layer is 5-50 nm. The electron transport layer 103 is a C60 or C60 derivative film layer, and the thickness of the C60 or C60 derivative film layer is 5-10 nm.

[0054] like Figure 3 The perovskite / silicon tandem solar cell shown comprises, from bottom to top, a metal grid electrode 106, a SiNx thin film 305, an aluminum oxide passivation layer 304, an N-type monocrystalline silicon wafer 301, a silicon oxide passivation layer 302, an N-type polycrystalline silicon layer 303, a transparent conductive ITO film or a P-type doped polycrystalline silicon film 307, a hole transport layer 101, a perovskite absorber layer 102, an electron transport layer 103, a transparent conductive film 104, and a metal grid electrode 105. The specific steps of its fabrication method include:

[0055] a. The TOPCon cell uses an N-type monocrystalline silicon wafer 301, and a double-sided texturing structure is formed on the surface of the N-type monocrystalline silicon wafer 301 after texturing and cleaning.

[0056] b. After the treatment in step a, a silicon oxide passivation layer 302 is deposited on the front side of the N-type monocrystalline silicon wafer 301 by thermal oxidation, and an aluminum oxide passivation layer 304 is deposited on the back side of the N-type monocrystalline silicon wafer 301 by atomic layer deposition.

[0057] c. After the treatment in step b, SiNx thin film 305 is deposited on the alumina passivation layer 304 using PECVD method;

[0058] d. After step c, an N-type polysilicon layer 303 is deposited on the silicon oxide passivation layer 302 using the LPCVD method;

[0059] e. After step d, a transparent conductive ITO film 307 is deposited on the surface of the N-type polysilicon layer 303 by magnetron sputtering; or, after step d, a P-type doped polysilicon film 307 is deposited on the surface of the N-type polysilicon layer 303 by LPCVD.

[0060] f. After step e, NiOx hole transport layer 101 is prepared on ITO transparent conductive film layer or P-type doped polycrystalline silicon thin film 307 by magnetron sputtering; or, after step e, organic hole transport layer 101 is prepared on ITO transparent conductive film layer or P-type doped polycrystalline silicon thin film 307 by vacuum evaporation.

[0061] g. After step f, a perovskite absorption layer 102 is formed on the surface of hole transport layer 101 using slot coating technology, and then annealed and dried at 150°C for 15 minutes; or, after step f, a perovskite absorption layer 102 is formed on the surface of hole transport layer 101 using a combination of vacuum evaporation and slot coating, and then annealed and crystallized to form a perovskite thin film.

[0062] h. After step g, an electron transport layer 103 is prepared on the perovskite absorber layer 102 using vapor deposition technology;

[0063] i. After step h, an ITO transparent conductive film layer 104 is prepared on the surface of the electron transport layer 103 using magnetron sputtering; or, after step h, a transparent conductive film layer 104 is prepared on the surface of the electron transport layer 103 using atomic layer deposition and magnetron sputtering; or, after step h, a transparent conductive film layer 104 is prepared on the surface of the electron transport layer 103 using reactive ion deposition.

[0064] j. After step i, low-temperature silver paste is printed on the surface of the transparent conductive film layer 104 to form metal grid electrodes 105 by screen printing technology. After drying, low-temperature silver paste is printed on the back of the battery to form metal grid electrodes 106, and then cured.

[0065] The silicon oxide passivation layers 302 and 304 have a thickness of 1-2 nm. The P-type doped polycrystalline silicon thin films and N-type doped polycrystalline silicon thin films have a thickness of 100-300 nm. The SiNx hole transport layer has a thickness of 70-100 nm. The electron transport layer 103 has a thickness of 10 nm. The transparent conductive ITO film has a thickness of 10-20 nm. The NiOx hole transport layer 101 has a thickness of 10-20 nm. The organic hole transport layer 101 has a thickness of 10-20 nm. The electron transport layer has a thickness of 5-50 nm. The electron transport layer 103 is a C60 or C60 derivative film, and the C60 or C60 derivative film has a thickness of 5-10 nm.

[0066] like Figure 4 The perovskite / silicon tandem solar cell shown comprises, from bottom to top, a metal grid electrode 106, a SiNx thin film 404, an alumina passivation layer 403, a P-type monocrystalline silicon wafer 401, an N-type emitter junction 402, a transparent conductive ITO film or a P-type doped polycrystalline silicon thin film 405, a hole transport layer 101, a perovskite absorber layer 102, an electron transport layer 103, a transparent conductive film 104, and a metal grid electrode 105. The specific steps of its fabrication method include:

[0067] a. The PERC cell uses a P-type monocrystalline silicon wafer 401, and a double-sided texturing structure is formed on the surface of the P-type monocrystalline silicon wafer 401 after texturing and cleaning.

[0068] b. After the process in step a, an N-type emitter junction 402 is formed on the front side of the P-type single crystal silicon wafer 401 using the thermal diffusion method;

[0069] c. After step b, an aluminum oxide passivation layer 403 is deposited on the back side of the P-type single crystal silicon wafer 401 using atomic layer deposition.

[0070] d. After step c, SiNx thin film 404 is deposited on the silicon oxide passivation layer 403 by PECVD.

[0071] e. After step d, a transparent conductive ITO film 405 is deposited on the surface of the N-type emitter junction layer 402 by magnetron sputtering; or, after step d, a P-type doped polycrystalline silicon thin film 405 is deposited on the surface of the N-type emitter junction layer 402 by LPCVD.

[0072] f. After step e, NiOx hole transport layer 101 is prepared on transparent conductive ITO film layer or P-type doped polycrystalline silicon thin film 405 by magnetron sputtering; or, after step e, organic hole transport layer 101 is prepared on ITO transparent conductive film layer or P-type doped polycrystalline silicon thin film 405 by vacuum evaporation.

[0073] g. After step f, a perovskite absorption layer 102 is formed on the surface of hole transport layer 101 using slit coating technology, and then annealed and dried; or, after step f, a perovskite absorption layer 102 is formed on the surface of hole transport layer 101 using a combination of vacuum evaporation and slit coating, and then annealed and crystallized to form a perovskite thin film.

[0074] h. After step g, an electron transport layer 103 is prepared on the perovskite absorber layer 102 using vapor deposition technology;

[0075] i. After step h, an ITO transparent conductive film layer 104 is prepared on the surface of the electron transport layer 103 using magnetron sputtering; or, after step h, a transparent conductive film layer 104 is prepared on the surface of the electron transport layer 103 using atomic layer deposition and magnetron sputtering; or, after step h, a transparent conductive film layer 104 is prepared on the surface of the electron transport layer 103 using reactive ion deposition.

[0076] j. After step i, low-temperature silver paste is printed on the surface of the transparent conductive film layer 104 to form metal grid electrodes 105 by screen printing technology. After drying, low-temperature silver paste is printed on the back of the battery to form metal grid electrodes 106, and then cured.

[0077] The thickness of the P-type doped polycrystalline silicon thin film 405 is 100-300 nm, the thickness of the N-type emitter junction layer 402 is 0.35-0.5 μm, the thickness of the SiNx thin film 404 is 70-90 nm, the thickness of the NiOx hole transport layer or organic hole transport layer is 10-20 nm, and the thickness of the transparent conductive ITO film is 10-20 nm; the electron transport layer 103 is a C60 or C60 derivative film, and the thickness of the electron transport layer is 5-50 nm.

[0078] like Figure 5 The perovskite / silicon tandem solar cell shown comprises, from bottom to top, a metal grid electrode 106, a SiNx layer 505, a P-type polycrystalline silicon thin film layer 504, a silicon oxide passivation layer 503, an N-type monocrystalline silicon wafer 501, an N-type emitter junction layer 502, a transparent conductive ITO film layer 507, a hole transport layer 101, a perovskite absorber layer 102, an electron transport layer 103, a transparent conductive film layer 104, and a metal grid electrode 105. The specific steps of its fabrication method include:

[0079] a. The PERC and TOPCon fused cell uses an N-type monocrystalline silicon wafer 501, and a double-sided texturing structure is formed on the surface of the N-type monocrystalline silicon wafer 501 after texturing and cleaning.

[0080] b. After the process in step a, an N-type emitter junction layer 502 is formed on the front side of the N-type monocrystalline silicon wafer 501 using a thermal diffusion method;

[0081] c. After step b, a silicon oxide passivation layer 503 is prepared on the back side of the N-type single crystal silicon wafer 501 by thermal oxidation.

[0082] d. After step c, a P-type polycrystalline silicon thin film layer 504 is prepared on the silicon oxide passivation layer 503 by LPCVD and thermal diffusion method;

[0083] e. After step d, a SiNx layer 505 is deposited on the P-type polycrystalline silicon thin film layer 504 using the PECVD method;

[0084] f. After step e, a transparent conductive ITO film 507 is deposited on the surface of the N-type emitter junction layer 502 by magnetron sputtering;

[0085] g. After step f, NiOx hole transport layer 101 is prepared on transparent conductive ITO film layer 507 by magnetron sputtering; or, after step e, organic hole transport layer 101 is prepared on transparent conductive ITO film layer 507 by vacuum evaporation.

[0086] h. After step g, a perovskite absorption layer 102 is formed on the surface of hole transport layer 101 using slot coating technology, and then annealed and dried at 150°C for 15 minutes; or, after step f, a perovskite absorption layer 102 is formed on the surface of hole transport layer 101 using a combination of vacuum evaporation and slot coating, and then annealed and crystallized to form a perovskite thin film.

[0087] i. After step h, an electron transport layer 103 is prepared on the perovskite absorber layer 102 using vapor deposition technology;

[0088] j. After step i, an ITO transparent conductive film layer 104 is prepared on the surface of the electron transport layer 103 using magnetron sputtering; or, after step h, a transparent conductive film layer 104 is prepared on the surface of the electron transport layer 103 using atomic layer deposition and magnetron sputtering; or, after step h, a transparent conductive film layer 104 is prepared on the surface of the electron transport layer 103 using reactive ion deposition.

[0089] k. After step j, low-temperature silver paste is printed on the surface of the transparent conductive film layer 104 to form a metal grid electrode 105. After drying, low-temperature silver paste is printed on the back of the battery to form a metal grid electrode 106, which is then cured.

[0090] The thickness of the N-type emitter junction layer 502 is 0.35-0.5 μm, the thickness of the silicon oxide passivation layer 503 is 1.3-1.7 nm, the thickness of the P-type doped polycrystalline silicon thin film 504 is 100-300 nm, the thickness of the SiNx layer 505 is 70-90 nm, the thickness of the transparent conductive ITO film layer 507 is 10-20 nm, the thickness of the NiOx hole transport layer or organic hole transport layer 101 is 10-20 nm, and the thickness of the electron transport layer 103 is 5-50 nm.

[0091] The purpose of this invention is to provide a design principle for a perovskite / silicon tandem solar cell structure. This principle addresses the different current gains caused by different bifacialities of the underlying silicon solar cells and the different back-side incident light, by adjusting the perovskite composition and thickness to achieve current matching in the perovskite / silicon tandem solar cell and maximize the conversion efficiency.

[0092] Example 1:

[0093] The solar cell in this embodiment is a tandem cell composed of perovskite and PERC silicon solar cells. From bottom to top, it includes a 20μm thick silver layer, an 80nm thick SiNx layer, a 5nm thick Al2O3 layer, a 170μm thick silicon wafer, a 0.35-0.5μm thick phosphorus-doped emitter junction layer, a 20nm thick ITO layer, a 20nm thick NiO layer, a 400nm thick perovskite layer, a 40nm thick PCBM layer, a 10nm thick SnO2 layer, a 110nm thick ITO layer, and a 20μm thick silver grid line.

[0094] Its preparation method specifically includes the following steps:

[0095] S1. A P-type (100) Czochralski-grown single-crystal silicon wafer with a resistivity of 1.6 Ω·cm and a thickness of 170 μm was used. The front side of the silicon wafer was cleaned and texturized with KOH solution. Additives were used to control the size and uniformity of the textured pyramids. The texturing temperature was 80-83℃, and the texturing time was 10-15 min. After texturing, an RCA cleaning step was performed to remove organic matter and metallic contaminants from the surface.

[0096] S2. After texturing, a phosphorus-doped emitter junction layer with a thickness between 0.35-0.5 μm is prepared on the front side of the silicon wafer using a high-temperature thermal diffusion method. The sheet resistance of the diffusion layer is approximately 85 Ω / □. The phosphorosilicate glass on the edge and back side of the silicon wafer is removed using a wet chemical etching method.

[0097] S3. An Al2O3 passivation film with a thickness of approximately 5 nm was deposited on the back side using atomic layer deposition (ALD). The preparation parameters were as follows: PM2H2O: 30±20 slm; deposition time: 150 s; temperature: 300±30℃; gas pressure: 6±2 mba.

[0098] S4. A SiNx antireflection film with a thickness of approximately 80 nm was deposited on the back side using plasma-enhanced chemical vapor deposition (PECVD). The plasma preparation parameters were as follows: SiH4: 730 sccm; NH3: 7000 sccm; deposition time: 850 s; temperature: 500 °C; pressure: 1500 mTorr; power: 6800 W.

[0099] S5. The Al2O3 and SiNx on the back side are grooved using a picosecond laser; aluminum paste is screen-printed at the laser-grooved area and dried and annealed at 730℃.

[0100] S6. An ITO thin film with a thickness of 20 nm is prepared on the front side by magnetron sputtering.

[0101] S7. Sputter a NiO thin film on ITO as a hole transport layer with a film thickness of 20 nm;

[0102] S8. Dissolve lead iodide / lead bromide at concentrations of 600 mg / ml and 40 mg / ml in a solvent in a 4:1 ratio of DMF / DMSO, spin coat the cavity layer from step S7 at a speed of 2000 rpm, and heat at 80°C for 1 min to obtain a lead iodide / lead bromide layer with a thickness of approximately 200 nm.

[0103] S9. A mixed solution of FAI / FABr / MAI / cesium iodide was spin-coated onto the lead iodide layer. The concentrations of this mixed solution in the IPA solvent were 80, 10, 10, and 17 mg / ml, respectively. The spin-coating speed was 3000 rpm. After spin-coating, the layer was heated at 140°C for 20 min to obtain a perovskite photoactive layer with a thickness of approximately 400 nm. The optical band gap of the perovskite absorption layer was 1.63 eV.

[0104] S10. Spin-coating PCBM solution onto the perovskite layer: PCBM is dissolved in o-dichlorobenzene at a concentration of 20 mg / ml, and the spin-coating speed is 6000 rpm. After spin-coating, heat at 100℃ for 30 min to achieve a thickness of approximately 40 nm.

[0105] S11. A 10 nm SnO2 thin film was prepared on the PCBM battery by ALD as a protective layer material; the preparation parameters were as follows: PM H2O: 30±20 slm; deposition time 150 s; temperature 100±5℃; gas pressure: 6±2 mba.

[0106] S12. Sputter an ITO thin film onto SnO2 as a transparent conductive film with a thickness of 110 nm;

[0107] S13. Print silver grid lines on the front and back of the battery, and sinter and anneal at 150 degrees for 30 minutes to complete the fabrication of perovskite / PERC tandem cells.

[0108] S14. Quantum efficiency measurement of perovskite / PERC tandem solar cells, with the perovskite cell contributing 20 mA / cm². 2 The PERC bottom cell contributes 18 mA / cm² current. 2 The current density increases by 10% when light is incident on the back of the PERC cell, reaching 20 mA / cm². 2 The current density is exactly equal to the current density of the front battery, thus achieving 20 mA / cm². 2 The current density is [not specified]; the PERC cell contributes 0.65V open-circuit voltage, and the perovskite cell contributes 1.05V open-circuit voltage, for a total open-circuit voltage of 1.70V; the fill factor is 0.78, and the efficiency of the tandem cell is 26.52%. Correspondingly, if a bifacial cell structure is not used, following the general current matching approach for tandem cells, the perovskite and PERC cells each contribute 19mA / cm². 2 If the current, voltage, and fill factor remain constant, the battery efficiency is only 25.19%.

[0109] Example 2:

[0110] The solar cell in this embodiment is a tandem cell composed of perovskite, PERC, and TOPCon structures. From bottom to top, it includes, in sequence, a 20 μm thick silver layer, an 80 nm thick SiNx layer, a 400 nm thick P-type doped polycrystalline silicon layer, a 1.5 nm thick SiO2 layer, a 160 μm thick n-type monocrystalline silicon wafer, a 0.35-0.5 μm thick phosphorus doped emitter junction layer, a 20 nm thick ITO layer, a 20 nm thick NiO layer, a 400 nm thick perovskite layer, a 40 nm thick PCBM layer, a 10 nm thick SnO2 layer, a 110 nm thick ITO layer, and a 20 μm thick silver grid line.

[0111] Its preparation method specifically includes the following steps:

[0112] S1. Use n-type (100) plane Czochralski-grown single-crystal silicon wafers with a resistivity of 1 Ω·cm and a thickness of 170 μm. The front side of the silicon wafer is cleaned and texturized with KOH solution. Additives are used to control the size and uniformity of the textured pyramids. The texturing temperature is 80-83℃, and the texturing time is 10-15 min. After texturing, an RCA cleaning step is performed to remove organic matter and metallic contaminants from the surface.

[0113] S2. After texturing, a phosphorus-doped emitter junction layer with a thickness of 0.35-0.5 μm is prepared on the front side of the silicon wafer using a high-temperature thermal diffusion method. The phosphorus-silicon glass on the back side of the silicon wafer is then removed using a wet chemical etching method.

[0114] S3. A SiO2 passivation layer is prepared on the back side by thermal oxidation, wherein the film thickness is approximately 1.3-1.7 nm.

[0115] S4. Deposit an intrinsic polycrystalline silicon thin film with a thickness of approximately 300 nm on the back SiO2 layer using low-pressure chemical vapor deposition (LPCVD); perform boron diffusion doping on the intrinsic polycrystalline silicon thin film using a high-temperature thermal diffusion method to form a p+ polycrystalline silicon thin film; remove the borosilicate glass coated on the front side of the silicon wafer using wet chemical etching, and perform RCA cleaning to remove contaminants.

[0116] S5. A SiNx layer with a thickness of 80 nm was deposited on the back side using the PECVD method.

[0117] S6. An ITO thin film with a thickness of 20 nm is prepared on the front side by magnetron sputtering.

[0118] S7. Sputter a NiO thin film on ITO as a hole transport layer with a film thickness of 20 nm;

[0119] S8. Dissolve lead iodide / lead bromide at concentrations of 600 mg / ml and 40 mg / ml in a solvent in a 4:1 ratio of DMF / DMSO, spin coat the cavity layer from step S7 at a speed of 2000 rpm, and heat at 80°C for 1 min to obtain a lead iodide / lead bromide layer with a thickness of approximately 200 nm.

[0120] S9. A mixed solution of FAI / FABr / MAI / cesium iodide was spin-coated onto the lead iodide layer. The concentrations of this mixed solution in the IPA solvent were 80, 10, 10, and 17 mg / ml, respectively. The spin-coating speed was 3000 rpm. After spin-coating, the layer was heated at 140°C for 20 min to obtain a perovskite photoactive layer with a thickness of approximately 400 nm. The optical band gap of the perovskite absorption layer was 1.61 eV.

[0121] S10. Spin-coating PCBM solution onto the perovskite layer: PCBM is dissolved in o-dichlorobenzene at a concentration of 20 mg / ml, and the spin-coating speed is 6000 rpm. After spin-coating, heat at 100℃ for 30 min to achieve a thickness of approximately 40 nm.

[0122] S11. A 10 nm SnO2 thin film was prepared on the PCBM battery by ALD as a protective layer material; the preparation parameters were as follows: PM H2O: 30±20 slm; deposition time 150 s; temperature 100±5℃; gas pressure: 6±2 mba.

[0123] S12. Sputter an ITO thin film onto SnO2 as a transparent conductive film with a thickness of 110 nm;

[0124] S13. Print silver paste on the front side of the battery and aluminum paste and silver grid lines on the back side. Sinter and anneal at 150 degrees for 30 minutes to complete the fabrication of perovskite / TOPCon tandem cells.

[0125] S14. Quantum efficiency measurement of perovskite / TOPCon tandem solar cells, with the perovskite cell contributing 21.3 mA / cm². 2 The TOPCon base cell contributes 18.5 mA / cm² current. 2 The current density increases by 15% when light is incident on the back of the TOPCon battery, reaching 21.3 mA / cm². 2 The current density is exactly equal to the current density of the front battery, thus achieving 21.3 mA / cm². 2 The current density is [not specified]; the TOPCon cell contributes 0.71V open-circuit voltage, and the perovskite cell contributes 1.05V open-circuit voltage, for a total open-circuit voltage of 1.76V; the fill factor is 0.78, resulting in an efficiency of 29.24% for the tandem cell. Correspondingly, without a bifacial cell structure, following the general current matching principle for tandem cells, both the perovskite and TOPCon cells contribute 19.9mA / cm². 2 If the current, voltage, and fill factor remain constant, the battery efficiency is only 27.31%.

[0126] Example 3:

[0127] The solar cell in this embodiment is a tandem cell composed of perovskite and silicon heterojunction solar cells. From bottom to top, it includes, in sequence, 20 μm thick silver, 110 nm thick ITO, 5 nm thick p-type doped amorphous silicon, 5 nm thick intrinsic amorphous silicon, 160 μm thick n-type monocrystalline silicon wafer, 5 nm thick intrinsic amorphous silicon, 5 nm thick n-type doped microcrystalline silicon oxide, 20 nm thick ITO, 20 nm thick NiO, 400 nm perovskite, 40 nm PCBM, 10 nm SnO2, 110 nm ITO, and 20 μm silver grid lines.

[0128] Its preparation method specifically includes the following steps:

[0129] S1. Use n-type (100) plane Czochralski-grown single-crystal silicon wafers with a resistivity of 1-5 Ω·cm and a thickness of 170 μm. The front side of the silicon wafer is cleaned and texturized with KOH solution, using K2SiO3 and IPA as additives. The texturizing temperature is 80-83℃, and the texturizing time is 10-15 min. After texturizing, an RCA cleaning step is performed to remove organic matter and metallic contaminants from the surface.

[0130] S2. After texturing, a 5 nm thick intrinsic amorphous silicon thin film is sequentially prepared on the front and back sides using plasma-enhanced chemical vapor deposition (PECVD). A 5 nm thick p-type doped amorphous silicon thin film is prepared on the back side, and a 5 nm thick n-type doped microcrystalline silicon oxide thin film is prepared on the front side. The deposition temperature does not exceed 250℃.

[0131] S3. An ITO thin film with a thickness of 110 nm is prepared on the back side by magnetron sputtering; an ITO thin film with a thickness of 20 nm is sputtered on the front side.

[0132] S4. Sputter a NiO thin film on ITO as a hole transport layer with a film thickness of 20 nm.

[0133] S5. A lead iodide / cesium bromide mixed layer with a thickness of approximately 200 nm was prepared by co-evaporation.

[0134] S6. A mixed solution of FAI / FABr / MACl was spin-coated onto the lead iodide / cesium bromide mixed layer. The concentrations of this mixed solution in the IPA solvent were 80, 10, 10, and 17 mg / ml, respectively. The spin-coating speed was 3000 rpm. After spin-coating, the layer was heated at 160℃ for 20 min to obtain a perovskite photoactive layer with a thickness of approximately 400 nm. The optical band gap of the perovskite absorption layer was 1.59 eV.

[0135] S10. A C60 thin film with a thickness of 10 nm is deposited on the perovskite layer by vapor deposition.

[0136] S11. A 10 nm SnO2 thin film was prepared on C60 by ALD as a protective layer material; the preparation parameters were as follows: PM H2O: 30±20 slm; deposition time 150 s; temperature 100±5℃; gas pressure: 6±2 mba.

[0137] S12. Sputter an ITO thin film onto SnO2 as a transparent conductive film with a thickness of 110 nm;

[0138] S13. Print silver grid lines on the front and back of the battery, and sinter and anneal at 150 degrees for 30 minutes to complete the fabrication of perovskite / silicon heterojunction tandem battery.

[0139] S14. Quantum efficiency measurement of perovskite / silicon heterojunction tandem solar cells, with the perovskite cell contributing 22 mA / cm². 2 The silicon heterojunction bottom cell contributes 18 mA / cm² current. 2 The current density increases by 20% when light is incident on the back of the silicon heterojunction cell, reaching 22 mA / cm². 2 The current density is exactly equal to the current density of the front battery, thus achieving 22 mA / cm². 2The current density is [not specified]. The silicon heterojunction cell contributes 0.73V open-circuit voltage, and the perovskite cell contributes 1.07V open-circuit voltage, for a total open-circuit voltage of 1.8V. With a fill factor of 0.78, the efficiency of the tandem cell is 30.89%. Correspondingly, following the general current matching approach for tandem cells, both the perovskite and silicon heterojunction cells contribute 20mA / cm². 2 If the current, voltage, and fill factor remain constant, the battery efficiency is only 28.08%.

[0140] Using silicon cells as the bottom layer is the best choice for double tandem cells: 1) Silicon cells are the mainstream product in the photovoltaic industry; 2) Tandem cells are composed of two sub-cells connected in series. Silicon cells have a higher open-circuit voltage, which can improve the open-circuit voltage of the tandem cells and thus improve the conversion efficiency of solar cells; 3) Silicon cells can be fabricated as bifacial structures, and the scattered light from the back side can be used to increase the current of the bottom layer cell.

[0141] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A perovskite / silicon tandem solar cell, characterized in that: It includes a silicon cell, a perovskite cell positioned above the silicon cell with a current greater than the silicon cell's backscattered photocurrent, and an intermediate connection structure connecting the perovskite cell and the silicon cell. The perovskite cell has a current greater than the silicon cell's backscattered photocurrent by no more than 20%. The perovskite cell employs a PIN structure, comprising, from top to bottom, a metal electrode, a transparent conductive layer, an electron transport layer, a perovskite absorption layer with an optical bandgap of 1.60 eV-1.63 eV, and a hole transport layer. The thickness of the perovskite absorption layer is 300-1000 nm, and its composition is MA. （1-x-y） FA x Cs y PbI （3-3x） Br 3y Perovskite layer (0 < x, 0 < y ≤ 1).

2. The perovskite / silicon tandem solar cell according to claim 1, characterized in that: The intermediate connection structure is a transparent conductive film layer, a microcrystalline silicon thin film layer, or a polycrystalline silicon thin film layer.

3. The perovskite / silicon tandem solar cell according to claim 1, characterized in that: The silicon cell is a bifacial silicon cell, which is a structure that combines one or more of the following: silicon heterojunction cell, TOPCon cell, or PERC cell.

4. The perovskite / silicon tandem solar cell according to claim 3, characterized in that: The silicon heterojunction cell comprises, from top to bottom, a P-type or N-type doped silicon-based thin film, an intrinsic amorphous silicon thin film, a silicon wafer, an intrinsic amorphous silicon thin film, a P-type doped amorphous silicon thin film, a transparent conductive thin film, and a metal electrode, stacked sequentially; or, the silicon heterojunction cell comprises, from top to bottom, an N-type doped silicon-based thin film, an intrinsic amorphous silicon thin film, a silicon wafer, an intrinsic amorphous silicon thin film, a P-type doped amorphous silicon thin film, a transparent conductive thin film, and a metal electrode, stacked sequentially. The TOPCon cell comprises, from top to bottom, a P-type polycrystalline silicon thin film layer, an N-type polycrystalline silicon thin film layer, a silicon oxide passivation layer, a monocrystalline silicon wafer, a silicon oxide passivation layer, a P-type polycrystalline silicon thin film layer, a SiNx passivation layer, and a metal electrode, stacked sequentially from top to bottom; or, the TOPCon cell comprises, from top to bottom, an N-type polycrystalline silicon thin film layer, a silicon oxide passivation layer, a monocrystalline silicon wafer, a silicon oxide passivation layer, a P-type polycrystalline silicon thin film layer, a SiNx passivation layer, and a metal electrode, stacked sequentially from top to bottom; or, the TOPCon cell comprises, from top to bottom, a P-type polycrystalline silicon thin film layer, an N-type polycrystalline silicon thin film layer, a silicon oxide passivation layer, a monocrystalline silicon wafer, an aluminum oxide passivation layer, a SiNx passivation layer, and a metal electrode, stacked sequentially from top to bottom; or, the TOPCon cell comprises, from top to bottom, an N-type polycrystalline silicon thin film layer, a silicon oxide passivation layer, a monocrystalline silicon wafer, an aluminum oxide passivation layer, a SiNx passivation layer, and a metal electrode. The PERC cell includes, from top to bottom, an N-type emitter junction layer, a P-type monocrystalline silicon wafer, an aluminum oxide passivation layer, a SiNx passivation layer, and a metal electrode, or the PERC cell includes, from top to bottom, a P-type polycrystalline silicon layer, an N-type emitter junction layer, a P-type monocrystalline silicon wafer, an aluminum oxide passivation layer, a SiNx passivation layer, and a metal electrode. The bifacial silicon solar cell is a PERC and TOPCon structure fusion cell. The PERC and TOPCon structure fusion cell includes, from top to bottom, an N-type emitter junction layer, a monocrystalline silicon wafer, a silicon oxide passivation layer, a P-type polycrystalline silicon thin film layer, a SiNx passivation layer, and a metal electrode, stacked sequentially. Alternatively, the PERC and TOPCon structure fusion cell includes, from top to bottom, a P-type polycrystalline silicon layer, an N-type emitter junction layer, a monocrystalline silicon wafer, a silicon oxide passivation layer, a P-type polycrystalline silicon thin film layer, a SiNx passivation layer, and a metal electrode, stacked sequentially.

5. The method for fabricating a perovskite / silicon tandem solar cell according to claim 3 or 4, characterized in that: A series perovskite cell is stacked above a silicon cell via an intermediate connecting structure. Based on the current of the perovskite cell or the current of the silicon cell without backscattered light, the current of the silicon cell without backscattered light or the current of the perovskite cell is adjusted so that the current of the perovskite cell is greater than the current of the silicon cell without backscattered light, wherein the current of the perovskite cell is greater than the current of the silicon cell without backscattered light by no more than 20%.

6. The method for fabricating a perovskite / silicon tandem solar cell according to claim 5, characterized in that: The fabrication of the perovskite solar cell includes the fabrication of a perovskite absorber layer, the composition of which is MA. （1-x-y） FA x Cs y PbI （3-3x） Br 3y (0 < x, 0 < y ≤ 1), by adjusting the composition ratio of MA, FA and Cs, and the composition ratio of I and Br, the optical band gap of the perovskite layer is changed to 1.60 eV-1.63 eV.

7. The method for preparing a perovskite / silicon tandem solar cell according to claim 6, characterized in that: The fabrication process of the perovskite absorber layer is as follows: a perovskite layer is coated on the surface of the perovskite absorber layer to be fabricated using slit coating technology, and then annealed and dried at 100-200℃ for 10-60 minutes to form a perovskite layer with a thickness of 300-1000nm; or, a perovskite layer is fabricated on the surface of the perovskite absorber layer to be fabricated using a combination of vacuum evaporation and slit coating, and then annealed and crystallized at 100-200℃ for 10-60 minutes to form a perovskite layer with a thickness of 300-1000nm.

8. The method for preparing a perovskite / silicon tandem solar cell according to claim 7, characterized in that: Its specific steps include, a. The silicon heterojunction solar cell uses an N-type monocrystalline silicon wafer (001), and a double-sided texturing structure is formed on the surface of the N-type monocrystalline silicon wafer (001) after texturing and cleaning; b. After the treatment in step a, an intrinsic amorphous silicon layer (002), an N-type microcrystalline silicon oxide layer (003), and a P-type microcrystalline silicon oxide layer (007) are sequentially deposited on the front side of an N-type monocrystalline silicon wafer (001) using PECVD. c. After step b, an intrinsic amorphous silicon layer (004) and a P-type amorphous silicon layer (005) are sequentially deposited on the back side of the N-type monocrystalline silicon wafer (001). d. After step c, ITO transparent conductive film (006) is deposited on the back side of the P-type amorphous silicon layer (005) by magnetron sputtering. e. After step d, an organic hole transport layer (101) is prepared on the P-type microcrystalline silicon oxide layer (007) by vacuum evaporation; or, after step d, an inorganic hole transport layer (101) is prepared on the P-type microcrystalline silicon oxide layer by physical deposition. f. After step d, a perovskite absorption layer (102) is formed on the surface of the hole transport layer (101) using slit coating technology. After coating, a perovskite film is formed by thermal annealing and crystallization. Alternatively, after step d, a perovskite absorption layer (102) is formed on the surface of the hole transport layer (101) using a combination of vacuum evaporation and slit coating. After coating, a perovskite film is formed by annealing and crystallization. g. After step f, an electron transport layer (103) is prepared on the perovskite absorber layer (102) by vapor deposition. h. After step g, an ITO transparent conductive film layer (104) is prepared on the surface of the electron transport layer (103) by magnetron sputtering; or, after step g, a transparent conductive film layer (104) is prepared on the surface of the electron transport layer (103) by atomic layer deposition and magnetron sputtering; or, after step g, a transparent conductive film layer (104) is prepared on the surface of the electron transport layer (103) by reactive ion deposition. i. After step h, low-temperature silver paste is printed on the surface of the transparent conductive film layer (104) to form metal grid line electrodes (105) by screen printing technology. After drying, low-temperature silver paste is printed on the back of the battery to form metal grid line electrodes (106), and then cured. Alternatively, its specific steps include, a. The TOPCon cell uses an N-type monocrystalline silicon wafer or a P-type monocrystalline silicon wafer (201), and a double-sided texturing structure is formed on the surface of the N-type monocrystalline silicon wafer or the P-type monocrystalline silicon wafer (201) after texturing and cleaning; b. After the treatment in step a, silicon oxide passivation layers (202) and (204) are deposited on both sides of the N-type single crystal silicon wafer or the P-type single crystal silicon wafer (201) by thermal oxidation. c. After step b, N-type doped polycrystalline silicon thin film (203) is deposited on silicon oxide passivation layer (202) and P-type doped polycrystalline silicon thin film (205) is deposited on silicon oxide passivation layer (204) using LPCVD. d. After step c, SiNx passivation layer (206) is deposited on the P-type doped polycrystalline silicon thin film (205) by PECVD. e. After step d, a transparent conductive ITO film (207) is deposited on the surface of the N-type doped polysilicon layer (203) by magnetron sputtering; or, after step d, an N-type doped polysilicon thin film (207) is deposited on the surface of the N-type doped polysilicon layer (203) by LPCVD. f. After step e, a NiOx hole transport layer (101) is prepared on the transparent conductive ITO film layer or the N-type doped polycrystalline silicon film (207) by magnetron sputtering; or, after step e, an organic hole transport layer (101) is prepared on the transparent conductive ITO film layer or the N-type doped polycrystalline silicon film (207) by vacuum evaporation. g. After step f, a perovskite absorption layer (102) is formed on the surface of the hole transport layer (101) using slit coating technology, and then annealed and dried at 150°C for 15 minutes; or, after step f, a perovskite absorption layer (102) is formed on the surface of the hole transport layer (101) using a combination of vacuum evaporation and slit coating, and then annealed and crystallized to form a perovskite film. h. After step g, an electron transport layer (103) is prepared on the perovskite absorber layer (102) by vapor deposition. i. After step h, an ITO transparent conductive film layer (104) is prepared on the surface of the electron transport layer (103) by magnetron sputtering; or, after step h, a transparent conductive film layer (104) is prepared on the surface of the electron transport layer (103) by atomic layer deposition and magnetron sputtering; or, after step h, a transparent conductive film layer (104) is prepared on the surface of the electron transport layer (103) by reactive ion deposition. j. After step i, low-temperature silver paste is printed on the surface of the transparent conductive film layer (104) to form a metal grid electrode (105). After drying, low-temperature silver paste is printed on the back of the battery to form a metal grid electrode (106), and then cured. Alternatively, its specific steps include, a. The TOPCon cell uses an N-type monocrystalline silicon wafer (301), and a double-sided texturing structure is formed on the surface of the N-type monocrystalline silicon wafer (301) after texturing and cleaning; b. After step a, a silicon oxide passivation layer (302) is deposited on the front side of the N-type monocrystalline silicon wafer (301) by thermal oxidation, and an aluminum oxide passivation layer (304) is deposited on the back side of the N-type monocrystalline silicon wafer (301) by atomic layer deposition. c. After step b, SiNx film (305) is deposited on the alumina passivation layer (304) by PECVD. d. After step c, an N-type polysilicon layer (306) is deposited on the silicon oxide passivation layer (302) using LPCVD. e. After step d, ITO transparent conductive film layer (307) is deposited on the surface of N-type polysilicon layer (306) by magnetron sputtering; or, after step d, P-type doped polysilicon thin film (307) is deposited on the surface of N-type polysilicon layer (306) by LPCVD. f. After step e, a NiOx hole transport layer (101) is prepared on the ITO transparent conductive film layer or the P-type doped polycrystalline silicon film (307) by magnetron sputtering; or, after step e, an organic hole transport layer (101) is prepared on the ITO transparent conductive film layer or the P-type doped polycrystalline silicon film (307) by vacuum evaporation. g. After step f, a perovskite absorption layer (102) is formed on the surface of the hole transport layer (101) using slit coating technology. After coating, it is annealed and dried at 150°C for 15 minutes. Alternatively, after step f, a perovskite absorption layer (102) is formed on the surface of the hole transport layer (101) using a combination of vacuum evaporation and slit coating. After coating, it is annealed and crystallized to form a perovskite film. h. After step g, an electron transport layer (103) is prepared on the perovskite absorber layer (102) by vapor deposition. i. After step h, an ITO transparent conductive film layer (104) is prepared on the surface of the electron transport layer (103) by magnetron sputtering; or, after step h, a transparent conductive film layer (104) is prepared on the surface of the electron transport layer (103) by atomic layer deposition and magnetron sputtering; or, after step h, a transparent conductive film layer (104) is prepared on the surface of the electron transport layer (103) by reactive ion deposition. j. After step i, low-temperature silver paste is printed on the surface of the transparent conductive film layer (104) to form metal grid electrodes (105) by screen printing technology. After drying, low-temperature silver paste is printed on the back of the battery to form metal grid electrodes (106), and then cured. Alternatively, its specific steps include, a. The PERC cell uses a P-type monocrystalline silicon wafer (401), and a double-sided texturing structure is formed on the surface of the P-type monocrystalline silicon wafer (401) after texturing and cleaning; b. After the treatment in step a, an N-type emitter junction (402) is formed on the front side of a P-type monocrystalline silicon wafer (401) using a thermal diffusion method. c. After step b, an aluminum oxide passivation layer (403) is deposited on the back side of a P-type single crystal silicon wafer (401) using atomic layer deposition. d. After step c, SiNx film (404) is deposited on the alumina passivation layer (403) by PECVD. e. After step d, a transparent conductive ITO film (405) is deposited on the surface of the N-type emitter junction layer (402) by magnetron sputtering; or, after step d, a P-type doped polycrystalline silicon thin film (405) is deposited on the surface of the N-type emitter junction layer (402) by LPCVD. f. After step e, a NiOx hole transport layer (101) is prepared on a transparent conductive ITO film or a P-type doped polycrystalline silicon film (405) by magnetron sputtering; or, after step e, an organic hole transport layer (101) is prepared on a transparent conductive ITO film or a P-type doped polycrystalline silicon film (405) by vacuum evaporation. g. After step f, a perovskite absorption layer (102) is formed on the surface of the hole transport layer (101) using slit coating technology, and then annealed and dried; or, after step f, a perovskite absorption layer (102) is formed on the surface of the hole transport layer (101) using a combination of vacuum evaporation and slit coating, and then annealed and crystallized to form a perovskite film. h. After step g, an electron transport layer (103) is prepared on the perovskite absorber layer (102) by vapor deposition. i. After step h, an ITO transparent conductive film layer (104) is prepared on the surface of the electron transport layer (103) by magnetron sputtering; or, after step h, a transparent conductive film layer (104) is prepared on the surface of the electron transport layer (103) by atomic layer deposition and magnetron sputtering; or, after step h, a transparent conductive film layer (104) is prepared on the surface of the electron transport layer (103) by reactive ion deposition. j. After step i, low-temperature silver paste is printed on the surface of the transparent conductive film layer (104) to form metal grid electrodes (105) by screen printing technology. After drying, low-temperature silver paste is printed on the back of the battery to form metal grid electrodes (106), and then cured. Alternatively, its specific steps include, a. The bifacial silicon cell is a PERC and TOPCon structure fusion cell. The PERC and TOPCon structure fusion cell uses an N-type monocrystalline silicon wafer (501). After texturing and cleaning, a bifacial texturing structure is formed on the surface of the N-type monocrystalline silicon wafer (501). b. After the treatment in step a, an N-type emitter junction (502) is formed on the front side of an N-type monocrystalline silicon wafer (501) using a thermal diffusion method. c. After step b, a silicon oxide passivation layer (503) is prepared on the back side of an N-type single-crystal silicon wafer (501) by thermal oxidation. d. After step c, a P-type polycrystalline silicon thin film layer (504) is prepared on the silicon oxide passivation layer (503) by LPCVD and thermal diffusion method. e. After step d, a SiNx layer (505) is deposited on the P-type polycrystalline silicon thin film layer (504) using the PECVD method. f. After step e, a transparent conductive ITO film (507) is deposited on the surface of the N-type emitter junction layer (502) by magnetron sputtering; or, after step d, a P-type doped polycrystalline silicon thin film (507) is deposited on the surface of the N-type emitter junction layer (502) by LPCVD. g. After step f, a NiOx hole transport layer (101) is prepared on the transparent conductive ITO film layer or the N-type doped polycrystalline silicon film (507) by magnetron sputtering; or, after step e, an organic hole transport layer (101) is prepared on the transparent conductive ITO film layer or the N-type doped polycrystalline silicon film (507) by vacuum evaporation. h. After step g, a perovskite absorption layer (102) is formed on the surface of the hole transport layer (101) using slit coating technology. After coating, it is annealed and dried at 150°C for 15 minutes; or, after step f, a perovskite absorption layer (102) is formed on the surface of the hole transport layer (101) using a combination of vacuum evaporation and slit coating. After coating, it is annealed and crystallized to form a perovskite film. i. After step h, an electron transport layer (103) is prepared on the perovskite absorber layer (102) by vapor deposition. j. After step i, an ITO transparent conductive film layer (104) is prepared on the surface of the electron transport layer (103) by magnetron sputtering; or, after step h, a transparent conductive film layer (104) is prepared on the surface of the electron transport layer (103) by atomic layer deposition and magnetron sputtering; or, after step h, a transparent conductive film layer (104) is prepared on the surface of the electron transport layer (103) by reactive ion deposition. k. After step j, low-temperature silver paste is printed on the surface of the transparent conductive film layer (104) to form a metal grid electrode (105). After drying, low-temperature silver paste is printed on the back of the battery to form a metal grid electrode (106), and then cured.

Images