A peak hold circuit with peak mark output

Abstract

The present invention seeks to protect a peak holding circuit with a peak mark output, comprising a peak holding circuit, a peak detection circuit, and a peak mark output buffer. The output of the peak holding circuit comes from the output of the previous stage, which may be the output of a filter shaper or a radiation signal output by other detection circuits. The two output ends of the peak holding circuit are the peak output and the current mirror voltage signal, respectively. The current mirror voltage signal is connected to the input end of the peak detection circuit, and the output end of the peak detection circuit is connected to the peak mark output buffer. The peak mark output buffer then outputs the peak mark signal to other modules. The peak holding circuit of the present invention can hold the waveform of the voltage signal of the previous stage at its peak value. The peak detection circuit can quickly respond and output a corresponding mark signal when the peak value arrives. The peak mark output buffer can convert the mark signal output by the peak detection circuit into a corresponding pulse signal.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog integrated circuit design, and in particular relates to a peak hold circuit with a peak mark output, and more particularly to a radiation detector readout circuit. Background Art

[0002] Once the radiation phenomenon was discovered, it was applied to various fields of life, such as space exploration, high-energy physics, security inspection, nuclear medicine imaging, etc. How to quickly and accurately measure the radiation energy has become the most critical issue in these fields. The peak hold circuit is a key component in nuclear electronic signal processing and has been fully integrated into multiple front-end dedicated readout chips as an important module. In CMOS design, the classic peak hold circuit uses a MOS current source as a rectifying element in the feedback loop of a high-gain amplifier. However, the non-idealities in the amplifier and feedback elements greatly limit their accuracy and stability, such as Figure 1 In addition, the classic peak detection and hold circuit uses only one PMOS tube for charging and has only one output terminal, so it can only output a peak signal but not a peak marker signal. In applications where the subsequent stage requires simulated accumulation of the incident signal, a digital signal output of the peak marker is required to provide an accurate peak arrival time marker. Summary of the Invention

[0003] The present invention aims to solve the above problems of the prior art. It proposes a peak hold circuit with a peak mark output. The technical solution of the present invention is as follows:

[0004] A peak holding circuit with a peak mark output includes a peak holding circuit, a peak detection circuit, and a peak mark output buffer. The input of the peak holding circuit usually comes from the output of the previous stage filter shaper. The two output ends of the peak holding circuit are the peak output and the current mirror voltage signal. The current mirror voltage signal is connected to the input end of the peak detection circuit. The output end of the peak detection circuit is connected to the peak mark output buffer and then outputs the peak mark signal to the back-end digital signal processing module. The peak holding circuit keeps the waveform of the previous stage voltage signal at its peak value. After the input signal passes through an inverting amplifier A, the inverting amplifier outputs the peak value at the rising stage of the signal. The terminal VC will decrease and pull down the gate of the current mirror composed of MPA and MPB. At this time, the current mirror charges the holding capacitor CH. When the signal is in the falling stage, the negative end of the reverse amplifier A is greater than the positive end, and the current mirror stops charging the holding capacitor, thereby achieving the peak holding power; the peak detection circuit is mainly composed of a comparator, and the positive and negative ends of the comparator are respectively connected to the VC of the peak holding circuit and a reference voltage. When the VC voltage is lower than the reference voltage, the comparator output becomes a low level, achieving the function of sensing the peak; the peak mark output buffer consists of two delay units and a NAND gate logic, which converts the falling edge of the peak detection circuit output into a negative pulse signal.

[0005] Furthermore, the peak hold circuit includes four PMOS transistors, namely MP1, MP2, MP3, and MP4, three NMOS transistors, namely MN1, MN2, and MN3, a holding capacitor CH, and two transmission gates T1 and T2, wherein T1 and T2 are controlled by external RESET signals and HOLD signals respectively, the sources of MP1, MP2, MP3, and MP4 and one end of T2 are connected to the power supply voltage VDD, the gates of MP1 and MP2 are connected and then connected to the drain of MP2 and the drain of MN2, the drain of MN1 is connected to the gates of MP3 and MP4 and then to the drain of MP3 as the output port VC, and VC is also connected to the other end of T2; the sources of MN1 and MN2 are connected to the drain of MN3, the gate of MN3 serves as the external bias voltage input terminal VBN, the source of MN3 and one end of CH are connected to the negative power supply VSS, the other end of CH is connected together with the drain of MP4 and the gate of MN2 as the peak output terminal PHO, and the gate of MN1 serves as the input terminal PDHI.

[0006] Furthermore, the PMOS tubes MP1, MP2 and NMOS tubes MN1, MN2, and MN3 in the peak hold circuit form a dual-input common-source amplifier, in which MP1 and MP2 serve as amplifier tubes and MN3 serves as a current source for two branches; MP3 and MP4 form a PMOS tube current mirror to charge the holding capacitor CH, T1 is a transmission gate for resetting CH, and when the RESET signal arrives, the upper end of CH will be fixed to a specified baseline level, and T2 is a transmission gate for controlling the holding capacitor to maintain the peak value. When the peak value is detected, in addition to the circuit itself automatically maintaining the peak value, an external HOLD signal is also input to pull the gate potential of the current mirror to the power supply voltage, and the current mirror stops charging CH, achieving the function of stabilizing the peak value; the maximum voltage change rate of the peak value is: Where V' imax The maximum voltage change rate maintained by the peak hold circuit, I dmax is the maximum current flowing through the PMOS current mirror, u p is the hole mobility, C ox is the unit capacitance of the gate oxide layer, V g is the gate voltage of the current mirror PMOS tube, V T is the threshold voltage of the PMOS tube, C h To maintain the capacitance value of the capacitor.

[0007] Furthermore, the peak detection circuit includes 7 PMOS transistors, namely MP5, MP6, MP7, MP8, MP9, MP10, and MP11, and 5 NMOS transistors, namely MN4, MN5, MN6, MN7, and MN8; the drain of MN4 and the sources of MP5 and MP6 are connected to the power supply voltage VDD, the source of MN4 is connected to the gate of MP8 and the drain of MN5, the sources of MN5, MN6, MN7 and MN8 and MP10 and MP11 are connected to the gate of MP8 and the drain of MN5. The gate of MN1 is connected to the negative power supply VSS, the drain of MP5 is connected to the source of MP7, the drain of MP7 is connected to the source of MP8 and MP9, the drains of MP8 and MP9 are connected to the sources of MP10 and MP11 respectively, the drain of MP10 and the drain of MN6 are connected to the gates of MN6 and MN7, the drain of MP9 is connected to the source of MP11, the drain of MP11 and the drain of MN7 are connected to the gate of MN8, and the drain of MP6 is connected to the drain of MN8 as the output PO of the peak detection circuit.

[0008] Furthermore, MN4 and MN5 in the peak detection circuit form a source follower, which reduces the VC point voltage by the threshold voltage of an NMOS tube, and is used to provide a comparison voltage for the gate of the MP8 tube. MP5 and MP7 form a folded common source and common gate current mirror under the bias of the VBP common source tube bias voltage and the VCP common gate tube bias voltage respectively. MP8 and MP9 serve as amplifier tubes of the entire comparator, MP10, MP11, MN6 and MN7 are loads, MN8 and MP6 serve as the second-stage common source amplifier, and MN8 is an amplifier tube.

[0009] Furthermore, the peak mark output buffer includes 10 PMOS transistors MP12, MP13, MP14, MP15, MP16, MP17, MP18, MP19, MP20, and MP21, and 10 NMOS transistors MN9, MN10, MN11, MN12, MN13, MN14, MN15, MN16, MN17, and MN18. The sources of MP12, MP13, MP14, MP15, MP16, MP17, MP18, MP19, MP20, and MP21 are connected to the power supply VDD, and the sources of MN9, MN10, MN11, MN13, MN14, MN15, MN16, MN17, and MN18 are connected to the negative power supply VSS. MP12 and MN9 form an inverter. The gate of MP12 is connected to the gate of MN9 as the input of the inverter, and the drain of MP12 is connected to the drain of MN9 as the output of the inverter. MP13 and MN10, MP14 and MN11 form inverters in the same way and are connected end to end. MP17 and MN14, MP18 and MN15, MP19 and MN16, MP20 and MN17, MP21 and MN18 also form inverters in the same way and are connected end to end. The drains of MP15 and MP16 are connected to the drain of MN12 as the output PDO of the peak mark output buffer. The source of MN12 is connected to the drain of MN13, the gates of MP15 and MN13 are connected to the drain of MP14 and the gate of MP17, and the gates of MP16 and MN12 are connected to the drain of MP21.

[0010] Furthermore, the three inverters MP12 and MN9, MP13 and MN10, MP14 and MN11 in the peak mark output buffer constitute the first delay unit, and the five inverters MP17 and MN14, MP18 and MN15, MP19 and MN16, MP20 and MN17, MP21 and MN18 constitute the second delay unit. After the peak hold circuit senses the peak signal, the voltage signal at VC of the current mirror will drop. When it is less than the reference voltage VREF, the detection circuit will immediately output a level rising edge. After passing through two delay units, a falling edge and a delayed rising edge are obtained respectively. After the peak ends, a rising edge and a falling edge are also obtained. The purpose is to obtain a negative pulse signal whose pulse width is only related to the delay time after the waveform after the two delays is negated, which is used for subsequent digital signal processing.

[0011] The advantages and beneficial effects of the present invention are as follows:

[0012] 1. In addition to the peak-hold circuit in the classic circuit, the present invention utilizes the voltage jump at the current mirror terminal when a peak value is reached. By introducing a fast comparator and setting a reasonable threshold voltage, a peak detection circuit is formed. This circuit outputs both the peak value and a peak arrival marker signal. This peak marker signal can be used in the back-end digital processing module, for example, to prompt the ADC (analog-to-digital converter) to acquire the signal and start conversion, shortening the entire signal processing cycle.

[0013] 2. The peak holding circuit of the present invention adds a HOLD signal to the gate of the charging current mirror. When the peak value is detected, the charging function of the current mirror is directly turned off, so that the holding capacitor is always maintained at the peak value, avoiding unstable voltage fluctuations or charge leakage at the output end that lead to a decrease in the accuracy of peak detection, thereby improving the detection accuracy and energy resolution of the entire channel.

[0014] 3. The peak hold circuit of the present invention additionally adds a peak mark output buffer. In addition to improving the load capacity of the peak mark signal, the mark signal first passes through two delay units, and then the two signals before and after the delay are negated. The output digital pulse signal width is independent of the input signal. Otherwise, the width of the output digital pulse signal will change with the size of the input signal, expanding its application range. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a block diagram of a classic peak detection circuit according to a preferred embodiment of the present invention.

[0016] Figure 2 Block diagram of a peak hold circuit with a peak marker output according to the present invention.

[0017] Figure 3 Schematic diagram of the peak hold circuit of the present invention.

[0018] Figure 4 Schematic diagram of the peak detection circuit of the present invention.

[0019] Figure 5 Schematic diagram of the peak marker output buffer of the present invention.

[0020] Figure 6 Transient simulation results of a peak-hold circuit.

[0021] Figure 7 Simulation results of the peak detection circuit and peak marker output buffer.

[0022] Figure 8 Overall circuit output linearity simulation results;

[0023] Figure 9 This figure shows the general structure of a peak hold circuit with a peak marker output. DETAILED DESCRIPTION

[0024] The following will describe the technical solutions in the embodiments of the present invention in detail with reference to the accompanying drawings. The described embodiments are only a part of the embodiments of the present invention.

[0025] The technical solution of the present invention to solve the above technical problems is:

[0026] In the embodiment of the present application, the voltage at the current mirror end will jump when the peak arrives, and a peak detection circuit is added. While outputting the peak value, it can also output a mark signal when the peak value arrives. A HOLD signal is added. When the peak value arrives, the charging function of the current mirror is directly turned off, so that the holding capacitor is maintained until the peak value, thereby improving the accuracy of the peak detection, and further improving the detection accuracy and energy resolution of the entire channel. By adding a peak mark output buffer, the output digital pulse signal width will be independent of the input signal, thereby expanding its application range.

[0027] Example

[0028] like Figure 2 、 Figure 9 As shown, it includes a peak hold circuit, a peak detection circuit, and a peak marker output buffer. The output of the peak hold circuit comes from the output of the previous stage, which can be the output of the filter shaper or the radiation signal output by other detection circuits. The two output terminals of the peak hold circuit are the peak output and the current mirror voltage signal. The current mirror voltage signal is connected to the input terminal of the peak detection circuit. The output terminal of the peak detection circuit is connected to the peak marker output buffer, which then outputs the peak marker signal to other modules.

[0029] like Figure 3 As shown, the peak hold circuit includes four PMOS transistors, namely MP1, MP2, MP3, and MP4; three NMOS transistors, namely MN1, MN2, and MN3; a holding capacitor CH; and two transmission gates T1 and T2. T1 and T2 are controlled by external RESET and HOLD signals, respectively. The sources of MP1, MP2, MP3, and MP4, as well as one end of T2, are connected to the power supply voltage VDD. The gates of MP1 and MP2 are connected, and then to the drain of MP2 and the drain of MN2. The drain of MN1 is connected to the gates of MP3 and MP4, and then to the drain of MP3 as the output port VC. VC is also connected to the other end of T2. The sources of MN1 and MN2 are connected to the drain of MN3. The gate of MN3 serves as the external bias voltage input terminal VBN. The source of MN3 and one end of CH are connected to the negative power supply VSS. The other end of CH, the drain of MP4, and the gate of MN2 are connected together to form the peak output terminal PHO. The gate of MN1 serves as the input terminal PDHI.

[0030] like Figure 3 As shown, the PMOS transistors MP1 and MP2 and the NMOS transistors MN1, MN2, and MN3 in the peak hold circuit form a dual-input common-source amplifier, where MP1 and MP2 serve as amplifiers and MN3 serves as the current source for the two branches. MP3 and MP4 form a PMOS transistor current mirror to charge the holding capacitor CH. T1 is the transmission gate that resets CH. When the RESET signal arrives, the upper end of CH will be fixed to the specified baseline level. T2 is the transmission gate that controls the peak value of the holding capacitor. When the peak value is detected, in addition to the circuit itself automatically maintaining the peak value, an external HOLD signal is also input to pull the gate potential of the current mirror to the power supply voltage. The current mirror stops charging CH and achieves the function of stabilizing the peak value. The maximum voltage change rate of the peak value is: Where V' imax The maximum voltage change rate maintained by the peak hold circuit, I dmax is the maximum current flowing through the PMOS current mirror, u p is the hole mobility, C ox is the unit capacitance of the gate oxide layer, V g is the gate voltage of the current mirror PMOS tube, V T is the threshold voltage of the PMOS tube, C h To maintain the capacitance value of the capacitor.

[0031] like Figure 4As shown, the peak detection circuit of the present invention includes 7 PMOS transistors, namely MP5, MP6, MP7, MP8, MP9, MP10, and MP11, and 5 NMOS transistors, namely MN4, MN5, MN6, MN7, and MN8. The drain of MN4 and the sources of MP5 and MP6 are connected to the power supply voltage VDD together, the source of MN4 is connected to the gate of MP8 and the drain of MN5, the sources of MN5, MN6, MN7 and MN8 and the gates of MP10 and MP11 are connected to the negative power supply VSS, the drain of MP5 is connected to the source of MP7, the drain of MP7 is connected to the sources of MP8 and MP9, the drains of MP8 and MP9 are connected to the sources of MP10 and MP11 respectively, the drain of MP10 and the drain of MN6 are connected to the gates of MN6 and MN7, the drain of MP9 is connected to the source of MP11, the drain of MP11 and the drain of MN7 are connected to the gate of MN8, and the drain of MP6 is connected to the drain of MN8 as the output PO of the peak detection circuit.

[0032] like Figure 4 As shown, in the peak detection circuit, MN4 and MN5 act as a source follower path, reducing the VC point voltage by the threshold voltage of an NMOS tube to provide a comparison voltage for the gate of MP8 tube. MP5 and MP7 form a folded common source and common gate current mirror under the bias of VBP and VCP respectively. MP8 and MP9 serve as amplifier tubes of the entire comparator, MP10, MP11, MN6 and MN7 serve as loads, MN8 and MP6 serve as the second-stage common source amplifier, and MN8 serves as an amplifier tube. The gain of the entire peak detection circuit can reach more than 70dB, providing a good foundation for maintaining accuracy.

[0033] like Figure 5As shown, the peak mark output buffer includes 10 PMOS transistors MP12, MP13, MP14, MP15, MP16, MP17, MP18, MP19, MP20, and MP21, and 10 NMOS transistors MN9, MN10, MN11, MN12, MN13, MN14, MN15, MN16, MN17, and MN18. The sources of MP12, MP13, MP14, MP15, MP16, MP17, MP18, MP19, MP20, and MP21 are connected to the power supply VDD, and the sources of MN9, MN10, MN11, MN13, MN14, MN15, MN16, MN17, and MN18 are connected to the negative power supply VSS. MP12 and MN9 form an inverter. The gate of MP12 is connected to the gate of MN9 as the input of the inverter, the drain of MP12 is connected to the drain of MN9 as the output of the inverter, MP13 and MN10, MP14 and MN11 form an inverter in the same way and are connected end to end, MP17 and MN14, MP18 and MN15, MP19 and MN16, MP20 and MN17, MP21 and MN18 also form an inverter in the same way and are connected end to end, the drains of MP15 and MP16 are connected to the drain of MN12 as the output PDO of the peak mark output buffer, the source of MN12 is connected to the drain of MN13, the gates of MP15 and MN13 are connected to the drain of MP14 and the gate of MP17, and the gates of MP16 and MN12 are connected to the drain of MP21.

[0034] like Figure 5 As shown, the three inverters MP12 and MN9, MP13 and MN10, and MP14 and MN11 in the peak mark output buffer constitute the first delay unit, and the five inverters MP17 and MN14, MP18 and MN15, MP19 and MN16, MP20 and MN17, and MP21 and MN18 constitute the second delay unit. After the peak hold circuit senses the peak signal, the voltage signal at VC of the current mirror will drop. When it is less than the reference voltage VREF, the detection circuit will immediately output a level rising edge. After passing through two delay units, a falling edge and a delayed rising edge are obtained respectively. After the peak ends, a rising edge and a falling edge are also obtained. The purpose is to obtain a negative pulse signal whose pulse width is only related to the delay time after the waveforms after the two delays are negated, which is used for subsequent digital signal processing.

[0035] Simulation Results

[0036] The circuit is simulated in the range of 0fC to 15fC, with a scanning interval of 1fC, and the result is Figure 6The output waveform of the present invention shows that the peak holding circuit with peak mark output can well follow the output waveform (PDHI) of the pre-stage filter shaper, and the maximum holding error is less than 3mV. Figure 7 As shown, the reference voltage VREF is set to 1.8V. It can be seen from the figure that the voltage at point VC begins to drop when the signal rises, and PO jumps from a low level to a high level when the peak is reached. After a delay of 20ns through the first delay unit, the first delayed signal DELAY1 is obtained, and after a delay of 45ns through the second delay unit, the first delayed signal DELAY2 is obtained. After the negation, the peak mark output signal PDO is obtained, which meets the expected output timing.

[0037] like Figure 8 As shown, a least squares fit is performed on the peak value of the PDHI (after subtracting the baseline) to obtain a fitting curve. The nonlinearity of each point is obtained by combining the fitting curve with the 15 simulated points. It can be seen that the nonlinearity of the entire hold circuit is less than 1%. Similarly, after fitting the PDH output, the nonlinearity is better than 4%. This shows that the peak hold circuit with a peak marker output of the present invention has a very low impact on linearity.

[0038] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0039] The above embodiments should be understood as merely illustrating the present invention and not as limiting the scope of protection of the present invention. After reading the contents of the present invention, technicians may make various changes or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A peak hold circuit with a peak mark output, characterized in that: It includes a peak holding circuit, a peak detection circuit and a peak mark output buffer. The input of the peak holding circuit comes from the output of the previous stage filter shaper. The two output ends of the peak holding circuit are the peak output and the current mirror voltage signal. The current mirror voltage signal is connected to the input end of the peak detection circuit. The output end of the peak detection circuit is connected to the peak mark output buffer and then outputs the peak mark signal to the back-end digital signal processing module. The peak holding circuit keeps the waveform of the previous stage voltage signal at its peak value. After the input signal passes through an inverting amplifier A, the inverting amplifier output terminal VC will decrease in the rising stage of the signal, and M The gate of the current mirror formed by PA and MPB is pulled low, at which point the current mirror charges the holding capacitor CH. When the signal is in the falling phase, the negative end of the inverting amplifier A is greater than the positive end, and the current mirror stops charging the holding capacitor, thereby achieving the peak hold power. The peak detection circuit is mainly composed of a comparator, the positive and negative ends of the comparator are respectively connected to the VC of the peak hold circuit and a reference voltage. When the VC voltage is lower than the reference voltage, the comparator output becomes a low level, achieving the function of sensing the peak. The peak mark output buffer consists of two delay units and a NAND gate logic, which converts the falling edge of the peak detection circuit output into a negative pulse signal. The peak hold circuit includes four PMOS transistors, namely MP1, MP2, MP3, and MP4, three NMOS transistors, namely MN1, MN2, and MN3, a holding capacitor CH, and two transmission gates T1 and T2, wherein T1 and T2 are controlled by external RESET and HOLD signals respectively. The sources of MP1, MP2, MP3, and MP4 and one end of T2 are connected to the power supply voltage VDD, the gates of MP1 and MP2 are connected and then connected to the drain of MP2 and the drain of MN2, the drain of MN1 is connected to the gates of MP3 and MP4 and then to the drain of MP3 as the output port VC, and VC is also connected to the other end of T2; the sources of MN1 and MN2 are connected to the drain of MN3, the gate of MN3 serves as the external bias voltage input terminal VBN, the source of MN3 and one end of CH are connected to the negative power supply VSS, the other end of CH is connected together with the drain of MP4 and the gate of MN2 as the peak output terminal PHO, and the gate of MN1 serves as the input terminal PDHI.

2. A peak hold circuit with a peak mark output according to claim 1, characterized in that: In the peak hold circuit, the PMOS transistors MP1 and MP2 and the NMOS transistors MN1, MN2, and MN3 form a dual-input common-source amplifier, wherein MP1 and MP2 serve as amplifiers and MN3 serves as a current source for two branches; MP3 and MP4 form a PMOS transistor current mirror to charge the holding capacitor CH; T1 is a transmission gate for resetting CH. When the RESET signal arrives, the upper end of CH will be fixed to a specified baseline level; T2 is a transmission gate for controlling the peak value of the holding capacitor. When a peak value is detected, in addition to the circuit automatically maintaining the peak value, an external HOLD signal is also input to pull the gate potential of the current mirror to the power supply voltage, causing the current mirror to stop charging CH and achieve a stable peak value; the maximum voltage change rate of the peak value is: Where V' imax The maximum voltage change rate maintained by the peak hold circuit, I dmax is the maximum current flowing through the PMOS current mirror, u p is the hole mobility, C ox is the unit capacitance of the gate oxide layer, V g is the gate voltage of the current mirror PMOS tube, V T is the threshold voltage of the PMOS tube, C h To maintain the capacitance value of the capacitor.

3. The peak hold circuit with a peak mark output according to claim 1, characterized in that: The peak detection circuit includes 7 PMOS transistors, namely MP5, MP6, MP7, MP8, MP9, MP10, and MP11, and 5 NMOS transistors, namely MN4, MN5, MN6, MN7, and MN8; the drain of MN4 and the sources of MP5 and MP6 are connected to the power supply voltage VDD, the source of MN4 is connected to the gate of MP8 and the drain of MN5, the sources of MN5, MN6, MN7 and MN8 and the gates of MP10 and MP11 are connected to the negative power supply VSS, the drain of MP5 is connected to the source of MP7, the drain of MP7 is connected to the sources of MP8 and MP9, the drains of MP8 and MP9 are connected to the sources of MP10 and MP11 respectively, the drain of MP10 and the drain of MN6 are connected to the gates of MN6 and MN7, the drain of MP9 is connected to the source of MP11, the drain of MP11 and the drain of MN7 are connected to the gate of MN8, and the drain of MP6 is connected to the drain of MN8 as the output PO of the peak detection circuit.

4. A peak hold circuit with a peak mark output according to claim 3, characterized in that: In the peak detection circuit, MN4 and MN5 form a source follower, which reduces the VC point voltage by the threshold voltage of an NMOS tube, and is used to provide a comparison voltage for the gate of the MP8 tube. MP5 and MP7 form a folded common source and common gate current mirror under the bias of the VBP common source tube bias voltage and the VCP common gate tube bias voltage respectively. MP8 and MP9 serve as amplifier tubes of the entire comparator, MP10, MP11, MN6 and MN7 serve as loads, MN8 and MP6 serve as the second-stage common source amplifier, and MN8 serves as an amplifier tube.

5. The peak hold circuit with a peak mark output according to claim 1, characterized in that: The peak mark output buffer includes 10 PMOS transistors MP12, MP13, MP14, MP15, MP16, MP17, MP18, MP19, MP20, and MP21, and 10 NMOS transistors MN9, MN10, MN11, MN12, MN13, MN14, MN15, MN16, MN17, and MN18. The sources of MP12, MP13, MN14, MP15, MP16, MP17, MP18, MP19, MP20, and MP21 are connected to the power supply VDD, and the sources of MN9, MN10, MN11, MN13, MN14, MN15, MN16, MN17, and MN18 are connected to the negative power supply VSS. MP12 and MN9 form an inverter, and MP11 is connected to the negative power supply VSS. The gate of MP2 is connected to the gate of MN9 as the input of the inverter, the drain of MP12 is connected to the drain of MN9 as the output of the inverter, MP13 and MN10, MP14 and MN11 form an inverter in the same way and are connected end to end, MP17 and MN14, MP18 and MN15, MP19 and MN16, MP20 and MN17, MP21 and MN18 also form an inverter in the same way and are connected end to end, the drains of MP15 and MP16 are connected to the drain of MN12 as the output PDO of the peak mark output buffer, the source of MN12 is connected to the drain of MN13, the gates of MP15 and MN13 are connected to the drain of MP14 and the gate of MP17, and the gates of MP16 and MN12 are connected to the drain of MP21.

6. The peak hold circuit with a peak mark output according to claim 5, characterized in that: The three inverters MP12 and MN9, MP13 and MN10, and MP14 and MN11 in the peak mark output buffer constitute the first delay unit, and the five inverters MP17 and MN14, MP18 and MN15, MP19 and MN16, MP20 and MN17, and MP21 and MN18 constitute the second delay unit. After the peak hold circuit senses the peak signal, the voltage signal at VC of the current mirror will drop. When it is less than the reference voltage VREF, the detection circuit will immediately output a rising edge of the level. After passing through two delay units, a falling edge and a delayed rising edge are obtained respectively. After the peak ends, a rising edge and a falling edge are also obtained. The purpose is to obtain a negative pulse signal whose pulse width is only related to the delay time after the waveform after the two delays is negated, which is used for subsequent digital signal processing.

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