Multilayer capacitors

Abstract

The invention relates to a multilayer capacitor (1), comprising a capacitor element (2), the capacitor element having at least two sections (2A, 2B), wherein each section comprises a plurality of layer planes, wherein a dielectric layer (5) consisting of ceramic and an electrode layer arranged therebetween are provided, wherein the dielectric layer and the electrode layer are arranged one above the other in a layer sequence, wherein the electrode layer comprises different electrodes, wherein at least a first and a second electrode (3, 4) are provided, wherein the different electrodes overlap in an active region (9A), wherein the different electrodes do not overlap in a passive region (9B), wherein a plurality of sections are arranged one above the other in a stacking direction, wherein the outermost dielectric layers of two sections form a connection region (12), in which the sections are firmly connected to one another parallel to the layer planes, wherein the connection region contains a load relief region (13), and wherein the load relief region occupies at least the entire passive region of the capacitor.

Description

Technical Field

[0001] The invention relates to a ceramic-based multilayer capacitor comprising dielectric layers and electrodes arranged between the dielectric layers. Background Art

[0002] Examples of multilayer capacitors are known to the person skilled in the art from the prior art.

[0003] In ceramic-based multilayer capacitors with piezoelectric properties, deformation of the electroceramic material generally occurs when a capacitor voltage is applied.

[0004] Frequent deformation will cause material fatigue and thus fracture of the ceramic material.

[0005] Furthermore, known multilayer capacitors have various other technical problems in use. Summary of the invention

[0006] It is therefore an object of the present invention to provide a multilayer capacitor having improved material properties and an improved geometry.

[0007] The objectives are at least partially achieved by the multilayer capacitor disclosed in the present invention.

[0008] Other implementations are found in the description that follows.

[0009] A multilayer capacitor is disclosed, comprising a capacitor element having at least two sections. The sections have a dielectric layer made of ceramic and an electrode layer arranged therebetween, the dielectric layer and the electrode layer being arranged one above the other in a layer sequence. The electrode layer comprises different electrodes, at least a first and a second electrode.

[0010] Different electrodes, ie for example the first and second electrode, overlap in the active region. The region where the different electrodes do not overlap is referred to as the inactive region.

[0011] In the inactive region, for example only electrodes of the same type overlap, ie only the first electrode or only the second electrode or only electrodes of any other identical type.

[0012] Additionally or alternatively, the inactive region may be a region of the capacitor element in which no electrodes are arranged. Such a region may be, for example, an edge region that adjoins the outer side of the capacitor element, since the electrodes generally do not extend over the entire width of the capacitor element.

[0013] Within the capacitor element, a plurality of segments are arranged one above the other in a stacking direction, wherein the outermost dielectric layers of two segments form a connection region in which the segments are firmly connected to one another parallel to the layer plane. The connection region is formed, for example, by the lowermost dielectric layer of the upper segment and the uppermost dielectric layer of the lower segment.

[0014] The two dielectric layers are firmly connected to each other, for example, by sintering. By sintering the sections arranged one above the other together, the adjacent dielectric layers are physically and chemically connected to each other.

[0015] Any number of segments can be connected to one another. A connecting region is formed between each two segments.

[0016] The connection region comprises a load-relief region which is arranged in a plane parallel to the electrodes. The load-relief region occupies at least the entire passive area of ​​the capacitor.

[0017] In the load relief area, the connection of the segments becomes weaker or interrupted. The load relief area keeps the mechanical stresses in the multilayer capacitor low. The thickness of the segments is preferably small so that the mechanical stresses in the segments do not cause cracks in the capacitor.

[0018] Preferably, the weak part is formed in the stacking direction, which corresponds to the field direction of the capacitor. The weak part can be realized by forming a gap or using materials with different elastic moduli, preferably materials with small elastic modulus values. Alternatively, the weak part can be realized by embedding a material that is harder or more brittle than the ceramic. Under load, the material will break.

[0019] Such mechanical stresses are generated, for example, when a capacitor voltage is applied. In particular, mechanical stresses between active and passive regions should be expected, since they are electrically loaded differently. If no load-relief regions are provided within the capacitor, such stresses can accumulate over the entire capacitor without hindrance.

[0020] Through weak points and interruptions in the connection of the segments, in particular in the passive region, a build-up of mechanical stresses is avoided, which would result in breaks or cracks in the capacitor.

[0021] In one embodiment, the relief region is designed as a region between the segments and parallel to the layer plane, in which the segments are not firmly connected to one another.

[0022] The described weakening of the connection between the segments can thereby be easily realized.

[0023] In one embodiment, the load-relief region is structured. In particular, the load-relief region can have at least one recess. For example, a connecting region is formed within the recess, in which the segments are firmly connected to one another, in particular firmly sintered to one another.

[0024] In one embodiment, the relief area is designed as a gap between the segments.

[0025] In particular, the dielectric layers of different sections can be spaced apart from one another in the relief region. The dielectric layers can also lie against one another in the relief region and not be connected to one another or only partially or only with reduced adhesion.

[0026] In at least one embodiment, the gap between the segments is smaller than the thickness of the dielectric layer. The individual layer planes of the capacitor element generally each have the same layer thickness.

[0027] In one embodiment of the multilayer capacitor, the load relief region comprises a material having an elastic modulus that is different from the elastic modulus of the dielectric layer.

[0028] In order to produce a multilayer capacitor, a green film, in particular a ceramic green film, is provided to form a dielectric layer. A first paste, for example containing an organic or inorganic material, is applied, for example printed, on at least one green film which will later form the outer dielectric layer of the segment. The first paste is preferably applied only at the locations where the load relief areas are provided.

[0029] A second metallic paste for the electrode material is printed on the other green film that will later form the inner dielectric layer of the segment. Printing and coating can be performed by applying the electrodes alternately in the stack slightly offset relative to one another, whereby they can then be contacted in a comb-like manner on one side at their respective exit surfaces.

[0030] The green film is provided as a sintered stack. Preferably, the first paste is designed in such a way that co-sintering of the dielectric layer is completely or partially prevented at the locations where the first paste is applied, so that a load-relief region is formed in this manner.

[0031] The coated and pressed stack can then be singulated into individual capacitors in a mass production process.

[0032] After cutting, the binder is first baked out of the segmented capacitors (debinding). This is followed by a firing process (sintering). Here, the ceramic powder is sintered at a temperature preferably between 900° C. and 1200° C. and acquires its final, mostly crystalline structure. During the process, the individual dielectric layers are connected to form a monolithic structure. The dielectric layers of the segments arranged one above the other are also firmly connected to one another.

[0033] The ceramic acquires its desired dielectric properties only through this firing process. The firing process is followed by a cleaning step and, in at least one embodiment, the application of the external contacts.

[0034] In one embodiment, the load relief region is formed at least in all regions adjoining the outer side of the capacitor element.

[0035] In one embodiment, the depth to which the relief region extends from the outside into the capacitor element is approximately the stack height of the section adjacent to the relief region or the dimension between the uppermost and lowermost electrodes in an adjacent section. Adjacent sections usually each have the same stack height.

[0036] In another embodiment, the depth of the inactive region at the outside of the capacitor is approximately the stack height of the adjacent segments.

[0037] In one embodiment, the depth of the relief region extending from the outside into the capacitor element corresponds to twice the depth of the passive region at the outside of the capacitor. The depth of the relief region is therefore related to the depth of the passive region.

[0038] Such a dimensioning of the relief region prevents a build-up of mechanical stresses which would lead to cracks or similar fatigue phenomena in the capacitor.

[0039] Additionally or alternatively, in one embodiment, the relief region can include further sections which are not formed directly on the outside of the capacitor element. In this case, the dimensions of the relief region should again correspond at least to the dimensions described in the previous paragraph.

[0040] In one embodiment, the unloading region is at least partially arranged in the region in which the different electrodes overlap. Thus, the unloading region is at least partially formed in the active region of the capacitor element.

[0041] In this embodiment, the load relief region also includes all regions of the connection region which are arranged in the inactive region of the capacitor element.

[0042] Such an enlarged load relief area further reduces the mechanical stress between the individual sections.

[0043] In one embodiment, the relief region has at least one section which does not adjoin the outer side of the capacitor element.

[0044] In one embodiment, the connection region comprises a plurality of mutually spaced-apart load-relief regions.

[0045] In one embodiment, the connection region comprises a plurality of mutually spaced-apart relief regions which at least partially do not adjoin the outer side of the capacitor element.

[0046] The last three embodiments are advantageous in particular in the case of large capacitor diameters.

[0047] Such an enlarged load-relief region or regions in the connecting region further reduces the mechanical stresses between the individual segments.

[0048] In one embodiment of the multilayer capacitor, the first and the second electrode at least partially overlap.

[0049] The first and second electrodes form, in their overlapping region, an active region in which an electric field acts, so that mechanical stresses are generated within the dielectric layer.

[0050] In one embodiment, the electrode comprises one or more of copper, silver, nickel, platinum and palladium. These metals are particularly suitable due to their high electrical conductivity.

[0051] For easy and cost-effective production, it is preferred to sinter the entire multilayer capacitor in one step, as described above. The sintering step is therefore carried out after the individual layers have been stacked.

[0052] In order to implement this method, the sintering temperature of the ceramic used for the dielectric layer must not exceed the melting temperature of the metal used for the electrode. This can be achieved by selecting a suitable electrode metal or a suitable ceramic.

[0053] In at least one embodiment, two separate external contacts are applied on a relief surface on the outer side of the capacitor element for contacting the first and second electrodes, wherein the electrodes relief from the capacitor element on the relief surface.

[0054] The external contacts are preferably applied to opposite outer surfaces of the multilayer capacitor.

[0055] In contrast, any third electrode or further electrodes are not contacted by the external contact.

[0056] In one embodiment of the multilayer capacitor, each segment includes at least three different types of electrode layers, wherein in a first electrode layer, a first electrode and a second electrode are formed opposite to each other and separated by a dielectric segment, in a second electrode layer only the first electrode is formed and in a third electrode layer only the second electrode is formed, and wherein the first electrode layer respectively forms the outermost electrode layer of each segment in the stacking direction.

[0057] The first electrode and the second electrode are opposed to each other in the first electrode layer in a direction perpendicular to the stacking direction of the multilayer capacitor. Dielectric layers are respectively formed between the electrode layers.

[0058] The described embodiment has the advantage that, since the first and second electrodes each have the same electrical polarization as the adjacent external contact, no electrical fields are formed in the outer sections of the sections or between two sections.

[0059] Furthermore, the electrodes of the first electrode layer are also partially adjacent to electrodes of the same electrical polarization within the segment. Therefore, no electric field is formed in a relatively large area. Therefore, the individual layers within the active area of ​​the segment also have no electric field.

[0060] Thus, the undesired migration of charged particles from the outside into the interior of the capacitor can be avoided. This has the advantage of greater resistance to material changes caused by moisture.

[0061] In one embodiment, the multilayer capacitor comprises at least one third electrode which is not in contact with any external contact, wherein the third electrode layer overlaps the first electrode and the second electrode.

[0062] Such electrodes are also called "floating" electrodes or "schwebende" electrodes in German.

[0063] In one embodiment, the multilayer capacitor comprises at least one third electrode which does not adjoin any outer side of the capacitor element.

[0064] Preferably, the multilayer capacitor and in particular each section of the multilayer capacitor has a plurality of first electrodes, a plurality of second electrodes and a plurality of third electrodes.

[0065] In one embodiment, the capacitor has at least one series circuit of two capacitances. In particular, the first capacitance can be formed by overlapping at least one first electrode with at least one third electrode, and the second capacitance can be formed by overlapping at least one second electrode with at least one third electrode.

[0066] In one embodiment, the multilayer capacitor comprises a further electrode which is arranged in an inactive region of the capacitor and does not overlap with electrodes of different polarity.

[0067] Therefore, no electric field is formed between these electrodes. Such electrodes are called passive or blind electrodes.

[0068] The mechanical stresses which usually occur between regions with electrodes and regions without electrodes within the capacitor element are reduced by such blind electrodes.

[0069] The combined use of blind electrodes and load relief regions can therefore minimize mechanical stresses in the multilayer capacitor and increase the robustness of the capacitor. In this way, the thermomechanical and electrical load capacity of the multilayer capacitor can be optimized.

[0070] In a further embodiment, the external contact comprises a multi-layer sputtered layer, which comprises a layer composed of chromium, nickel and at least one of silver or gold, wherein the layers are applied to the exit surface in this order.

[0071] The chromium layer applied directly to the exit surface enables high adhesion of the sputtered layer at the exit surface. The layer composed of silver or gold has high electrical conductivity and is therefore mainly used for electrical contact between electrodes. All electrodes of one type can be electrically connected to each other and thus connected in parallel by the sputtered layer described.

[0072] The intermediate layer consisting of nickel serves as a diffusion barrier. For example, all first electrodes that all exit from the capacitor element at the same first face can be electrically connected to each other via the first sputtered layer. Furthermore, all second electrodes that all exit at the second face can be electrically connected or connected in parallel via a further second sputtered layer, so that, for example, the entire stack including all first electrodes and all second electrodes forms a single multilayer capacitor.

[0073] In one embodiment, the external contact further comprises a fine-mesh copper grid applied on the sputtered layer.

[0074] The copper grid covers the entire sputtered layer and thus prevents cracks from forming in the sputtered layer or even detachment of the sputtered layer in the event of mechanical deformation of the capacitor element.

[0075] In one embodiment, the external contact further comprises a metal sheet, through which the capacitor element is contacted to the outside. The metal sheet is arranged on the sputtered layer.

[0076] In one embodiment, the metal sheet is attached to the sputtered layer by means of a solder connection.

[0077] In a further embodiment, the metal sheet is applied to the sputtered layer by means of a sintered silver layer.

[0078] The sputtered layer described generally has a thickness in the nanometer range, while the silver layer has a thickness in the micrometer range. This sintered silver layer covering the entire sputtered layer holds the sputtered layer together in the event of deformation of the capacitor element and, for example, prevents the sputtered layer from detaching.

[0079] The silver layer also fixes the metal sheet on the sputtered layer. Therefore, no additional solder connection is required. For this purpose, silver is applied to the sputtered layer and the metal sheet is placed directly on it. The silver layer is sintered only after the metal sheet is placed at the lowest possible pressure.

[0080] In at least one embodiment, the silver layer is sintered at low pressure to achieve a residual porosity of about 35%.

[0081] This porosity is small enough to only slightly reduce the electrical and thermal conductivity of the silver. Due to its high electrical and thermal conductivity, the silver layer also enables a good electrical connection of the metal sheet on the sputtered layer. In addition, however, the silver with the porosity described has a sufficiently high ductility to ensure thermomechanical relief.

[0082] Furthermore, sintered silver layers have less material fatigue under mechanical or thermomechanical loads than, for example, soldered layers.

[0083] Since the process temperatures during sintering are generally lower than during soldering, relatively low thermomechanical stresses also occur and the process can be carried out relatively simply and cost-effectively.

[0084] In the case of pure silver, the high melting point of the sintered silver of up to 962° C. ensures a high temperature stability of the silver layer, which enables further process steps at high temperatures.

[0085] In one embodiment, the metal sheet includes two copper layers and an Invar layer disposed therebetween.

[0086] Copper has particularly good electrical and thermal conductivity.

[0087] An iron-nickel alloy containing approximately 1 / 3 nickel and 2 / 3 iron is called Invar. This material has a particularly low coefficient of thermal expansion. In particular, the coefficient of thermal expansion is close to that of ceramics. Due to the combination with copper, sufficient conductivity of the connection contacts can be ensured despite the low electrical conductivity of Invar.

[0088] As an alternative to Invar, other iron-nickel alloys or iron-nickel-cobalt alloys can also be used.

[0089] To produce the described metal sheet, for example, a copper layer is rolled onto an Invar sheet.

[0090] The outer surface of the copper layer may be silver plated in order to improve the bond between the copper and the sintered silver layer. In one embodiment, the silver plated portion is applied by electroplating.

[0091] In one embodiment, the metal sheet of the external contact includes a copper layer having a meander-shaped geometry.

[0092] The copper layer is applied directly to the silver layer. The copper layer preferably has a meandering, grid-like geometry. The copper layer can also be silver-plated. The silver plating is preferably performed by electroplating. The copper layer can be sintered directly to the silver layer.

[0093] Due to its excellent thermal and electrical conductivity, copper is preferably used for the external contacts of the capacitor.

[0094] In one embodiment, the multilayer capacitor comprises separable capacitor elements which can be assembled and disassembled as desired at contact surfaces, wherein the contact surfaces are arranged normal to the layer planes and the external contacts.

[0095] Thus, multilayer capacitors of any desired size can be flexibly constructed. The described capacitor elements can be produced in standard sizes in series production and then assembled as required.

[0096] The individual capacitor elements can be fixed, for example, via a sintered silver layer applied to the outer surfaces, which extends over the outer surfaces of all capacitor elements and thus holds them together.

[0097] In one embodiment, the ceramic is an antiferroelectric dielectric.

[0098] The dielectric layers may have piezoelectric or electrostrictive properties, so that when a voltage is applied across the multilayer capacitor, the layers deform.

[0099] In one embodiment, the ceramic comprises lead zirconate titanate. Lead zirconate titanate generally crystallizes in a perovskite structure. Such ceramics are antiferroelectric dielectrics, which can be advantageously used in the multilayer capacitors.

[0100] In one embodiment, the ceramic has the following composition, which has advantageous properties when used in capacitors:

[0101] Pb( y-1.5a-0.5b+c+0.5d-0.5e-f )Ca a A b (Zr 1-x Ti x ) (1-c-d-e-f) E c Fe d Nb e W f O3,

[0102] Wherein A is selected from the group consisting of Na, K and Ag; E is selected from the group consisting of Cu, Ni, Hf, Si and Mn; and applicable is

[0103] 0.05≤x≤0.3;

[0104] 0 <a<0.14;

[0105] 0≤b≤0.12;

[0106] 0≤c≤0.12;

[0107] 0≤d≤0.12;

[0108] 0≤e≤0.12;

[0109] 0≤f≤0.12;

[0110] 0.9≤y≤1.5 and

[0111] 0.001 <b+c+d+e+f。

[0112] The ceramic has a low sintering temperature of between 900° C. and 1200° C. Furthermore, the ceramic is characterized by a high resistance and low material fatigue.

[0113] In one embodiment, the ceramic has the following composition, which has similar advantageous properties when used in capacitors:

[0114] Pb (1-1.5a-0.5b+1.5d+e+0.5f) A a E b (Zr 1-x Ti x ) (1-c-d-e-f) Li d G e Fe f Si c O3+y PbO,

[0115] in

[0116] A is selected from the group consisting of La, Nd, Y, Eu, Gd, Tb, Dy, Ho, Er and Yb;

[0117] E is selected from the group consisting of Na, K and Ag;

[0118] G is selected from the group consisting of Cu, Ni, Co and Mn;

[0119] And applicable

[0120] 0.1≤x≤0.3;

[0121] 0 <a≤0.12;

[0122] 0≤b≤0.12;

[0123] 0≤c≤0.12;

[0124] 0≤d≤0.12;

[0125] 0 <e≤0.12;

[0126] 0≤f≤0.12;

[0127] 0≤y≤1 and

[0128] 0 <b+d+e+f。

[0129] In another embodiment, the ceramic has the following composition, which has similar advantageous properties when used in capacitors:

[0130] Pb (1-1.5a+e) A a (Zr 1-x Ti x ) (1-c-e) E e Si c O3+y PbO,

[0131] in

[0132] A is selected from the group consisting of La, Nd, Y, Eu, Gd, Tb, Dy, Ho, Er and Yb;

[0133] E is selected from the group consisting of Cu and Ni;

[0134] And it applies to

[0135] 0.05≤x≤0.3;

[0136] 0 <a≤0.12;

[0137] 0≤c≤0.12;

[0138] 0.001≤e≤0.12 and

[0139] 0≤y<1.

[0140] In another embodiment, the ceramic comprises sodium strontium titanate. This ceramic is also an antiferroelectric dielectric, which can be advantageously used in the multilayer capacitor.

[0141] In one embodiment, the ceramic has the following composition, which has advantageous properties when used in capacitors:

[0142] [Pb (1-r) (Ba x Sr y Ca z ) r ] (1-1.5a-1.5b-0.5c) (X a Y b )A c (Zr 1-d Ti d )O3,

[0143] wherein X and Y are each a rare earth metal selected from the group consisting of La, Nd, Y, Eu, Gd, Tb, Dy, Ho, Er and / or Yb; A is a monovalent ion;

[0144] Applicable to

[0145] x+y+z=1;

[0146] 0≤x;

[0147] 0 ≤ y;

[0148] 0 ≤ z;

[0149] 0 < r ≤ 0.3;

[0150] 0 < d ≤ 1;

[0151] 0 < a ≤ 0.2;

[0152] 0 ≤ b ≤ 0.2 and

[0153] 0 < c ≤ 0.2.

[0154] In another embodiment, the ceramic has the following composition, which also has advantageous properties when used in a capacitor:

[0155] (Bi a Na b Sr c )(Mg d Ti 1-d )O3,

[0156] wherein applicable

[0157] 0.10 ≤ a ≤ 0.65;

[0158] 0 < b ≤ 0.45;

[0159] 0 < c ≤ 0.85;

[0160] 0 < d < 0.20 and

[0161] 0.95 ≤ a + b + c ≤ 1.05.

[0162] In another embodiment, the ceramic has the following composition, which also has advantageous properties when used in a capacitor:

[0163] (Bi a Na b Sr c )(Zn d Ti 1-d )O3,

[0164] wherein applicable

[0165] 0.09 ≤ a ≤ 0.58,

[0166] 0.09 ≤ b ≤ 0.42,

[0167] 0.05 ≤ c ≤ 0.84;

[0168] 0 < d ≤ 0.08 and

[0169] 0.95 ≤ a + b + c ≤ 1.05.

[0170] In addition to the compositions mentioned, further compositions which are not mentioned exhaustively are also possible.

[0171] A capacitor having the above-mentioned characteristics is suitable for use as a DC link capacitor or a buffer capacitor.

[0172] Due to the characteristics of capacitors, in some applications no additional snubber capacitor is used when used as a DC link capacitor.

[0173] Another application of the described capacitors is as filter capacitors. Due to their high-frequency properties, interfering signals up to the MHz range can be effectively attenuated and filtered. BRIEF DESCRIPTION OF THE DRAWINGS

[0174] The present invention is described in detail below based on the embodiments. The present invention is not limited to the examples listed.

[0175] The accompanying drawings show:

[0176] Figure 1 A schematic side view of a first specific embodiment not according to the invention showing a multilayer capacitor comprising a first and a second electrode in one section.

[0177] Figure 2 A schematic side view of a second exemplary embodiment of a multilayer capacitor comprising a first and a second electrode in two sections is shown.

[0178] Figure 3 A schematic plan view of a second exemplary embodiment of a multilayer capacitor comprising a first and a second electrode in two sections is shown.

[0179] Figure 4 A schematic side view of a third exemplary embodiment of a multilayer capacitor comprising a first and a second electrode in two sections is shown.

[0180] Figure 5 A schematic plan view of a third exemplary embodiment of a multilayer capacitor comprising a first and a second electrode in two sections is shown.

[0181] Figure 6 A schematic side view of a fourth exemplary embodiment of a multilayer capacitor comprising a first, a second and a third electrode in two sections is shown.

[0182] Figure 7 A schematic plan view of a fourth exemplary embodiment of a multilayer capacitor comprising a first, a second and a third electrode in two sections is shown.

[0183] Figure 8 A schematic side view of a fifth exemplary embodiment of a multilayer capacitor comprising a first and a second electrode in two sections is shown.

[0184] Fig. 9 A schematic plan view of a fifth exemplary embodiment of a multilayer capacitor comprising a first and a second electrode is shown in two sections.

[0185] Fig.10 A schematic side view of a sixth exemplary embodiment of a multilayer capacitor comprising a first and a second electrode in two sections is shown.

[0186] Fig.11 A schematic plan view of a sixth exemplary embodiment of a multilayer capacitor comprising a first and a second electrode in two sections is shown.

[0187] Fig.12 A schematic side view of a seventh exemplary embodiment of a multilayer capacitor comprising first to sixth electrodes in two sections is shown.

[0188] Fig.13 A schematic plan view of a seventh exemplary embodiment of a multilayer capacitor comprising first to sixth electrodes in two sections is shown.

[0189] Fig.14 A schematic side view of an eighth exemplary embodiment of a multilayer capacitor comprising first and second, and fourth and fifth electrodes in two sections is shown.

[0190] Fig.15 A schematic plan view of an eighth exemplary embodiment of a multilayer capacitor comprising a first and a second, as well as a fourth and a fifth electrode in two sections is shown.

[0191] Fig.16 A ninth exemplary embodiment of a multilayer capacitor including an external contact is shown in a schematic side view.

[0192] Fig.17 A schematic side view shows a metal plate of an external contact of a ninth exemplary embodiment of a multilayer capacitor. DETAILED DESCRIPTION

[0193] Figure 1 A first exemplary embodiment of a multilayer capacitor 1 is shown. The drawing is essentially limited to the illustration of a capacitor element 2. Other components such as external contacts are Figure 1 Not shown in FIG.

[0194] The capacitor 1 shown is constructed similarly to the example according to the invention of a multilayer capacitor, but does not include the connection region and the load relief region.

[0195] The capacitor element 2 comprises a stack comprising three first electrodes 3, three second electrodes 4 and dielectric layers 5 arranged between or around the electrodes. The layers are arranged one above the other in a defined stacking direction.

[0196] The first electrode 3 and the second electrode 4 extend away from the cuboid capacitor element 2 at two opposite sides. These surfaces are referred to as first and second exit surfaces 6 / 7. The exit surfaces 6 / 7 are arranged normal to the stacking direction.

[0197] At the exit surface 6 / 7, the electrodes respectively related are connected to each other via conductive external contacts 8. The external contacts 8 respectively cover most of the exit surface 6 / 7. In other embodiments, the external contacts 8 can also cover a smaller part of the exit surface 6 / 7 or the entire exit surface 6 / 7.

[0198] Since the electrodes 3 / 4 do not extend to the respectively opposite exit surfaces 7 / 6, two regions to be distinguished are obtained in the multilayer capacitor 1. In these regions, the first and second electrodes 3 / 4 overlap in the center of the capacitor element 2. These regions are referred to as active regions 9A. In the regions adjacent to the exit surfaces, only the first electrode or only the second electrode 3 / 4 is respectively present. These regions are referred to as inactive regions 9B.

[0199] On both side surfaces of the capacitor element 2, a region without electrodes is adjacent normal to the exit surface 6 / 7 and normal to the stacking direction. These regions are also referred to as inactive regions 9B (see Figure 3 ).

[0200] The overlapping electrodes 3 / 4 act as a capacitor when a voltage is applied via the external contact 8 . Due to the voltage between the first and second electrodes 3 / 4 , an electric field then acts in the active region 9A of the multilayer capacitor 1 .

[0201] It should be noted here that the electric field does not necessarily have to be present over the entire stack height in the active region 9A. Rather, the electric field is only formed between electrodes of different electrical polarizations, i.e., for example, in the dielectric layer 5 arranged between the first and second electrodes 3 / 4. Between the internal electrode and the external contact, a field is also formed when the electrical polarization is different.

[0202] The dielectric layer 5 of the present multilayer capacitor 1 consists of an antiferroelectric ceramic material. In an electric field, polarization of the domains of the crystal structure of the ceramic occurs.

[0203] The electrodes are made of conductive materials such as copper, silver, nickel, palladium or platinum.

[0204] The polarization causes lattice deformations in the ceramic. Due to the lattice deformations, mechanical stresses are generated within the multilayer capacitor 1. Due to the small stack height, these mechanical stresses can be neglected in the first example.

[0205] The ceramic material of this embodiment is a perovskite ceramic. Perovskite ceramics generally have antiferroelectric properties. Due to the composition of the ceramic corresponding to any one of the embodiments, favorable properties for capacitors such as high mechanical resistance and long service life can also be achieved.

[0206] exist Figure 2 and Figure 3 The multilayer capacitor 1 shown in corresponds substantially to the multilayer capacitor 1 of the first example.

[0207] exist Figure 3 In the plan view of FIG. 1 , the side surfaces 10 / 11 of the capacitor element 2 already described above are also drawn normal to the exit surface 6 / 7 and normal to the stacking direction.

[0208] Except in Figure 1 In addition to the capacitors shown in Figure 2 and 3 The capacitor in the embodiment has a second section, wherein the sections are arranged one above the other in the stacking direction. The individual sections of the second embodiment correspond to the sections of the first example.

[0209] The segments are connected via the connection region 12. Within the connection region 12 there is a relief region 13. The second exemplary embodiment is therefore an implementation of the claimed invention. Features and characteristics of the multilayer capacitor 1 of the second example which correspond to the first example are not elaborated again.

[0210] The connection region 12 comprises the same dielectric ceramic material as the dielectric layers in the sections 2A and 2B of the capacitor element 2 .

[0211] The connection region 12 includes the lowermost dielectric layer of the first section 2A and the uppermost dielectric layer of the second section 2B which are arranged one above the other in the stacking direction. There is no electrode in the connection region 12 .

[0212] At the edge of the connection region there is a continuous relief region 13 along the entire outer circumference of the capacitor element 2. The relief region 13 is arranged between the lowermost dielectric layer of the first section 2A and the uppermost dielectric layer of the second section 2B.

[0213] The depth of the relief region 13 , measured from the outer side of the capacitor element 2 to the innermost point in the capacitor element 2 , preferably corresponds to the stack height of the segments.

[0214] This ensures that mechanical stresses caused by deformation of the ceramic in an electric field do not build up over the segments and thus lead, for example, to cracks in the material.

[0215] The relief region 13 includes all inactive regions 9B of the multilayer capacitor 1. That is, the relief region 13 is arranged within the connection region 12 parallel to all sections of the segment that include only one electrode or no electrode. In addition, the relief region 13 extends partially into the active region 9A of the capacitor element 2.

[0216] Observed from the stacking direction, as in Figure 3As shown in FIG. 1 , the active region 9A has a rectangular shape. The inactive region 9B forms a rectangular frame surrounding the active region 9A. The load relief region 13 forms a rectangular frame surrounding the inactive region 9B and furthermore partially overlapping the active region 9A.

[0217] The stress relief region 13 is the region in which the dielectric layers 5 stacked one above the other are not firmly connected to one another or are only partially connected to one another.

[0218] To manufacture such a multilayer capacitor 1 according to the second embodiment, a ceramic green film containing a perovskite material is provided to constitute the dielectric layer 5. A first paste containing an organic material is printed onto the uppermost green film of the second section 2B.

[0219] A second paste of metal is printed onto the other green film in the desired areas to form electrodes. The green films are arranged into a stack which is sintered.

[0220] The organic first paste is designed to completely or partially prevent sintering of the dielectric layer 5 at the locations where the first paste is applied, so that a stress-relief region 13 is formed there.

[0221] Figure 4 and 5 A further exemplary embodiment of a multilayer capacitor 1 according to the invention is shown.

[0222] The main features of embodiment 3 correspond to those of embodiment 2. These features are not restated.

[0223] In this example, in addition to the outer section 13A along the circumference of the capacitor element 2, the load relief area 13 also includes an inner section 13B extending between the outer sides parallel to the exit surface 6 / 7 of the capacitor element 2. The width of the inner section can be changed arbitrarily. In this embodiment, the width of the inner section is greater than the width of the outer section.

[0224] The inner section of the relief region 13 is arranged completely parallel to the active region 9A of the multilayer capacitor 1 .

[0225] Even in the case of large dimensions of the individual layers or high stack heights, an accumulation of mechanical stresses occurring in the capacitor 1 can be effectively avoided by means of such an additional inner section of the relief region 13 .

[0226] The relief region 13 has the shape of a rectangular frame when viewed in the stacking direction, the long sides of which are connected by means of cross members which correspond to the inner section of the relief region 13 .

[0227] It should be noted that in the illustrated construction of the third exemplary embodiment of the capacitor 1, it is possible for charged particles to migrate undesirably from the outside to the inside of the capacitor. Charged particles can be, for example, protons which are present in the outer surface of the capacitor 1 due to moisture. The reason for this is that an electric field is formed in the outermost dielectric layer 5A of the capacitor 1 between the uppermost second electrode 4A and the first external contact. This effect is further enhanced if the external contact also covers a part of the upper side 1A of the capacitor 1, for example due to errors during coating.

[0228] exist Figure 6 and Figure 7 Detailed Description of the Invention A fourth exemplary embodiment of a multilayer capacitor 1 is shown, the features of which partially correspond to those of the preceding exemplary embodiments. These features will not be explained again.

[0229] Unlike the previous embodiments, the multilayer capacitor 1 in the fourth embodiment includes a third electrode 14 in addition to the first and second electrodes. The third electrode 14 is an internal so-called floating electrode that is not adjacent to the outside of the capacitor element 2. Therefore, the third electrode 14 is not contacted from the outside.

[0230] In contrast to the previous exemplary embodiments, the first and second electrodes 3 / 4 are each arranged in the same layer plane, but are furthermore separated by a dielectric section.

[0231] The layer plane including the third electrode 14 is arranged between the layer planes including the first and second electrodes.

[0232] This forms a multilayer capacitor 1 comprising two capacitors connected in series: a first capacitor 1B formed between the first and third electrodes and a second capacitor 1C formed between the third and second electrodes.

[0233] Between the two active regions 9A of the capacitors 1B and 1C there is an inactive region 9B in which only the third electrode 14 is present, so that electrodes of different types do not overlap.

[0234] In the present exemplary embodiment, the relief region 13 is designed similarly to the third exemplary embodiment. The relief region 13 therefore comprises an outer section and an inner section along the circumference of the capacitor element 2 .

[0235] Furthermore, due to the additional inner section, the entire inactive region 9B of the capacitor element 2 is covered by the relief region 13. Furthermore, the relief region 13 also extends into the outer regions of the two active regions 9A of the capacitors 1B and 1C.

[0236] Furthermore, in the fourth embodiment described, it is advantageous that no electric field is formed between the outermost first or second electrode 3A / 4A and the adjacent outer contact of each segment 2A / 2B of the capacitor 1, since they each have the same electrical polarization. Therefore, there is also no electric field in the individual layers within the active region 9A.

[0237] It is thus possible to avoid an undesired migration of charged particles from the outside into the interior of the capacitor 1. Such charged particles may be protons, for example, which may be present on the outside of the capacitor 1 due to moisture.

[0238] Figure 8 and Fig. 9 There is shown a fifth example of the multilayer capacitor 1. Features corresponding to the previous embodiments are not re-described.

[0239] The multilayer capacitor 1 shown again comprises only the first and second electrodes. However, the electrodes have different dimensions. In a first layer plane, the first and second electrodes are arranged opposite each other and are separated by a dielectric section. The first layer plane is designed similarly to the fourth embodiment.

[0240] Since the first and second electrodes 3B, 4B each have the same electrical polarization as the adjacent external contacts, no electrical field is formed in the outer sections of the sections 2A / 2B or between the two sections.

[0241] In addition, unlike electrodes 3A and 4A, electrodes 3B and 4B are not adjacent to electrodes of opposite polarization within capacitor 1. Therefore, no electric field is formed in a relatively large area. Therefore, there is no electric field in the layers within active region 9A.

[0242] In the described embodiment, it is again advantageous that no electric field is formed between the outermost first or second electrode 3A / 4A / 3B / 4B and the adjacent external contact of each segment 2A / 2B of the capacitor 1, since these each have the same electrical polarization. Undesired migration of charged particles from the outside into the interior of the capacitor 1 can thus be avoided.

[0243] This has the advantage of greater resistance to material changes caused by moisture.

[0244] The distance between the first electrode and the second electrode in the first layer plane corresponds at least to the thickness of the dielectric layer 5 in the stacking direction. The distance is preferably 1.5 to 3 times the thickness. Thus, for example, a current flow directly from the first electrode 3B to the opposite second electrode 4A can be avoided.

[0245] The maximum size of the electrode in the first layer plane is predetermined by the spacing. The minimum size of the same electrode corresponds to the depth of the inactive region 9B along the outer circumference of the capacitor. The depth of the electrode preferably corresponds to at least twice this depth.

[0246] In addition, there is a second layer plane, in which only the first electrode 3 is present, and a third layer plane, in which only the second electrode 4 is present. In these layer planes, the corresponding electrodes extend almost to the opposite exit surface. The distance of the electrodes from the opposite exit surface corresponds to the depth of the passive region along the circumference of the layer plane. These layer planes are constructed similarly to the third embodiment.

[0247] The second layer planes and the third layer planes are arranged alternately one above the other, with dielectric layers 5 respectively located between them.

[0248] The connecting region 12 and the load-relief region 13 are designed as in the previous example. The load-relief region 13 comprises an outer frame-like section and an inner cross-beam-like section.

[0249] The outer passive region 9B and a part of the inner active region 9A are covered by the load relief region 13, as shown in Figure 5 As shown in the graphic.

[0250] In contrast to the fourth exemplary embodiment, here no inactive region 9B is present in the center of capacitor element 2 .

[0251] Fig.10 and 11 A sixth exemplary embodiment of a multilayer capacitor 1 is shown. The individual sections are constructed similarly to the fourth exemplary embodiment. However, the sixth exemplary embodiment differs from the fourth exemplary embodiment in the type of representation of the relief region 13 .

[0252] While in the fourth embodiment, there is only a single section of the relief region 13B in the interior of the capacitor in addition to the outer section of the relief region 13A, the sixth embodiment has a plurality of different sections 13B in the interior. All these sections 13B are connected to each other or to the outer section 13A of the relief region. These sections are preferably designed so that a uniform relief of mechanical stresses can be achieved. The inner sections 13B of the relief region can be arranged parallel to each other or cross each other. The number of sections and their shape and size can be changed arbitrarily.

[0253] Fig.12 and 13 A further embodiment of a multilayer capacitor 1 is shown. Embodiment 7 corresponds essentially to embodiment 4. It comprises a first, a second and a third electrode 3 , 4 and 14 .

[0254] In contrast to the fourth embodiment, the seventh embodiment also shows fourth, fifth and sixth electrodes 15, 16 and 17. These are blind electrodes that fill the inactive region 9B and do not themselves produce the active region 9A.

[0255] The fourth and fifth electrodes 15 and 16 are arranged in the outer passive region of the capacitor element 2. They are arranged close to the external contacts and can touch them. The fourth and fifth electrodes do not generate an electric field because they only overlap with electrodes of the same polarity.

[0256] The fourth electrode 15 that is in contact with the first external contact only overlaps with such fourth electrode 15 or the first electrode 3 .

[0257] The fifth electrode 16 that is in contact with the second external contact only overlaps with such fifth electrode 16 or the second electrode 4 .

[0258] In the same layer plane as the first and second electrodes, the sixth electrode 17 is arranged centrally in the capacitor element 2 between the first and second electrodes 3 and 4. The sixth electrode 17 overlaps only with the other sixth electrode 17 and the third electrode 14. Since there is no overlap of different electrodes of different polarity in this region, this is also an inactive region 9B of the capacitor element 2. In the present exemplary embodiment, the sixth electrodes are arranged congruently one above the other in the stacking direction.

[0259] Perpendicularly to the field direction, the distance between the blind electrode and the active electrode corresponds at least to the thickness of the dielectric layer 5 , preferably to 1.5 to 3 times the thickness of the dielectric layer 5 .

[0260] The use of blind electrodes reduces mechanical stress and mechanical stretching that would normally occur between regions with electrodes and regions without electrodes.

[0261] Thus, by using blind electrodes and relief regions, mechanical stresses in the multilayer capacitor 1 can be minimized and the robustness of the capacitor can be increased. The thermomechanical and electrical load capacity of the multilayer capacitor 1 can thus be optimized.

[0262] Fig.14 and Fig.15 An eighth exemplary embodiment of a multilayer capacitor 1 is shown which corresponds substantially to a combination of the fifth and seventh exemplary embodiments.

[0263] In this embodiment, in addition to the first and second electrodes 3 and 4, there are fourth and fifth electrodes 15 and 16 along the outer circumference of the electrode layer. The fourth and fifth electrodes 15 and 16 are in the same layer as the first and second electrodes 3 and 4.

[0264] The fourth and fifth electrodes 15, 16 are configured as blind electrodes similar to embodiment 7. The fourth and fifth electrodes overlap only with electrodes of the same polarity. The distance between the fourth and fifth electrodes 15, 16 and the active electrode preferably corresponds to 1.5 to 3 times the thickness of the dielectric layer 5, but at least corresponds to the thickness of the dielectric layer 5, so as to avoid current flow between the active electrode and the opposite blind electrode.

[0265] Thus, the electrodes 15A and 16B in each outermost segment layer fulfil the same purpose as the electrodes 3A and 4B in the fifth embodiment, but are formed at the minimum suitable depth.

[0266] Since the layer containing the first and fourth electrodes or the second and fifth electrodes always has the same electrode geometry or the electrodes are only arranged in a mirror-image manner, the same template can be used each time to print the electrode layers.

[0267] Fig.16 A ninth embodiment of the multilayer capacitor 1 is shown. The capacitor element 2 can be configured corresponding to one of the above-described examples.

[0268] On the exit surfaces of the electrodes 6 and 7, an external contact 8 is furthermore applied. The external contact 8 comprises a plurality of layers. A sputtered layer 8A covering the entire exit surface 6 / 7 is applied directly onto the exit surface 6 / 7. The sputtered layer 8A comprises three sub-layers consisting of chromium, nickel and silver.

[0269] All the first electrodes or all the second electrodes can be electrically connected to each other through the sputtered layer 8A described and thus connected in parallel.

[0270] A metal plate 18 is applied to the sputtered layer 8A for external contacting by means of a sintered silver layer 19 .

[0271] The sintered silver layer 19 covering the entire sputtered layer 8A holds the sputtered layer 8A together in the event of deformation of the capacitor element 2 and prevents the sputtered layer 8A from falling off, for example.

[0272] In the present exemplary embodiment, the silver layer 19 has a thickness of approximately 20 μm to 30 μm. The porosity of the silver in this layer is 35%.

[0273] The silver layer 19 also fixes the metal sheet 18 on the sputtered layer 8A. Therefore, no solder connection is required. For this purpose, silver is applied to the sputtered layer and the metal sheet 18 is placed directly on it. The silver layer 19 is sintered only after the metal sheet 18 is placed.

[0274] Due to its high electrical conductivity, the silver layer 19 also enables a good electrical connection of the metal sheet 18 to the sputtered layer 8A.

[0275] In order to improve the adhesion of the metal sheet 18 at the silver layer 19, in the present embodiment, the surface of the metal sheet 18 is silver-plated. The surface is preferably electro-silver-plated. Therefore, an electro-plated silver layer 20 is formed on the surface of the metal sheet 18, which is arranged between the metal sheet 18 and the silver layer 19. The thickness of the electro-plated silver layer 20 is between 5 μm and 10 μm.

[0276] In this embodiment, the metal sheet 18 of the external contact portion, such as Fig.17 As shown in the detailed figure in FIG. 1 , it comprises two copper layers 18B and an Invar layer 18A located therebetween. Instead of Invar, the intermediate layer may also comprise another iron-nickel alloy or an iron-nickel-cobalt alloy.

[0277] Due to the intermediate Invar layer, the metal sheet 18 has the required mechanical strength. Due to the low thermal expansion of Invar, mechanical stresses during temperature changes can be avoided. Thus, the formation of cracks in the external contacts of the capacitor or in the ceramic can be prevented as much as possible.

[0278] Copper layer 18B is applied to the Invar layer 18A on the outside, preferably rolled. Copper layer 18B has high thermal conductivity and high electrical conductivity. Thus, an external contact can be provided which has a low coefficient of thermal expansion and thus high mechanical stability on the one hand, and high thermal conductivity and high electrical conductivity on the other hand.

[0279] The copper layer 18B is applied to both sides of the Invar layer 18A with equal layer thickness. By applying the copper uniformly on both sides, the formation of a bimetallic strip with unfavorable properties for this application is avoided. The ratio of the layer thickness of copper-Invar-copper is preferably 1:3:1. In the present example, a metal sheet with a total thickness of 0.15 mm is used. The thickness of the Invar layer 18A is 90 μm and the thickness of the copper layer 18B is 30 μm in each case.

[0280] By using predominantly silver and copper in the described layer construction of the external contact, an external contact is achieved which has a high electrical and thermal conductivity.

[0281] The described layer structure also makes it possible to adjust the coefficient of thermal expansion, increase the thermomechanical load capacity and thus the durability, and improve the maximum current carrying capacity. This results in an optimized failure reliability during operation.

[0282] Capacitors with the above characteristics are suitable for use as DC link or buffer capacitors. Due to the small parasitic variables, especially the small equivalent series inductance, and the fact that the capacitor can be placed close to the semiconductor, the rectifier circuit can be kept small. Therefore, inductive overvoltages can be well attenuated during the shutdown process. Due to the characteristics of the capacitor, in some applications, when used as a DC link capacitor, an additional buffer capacitor can be omitted.

[0283] Another application of the described capacitors is as filter capacitors. Due to their high-frequency properties, interference signals up to the MHz range, which are far above the operating frequency of the power inverter, can be effectively suppressed and filtered.

[0284] In another embodiment not shown, a copper layer is applied to the silver layer 19 instead of the metal sheet 18. In this example, the copper layer has a meandering, grid-like geometry. The copper layer is also silver-plated here. The silver plating is performed by electroplating. The copper layer is sintered directly with the silver layer.

[0285] Reference numerals list

[0286] 1 Multilayer capacitor

[0287] 1A capacitor upper side

[0288] 1B First capacitor

[0289] 1C Second capacitor

[0290] 2 Capacitor elements

[0291] Sections 2A and 2B

[0292] 3.3A, 3B First electrode

[0293] 4, 4A, 4B Second electrode

[0294] 5 Dielectric layer

[0295] 6 First departure

[0296] 7 Second departure

[0297] 8 External contact

[0298] 8A Sputtering layer

[0299] 9A Active Area

[0300] 9B Passive Area

[0301] 10, 11 Side

[0302] 12 Connection Area

[0303] 13. Unloading area

[0304] 13A External section of the relief area

[0305] 13B Inner section of the load relief area

[0306] 14. Third electrode

[0307] 15, 15A Fourth electrode

[0308] 16, 16A Fifth electrode

[0309] 17 Sixth electrode

[0310] 18 Metal Sheet

[0311] 18A Invar alloy layer

[0312] 18B copper layer

[0313] 19 Silver Layer

[0314] 20 Silver plating layer

Claims

1. A multilayer capacitor (1), comprising a capacitor element (2), the capacitor element having at least two sections (2A, 2B), wherein each section comprises a plurality of layer planes, wherein dielectric layers (5) composed of ceramic and electrode layers arranged therebetween are present, wherein the dielectric layers and the electrode layers are arranged one above the other in a layer sequence, wherein the electrode layers comprise different electrodes, wherein the electrodes comprise at least a first electrode and a second electrode (3, 4), wherein the different electrodes overlap in an active region (9A), wherein the different electrodes do not overlap in a passive region (9B), wherein a plurality of sections are arranged one above the other in a stacking direction, wherein the outermost dielectric layers of two sections form a connection region (12), wherein the sections are firmly connected to one another parallel to the layer planes, wherein the connection region contains a load relief region (13), and wherein the load relief region occupies at least the entire passive region of the capacitor, Each segment includes at least three different types of electrode layers, wherein in a first electrode layer, the first electrode and the second electrode are formed opposite to each other and separated by a dielectric segment, in a second electrode layer only the first electrode is formed and in a third electrode layer only the second electrode is formed, and wherein the first electrode layer respectively forms the outermost electrode layer of each segment in the stacking direction.

2. The multilayer capacitor according to claim 1, The relief region is designed in this case as a region between the segments and parallel to the slice plane in which the segments are not firmly connected to one another.

3. The multilayer capacitor according to claim 1 or 2, The relief region is designed in this case as a gap between the segments.

4. The multilayer capacitor according to claim 1 or 2, The load relief region comprises a material having an elastic modulus different from an elastic modulus of the dielectric layer.

5. The multilayer capacitor according to claim 1 or 2, The load relief region is formed at least in all regions (13A) adjacent to the outer side of the capacitor element.

6. The multilayer capacitor according to claim 1 or 2, The load relief region is formed at least partially in the active region.

7. The multilayer capacitor according to claim 1 or 2, The relief region has at least one section (13B) which does not adjoin an outer side of the capacitor element.

8. The multilayer capacitor according to claim 1 or 2, The connecting area includes a plurality of load relief areas separated from each other.

9. The multilayer capacitor according to claim 8, The load relief regions separated from one another at least partially do not adjoin the outer side of the capacitor element.

10. The multilayer capacitor according to claim 1 or 2, The first electrode and the second electrode at least partially overlap.

11. The multilayer capacitor according to claim 1 or 2, The electrodes include copper or silver.

12. The multilayer capacitor according to claim 1 or 2, Two separate external contacts (8) are applied to the exit surfaces (6, 7) on the outer side of the capacitor element for contacting the first electrode and the second electrode, wherein the electrodes exit the capacitor element at the exit surfaces.

13. The multilayer capacitor of claim 12, comprising at least one third electrode (14), which is not contacted by any external contact, wherein the third electrode overlaps the first electrode and the second electrode.

14. The multilayer capacitor according to claim 1 or 2, comprising a further electrode (15, 16, 17) which is arranged in an inactive region of the capacitor and does not overlap with any electrode of a different polarity.

15. The multilayer capacitor according to claim 12, The external contact comprises a multi-layer sputtered layer (8A), comprising a layer consisting of chromium, a layer consisting of nickel and a layer consisting of at least one of silver or gold, wherein the layers are applied to the exit surface in the order of a layer consisting of chromium - a layer consisting of nickel - a layer consisting of at least one of silver or gold.

16. The multilayer capacitor according to claim 15, The external contact comprises a metal sheet (18) which is attached to the sputtered layer by means of a solder connection.

17. The multilayer capacitor according to claim 15, The external contact comprises a metal sheet (18) which is applied to the sputtered layer by means of a sintered silver layer (19).

18. The multilayer capacitor according to claim 16, The metal sheet comprises two copper layers (18B) and an Invar alloy layer (18A) arranged therebetween.

19. The multilayer capacitor according to claim 16, The metal sheet includes a copper layer having a meander-shaped geometry.

20. The multilayer capacitor according to claim 12, The multilayer capacitor comprises separable capacitor elements which can be combined and disassembled as desired on contact surfaces (10, 11), wherein the contact surfaces are arranged perpendicular to the layer planes and the external contacts.

21. The multilayer capacitor according to claim 1 or 2, The ceramic is an antiferroelectric dielectric.

22. The multilayer capacitor according to claim 1 or 2, The ceramic comprises lead zirconate titanate.

23. The multilayer capacitor according to claim 1 or 2, The ceramic comprises sodium strontium titanate.

24. The multilayer capacitor according to claim 1 or 2, The capacitor is used as a DC link capacitor and / or a buffer capacitor and / or a filter capacitor.

25. The multilayer capacitor according to claim 1 or 2, The connection region (12) includes a plurality of relief regions (13B), wherein the relief regions at least partially do not adjoin the outer side of the capacitor element (2) and the relief regions intersect.

26. The multilayer capacitor according to claim 1 or 2, Blind electrodes (15, 16, 17) are arranged in the passive region (9B) in the same layer plane as the first and second electrodes (3, 4), and the passive region does not overlap with electrodes of different polarities.

27. A multilayer capacitor (1), comprising a capacitor element (2), the capacitor element having at least two sections (2A, 2B), wherein each section comprises a plurality of layer planes, wherein dielectric layers (5) composed of ceramic and electrode layers arranged therebetween are present, wherein the dielectric layers and the electrode layers are arranged one above the other in a layer sequence, wherein the electrode layers comprise different electrodes, wherein at least a first electrode and a second electrode (3, 4) are present in the active region (9A), wherein the different electrodes overlap in the passive region (9B), wherein the different electrodes do not overlap in the passive region (9B), wherein a plurality of sections are arranged one above the other in a stacking direction, wherein the outermost dielectric layers of two sections form a connection region (12), wherein the sections are firmly connected to one another parallel to the layer planes, wherein the connection region contains a load relief region (13), and wherein the load relief region occupies at least the entire passive region of the capacitor, The load relief region comprises a material having an elastic modulus different from an elastic modulus of the dielectric layer.

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