Sealing layer for ohmic alloy contact area

Abstract

Form an ohmic contact sealing layer, the ohmic contact sealing layer being disposed at the intersection between the sidewall of the ohmic contact and the surface of the semiconductor; form an ohmic contact sealing layer at the intersection between the sidewall of the ohmic contact and the surface of the semiconductor; and treat the semiconductor with the ohmic contact using a chemical etchant.

Description

Technical Field

[0001] The present disclosure generally relates to ohmic contacts on semiconductor devices. Background Art

[0002] As is known in the art, ohmic contacts are used in many integrated circuit applications. One such application is the formation of a field effect transistor (FET), which includes a semiconductor having a source contact and a drain contact and a gate contact disposed between the source contact and the drain contact; the gate contact controls the flow of charge carriers through the semiconductor between the source contact and the drain contact. A field effect transistor requires good, i.e., low resistance, semiconductor ohmic contacts to reduce unnecessary voltage drops and unnecessary power dissipation. More particularly, good ohmic contacts require that the metal used for the source and drain contacts be alloyed into the semiconductor surface and form a highly doped and low resistance region.

[0003] For gallium arsenide (GaAs) field effect transistors, nickel has been used as the underlayer for the source and drain contacts, and during a high temperature alloying step, nickel diffuses into the GaAs semiconductor. However, after alloying, nickel (Ni) can form an oxide that leaches out of the ohmic contacts during subsequent wet chemical steps used in FET fabrication. More particularly, in many FETs, the source and drain contacts form ohmic contacts with a relatively highly doped semiconductor layer, while the gate forms a Schottky contact with a region of a low doped or undoped semiconductor layer disposed beneath the relatively highly doped semiconductor layer; this Schottky contact region is exposed by etching a notch in the upper semiconductor layer to expose the gate contact region on the lower semiconductor layer. In the case of a gallium arsenide (GaAs) semiconductor based material, one component of the etchant used to form the notch is an oxidizer (such as hydrogen peroxide), which can cause undesirable nickel leaching when it contacts the source and drain ohmic contact regions. "Ohmic Ooze" refers to the formation of nickel oxide phases that spray onto the gate channel along the ohmic edges when the NiGeAs phase is exposed to process chemicals prior to the dielectric passivation deposition step. This leached or leaked nickel metal can cause short circuits, which, if severe enough, can have an adverse effect on the yield and reliability of the FET. More particularly, any nickel or nickel-containing alloy exposed on the surface or along the edges of the ohmic contacts is prone to oxidation during subsequent process steps until the ohmic contacts are passivated. Standard passivation methods (such as using a dielectric passivation layer) are typically deposited only after the Schottky gate contacts are completed to prevent any effect of the etching of the passivation layer on the formation of the Schottky gate contacts. Summary of the Invention

[0004] According to the present disclosure, a method is provided, which includes: depositing an ohmic contact sealing layer disposed at an intersection between a sidewall of an ohmic contact and a surface of a semiconductor; and treating the semiconductor with the ohmic contact using a wet chemical agent.

[0005] In one embodiment, the ohmic contact sealing layer is a polycrystalline, amorphous dielectric.

[0006] In one embodiment, the ohmic contact sealing material includes a metal (is composed of a metal).

[0007] In one embodiment, the wet chemical agent is an etchant.

[0008] In one embodiment, a field effect transistor (FET) is provided, which includes: a semiconductor; and an ohmic contact sealing layer disposed at an intersection between a sidewall of an ohmic contact and a surface of the semiconductor; the ohmic contact sealing layer is a non-single crystal material.

[0009] In one embodiment, a method for forming a field effect transistor is provided, which includes: depositing an ohmic contact sealing layer disposed at: (a) an intersection between a sidewall of a source contact and a semiconductor surface; and (b) an intersection between a sidewall of a drain contact and a semiconductor surface; forming a notch in the semiconductor surface between the source contact and the drain contact; and forming a gate contact in the notch that contacts the semiconductor.

[0010] In one embodiment, the method includes forming a passivation layer on the ohmic contact sealing layer.

[0011] In one embodiment, the gate contact and the ohmic contact sealing layer include the same metal (are composed of the same metal).

[0012] In one embodiment, the ohmic contact sealing layer is formed before the notch is formed.

[0013] In one embodiment, the ohmic contact sealing layer is formed after the notch is formed.

[0014] In one embodiment, a method for forming a field effect transistor (FET) is provided, which includes: forming a material on a source ohmic contact metal and a drain ohmic contact metal, the material including a portion of a gate Schottky contact (contact) metal.

[0015] In one embodiment, the source contact and the drain contact include nickel (are composed of nickel).

[0016] In one embodiment, the FET includes gallium arsenide (is composed of gallium arsenide).

[0017] In one embodiment, the material is an oxidation-retarding material that is used to retard the oxidation of the source ohmic contact metal and the drain ohmic contact metal.

[0018] In one embodiment, the material retards the leaching of the ohmic contact metal during processing after the formation of the ohmic contact metal.

[0019] In one embodiment, a field-effect transistor (FET) is provided that includes: a semiconductor; a source contact that makes an ohmic contact with a first portion of the semiconductor surface; a drain contact that makes an ohmic contact with a second portion of the semiconductor surface; a gate contact disposed between the source contact and the drain contact, the gate contact including an ohmic-contact (contact) sealed gate metal that has a first portion configured to make a Schottky contact with a third portion of the semiconductor surface, the third portion of the semiconductor surface being laterally spaced apart from both the first portion and the second portion of the semiconductor surface; wherein the ohmic-contact sealed gate metal has a second portion disposed at an intersection of a sidewall of the source contact and the first portion of the semiconductor surface; wherein the ohmic-contact sealed gate metal has a third portion disposed at an intersection between a sidewall of the drain contact and the second portion of the semiconductor surface; and wherein the second portion of the ohmic-contact sealed gate metal and the third portion of the ohmic-contact sealed gate metal are laterally spaced apart from the first portion of the gate metal.

[0020] Details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will be apparent from the description, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a simplified, diagrammatic, cross-sectional view of a field-effect transistor in accordance with the present disclosure; and

[0022] Figures 2A - 2J is a simplified, diagrammatic, cross-sectional view of the steps for forming a Figure 1 field-effect transistor in accordance with the present disclosure.

[0023] Figure 3 is a simplified, diagrammatic, cross-sectional view of a field-effect transistor in accordance with an alternative embodiment of the present disclosure; and

[0024] Figures 4A - 4D is a simplified, diagrammatic, cross-sectional view of the steps for forming a Figure 3 field-effect transistor in accordance with an alternative embodiment of the present disclosure.

[0025] Like reference numerals in the various figures indicate like elements. DETAILED DESCRIPTION

[0026] Now refer to Figure 1, as shown in the figure, the field - effect transistor (FET) 10 has a gallium arsenide (GaAs) substrate 12, a low - doped or undoped GaAs epitaxial layer 14 located on the upper surface of the substrate 12, and a doped (here, for example, N + doped (e.g., silicon - doped)) GaAs layer 16. The contacts of the source S and the drain D are formed in the corresponding parts of the upper surface of the N + doped layer 16 in the manner to be described. Here, it suffices to state that the source and drain metals (here, for example, Ni, Ge, and Au) are alloyed into the corresponding parts of the upper surface of the N + doped GaAs layer 16 using the time and temperature during the heating structure to form the alloyed ohmic contact (contact) regions 18, as shown in the figure. The gate G forms a Schottky contact (i.e., Schottky contact region) with the upper part of the undoped GaAs epitaxial layer 14; it should be noted that the gate contact G passes through a notch 20 formed in a part of the N + doped GaAs layer 16, and the notch 20 terminates in the undoped GaAs epitaxial layer 14, as shown in the figure. It should be noted that the ohmic contact seal layer 22, which will be described in detail below, is provided as a continuous material on the following parts: the upper parts of the source S and drain D contacts; the side walls of the source S and drain D contacts; and then on a part of the alloyed ohmic contact region 18, including the interface 23 between the source S and drain D contacts and the N alloyed ohmic contact region 18, as shown in the figure. Here, for example, the ohmic contact seal layer is a dielectric, here, for example, silicon oxide or silicon nitride. It should be noted that the seal layer 22 can be a metal, such as Ti, Pt, and Au. Further noted that, as shown in the figure, there is a gap (GAP) between the ohmic contact seal layer 22 and the gate contact G. As shown in the figure, a conventional passivation / capping layer 25 and an electrode 27 are provided.

[0027] Now refer to Figure 2A and 2B , as Figure 2A shown, a gallium arsenide (GaAs) substrate 12, a low - doped or undoped GaAs epitaxial layer 14 located on the upper surface of the substrate 12, and a doped (here, for example, N + doped) GaAs layer 16 are provided, as Figure 2B shown, a mask 30 is formed on the surface, and the mask 30 is patterned to have a window or opening 32.

[0028] Refer to Figure 2C , as shown in the figure, a metal layer 34 (here, for example, Ni, Ge, and Au) is sequentially deposited on the surface by evaporation; it should be noted that, as shown in the figure, a part of the metal layer 34 reaches the exposed part of the surface of the N + doped GaAs layer 16 through the window 32 formed in the mask 30.

[0029] Now refer to Figure 2D , as shown in the figure, the mask 30 ( Figure 2C) is lifted so that the portion of the metal layer 34 on the previously exposed portion of the surface of the N+ doped GaAs layer 16 is left, thereby forming the source S and drain D contacts, as shown.

[0030] Now referring to Figure 2E , the structure is heated within a certain temperature range (400 - 425 degrees Celsius in this example) for a certain period of time (30 - 60 seconds in this example) to alloy the metal 34 with the previously exposed portion of the surface of the underlying N+ doped GaAs layer to form an alloyed ohmic contact region 18 composed of a gallium, arsenic, nickel, germanium, and gold alloy phase in the N+ doped GaAs layer, as shown. It should be noted that, as shown, the alloying process causes the alloyed ohmic contact region 18 to laterally diffuse beyond the sidewalls of the source S and drain D contacts.

[0031] Now referring to Figure 2F , as shown, an ohmic contact seal layer 22 is deposited on the entire surface of the structure. More particularly, here a dielectric seal layer is formed by depositing a continuous dielectric film (such as silicon dioxide SiO2 deposited by atomic layer deposition (ALD)) on the entire wafer surface.

[0032] Referring to Figure 2G , a photoresist mask 35 is formed on the ohmic contact seal layer 22, as shown, and the mask 35 has a window 37. An etchant (here hydrofluoric acid for example) is brought into contact with the masked surface to remove the portion of the ohmic contact seal layer 22 exposed by the window 37, thereby producing the structure shown after stripping the mask 35. Figure 2H as shown.

[0033] Referring to Figure 2I , as shown, a mask 50 is formed on the structure, and the mask 50 has a window 21 on the upper surface of the structure, and a notch 20 will be formed at the window 21. The notch 20 ( Figure 1 ) is formed using a suitable wet chemical etchant (here citric acid for example) as Figure 2I shown. It should be noted that the seal layer 22 can prevent nickel in the source S and drain D contacts from leaking out of the alloyed contact region 18.

[0034] After removing the mask 50, as Figure 2J shown, a new mask 51 is formed, and the mask 51 has a window 23 formed therein above the notch 20, as shown. As Figure 2J shown, a gate metal 52 is deposited on the mask 51, and the gate metal 52 is deposited through the window 23 in the photoresist 51 onto the portion of the surface of the notch 20 exposed by the window 23.

[0035] The mask 51 is lifted, thereby removing the metal 52 thereon, but leaving the portion of the gate metal 52 located in the notch 20 to form a gate contact G that makes a Schottky contact with the Schottky contact region (SCR). Then, a conventional passivation / vitrification layer 25 and a contact (contact) metal layer 27 are provided in any conventional manner to produce Figure 1 the FET 10 shown in

[0036] It should be understood that, in addition to the FET, a dielectric seal layer under other parts of the MMIC (monolithic microwave integrated circuit) circuit can also be left to provide early passivation.

[0037] Now referring to Figure 3 , the field effect transistor (FET) 10' is shown to have a gallium arsenide (GaAs) substrate 12, a low-doped or undoped GaAs epitaxial layer 14 on the upper surface of the substrate 12, and a doped (here, for example, N+-doped (such as silicon-doped)) GaAs layer 16. Source S and drain D contacts are formed on corresponding portions of the upper surface of the N+-doped layer 16 in the manner to be described. Here, it suffices to state that the source and drain metals (here, for example, Ni, Ge, and Au) are alloyed into the corresponding portions of the upper surface of the N+-doped GaAs layer 16 using the time and temperature during the heating structure to form alloyed ohmic contact regions 18, as shown in the figure.

[0038] The gate contact G makes a Schottky contact with the upper portion of the undoped GaAs epitaxial layer 14, that is, the Schottky contact region (SCR); it should be noted that the gate contact passes through a notch 20 formed in a portion of the N+-doped GaAs layer 16, and the notch 20 terminates in the undoped GaAs epitaxial layer 14, as shown in the figure. It should be noted that the ohmic contact seal layer / Schottky contact material 22' is provided as a continuous material on the following parts: the upper portions 22'b of the source S and drain D contacts; the sidewalls of the source S and drain D contacts; and then on a portion of the alloyed ohmic contact region 18, the portion including the interface 23 between the source S and drain D contacts and the N alloyed ohmic contact region 18, as shown in the figure. As described below, a portion 22'a of the ohmic contact seal layer / Schottky contact material 22' is used for the gate contact G. The ohmic contact seal layer (seal) 22'b and the gate contact 22'a are formed of the same material 22' and are formed on the FET 10' in the same processing step. Here, for example, the material of the ohmic contact seal layer / Schottky contact material 22' is Ti, Pt, and Au. It should be noted that, as shown in the figure, there is a gap (GAP) between the portion 22'a and the portion 22'b of the ohmic contact seal layer / Schottky contact material 22'. As shown in the figure, a conventional passivation / vitrification layer 25 and an electrode 27 are provided.

[0039] Now referring to Figure 4A , in the present embodiment, after forming the structure shown in Figure 2E : a mask 40' is formed on the upper surface, the mask 40' having a window 42' to expose a portion of layer 16 at which the notch 20 is to be formed, as shown. As Figure 4B shown, using a suitable wet chemical etchant (here citric acid for example), the notch 20 ( Figure 4B ) is formed; then as Figure 4C shown, the mask 40' is removed.

[0040] Referring to Figure 4D , as shown, a mask 50' is formed on the structure; and, as shown, an ohmic contact seal layer / schottky contact material 22' is deposited by evaporation through the window 52 of the mask 50', here Ti, Pt and Au for example. After the mask 50' is lifted off, the FET 10' is thus formed, as Figure 3 shown. These steps simultaneously form: a schottky contact between the ohmic contact seal layer / schottky contact material 22' and the gate electrode G 22'a ( Figure 3 ) of the low-doped GaAs layer 14; and another portion of the ohmic contact seal layer / schottky contact material 22', namely portion 22b' ( Figure 3 ), which portion 22b': is on the source and drain contacts S and D; is on the alloyed region 18; and is on the N+-doped GaAs layer 16; it should be noted that portion 22'b is in contact with the alloyed region 18 and the N+-doped GaAs layer 16. This portion 22'b is an oxidation-retarding material which is used to retard the oxidation of the source ohmic contact (contact) metal and the drain ohmic contact metal, thus retarding the leaching of the ohmic contact metal during the processing steps after the formation of the ohmic contact metal. As shown, a conventional passivation / vitrification layer 25 and electrodes 27 ( Figure 3 ) are formed.

[0041] It should now be understood that the method according to the present disclosure includes: depositing an ohmic contact seal layer which is disposed at the intersection between the sidewalls of the ohmic contact and the surface of the semiconductor; and subjecting the semiconductor having the ohmic contact to a wet chemical agent. The method may singly or in combination include one or more of the following features, which features include: wherein the seal layer is a metal; wherein the seal layer is a solid dielectric; or wherein the wet chemical agent is an etchant.

[0042] It should now be understood that a field-effect transistor (FET) according to the present disclosure includes: a semiconductor; and an ohmic contact sealing layer disposed at an intersection between a sidewall of an ohmic contact and a surface of the semiconductor; the ohmic contact sealing layer being a non-single crystal material. The field-effect transistor may individually or in combination include one or more of the following features, the features including: wherein the ohmic contact sealing layer is a metal, or wherein the ohmic contact sealing layer is a solid dielectric.

[0043] It should now also be understood that a method for forming a field-effect transistor according to the present disclosure includes: depositing an ohmic contact sealing layer that is disposed at: (a) an intersection between a sidewall of a source contact and a surface of the semiconductor; and (b) an intersection between a sidewall of a drain contact and a surface of the semiconductor; forming a notch in the surface of the semiconductor between the source contact and the drain contact; and forming a gate contact in the notch that contacts the semiconductor. The method may individually or in combination include one or more of the following features, the features including: forming a passivation layer over the ohmic contact sealing layer; wherein the ohmic contact sealing layer includes a solid dielectric (is composed of a solid dielectric); wherein the ohmic contact sealing layer includes a metal (is composed of a metal); wherein the gate contact and the ohmic contact sealing layer include the same metal (are composed of the same metal); wherein the ohmic contact sealing layer is formed before the notch is formed; wherein the ohmic contact sealing layer is formed after the notch is formed; wherein the semiconductor includes an upper semiconductor layer and a lower semiconductor layer, and wherein the source contact and the drain contact contact an upper surface of the upper semiconductor layer, and wherein the notch extends from the upper surface through the first semiconductor layer to the second semiconductor layer; wherein a first portion of the metal is disposed on the source contact and the upper semiconductor layer, a second portion of the metal is disposed on the drain contact and the upper semiconductor layer, and the gate contact includes a third portion of the metal; wherein the third portion of the metal makes a Schottky contact with the lower semiconductor layer; wherein the second and third portions of the ohmic contact sealing gate metal retard oxidation of the source contact at an intersection between a sidewall of the source contact and a first portion of the semiconductor surface, and retard oxidation of the drain contact at an intersection between a sidewall of the drain contact and a second portion of the semiconductor surface; wherein a third portion of the semiconductor surface is recessed below the first portion of the semiconductor surface and the second portion of the semiconductor surface; wherein the source contact and the drain contact include nickel; or wherein the semiconductor includes gallium arsenide.

[0044] It should also be understood now that a field effect transistor (FET) according to the present disclosure includes: an ohmic contact sealing layer disposed at (a) the intersection between the sidewall of the source contact and the surface of the semiconductor; and (b) the intersection between the sidewall of the drain contact and the surface of the semiconductor; wherein the ohmic contact sealing layer is spaced apart from the gate contact by a gap in the ohmic contact sealing layer between the source contact and the gate contact and a gap between the drain electrode and the gate electrode; and wherein the ohmic contact sealing layer comprises a non-single crystal material (is composed of a non-single crystal material).

[0045] It should also be understood now that a field effect transistor (FET) according to the present disclosure includes: a source contact in ohmic contact with the surface of the upper semiconductor layer; a drain contact in ohmic contact with the surface of the upper semiconductor layer; wherein the upper semiconductor layer has a notch in the semiconductor surface between the source contact and the drain contact, and the notch terminates at the lower semiconductor layer; a gate contact disposed in the notch and in contact with the lower semiconductor layer; and an ohmic contact sealing layer disposed at (a) the intersection between the sidewall of the source contact and the surface of the upper semiconductor layer, and (b) the intersection between the sidewall of the drain contact and the surface of the upper semiconductor layer; wherein the ohmic contact sealing layer is spaced apart from the gate contact by a gap in the ohmic contact sealing layer between the source contact and the gate contact and a gap between the drain electrode and the gate electrode; and wherein the ohmic contact sealing layer comprises a non-single crystal material. The field effect transistor may individually or in combination include one or more of the following features, the features including: wherein the ohmic contact sealing layer is a solid dielectric, or wherein the ohmic contact sealing layer is a metal.

[0046] It should also be understood now that a method for forming a field effect transistor according to the present disclosure includes: forming a material on the source ohmic contact metal and the drain ohmic contact metal, the material including a portion of the gate Schottky contact (contact) metal. The method may individually or in combination include one or more of the following features, the features including: wherein the source contact and the drain contact include nickel; wherein the FET includes gallium arsenide; wherein the material is an oxidation retardant material to retard the oxidation of the source ohmic contact metal and the drain ohmic contact metal; or wherein the material retards the leaching of the ohmic contact metal during processing after the formation of the ohmic contact metal.

[0047] It should also be understood that a field effect transistor (FET) according to the present disclosure includes: a semiconductor; a source contact in ohmic contact with a first portion of the semiconductor surface; a drain contact in ohmic contact with a second portion of the semiconductor surface; a gate contact disposed between the source contact and the drain contact, the gate contact including an ohmic contact-sealing gate metal having a first portion configured to be in Schottky contact with a third portion of the semiconductor surface, the third portion of the semiconductor surface being laterally spaced from the first portion and the second portion of the semiconductor surface; wherein the ohmic contact-sealing gate metal has a second portion disposed at an intersection of a sidewall of the source contact and the first portion of the semiconductor surface; wherein the ohmic contact-sealing gate metal has a third portion disposed at an intersection between a sidewall of the drain contact and the second portion of the semiconductor surface; and wherein the second portion of the ohmic contact-sealing gate metal and the third portion of the ohmic contact-sealing gate metal are laterally spaced from the first portion of the gate metal. The field effect transistor may individually or in combination include one or more of the following features, the features including: wherein the third portion of the semiconductor surface is recessed below the first portion of the semiconductor surface and the second portion of the semiconductor surface; wherein the source contact and the drain contact include nickel; or wherein the semiconductor includes gallium arsenide.

[0048] It should also be understood that a field effect transistor (FET) according to the present disclosure includes: a semiconductor; and an ohmic contact-sealing layer disposed at an intersection between a sidewall of the ohmic contact and the surface of the semiconductor; the ohmic contact-sealing layer being polycrystalline, amorphous dielectric, or including metal.

[0049] Some embodiments of the present disclosure have been described. However, it can be understood that various modifications can be made without departing from the spirit and scope of the present disclosure. Accordingly, other embodiments are also within the scope of the following claims.

Claims

1. A method for forming a field effect transistor, comprising: Depositing an ohmic contact sealing layer disposed at the intersection between: (a) the sidewall of the source contact and the surface of the semiconductor; And (b) the intersection between the sidewall of the drain contact and the surface of the semiconductor, wherein the source contact and the drain contact comprise nickel; Forming a notch in the surface of the semiconductor between the source contact and the drain contact; and Forming a gate contact in the notch, the gate contact being in contact with the semiconductor, Wherein the semiconductor comprises an upper semiconductor layer and a lower semiconductor layer, Wherein the source contact and the drain contact are in contact with the upper surface of the upper semiconductor layer, and wherein the notch extends from the upper surface through the upper semiconductor layer to the lower semiconductor layer, and Wherein the gate contact and the ohmic contact sealing layer comprise the same metal, and wherein the ohmic contact sealing layer is formed after the notch is formed.

2. The method according to claim 1, comprising forming a passivation layer on the ohmic contact sealing layer.

3. The method according to claim 1, wherein, The ohmic contact sealing layer comprises a solid dielectric.

4. The method according to claim 1, wherein The field effect transistor comprises gallium arsenide.

5. The method according to claim 1, wherein The ohmic contact sealing layer is an oxidation retardant material for retarding the oxidation of the source contact and the drain contact.

6. The method according to claim 1, wherein, The ohmic contact sealing layer retards the leaching of the ohmic contact metal during the processing after the formation of the ohmic contact metal.

7. A field effect transistor (FET), comprising: A source contact in ohmic contact with the surface of the upper semiconductor layer; A drain contact in ohmic contact with the surface of the upper semiconductor layer; Wherein the source contact and the drain contact comprise nickel; and Wherein the upper semiconductor layer has a notch in its surface between the source contact and the drain contact, the notch terminating in the lower semiconductor layer; A gate contact disposed in the notch and in contact with the lower semiconductor layer; and An ohmic contact sealing layer disposed at the intersection between: (a) the sidewall of the source contact and the surface of the upper semiconductor layer; and (b) the intersection between the sidewall of the drain contact and the surface of the upper semiconductor layer; Wherein the ohmic contact sealing layer is spaced apart from the gate contact by a gap in the ohmic contact sealing layer between the source contact and the gate contact and a gap between the drain contact and the gate contact; and Wherein the ohmic contact sealing layer is a metal, wherein a first portion of the metal is disposed on the source contact and the upper semiconductor layer, a second portion of the metal is disposed on the drain contact and the upper semiconductor layer, and the gate contact comprises a third portion of the metal.

8. The field effect transistor according to claim 7, wherein, The third portion of the metal is in Schottky contact with the lower semiconductor layer.

9. The field effect transistor according to claim 7, wherein, The semiconductor comprising the upper semiconductor layer and the lower semiconductor layer comprises gallium arsenide.

10. The field effect transistor according to claim 7, wherein The ohmic contact sealing layer retards oxidation of the source contact at the intersection between the sidewall of the source contact and the surface of the upper semiconductor layer, and retards oxidation of the drain contact at the intersection between the sidewall of the drain contact and the surface of the upper semiconductor layer.

11. A field effect transistor (FET) comprising: A source contact in ohmic contact with the surface of an upper semiconductor layer; A drain contact in ohmic contact with the surface of the upper semiconductor layer; Wherein the upper semiconductor layer has a notch in the surface of the upper semiconductor layer between the source contact and the drain contact, and the notch terminates in a lower semiconductor layer; A gate contact disposed in the notch and in contact with the lower semiconductor layer; and An ohmic contact sealing layer disposed at: (a) the intersection between the sidewall of the source contact and the surface of the upper semiconductor layer; and (b) the intersection between the sidewall of the drain contact and the surface of the upper semiconductor layer; Wherein the ohmic contact sealing layer is spaced apart from the gate contact by a gap in the ohmic contact sealing layer between the source contact and the gate contact and a gap between the drain contact and the gate contact; and Wherein the ohmic contact sealing layer comprises a non-single crystal material.

12. The field effect transistor according to claim 11, wherein, The ohmic contact sealing layer is a solid dielectric.

13. The field effect transistor according to claim 11, wherein, The ohmic contact sealing layer is a metal.

14. The field effect transistor according to claim 13, wherein, A first portion of the metal is disposed on the source contact and the upper semiconductor layer, a second portion of the metal is disposed on the drain contact and the upper semiconductor layer, and the gate contact comprises a third portion of the metal.

15. The field effect transistor according to claim 14, wherein, The third portion of the metal is in Schottky contact with the lower semiconductor layer.

16. The field effect transistor according to claim 14, wherein, The first portion and the second portion of the metal retard oxidation of the source contact at the intersection between the sidewall of the source contact and the first portion of the surface of the upper semiconductor layer, and retard oxidation of the drain contact at the intersection between the sidewall of the drain contact and the second portion of the surface of the upper semiconductor layer.

17. The field effect transistor according to claim 16, wherein, A third portion of the surface of the upper semiconductor layer is recessed below the first portion of the surface of the upper semiconductor layer and the second portion of the surface of the upper semiconductor layer.

18. The field effect transistor according to claim 16, wherein, The source contact and the drain contact comprise nickel.

19. The field effect transistor according to claim 18, wherein The upper semiconductor layer and the lower semiconductor layer comprise gallium arsenide.

20. A field effect transistor (FET) comprising: A semiconductor; A source contact in ohmic contact with a first portion of the semiconductor surface; A drain contact in ohmic contact with a second portion of the semiconductor surface; A gate contact disposed between the source contact and the drain contact and comprising an ohmic contact sealing gate metal having a first portion configured to be in Schottky contact with a third portion of the semiconductor surface, the third portion of the semiconductor surface being laterally spaced apart from both the first portion and the second portion of the semiconductor surface; Wherein the ohmic contact sealing gate metal has a second portion disposed at the intersection between the sidewall of the source contact and the first portion of the semiconductor surface; Wherein the ohmic contact sealing gate metal has a third portion disposed at the intersection between the sidewall of the drain contact and the second portion of the semiconductor surface; Wherein, the second part of the ohmic contact encapsulating gate metal and the third part of the ohmic contact encapsulating gate metal are laterally spaced apart from the first part of the gate metal; and Wherein, the third part of the semiconductor surface is recessed below the first part and the second part of the semiconductor surface.

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