Hysteretic Boost Converter with Inductor Peak Current Shifting

Abstract

An electronic device (100A, 100B) has a DC / DC boost converter (100A, 100B) including a power NFET (M1). The power NFET is coupled between a first pin (P1) and a ground plane, and the first pin (P1) can be coupled to a battery (103) through an inductor (L). A switch node (SW) is coupled to a third pin (P3), and the third pin (P3) can be coupled to a diode (D1) to provide a boosted output voltage (Vbst). A gate driver (102) can receive a FET on signal (FET ON) and drive the gate of the power NFET. A digital logic circuit (104) provides the FET turn-on signal and includes an Ipeak shift circuit (106) that dynamically changes the value of a peak inductor current (Ipeak) in response to one or more determinations related to one of the boosted output voltage Vbst from the third pin (P3), the boosted output voltage Vbst from the fourth pin (P4), and a switching frequency (Fsw) of the DC / DC boost converter.

Description

[0001] The disclosed embodiments relate generally to the field of boost converters. More particularly, and not in any limiting manner, the present disclosure relates to a hysteretic boost converter with inductor peak current (Ipeak) shifting. Background Art

[0002] During operation of the DC / DC boost converter, a feedback loop using the boosted output voltage provides the gate voltage and logic for controlling the power transistor. When the DC / DC boost converter has a large inductor peak current, the low-side power field effect transistor (FET) needs to receive a gate voltage much higher than the threshold voltage in order to pass the desired peak inductor current; if a high gate voltage on the low-side power FET is not always possible, the size of the low-side power FET can be increased to accommodate the desired large Ipeak value. However, when the power supply is a low-voltage battery, increasing the size of the power FET may be undesirable due to increased die cost, chip form factor, and shortened battery life. These conflicting requirements are particularly present when the boosted output voltage is low, for example, during startup, especially when the battery voltage drops.

[0003] Further problems can occur during operation when the load current drops. With lighter loads, the boost converter does not need to work as hard, so the switching frequency can drop into the audio band and cause interference. Dummy loads can be added to maintain the switching frequency above the audio band, although this traditional approach significantly reduces the efficiency of the boost converter. Summary of the invention

[0004] The disclosed embodiments provide two shifting methods that dynamically change the value of the inductor peak current during operation of the boost converter. During startup, when the gate voltage is low, the inductor peak current is initially set to a low value. Once the gate voltage increases to the desired operating range, the inductor peak current is dynamically shifted to a target peak value that can be determined, for example, by a register input.

[0005] When the load current decreases to a point where the switching frequency may drop into the audio band, shifting can also be performed dynamically to reduce the value of the inductor peak current in a step-by-step manner. By reducing the value of the inductor peak current, each cycle of the DC / DC boost converter provides a smaller boost to the output voltage and requires the switching frequency to increase to maintain a given output voltage. When the load current increases again, the inductor peak current can be increased in a step-by-step manner to meet the changing demand. The inductor peak current can be reduced in a relatively slow step-by-step manner and increased in a faster step-by-step manner to prevent a sharp drop in the output voltage. Instead of directly monitoring the switching frequency, shifting can be performed in response to shifting in an associated indicator, such as the idle state time, which is a component of the cycle time, which is the inverse of the switching frequency.

[0006] In one aspect, an embodiment of an electronic device including a DC / DC boost converter is disclosed. The DC / DC boost converter includes a power N-type field effect transistor (NFET) coupled between a first pin for coupling to a battery voltage through an inductor and a second pin for coupling to a ground plane, a switch node between the first pin and the power NFET, the power NFET coupled to a third pin for coupling to a diode to provide a boosted output voltage; a gate driver coupled to receive a FET turn-on signal and drive a gate of the power NFET; and a digital logic circuit coupled to provide the FET turn-on signal, the digital logic circuit including an Ipeak shift circuit coupled to dynamically change a value of a peak inductor current in response to one or more determinations related to one of the boosted output voltage and a switching frequency of the DC / DC boost converter.

[0007] In another aspect, a method of operating a DC / DC voltage converter is disclosed. The method includes receiving a target peak value for a peak inductor current; and dynamically changing the value of the peak inductor current in response to one or more determinations related to one of a boosted output voltage and a switching frequency of the DC / DC boost converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the figures of the accompanying drawings, the embodiments of the present disclosure are illustrated by way of example and not limitation, wherein similar references indicate similar elements. It should be noted that different references to "one" or "an" embodiment in the present disclosure are not necessarily to the same embodiment, and such references may mean at least one. Further, when describing a particular feature, structure or characteristic in conjunction with an embodiment, it should be considered that, whether or not explicitly described, it is within the knowledge of a person skilled in the art to implement such features, structures or characteristics in conjunction with other embodiments. As used herein, the term "coupled" is intended to mean an indirect or direct electrical connection, unless qualified as "communicatively coupled", which may include a wireless connection. Therefore, if a first device is coupled to a second device, the connection may be by direct electrical connection, or by indirect electrical connection via other devices and connections.

[0009] The accompanying drawings are incorporated into and form a part of the specification to illustrate one or more exemplary embodiments of the present disclosure. Various advantages and features of the present disclosure will be understood from the following detailed description taken in conjunction with the appended claims and with reference to the accompanying drawings, wherein:

[0010] Figure 1A Describes an example of a DC / DC boost converter according to an embodiment of the present disclosure, into which the disclosed method of operation may be incorporated;

[0011] Figure 1B A block diagram depicting an example DC / DC boost converter according to an embodiment of the present disclosure, into which the disclosed operating methods may be incorporated;

[0012] Figure 2A depicts the inductor current waveform of a DC / DC boost converter during continuous conduction mode;

[0013] Figure 2B depicts several waveforms of a DC / DC boost converter during discontinuous conduction mode;

[0014] Figure 3 depicts various signals of a DC / DC boost converter during startup according to an embodiment of the present disclosure;

[0015] Figure 4 depicts various signals that vary with load during operation of a DC / DC boost converter according to an embodiment of the present disclosure;

[0016] Figure 5 depicts various signals during a simulation of a DC / DC boost converter according to an embodiment of the present disclosure;

[0017] Figure 6 Describes an overall method of operating a DC / DC boost converter according to an embodiment of the present disclosure;

[0018] Fig. 6A depicts a first peak inductor current shifting method according to an embodiment of the present disclosure;

[0019] Figure 6B depicts a second peak inductor current shifting method according to an embodiment of the present disclosure; and

[0020] Figure 7 An example of a smoke detector incorporating a DC / DC boost converter according to an embodiment of the present disclosure is depicted. DETAILED DESCRIPTION

[0021] Specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In the following detailed description of embodiments of the present invention, many specific details are set forth to provide a more thorough understanding of the present invention. However, it is apparent to one of ordinary skill in the art that the present invention can be practiced without these specific details. In other examples, well-known features are not described in detail to avoid unnecessarily complicating the description.

[0022] Figure 1A An example of a DC / DC boost converter 100A according to an embodiment of the present disclosure is depicted, in which the disclosed inductor peak current shifting can be implemented. The DC / DC boost converter chip 101 includes a low-side power FET M1 (which is an N-type power FET), and four pins: a first pin P1, a second pin P2, a third pin P3, and a fourth pin P4. Within the DC / DC boost converter chip 101, a switch node SW is located between the first pin P1 and the third pin P3, and the low-side power FET M1 is coupled between the switch node SW and the second pin P2. An inductor L is coupled between the first pin P1 and a power supply, which is connected to the power supply at Figure 1A In the middle is a battery 103. An input capacitor Cin has a first terminal coupled to a first node 105 located between the battery 103 and the inductor L and a second terminal coupled to a lower rail, which may be a ground plane. The battery 103 has a battery voltage Vbat and a battery resistance Rbat; the inductor L has an inductor resistance Rind.

[0023] The third pin P3 is coupled to the first diode D1 to provide the boosted output voltage Vbst to the load represented by the load current I_load. The output capacitor Cout has a first terminal coupled to the second node 107 and a second terminal coupled to the lower rail, the second node 107 being located between the first diode D1 and the load current I_load. The feedback loop is coupled to the second node 107 and the fourth pin P4 to provide the gate driver supply voltage Vcc to the DC / DC boost converter chip 101. Figure 1AIn the embodiment shown in , a clamp circuit 109 is provided to clamp the boosted output voltage Vbst to the desired gate driver supply voltage Vcc, although the need for a clamp circuit depends on the specific implementation. A second diode D2 is coupled between the first node 105 and the second node 107 to provide an initial voltage to both the feedback loop of the gate driver supply voltage Vcc and the boosted output voltage Vbst. In one embodiment, both the first diode D1 and the second diode D2 are Schottky diodes.

[0024] In one embodiment, the components of the DC / DC boost converter 100A shown have the following values: the battery resistance Rbat is 0.1Ω, the inductor resistance Rind is less than or equal to 0.56Ω, the input capacitance Cin is 10μF, the output capacitance Cout is 4.7μF, the battery voltage Vbat is equal to or greater than 2V, and the boosted output voltage Vbst between about 2.7V and about 11.5V is clamped to provide a gate driver supply voltage Vcc between about 1.7V and about 6.2V. When the battery voltage Vbat is at a minimum value of 2.0V, then the minimum gate driver supply voltage Vcc that can be provided to the gate of the low-side power FET M1 is 1.7V, i.e., the battery voltage Vbat minus the diode drop across the second diode D2.

[0025] When designing the values ​​mentioned above, one issue that was addressed was how to meet the target peak inductor current Ipeak of 500mA when the gate driver supply voltage Vcc was at a low value of 1.7V. Table 1 below provides the threshold voltage of the low-side power FET M1 at process and temperature corners:

[0026]

[0027] Table 1

[0028] At the worst corner, ie, a weak transistor at a temperature of -40°C, the threshold voltage Vth is 1.52V.

[0029] Table 2 provides a comparison of the peak inductor current Ipeak achievable at various values ​​of the gate driver supply voltage Vcc using a drain / source voltage Vds of 0.2V at the worst corner of the low-side power FET M1:

[0030] Vcc[V] Ipeak[mA] Vcc[V] Ipeak[mA] 1.7 44 2.3 339 1.8 86 2.4 382 1.9 137 2.5 422 2.0 191 2.6 459 2.1 243 2.7 492 2.2 293

[0031] Table 2

[0032] As can be seen from Table 2, when the gate driver supply voltage Vcc is 2.7 V, the low-side power FET M1 can provide 492 mA of current, while when the gate driver supply voltage Vcc is only 1.7 V, the low-side power FET M1 can only provide 44 mA of current. In other words, in order to meet the peak inductor current Ipeak of 500 mA, the size of the low-side power FET M1 needs to be increased by 11 times, or a charge pump needs to be incorporated into the design to boost the gate voltage to 2.7 V. These alternatives come at the expense of a much larger die size and much lower efficiency of the DC / DC boost converter chip 101, while the strong desire to maintain low cost and high efficiency remains.

[0033] Unlike using prior art solutions, the current embodiment performs a first peak inductor current shifting method by setting the peak inductor current Ipeak to an initial peak value, which in one embodiment is less than or equal to about 40 mA. Using this initial peak value, the rise rate of the boosted output voltage Vbst of the DC / DC boost converter 100A is slower than when the value of the peak inductor current Ipeak is higher, but the startup of the DC / DC boost converter is guaranteed. Then, once the boosted output voltage Vbst reaches a threshold output voltage, such as 3.0V in one embodiment, the peak inductor current Ipeak can be moved to a target peak value, such as 500 mA. Although this first peak inductor current shifting method is mainly used during startup, if the boosted output voltage Vbst drops below the threshold output voltage, the initial peak value of the peak inductor current Ipeak can be reused until the boosted output voltage Vbst rises above the threshold again.

[0034] When the load current changes, the second peak inductor current shifting method can be used. During the operation of the DC / DC boost converter 100A, the load current I_load can vary by several orders of magnitude. When the load current drops, the switching frequency Fsw of the DC / DC boost converter 100A slows down to maintain a stable value of the increased output voltage Vbst. If the load current I_load drops too much, there is a risk that the switching frequency Fsw will drop into the audio band, where the switch may cause audible noise and interference with the audio signal. For this reason, it is desirable to keep the switching frequency Fsw above the audio band.

[0035] A conventional solution to a drop in the load current I_load is to provide a dummy load on the output to maintain operation of the switching frequency Fsw at a faster rate, which again reduces the efficiency of the DC / DC boost converter 100A. In contrast, the disclosed embodiment reduces the value of the peak inductor current Ipeak in a step-by-step manner so that the switching frequency Fsw can be maintained above the audio band. When the load current I_load later increases, the value of the peak inductor current Ipeak can be increased in a step-by-step manner to maintain the output voltage. An implementation of the disclosed second inductor current shifting method may be better understood with reference to some of the control signals generated in the DC / DC boost converter and by understanding how these control signals relate to the switching of the low-side power FET M1. Reference will be made to the disclosed locations where the control signals are generated. Figure 1B and reference inductor current to describe the behavior of several control signals Figure 2A and 2B Interpret the control signals.

[0036] Figure 1B Depicted is a block diagram of an example DC / DC boost converter 100B in which the disclosed operating methods may be implemented. Figure 1B and Figure 1A Similar, but more details are provided about the DC / DC boost converter chip 101. Within the DC / DC boost converter chip 101, the switch node SW is again located between the first pin P1 and the third pin P3, and the low-side power FET M1 is coupled between the switch node SW and the lower rail. The gate driver circuit 102 is coupled to receive the FET on signal FET_ON and controls the low-side power FET M1 in response to the FET on signal FET_ON.

[0037] The digital logic circuit 104 including the Ipeak shift circuit 106 in the current embodiment dynamically determines the switching frequency Fsw of the DC / DC boost converter 100B and creates the FET turn-on signal FET_ON. The switching frequency Fsw is determined by factors including the load current I_load and the peak inductor current Ipeak. As previously mentioned, when the load current drops, the switching frequency Fsw of the DC / DC boost converter 100B slows down to maintain a stable value of the increased output voltage Vbst, and care must be taken to ensure that the switching frequency Fsw does not drop into the audio range. The digital logic circuit 104 can monitor related indicators instead of directly monitoring the switching frequency Fsw. In one embodiment, the idle state time is monitored as explained below.

[0038] The input received by the digital logic circuit 104 includes signals from four comparators. The current limit comparator 108 compares the current (which is received on the inverting input) through the low-side power FET M1 with the value set for the peak inductor current Ipeak. The current value of the peak inductor current Ipeak is provided to the non-inverting input of the current limit comparator 108 by the Ipeak selection circuit 116. In one embodiment, the target peak value of the peak inductor current Ipeak can be set in firmware, and can have a value between 30mA and 500mA. It should be recognized that during the time when the low-side power FET M1 is turned on, the current through the low-side power FET M1 is the same as the current through the inductor L. Therefore, the current limit comparator 108 determines when the current through the inductor L is equal to the peak inductor current Ipeak, and provides a current limit signal CUR_LIM to signal that the inductor current I_ind has reached the peak inductor current Ipeak, and the low-side power FET M1 can be turned off.

[0039] The zero current comparator 110, the boost high comparator 112, and the power good comparator 114 each receive one or both of the two feedback signals provided by the first feedback selection circuit 118 and the second feedback selection circuit 120. The first feedback selection circuit 118 receives the switch node feedback voltage Vfb,sw from the switch node SW via the first resistor divider 119, scales the switch node feedback voltage Vfb,sw according to the target output voltage of the boosted output voltage Vbst, and provides the scaled switch node feedback voltage Vsfb,sw. The second feedback selection circuit 120 receives the boosted feedback voltage Vfb,bst from the boosted output voltage Vbst via the fourth pin P4 and the second resistor divider 121, scales the boosted feedback voltage Vfb,bst according to the target output voltage of the boosted output voltage Vbst, and provides the scaled boosted feedback voltage Vsfb,bst.

[0040] The zero current comparator 110 receives the scaled switch node feedback voltage Vsfb,sw on the inverting input and the scaled boosted feedback voltage Vsfb,bst on the non-inverting input. It should be noted that the switch node voltage Vsw is separated from the boosted output voltage Vbst by one diode drop across the second diode D2, but this difference disappears when the current through the first diode D1 is zero. Therefore, the zero current comparator 110 is able to detect the zero crossing of the inductor current I_ind by determining when the switch node voltage Vsw is equal to 85% of the boosted output voltage Vbst, and sets the zero current signal CUR_ZRO high when this condition is true. The zero current signal CUR_ZRO will remain high until the inductor current I_ind next reaches the peak current limit Ipeak, as will be demonstrated.

[0041] The boost high comparator 112 and the power good comparator 114 both receive the scaled boosted feedback voltage Vsfb,bst on respective non-inverting inputs. The boost high comparator 112 compares the scaled boosted feedback voltage Vsfb,bst with a first reference voltage representing a target output voltage. In one embodiment, the first reference voltage is 1.5V. Using the scaled voltage, the boost high comparator 112 effectively compares the boosted output voltage Vbst with the target output voltage, and sets the boosted voltage high signal BST_HI to a high value when the boosted output voltage Vbst is greater than the target output voltage.

[0042] The power good comparator 114 compares the scaled boosted feedback voltage Vsfb,bst with a second reference voltage representing a rising threshold. In one embodiment, the second reference voltage is 1.425V, which is 95% of the target output voltage 1.5V. Although not specifically shown, the power good comparator 114 also compares the scaled boosted feedback voltage Vsfb,bst with a third reference voltage representing a falling threshold. In one embodiment, the third reference voltage is 1.275V, which is 85% of 1.5V. The power good comparator 114 provides a power good signal PGOOD, which indicates to the digital logic circuit 104 that the scaled boosted feedback voltage is between the second reference voltage and the third reference voltage, i.e., the power supply is within the target range.

[0043] Figure 2A and 2B The inductor current during two different operating modes is graphically illustrated to show how the DC / DC boost converter 100B drops into the audio frequency band. Figure 2A depicts the inductor current I_ind during continuous conduction mode (CCM), and Figure 2B Plotting the inductor current I_ind during discontinuous conduction mode (DCM). Figure 2A During CCM in , the low-side power FET M1 is turned on during the on-state time Ton, and the inductor current I_ind rises at a constant rate until the inductor current I_ind reaches the peak inductor current Ipeak. At this point, the low-side power FET M1 is turned off during the off-state time Toff, and the inductor current I_ind steadily decreases until the inductor current I_ind reaches zero. When the inductor current I_ind reaches zero during CCM, it is determined that further charging is required immediately, and the cycle begins again. In CCM, the inductor current I_ind is rising or falling at any time, and the cycle time Tcycle is equal to Ton plus Toff.

[0044] In contrast, Figure 2BAs seen in , during DCM, the inductor current I_ind rises during the on-state time Ton to reach the peak inductor current Ipeak, and then falls during the off-state time Toff until the inductor current I_ind reaches zero. Once the inductor current I_ind reaches zero, it is determined that no further current is required for a certain period of time. This determination is made by checking the value of the boosted voltage high signal BST_HI when the zero current signal CUR_ZRO goes high. If the boosted voltage high signal BST_HI is high, then this indicates that no additional current is required, and an idle state time Tidle then occurs until the boosted voltage high signal BST_HI is low again. During DCM, the cycle time Tcycle is equal to Ton plus Toff plus Tidle. When the DC / DC boost converter 100B operates in CCM, the design will ensure that the switching frequency Fsw is greater than the audio band; however, when the idle state time Tidle becomes too large, the switching frequency Fsw may be in danger of falling into the audio band.

[0045] Therefore, the Ipeak shift circuit 106 can monitor the values ​​of the boosted voltage high signal BST_HI and the zero current signal CUR_ZRO to determine the length of the idle state time Tidle (if any). In one embodiment, in response to the Ipeak shift circuit 106 determining that the zero current signal CUR_ZRO has a rising edge and the boosted voltage high signal BST_HI has a high value, the Ipeak shift circuit 106 starts counting clock cycles until the boosted voltage high signal BST_HI has a falling edge. In one embodiment, an 8 MHz oscillator clock is used to measure the idle state time Tidle.

[0046] When the idle state time Tidle is greater than a first idle state threshold (e.g., 10 μs), the value of the peak inductor current Ipeak is reduced by a decrement according to the rules of the control process. In one embodiment, if a series of N consecutive cycles each have a corresponding idle state time Tidle greater than the first idle state threshold, then the decrement is applied. When a series of N consecutive cycles is required to trigger the decrement, a single cycle with an idle state time Tidle greater than a second idle state threshold (e.g., 32 μs) may also trigger a decrement of the peak inductor current Ipeak. The peak inductor current Ipeak may be decremented in this manner until it is determined that the possibility of falling into the audio band is no longer a threat.

[0047] When the peak inductor current Ipeak has decreased to a value below the target peak value, the DC / DC boost converter 100B needs to monitor whether the increased output voltage Vbst is still sufficient to meet the requirements of the load. When the load current I_load increases, the increased output voltage Vbst will decrease. If the Ipeak shift circuit 106 detects that the increased output voltage Vbst has dropped a given voltage drop, the peak inductor current Ipeak increases by an incremental amount. The peak inductor current Ipeak can be increased in a step-by-step manner until the increased output voltage Vbst stabilizes at the target output voltage again. In one embodiment, the peak inductor current Ipeak increases in each cycle when the increased output voltage Vbst is less than 85% of the target value (e.g., 11.5v). It is important to ensure that the increased output voltage Vbst is as constant as possible. For this reason, increasing the value of the peak inductor current Ipeak will generally occur at a faster rate than decreasing the peak inductor current Ipeak.

[0048] like Figure 1A and Figure 1B As shown in FIG. 5 , the use of Ipeak shifting in a DC / DC boost converter is effective because of the relationship between the boost converter cycle time Tcycle and the peak inductor current Ipeak and the load current I_load:

[0049]

[0050] Fsw is the switching frequency and is the inverse of the cycle time Tcycle.

[0051] Equation 1 confirms that reducing the peak inductor current Ipeak by a factor of 10 compensates for reducing the load current I_load by a factor of 100!

[0052] The relationship between the inductor voltage V_ind and the inductor current I_ind can be expressed by the following equation:

[0053]

[0054] Where L is the inductance of the inductor. Equation 2 can be rewritten as:

[0055]

[0056] The on-time T of the low-side power FET M1 can be expressed by the following equation:

[0057]

[0058] It should be noted that the load current I_ind is substantially linear between zero and the peak inductor current Ipeak in both the on-state and the off-state, and can be replaced by Ipeak / 2 for a first order approximation in the calculation. For an inductance L equal to 33 μH, a peak inductor current Ipeak equal to 500 mA, and a minimum value of the expression (Vin-I_ind*Rind-Rdson*I_ind) equal to 1.5 V, the value of the on-state time Ton is equal to 11 μs. The value of the off-state time Toff is expressed by the following equation:

[0059]

[0060] For an inductance of 33 μH, an inductor peak current of 500 mA, an output voltage Vout of 11.5 V, and the minimum value of the expression (Vout-Vin+Rind*I_ind+Vd) of 10 V, the off-state time Toff is equal to 1.65 μs. In general, the cycle time Tcycle is equal to Ton plus Toff of 12.65 μs.

[0061] During CCM mode, the cycle time Tcycle, which is equal to the on-state time Ton plus the off-state time Toff, can be expressed as follows:

[0062]

[0063] It can be rewritten as:

[0064]

[0065] Where η is the boost efficiency. Ignoring the core loss of the inductor L, the boost efficiency η can be expressed as:

[0066]

[0067] During DCM mode, the cycle time Tcycle is equal to the on-state time Ton plus the off-state time Toff plus the idle state time Tidle and can be expressed as:

[0068]

[0069] When R_ind*Ipeak / 2 is much smaller than Vout-Vin+Vd in the denominator, the cycle time Tcycle is proportional to Ipeak 2 / I_load. It can also be noted that the cycle time Tcycle is also proportional to the inductance L. Smaller inductance means higher switching frequency, although the inductance needs to meet the saturation current greater than the peak inductor current Ipeak.

[0070] With the math involved, we now look at the signals on the DC / DC boost converter 100B during the two Ipeak shifting methods. Figures 3 to 5 As shown in . Figure 3 Several waveforms from a DC / DC boost converter in which the disclosed first Ipeak shifting method is implemented are depicted. FIG. 300A depicts the gate driver supply voltage Vcc and the boosted output voltage Vbst. FIG. 300B depicts the power good signal Pgood; FIG. 300C depicts the boosted voltage high signal BST_HI; FIG. 300D depicts the current limit signal CUR_LIM; FIG. 300E depicts the zero current signal CUR_ZRO; FIG. 300F depicts the value of the peak inductor current Ipeak; and FIG. 300G depicts the inductor current I_ind. It may be noted in this figure and the following figures that although the peak inductor current Ipeak is discussed in milliamperes, the measured values ​​are shown as equivalent millivolts.

[0071] At startup, the gate driver supply voltage Vcc and the boosted output voltage Vbst in (300A) both start at 1.7V, which is the supply voltage from the battery minus the diode drop. The peak inductor current Ipeak (300F) is set to an initial peak of 40mA. The current limit signal CUR_LIM (300D) and the zero current signal CUR_ZRO (300E) begin to operate to control the operation of the low-side power FET M1, which causes a small amount of inductor current I_ind (300G) to be provided at the output pin each time the low-side power FET M1 is turned off, and thus causes both the gate driver supply voltage Vcc and the boosted output voltage Vbst (300A) to increase. This continues until the boosted output voltage Vbst reaches the threshold output voltage, which is 3.0V in the simulation shown.

[0072] When the boosted output voltage Vbst (300A) reaches the threshold output voltage, the peak inductor current Ipeak (300F) is set to a target peak value, which is 500mA in this embodiment. This causes the inductor current I_ind (300G) to have a wider swing because the amount of inductor current provided when the low-side power FET M1 is turned off increases to the new value of the peak inductor current Ipeak; both the gate driver supply voltage Vcc and the boosted output voltage Vbst now increase at a faster rate. In this embodiment, the gate driver supply voltage Vcc is clamped at 4.6V, but the boosted output voltage Vbst continues to climb to a target output voltage of approximately 11.5V. At 85% of the target output voltage, the power good signal Pgood (300B) goes high, and at 95% of the target output value, the boosted voltage high signal BST_HI (300C) begins to operate and indicates whether any idle time is required.

[0073] Figure 4 Several waveforms from a DC / DC boost converter in which the disclosed second Ipeak shifting method is implemented are depicted. Graph 400A depicts a boosted output voltage Vbst; Graph 400B depicts a load current I_load as it is varied to test the DC / DC boost converter operation; Graph 400C depicts a boosted voltage high signal BST_HI; Graph 400D depicts a zero current signal CUR_ZRO; Graph 400E depicts a downshift signal SHFT_DN; Graph 400F depicts an upshift signal SHFT_UP; Graph 400G depicts a peak inductor current Ipeak when this value is shifted; and Graph 400H depicts an inductor current I_ind.

[0074] At time T1, the boosted output voltage Vbst (400A) has reached the target output voltage, but the load current I_load is 0Amp. Since the zero current signal CUR_ZRO (400D) has a rising edge, the boosted voltage high signal BST_HI (400C) is determined to be high; the boosted voltage high signal BST_HI remains high until time T2. Due to the extended period in which the boosted voltage high signal BST_HI is high, the Ipeak shift circuit 106 determines that one cycle exceeds the second preset time, and the downshift signal SHFT_DN (400E) is activated, causing the inductor peak current Ipeak (400G) to decrease from 500mA to 450mA. At time T2, the load current I_load (400B) rises to 30.0 mA and normal switching of the DC / DC boost converter resumes at a peak inductor current Ipeak of 450 mA (400F), as shown by the boosted voltage high signal BST_HI (400C) and the zero current signal CUR_ZRO (400D).

[0075] At time T3, the load current I_load drops from 30.0 mA to 2.5 mA, and the switching frequency slows to compensate for the reduced current demand, as shown by the longer period of time that the boost voltage high signal BST_HI (400C) and the zero current signal CUR_ZRO (400D) remain in the high state. Shortly thereafter, the logic circuit detects the increased idle time and sets the downshift signal SHFT_DN (400E) high. During the time that the downshift signal SHFT_DN is high, the Ipeak shift circuit 106 adjusts the peak inductor current Ipeak (400G) downward at each cycle in this example, and the switching frequency increases until the downshift signal SHFT_DN (400E) is finally set low again after the value of the peak inductor current Ipeak (400G) decreases to 100 mA.

[0076] At time T4, the load current I_load (400B) increases from 2.5 mA to 20 mA, causing the boosted output voltage Vbst (400A) to drop. This change in boosted output voltage Vbst is quickly detected, and the up-shift signal SHFT_UP (400F) goes high. In response, the Ipeak shift circuit 106 adjusts the peak inductor current Ipeak (400G) upward until the peak inductor current Ipeak reaches 450 mA, at which point the boosted output voltage Vbst (400A) returns to the target output voltage. It may be noted that the time to increase the peak inductor current Ipeak from 100 mA to 450 mA is much shorter than the time to decrease the peak inductor current Ipeak by the same amount, because maintaining the boosted output voltage Vbst at a constant value is a high priority.

[0077] At time T5, the load current I_load (400B) decreases again, this time from 20mA to 5mA. When a decreasing switching cycle is detected, the downshift signal SHFT_DN (400E) is set high again, and the peak inductor current Ipeak (400G) decreases downward again until the switching frequency increases to a frequency that does not cause audible noise. In the example shown, the peak inductor current Ipeak decreases from 450mA to 130mA. By comparing the first downshift after time T3 with the second downshift after time T5, it can be seen that the speed at which the peak inductor current Ipeak decreases depends on the current cycle time, and the rate of change increases as the cycle time decreases.

[0078] At time T6, the load current I_load (400B) increases again, from 5 mA to 30 mA, and pulls the boosted output voltage Vbst (400A) low. Once the voltage drop is detected, the upshift signal SHFT_UP (400F) is set high, thereby enabling the Ipeak shift circuit 106 to increment the peak inductor current Ipeak. Since the voltage drop at time T6 is greater than the voltage drop at time T4, the boosted voltage high signal BST_HI (400C) remains low for a longer period of time, thereby signaling the continued need to restore the boosted output voltage Vbst (400A) to a nominal value. Although the peak inductor current Ipeak (400G) returns to the target value of 500mA quickly, the recovery of the boosted output voltage Vbst takes longer, so the boosted voltage high signal BST_HI (400C) remains low and the upshift signal SHFT_UP (400F) remains high until the boosted output voltage Vbst (400A) returns to approximately 11.5V.

[0079] Figure 5 Several waveforms from a DC / DC boost converter in which the disclosed first and second Ipeak shifting methods are implemented are depicted, emphasizing the fact that it is within the scope of the present disclosure to implement one or both of the disclosed shifting methods in a DC / DC boost converter. Graph 500A depicts a boosted output voltage Vbst; Graph 500B depicts a boosted voltage high signal BST_HI; Graph 500C depicts a zero current signal CUR_ZRO; Graph 500D depicts a power good signal Pgood; Graph 500E depicts a gate driver supply voltage Vcc; Graph 500F depicts a peak inductor current Ipeak; Graph 500G depicts an upshift signal SHFT_UP; Graph 500H depicts a downshift signal SHFT_DN; Graph 500I depicts an inductor current I_ind; and Graph 500J depicts a load current I_load. During a first time period GS1, the first Ipeak shifting method is confirmed and during a second time period GS2, the second Ipeak shifting method is confirmed.

[0080] At the beginning of the first time period GS1, the boosted output voltage Vbst (500A) is at a minimum value of about 1.7V, and the gate driver supply voltage Vcc (500E) has the same value. The peak inductor current Ipeak (500F) has an initial peak value of about 40mA, so that when the switching of the low-side power transistor M1 begins, the boosted output voltage Vbst (500A) and the gate driver supply voltage Vcc (500E) rise in slow increments. During this time period, the load current I_load (500J) is zero. Once the boosted output voltage Vbst reaches the threshold output voltage of about 3V in about 0.55 milliseconds in the simulation, the peak inductor current Ipeak (500F) is set to a target peak value of 500mA, and the boosted output voltage Vbst (500A) rises faster to a target output voltage of about 11.5V; the gate driver supply voltage Vcc (500E) follows the boosted output voltage Vbst to a value of about 4.7V, where the gate driver supply voltage Vcc is clamped. Once the boosted output voltage Vbst (500A) reaches 85% of the target output voltage, the power good signal Pgood (500D) goes high, and the logic circuit begins to operate, causing the up shift signal SHFT_UP (500G) to go high. Since the peak inductor current Ipeak (500F) has been set to the target peak value of 500mA, no further action is taken to increase the peak inductor current at this time.

[0081] The DC / DC boost converter 100B now enters the second time period GS2. When entering the simulation 2ms, the load current I_load (500J) changes from zero to 30mA. Due to the longer idle state time observed in the previous cycle (e.g., see the boost voltage high signal BST_HI (500B)), the downshift signal SHFT_DN (500H) becomes high in a short period of time, and the peak inductor current Ipeak (500F) decreases to 450mA. When entering the simulation 2.5ms, the load current I_load (500J) drops from 30mA to 2.5mA, and the switching frequency slows down, as reflected in the boost voltage high signal BST_HI (500B). After several switching cycles, the condition is identified and the downshift signal SHFT_DN (500H) is set to high, and the peak inductor current Ipeak (500F) decreases from 450mA to 80mA in a period of about 0.55 milliseconds.

[0082] At 3.5 milliseconds, the load current I_load (500J) rises to a value of 20mA, the up-shift signal SHFT_UP (500G) goes high briefly, and the peak inductor current Ipeak (500F) increases to 320mA to ensure that the boosted output voltage Vbst (500A) remains stable. At 4.0 milliseconds, the load current I_load (500J) decreases from 20mA to 5.0mA; after several switching cycles, the down-shift signal SHFT_DN (500H) goes high, and the peak inductor current Ipeak (500F) decreases in a series of steps to a value of 130mA. At 4.5 milliseconds, the load current I_load (500J) rises again to 30.0mA, the up-shift signal SHFT_UP (500G) goes high, and the peak inductor current Ipeak (500F) increases to a target peak value of 500mA.

[0083] Figure 6 Depicting an overall method 600 of operating a DC / DC boost converter according to an embodiment of the present disclosure; Fig. 6A and Figure 6B How the elements of method 600 are performed is further defined. Fig. 6A Depicting a first Ipeak shifting method 600A; and Figure 6B A second Ipeak shifting method 600B is depicted. The method 600 begins by receiving 605 a target peak value for the peak inductor current Ipeak. The target peak value may be provided in a number of ways, including hardwiring into the circuit, although more generally, the target peak value is provided in firmware, or programmed into the system using a pin input or a register input. In the embodiment shown herein, the target peak value is 500 mA, although this is only an example and not a limitation.

[0084] The method then continues to dynamically change 610 the value of the peak inductor current Ipeak in response to one or more determinations related to one of the increased output voltage and switching frequency of the DC / DC boost converter. As seen in the previous discussion, the first Ipeak shifting method relies on the value of the increased output voltage Vbst to increase the peak inductor current Ipeak to a target peak value, while the second shifting method utilizes the switching frequency, or an alternative to the switching frequency, such as the idle state time or the total switching cycle time, to adjust the peak inductor current Ipeak downward, and uses the increased output voltage Vbst to adjust the peak inductor current Ipeak upward.

[0085] In method 600A, dynamically changing the value of the peak inductor current Ipeak includes setting 615 the peak inductor current to an initial peak value at startup, the initial peak value being lower than the target peak value. In one embodiment, the initial peak value is 40mA and the target peak value is 500mA. Then, the method continues to set 620 the peak inductor current Ipeak to the target peak value in response to determining that the boosted output voltage is not less than the threshold output voltage. In one embodiment, the threshold output voltage is 3.0V, which can provide a target peak value for the inductor peak current Ipeak when used as the gate voltage of the low-side NFET M1. Finally, in response to determining that the boosted output voltage has dropped below the threshold output voltage, the Ipeak shift circuit can reset 625 the peak inductor current Ipeak to the initial peak value, and then restore the peak inductor current Ipeak to the target peak value in response to determining that the boosted output voltage is not less than the threshold output voltage.

[0086] In method 600B, dynamically changing the value of the peak inductor current includes determining 630 the duration of the corresponding idle state time of each switching cycle. The value of the peak inductor current Ipeak may be reduced 635 by a decremental amount in response to determining that a first selectable number of consecutive switching cycles each have a corresponding idle state time greater than a first idle state threshold (e.g., 10 μsec). The value of the peak inductor current Ipeak may also be reduced 640 in response to determining that a single switching cycle has a corresponding idle state time greater than a second idle state threshold (e.g., 32 μsec). The boosted output voltage is also monitored 645 to determine whether the boosted output voltage remains at a target output voltage. In response to determining that the boosted output voltage has dropped below the target output voltage, the value of the peak inductor current Ipeak is increased 650 by an incremental amount unless the peak inductor current is already at a target peak value.

[0087] Figure 7An example of a smoke detector 700 incorporating a DC / DC boost converter 702 is depicted in accordance with an embodiment of the present disclosure. The smoke detector 700 includes an IC chip 701 having several circuits implemented thereon. The IC chip 701 includes a DC / DC boost converter 702, which may be implemented using the hardware disclosed in the DC / DC boost converter chip 101 and the disclosed Ipeak shifting method discussed in methods 600, 600A, and 600B. The IC chip 701 also includes a carbon monoxide detection circuit 704, a photodetection circuit 706, an ion detection circuit 708, and a siren driver 721. In one embodiment, the photodetection circuit 706 also includes a first light emitting diode (LED) driver 712 and a second LED driver 714. The carbon monoxide detection circuit 704 is coupled to a first plurality of pins 705; the photodetection circuit 706 is coupled to a second plurality of pins 707; the ion detection circuit 708 is coupled to a third plurality of pins 709; and the siren driver 721 is coupled to a fourth plurality of pins 711. The multiplexer 710 may receive input signals from each of the carbon monoxide detection circuit 704 , the photoelectric detection circuit 706 , and the ion detection circuit 708 .

[0088] The DC / DC boost converter 702 is coupled to a first pin P1 to receive power from a battery BAT through an inductor L, and to a third pin P3 to provide an increased output voltage Vbst. The connection to the second pin P2 is not specifically shown. The third pin P3 is also coupled to a fourth pin P4, which provides the increased output voltage Vbst to a low dropout (LDO) regulator 720. Pin P4 may also be coupled to an AC / DC converter 732, which may provide a substitute for the voltage provided by the battery BAT. The LDO regulator 720 provides a gate driver supply voltage Vcc to the IC chip 701. The gate driver supply voltage Vcc is distributed to the DC / DC boost converter 702 (where the voltage may be clamped), and a microcontroller (MCU) LDO 716, an internal LDO 718, and a Vcc divider 719. MCU LDO 716 provides supply voltage to MCU 730 and I / O buffers (not specifically shown); internal LDO 718 provides supply voltage to internal circuits such as data core and analog blocks, such as carbon monoxide detection circuit 704, photoelectric detection circuit 706, and ion detection circuit 708; and Vcc voltage divider 719 provides supply voltage to multiplexer 710. A siren driver 721 may be provided to drive a siren 729.

[0089] In the smoke detector 700, the carbon monoxide detection circuit 704 is coupled to the carbon monoxide sensor 722 through the first plurality of pins 705; the photodetection circuit 706, which may include the first LED driver 712 and the second LED driver 714, is coupled to the light sensor 724 and the LED 726 through the second plurality of pins 707; the ion detection circuit 708 is coupled to the ion sensor 728 through the third plurality of pins 709; and the alarm driver 721 is coupled to the alarm 729 through the fourth plurality of pins 711. The carbon monoxide sensor 722, the light sensor 724, and the ion sensor 728 collect the information needed to detect smoke and carbon monoxide in the area, and the alarm 729 sounds an audible sound alarm when smoke or carbon monoxide is detected. The IC chip 701 is also coupled to the MCU 730 through the fifth plurality of pins 713, where the IC chip 701 supplies both power and information to the MCU 730, and receives instructions to control various aspects of the operation of the smoke detector 700.

[0090] Applicants have disclosed a method of operating a DC / DC boost converter that dynamically changes the peak inductor current Ipeak to accommodate the changing needs of the DC / DC boost converter. The peak inductor current Ipeak may change during startup of the IC chip, and may also change any time the load current drops (which drops the switching frequency into the audio range) or the boosted output voltage drops (indicating that the peak inductor current Ipeak may be too low). Advantages may include one or both of power savings and area savings. Area savings may come from the size of one or both of the low-side power FET M1 and the gate driver circuit 102. Power consumption may be saved during startup or when the DC / DC boost converter is lightly loaded compared to using a dummy current load to keep the switching frequency above the audio band.

[0091] Although various embodiments have been shown and described in detail, the claims are not limited to any particular embodiment or example. None of the above detailed descriptions should be construed as implying that any particular component, element, step, action or function is necessary so that it must be included within the scope of the claims. Unless explicitly stated, an element in the singular form is not intended to mean "one and only one", but rather "one or more". All structural and functional equivalents of the elements of the embodiments described above known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the present claims. Therefore, those skilled in the art will recognize that the exemplary embodiments described herein can be practiced by various modifications and changes within the spirit and scope of the following appended claims.

Claims

1. An electronic device comprising a DC / DC boost converter, the DC / DC boost converter comprising: a voltage source providing a DC voltage; an inductor having a first inductor terminal and a second inductor terminal, the first inductor terminal being coupled to the voltage source; a power N-type field effect transistor NFET having a first current terminal and a second current terminal and a control terminal, the first current terminal being coupled to the second inductor terminal, and the second current terminal being grounded; a diode having a cathode and an anode, the anode coupled to the first current terminal and the cathode providing a boosted output voltage; a digital logic circuit having a digital logic input and a digital logic output, the digital logic input being coupled to the cathode and the digital logic output being coupled to the control terminal, the digital logic circuit being configured to determine a switching frequency of the power N-type field effect transistor (NFET) and to determine a duration of a corresponding idle state time of a corresponding switching cycle, the digital logic circuit including an Ipeak shift circuit configured to reduce a peak inductor current in response to a number of idle state times exceeding an idle state threshold.

2. The electronic device of claim 1 , wherein the Ipeak shift circuit is configured to set the peak inductor current to an initial peak value at startup, and to set the peak inductor current to a target peak value in response to the boosted output voltage being not less than a threshold output voltage, the target peak value being greater than the initial peak value.

3. The electronic device of claim 2 , wherein the Ipeak shift circuit is further configured to set the peak inductor current to the initial peak value in response to the boosted output voltage dropping below the threshold output voltage, and to set the peak inductor current to the target peak value in response to the boosted output voltage being not less than the threshold output voltage. 4 . The electronic device of claim 1 , wherein the idle state time is a first idle state time, and the Ipeak shift circuit reduces the peak inductor current in response to a corresponding switching cycle having an idle state time exceeding a second idle state threshold. 5 . The electronic device of claim 4 , wherein the Ipeak shift circuit increases the peak inductor current in response to the boosted output voltage dropping below a target output voltage.

6. The electronic device of claim 1 , wherein determining the duration of the corresponding idle state time comprises: monitoring a boosted voltage high signal and a zero current signal for each respective switching cycle, the boosted voltage high signal being set high when the boosted output voltage is greater than a target output voltage, the zero current signal being set high when an inductor current is zero, and the zero current signal being set low when the inductor current is at the peak inductor current; and In response to a rising edge of the zero current signal and the boosted voltage high signal being high, the corresponding idle state time is counted until the boosted voltage high signal is low.

7. The electronic device according to claim 6, further comprising: a zero current comparator having a first zero comparator input coupled to a first scaled boosted feedback voltage terminal and a second zero comparator input coupled to a second scaled boosted feedback voltage terminal and a zero comparator output configured to provide the zero current signal; and a boost high comparator having a first boost comparator input coupled to the second scaled boosted feedback voltage terminal, a second boost comparator input coupled to a first reference voltage terminal, and a boost comparator output configured to provide the boosted voltage high signal.

8. The electronic device according to claim 7, further comprising: a current limit comparator having a current limit comparator output and configured to compare a current through the power N-type field effect transistor (NFET) with the peak inductor current and provide a current limit signal at the current limit comparator output; and A power good comparator having a first power comparator input coupled to the second scaled boosted feedback voltage terminal, a second power comparator input coupled to a second reference voltage terminal and a third power comparator input coupled to a third reference voltage terminal, and a power comparator output providing a power good signal indicating when the scaled feedback voltage is between the second reference voltage and the third reference voltage. 9 . The electronic device according to claim 1 , wherein the electronic device comprises an integrated circuit (IC) chip, on which the power N-type field effect transistor (NFET), the gate driver and the digital logic circuit are manufactured.

10. The electronic device of claim 9, wherein the integrated circuit IC chip further comprises a power terminal coupled to a gate driver supply terminal, the gate driver supply terminal having a voltage derived from the boosted output voltage.

11. The electronic device according to claim 10, wherein the integrated circuit IC chip further comprises: Carbon monoxide detection circuit; Photoelectric detection circuit; an ion detection circuit, each of the carbon monoxide detection circuit, the photoelectric detection circuit, and the ion detection circuit being powered by the gate driver supply terminal; Siren drivers; and A multiplexer is coupled to the carbon monoxide detection circuit, the photoelectric detection circuit, and the ion detection circuit.

12. The electronic device according to claim 11, wherein the electronic device further comprises a smoke detector, the smoke detector comprising: Carbon monoxide sensor; Light sensor; Ion sensor; Siren; and Microcontroller.

13. A method of operating a DC / DC boost converter, the method comprising: receiving a target peak value of a peak inductor current; and dynamically changing the value of the peak inductor current in response to one or more of an increased output voltage and a switching frequency of the DC / DC boost converter; determining a duration of a corresponding idle state time for a corresponding switching cycle of the boost converter; reducing the peak inductor current in response to a first number of consecutive respective switching cycles having respective idle state times greater than a first idle state threshold; and The peak inductor current is reduced in response to the corresponding idle state time being greater than a second idle state threshold.

14. The method of claim 13, wherein dynamically changing the value of the peak inductor current comprises: setting the peak inductor current to an initial peak value at startup, the initial peak value being lower than the target peak value; and In response to the boosted output voltage being greater than a threshold output voltage, the peak inductor current is set to the target peak value.

15. The method of claim 14, further comprising setting the peak inductor current to the initial peak value in response to the boosted output voltage dropping below the threshold output voltage, and setting the peak inductor current to the target peak value in response to the boosted output voltage being not less than the threshold output voltage.

16. The method of claim 13, wherein determining the duration of the corresponding idle state time comprises: at the zero current comparator, in response to the switch node voltage being equal to a first percentage of the boosted output voltage, setting a zero current signal high; at the boost high comparator, in response to the boosted output voltage being greater than the target output voltage, setting a boost voltage high signal high; and In response to a rising edge of the zero current signal and the boosted voltage high signal is high, clock cycles are counted, and in response to a falling edge of the boosted voltage high signal the counting stops.

17. The method of claim 13, further comprising: monitoring the increased output voltage; and The peak inductor current is increased in response to the boosted output voltage dropping by a threshold amount.

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