Electronic device and method for implementing the same

Abstract

Devices and techniques for variable pipeline length in a barrel multithreaded processor are described herein. A completion time of an instruction may be determined prior to insertion into a pipeline of a processor. A conflict between the instruction and a different instruction based on the completion time may be detected. Here, the different instruction is already in the pipeline, and the conflict is detected when the completion time is equal to the previously determined completion time of the different instruction. The difference between the completion time and the non-conflicting completion time may then be calculated, and completion of the instruction may be delayed by the difference.

Description

Technical Field

[0001] In general, the present application relates to chiplet systems. In particular, the present application relates to variable pipeline length in barrel multithreaded processors. Background Art

[0002] Chiplets are an emerging technology for integrating various processing functions. In general, a chiplet system is composed of discrete modules (each referred to as a "chiplet") that are integrated on an interposer and interconnected by one or more established networks as needed in many instances to provide the desired functionality to the system. The interposer and the included chiplets may be packaged together to facilitate interconnection with other components of the larger system. Each chiplet may include one or more individual integrated circuits (ICs) or "chips," which may be combined with discrete circuit components and are commonly coupled to a respective substrate for attachment to the interposer. Most or all of the chiplets in the system will be individually configured for communication over one or more established networks.

[0003] The configuration of chiplets as individual modules of a system is different from such a system implemented on a single chip, which contains different device blocks (e.g., intellectual property (IP) blocks) on one substrate (e.g., a single die), such as a system on a chip (SoC), or multiple discrete packaged devices integrated on a printed circuit board (PCB). In general, chiplets provide better performance (e.g., lower power consumption, reduced latency, etc.) than discrete packaged devices, and chiplets provide greater production benefits than single die chips. These production benefits can include higher yields or reduced development costs and time.

[0004] A chiplet system may include, for example, one or more application (or processor) chiplets and one or more support chiplets. Here, the distinction between application chiplets and support chiplets is merely a reference to possible design scenarios for a chiplet system. Thus, for example, a synthetic vision chiplet system may include (by way of example only) an application chiplet for generating synthetic vision output, and support chiplets, such as a memory controller chiplet, a sensor interface chiplet, or a communication chiplet. In a typical use case, a synthetic vision designer may design an application chiplet and obtain support chiplets from other parties. Thus, design expenditures (e.g., in terms of time or complexity) are reduced by avoiding the design and production of functions included in the support chiplets. Chipsets also support tight integration of IP blocks that may otherwise be difficult, such as IP blocks manufactured using different processing technologies or using different feature sizes (or utilizing different contact technologies or spacings). Thus, multiple ICs or IC assemblies with different physical, electrical, or communication characteristics can be assembled in a modular manner to provide an assembly that implements the desired functionality. A chiplet system may also facilitate adaptation to the needs of different larger systems into which the chiplet system will be incorporated. In an example, an IC or other assembly may be optimized for power, speed, or heat generation for a particular function, as might be the case with a sensor, and may be more easily integrated with other devices than attempting to integrate them on a single die. Additionally, by reducing the overall size of the die, the yield of a chiplet tends to be higher than the yield of a more complex single-die device. Summary of the invention

[0005] In one aspect, the present application provides a device comprising: a pipeline circuit system for implementing a pipeline; an instruction write-back circuit system configured to: determine a completion time of an instruction before inserting it into the pipeline; detect a conflict between the instruction and a different instruction based on the completion time, wherein the conflict is detected when the completion time is equal to a second completion time of the different instruction in the pipeline; and calculate a difference between the completion time and a non-conflicting completion time; and a write delay circuit system configured to delay the completion of the instruction by the difference.

[0006] In another aspect, the present application provides a method comprising: determining a completion time of an instruction before inserting it into a pipeline of a processor; detecting a conflict between the instruction and a different instruction based on the completion time, wherein the conflict is detected when the completion time is equal to a second completion time of the different instruction; calculating a difference between the completion time and a non-conflicting completion time; and delaying completion of the instruction by the difference. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure. However, the drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0008] Figure 1A and 1B An example of a chiplet system according to an embodiment is described.

[0009] Figure 2 Components of an example of a memory controller chiplet in accordance with an embodiment are described.

[0010] Figure 3 Components in an example of a programmable atomic unit (PAU) according to an embodiment are described.

[0011] Figure 4 A process flow through a processor component for variable pipeline length in a barrel multithreaded processor according to an embodiment is described.

[0012] Figure 5 Flowchart of an example of a method for variable pipeline length in a barrel multithreaded processor according to an embodiment.

[0013] Figure 6 A block diagram of an example of a machine with which, in, or through which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0014] FIG. 1 described below provides an example of a chiplet system and components operating therein. The illustrated chiplet system includes a memory controller. This memory controller includes a programmable atomic unit (PAU) for executing a custom program, a programmable atomic operator, in response to a memory request for a programmable atomic operator. Figure 2 and 3 Additional details about the PAU are described. The processor of the PAU can be barrel multithreaded and pipelined. Barrel multithreaded processors provide several benefits, such as tolerating the latency of external memory requests when executing many simultaneous threads in a single core while maintaining high instruction execution throughput. However, lightly loaded barrel multithreaded processors may have problems. Here, lightly loaded means executing few (e.g., one or two) of the available (e.g., eight) hardware threads. In such cases, many clock cycles may be wasted on idle hardware threads.

[0015] A typical barrel multithreaded processor has a fixed pipeline length based on the number of hardware threads. Typically, at each clock, the register file switches to a new thread for a given pipeline stage. This means that the minimum time between thread instruction executions (e.g., between adjacent instructions in a thread) is equal to the number of supported hardware threads. Therefore, the delay before a thread can execute the next instruction is fixed, regardless of the instruction operation. This approach is used in many barrel multithreaded processors to keep the processor core control hardware simple. However, as noted above, this is inefficient for lightly loaded processors.

[0016] To address the lightly loaded barrel multithreaded processor problem, a variable length pipeline can be used in the processor. Here, the thread's instructions can be completed early, and the write back to the register can be performed as quickly as possible without waiting for the full processor pipeline to complete. This is achieved by tracking the thread identifier (ID) of the thread while the instruction is in the pipeline, and reinserting the thread ID into the thread ready to run queue when the register write back is completed. Once the thread ID is returned to the thread ready to run queue, the thread can be rescheduled, which potentially enables faster rescheduling of threads than is possible in traditional barrel multithreaded processor implementations.

[0017] A problem that may arise with variable pipeline lengths is register writeback conflicts between threads within a single clock cycle. In a traditional barrel multithreaded implementation, this conflict will not occur because the writeback cycle is at the same stage of the pipeline across the threads. Because the threads start the pipeline at different clock cycles, only one thread attempts to perform a writeback in any given cycle. However, in the case of a variable length pipeline, conflicts may occur.

[0018] To resolve register writeback conflicts, instruction register writebacks are checked to determine if there is a conflict. If there is no conflict, then once the instruction can be written back to the register, the instruction can be written back to the register. Therefore, with respect to a move instruction that is completed at the second stage of the pipeline, when the second stage is completed, the instruction can be written back to the register at a clock cycle. However, if there is a conflict, the instruction is tracked with a delay (e.g., in clock cycles). Therefore, a move instruction may conflict with an earlier instruction that takes a long time to complete (e.g., a later stage). Here, a delay can be given to the move instruction, such as a single clock cycle. When the move instruction is completed, the delay is queried and the move instruction is prevented from performing a writeback. Here, the move instruction remains in the pipeline until the delay expires and the writeback may be completed. At this point, the thread can be rescheduled.

[0019] By providing a variable length pipeline, a significant disadvantage of a barrel multithreaded processor is addressed. Although a barrel multithreaded processor is typically used when many threads are expected to be executed, many programs start with a single thread and are later changed to use more threads. Therefore, for many programs, when the pipeline has a fixed length, the barrel multithreaded processor may be inefficient until there is sufficient parallelism (e.g., hardware threads). By introducing a variable length pipeline, this problem can be improved. Additional details and examples are provided below.

[0020] Figure 1A and 1B An example of a chiplet system 110 according to an embodiment is described. Figure 1A 1 is a representation of a chiplet system 110 mounted on a peripheral board 105, which may be connected to a wider computer system, for example, via a peripheral component interconnect express (PCIe). The chiplet system 110 includes a package substrate 115, an interposer 120, and four chiplets, namely an application chiplet 125, a host interface chiplet 135, a memory controller chiplet 140, and a memory device chiplet 150. Other systems may include many additional chiplets to provide additional functionality, as will be apparent from the following discussion. The packaging of the chiplet system 110 is illustrated with a lid or cover 165, but other packaging techniques and structures for chiplet systems may be used. Figure 1B A block diagram of components in a chiplet system is labeled for clarity.

[0021] The application chiplet 125 is illustrated as including a network on chip (NOC) 130 to support a chiplet network 155 for inter-chiplet communications. In an example embodiment, the NOC 130 may be included on the application chiplet 125. In an example, the NOC 130 may be defined in response to selected supporting chiplets (e.g., chiplets 135, 140, and 150), enabling a designer to select an appropriate number or chiplet network connections or switches for the NOC 130. In an example, the NOC 130 may be located on a separate chiplet, or even within the interposer 120. In an example as discussed herein, the NOC 130 implements a chiplet protocol interface (CPI) network.

[0022] CPI is a packet-based network that supports virtual channels to enable flexible and high-speed interactions between chiplets. CPI implements bridging from a chiplet intra-network to a chiplet network 155. For example, the Advanced Extensible Interface (AXI) is a widely used specification for designing intra-chip communications. However, the AXI specification covers a large number of physical design options, such as the number of physical channels, signal timing, power, etc. Within a single chip, these options are typically selected to meet design goals, such as power consumption, speed, etc. However, in order to achieve flexibility in chiplet systems, adapters such as CPI are used to interface between various AXI design options that can be implemented in various chiplets. CPI bridges the chiplet intra-network across the chiplet network 155 by implementing a mapping of physical channels to virtual channels and encapsulating time-based signaling with a packetized protocol.

[0023] CPI can use a variety of different physical layers to transmit packets. The physical layer may include a simple conductive connection, or may include a driver to increase the voltage, or otherwise facilitate the transmission of signals over longer distances. An example of such a physical layer may include an advanced interface bus (AIB), which may be implemented in the intermediate layer 120 in various examples. AIB uses source synchronous data transmission with a forwarding clock to transmit and receive data. Packets are transmitted across the AIB relative to the transmitted clock at a single data rate (SDR) or a double data rate (DDR). AIB supports various channel widths. When operating in SDR mode, the AIB channel width is a multiple of 20 bits (20, 40, 60...), and for DDR mode, the AIB channel width is a multiple of 40 bits: (40, 80, 120...). The AIB channel width includes transmission and reception signals. The channel can be configured to have a symmetrical number of transmission (TX) and reception (RX) input / output (I / O), or an asymmetrical number of transmitters and receivers (e.g., all transmitters or all receivers). A channel can act as an AIB master or slave depending on which chiplet provides the master clock. The AIB I / O cell supports three clocking modes: asynchronous (i.e., unclocked), SDR, and DDR. In various instances, the unclocked mode is used for clocks and some control signals. The SDR mode can use a dedicated SDR-only I / O cell, or dual-use SDR / DDR I / O cells.

[0024] In an example, a CPI packet protocol (e.g., point-to-point or routable) may use symmetrical receive and transmit I / O units within an AIB channel. The CPI stream protocol allows for more flexible use of the AIB I / O units. In an example, an AIB channel in stream mode may configure the I / O units to be all TX, all RX, or half TX and half RX. The CPI packet protocol may use the AIB channel in SDR or DDR operating modes. In an example, the AIB channel is configured in increments of 80 I / O units (i.e., 40 TX and 40 RX) for SDR mode and in increments of 40 I / O units for DDR mode. The CPI stream protocol may use the AIB channel in SDR or DDR operating modes. Here, in an example, the AIB channel is in increments of 40 I / O units for both SDR and DDR modes. In an example, each AIB channel is assigned a unique interface identifier. The identifier is used during CPI reset and initialization to determine paired AIB channels across adjacent chiplets. In an example, the interface identifier is a 20-bit value that includes a seven-bit chiplet identifier, a seven-bit column identifier, and a six-bit link identifier. The AIB physical layer uses the AIB out-of-band shift register to transmit the interface identifier. The 20-bit interface identifier is transmitted in both directions across the AIB interface using bits 32 to 51 of the shift register.

[0025] AIB defines a stacked group of AIB channels as an AIB channel column. An AIB channel column has a certain number of AIB channels, plus auxiliary channels. Auxiliary channels contain signals for AIB initialization. All AIB channels in a column (except auxiliary channels) have the same configuration (e.g., all TX, all RX, or half TX and half RX, and have the same number of data I / O signals). In an example, the AIB channels are numbered in a continuous increasing order, starting with the AIB channel adjacent to the AUX channel. The AIB channel adjacent to the AUX is defined as AIB channel zero.

[0026] In general, the CPI interface of individual chiplets may include serialization-deserialization (SERDES) hardware. SERDES interconnects are well suited for scenarios requiring high-speed signaling and low signal counts. However, SERDEs may incur additional power consumption and longer latency for multiplexing and demultiplexing, error detection or correction (e.g., using block-level cyclic redundancy checks (CRCs)), link-level retries, or forward error correction. However, when low latency or energy consumption is the primary concern for ultra-short distance chiplet-to-chiplet interconnects, a parallel interface may be utilized whose clock rate allows data transfer with minimal latency. CPI includes elements for minimizing both latency and energy consumption for these ultra-short distance chiplet interconnects.

[0027] For flow control, CPI employs a credit-based technique. A receiver, such as application chiplet 125, provides credits representing available buffers to a sender, such as memory controller chiplet 140. In an example, a CPI receiver contains a buffer for each virtual channel for a given transmission time unit. Thus, if a CPI receiver supports five messages and a single virtual channel in time, then the receiver has five buffers arranged in five rows (e.g., one row per unit time). If four virtual channels are supported, then the receiver has twenty buffers arranged in five rows. Each buffer holds the payload of a CPI packet.

[0028] As the sender transmits to the receiver, the sender decrements the available credits based on the transmission. Once all credits of the receiver are used up, the sender stops sending packets to the receiver. This ensures that the receiver always has an available buffer to store the transmission.

[0029] When the receiver processes the received packets and frees up the buffer, the receiver communicates the available buffer space back to the sender. The sender can then use this credit back to allow the transmission of additional information.

[0030] Also illustrated is a chiplet mesh network 160 that uses direct chiplet-to-chiplet technology without the need for a NOC 130. The chiplet mesh network 160 can be implemented in CPI or another chiplet-to-chiplet protocol. The chiplet mesh network 160 typically implements a chiplet pipeline, where one chiplet acts as an interface to the pipeline, while other chiplets in the pipeline interface only interface with themselves.

[0031] In addition, dedicated device interfaces may also be used to interconnect the chiplets, such as one or more industry standard memory interfaces 145 (e.g., synchronous memory interfaces, such as DDR5, DDR 6). The connection of the chiplet system or individual chiplets to an external device (e.g., a larger system) can be through a desired interface (e.g., a PCIE interface). In an example, for example, an external interface may be implemented through a host interface chiplet 135, which in the depicted example provides a PCIE interface external to the chiplet system 110. When conventions or standards in the industry have converged on such dedicated interfaces 145, such interfaces are generally adopted. The illustrated example of a double data rate (DDR) interface 145 that connects a memory controller chiplet 140 to a dynamic random access memory (DRAM) memory device 150 is such an industry convention.

[0032] Among the multiple possible supporting chiplets, the memory controller chiplet 140 is likely to be present in the chiplet system 110 because of the almost ubiquitous use of storage for computer processing and the use of advanced technologies for memory devices. Therefore, the use of memory device chiplets 150 and memory controller chiplets 140 produced by other technologies enables chiplet system designers to obtain robust products produced by mature manufacturers. In general, the memory controller chiplet 140 provides a memory device specific interface to read, write or erase data. Typically, the memory controller chiplet 140 may provide additional features, such as error detection, error correction, maintenance operations, or atomic operator execution. For some types of memory, maintenance operations are often specific to the memory device 150, such as garbage collection in NAND flash or storage class memory, temperature adjustment in NAND flash memory (e.g., cross temperature management). In an example, the maintenance operation may include logical to physical (L2P) mapping or management to provide an indirect level between the physical and logical representations of data. In other types of memory, such as DRAM, some memory operations, such as refresh, may be controlled at certain times by a host processor or memory controller and at other times by the DRAM memory device or logic associated with one or more DRAM devices, such as an interface chip (in an example, a buffer).

[0033] Atomic operators are data manipulations that may be performed, for example, by the memory controller chiplet 140. In other chiplet systems, atomic operators may be performed by other chiplets. For example, an atomic operator of "increment" may be specified by the application chiplet 125 in a command that includes a memory address and possibly an increment value. Upon receiving the command, the memory controller chiplet 140 retrieves a number from the specified memory address, increments the number by the amount specified in the command, and stores the result. Upon successful completion, the memory controller chiplet 140 provides an indication of the success of the command to the application chiplet 125. Atomic operators avoid transmitting data across the chiplet network 160, thereby reducing the latency of executing such commands.

[0034] Atomic operators may be classified as built-in atomics or programmable (e.g., custom) atomics. Built-in atomics are a limited set of operations that are implemented invariantly in hardware. Programmable atomics are small programs that can be executed on a programmable atomic unit (PAU) (e.g., a custom atomic unit (CAU)) of a memory controller chiplet 140. FIG. 1 illustrates an example of a memory controller chiplet discussing a PAU.

[0035] The memory device chiplet 150 may be or include any combination of volatile memory devices or non-volatile memory. Examples of volatile memory devices include, but are not limited to, random access memory (RAM), such as DRAM, synchronous DRAM (SDRAM), Graphic Double Data Rate Type 6 SDRAM (GDDR6 SDRAM), and the like. Examples of non-volatile memory devices include, but are not limited to, NAND-type flash memory, storage class memory (e.g., phase change memory or memristor-based technology), ferroelectric RAM (FeRAM), and the like. The illustrated example includes the memory device 150 as a chiplet, however, the memory device 150 may reside elsewhere, such as in a different package on the peripheral board 105. For many applications, multiple memory device chiplets may be provided. In an example, these memory device chiplets may each implement one or more memory technologies. In an example, a memory chiplet may include multiple stacked memory dies of different technologies, such as one or more static random access memory (SRAM) devices stacked or otherwise communicating with one or more dynamic random access memory (DRAM) devices. The memory controller 140 may also be used to coordinate operations between multiple memory chiplets in the chiplet system 110; for example, utilizing one or more memory chiplets in one or more levels of cache storage and using one or more additional memory chiplets as main memory. The chiplet system 110 may also include multiple memory controllers 140, which may be used to provide memory control functionality for separate processors, sensors, networks, etc. For example, the chiplet architecture of the chiplet system 110 provides the advantage of allowing adaptation to different memory storage technologies and different memory interfaces through updated chiplet configurations without requiring redesign of the rest of the system architecture.

[0036] Figure 2Components of an example of a memory controller chiplet 205 according to an embodiment are illustrated. The memory controller chiplet 205 includes a cache 210, a cache controller 215, an off-die memory controller 220 (e.g., for communicating with an off-die memory 275), a network communication interface 225 (e.g., for interfacing with a chiplet network 285 and communicating with other chiplets), and a set of atomic and coalescing units 250. Components of this set may include, for example, a write coalescing unit 255, a memory hazard unit 260, a built-in atomic unit 265, or a PAU 270. The various components are illustrated logically, and they may not necessarily be implemented. For example, it is possible that the built-in atomic unit 265 includes different devices along the path to the off-die memory. For example, the built-in atomic unit 265 may be in an interface device / buffer on the memory chiplet, as discussed above. In contrast, the programmable atomic unit 270 may be implemented in a separate processor on the memory controller chiplet 205 (but in various examples may be implemented in other locations, such as on the memory chiplet).

[0037] The off-die memory controller 220 is directly coupled to the off-die memory 275 (e.g., via a bus or other communication connection) to provide write operations and read operations to and from one or more off-die memories, such as the off-die memory 275 and the off-die memory 280. In the depicted example, the off-die memory controller 220 is also coupled to the atomic and merge unit 250 for outputs and to the cache controller 215 (e.g., a memory-side cache controller) for inputs.

[0038] In an example configuration, cache controller 215 is directly coupled to cache 210 and may be coupled to network communication interface 225 for input (eg, incoming read or write requests) and to off-die memory controller 220 for output.

[0039] The network communication interface 225 includes a packet decoder 230, a network input queue 235, a packet encoder 240, and a network output queue 245 to support a packet-based chiplet network 285, such as CPI. The chiplet network 285 can provide packet routing between and among processors, memory controllers, mixed-thread processors, configurable processing circuits, or communication interfaces. In such packet-based communication systems, each packet typically includes destination and source addressing, as well as any data payload or instructions. In an example, depending on the configuration, the chiplet network 285 can be implemented as a collection of crossbar switches with a folded Clos configuration, or a mesh network providing additional connectivity.

[0040] In various examples, the chiplet network 285 can be part of an asynchronous switching fabric. Here, data packets can be routed along any of a variety of paths so that any selected data packet can reach the addressed destination at any of a number of different times, depending on the routing. Additionally, the chiplet network 285 can be implemented at least in part as a synchronous communication network, such as a synchronous mesh communication network. Both configurations of communication networks are contemplated for use in accordance with examples of the present disclosure.

[0041] The memory controller chiplet 205 may receive a packet with, for example, a source address, a read request, and a physical address. In response, the off-die memory controller 220 or cache controller 215 will read the data from the specified physical address (which may be in the off-die memory 275 or cache 210) and assemble a response packet with the source address containing the requested data. Similarly, the memory controller chiplet 205 may receive a packet with a source address, a write request, and a physical address. In response, the memory controller chiplet 205 will write the data to the specified physical address (which may be in the cache 210 or off-die memory 275 or 280) and assemble a response packet with the source address containing confirmation that the data was stored to the memory.

[0042] Thus, where possible, the memory controller chiplet 205 may receive read and write requests via the chiplet network 285 and process the requests using the cache controller 215 interfaced with the cache 210. If the cache controller 215 cannot handle the request, the off-die memory controller 220 handles the request by communicating with the off-die memory 275 or 280, the atomic and merge unit 250, or both. As described above, one or more levels of cache may also be implemented in the off-die memory 275 or 280; and in some such instances may be directly accessed by the cache controller 215. Data read by the off-die memory controller 220 may be cached by the cache controller 215 in the cache 210 for subsequent use.

[0043] Atomic and merge unit 250 is coupled to receive (as input) the output of off-die memory controller 220 and provides the output to cache 210, network communication interface 225, or directly to chiplet network 285. Memory hazard unit 260, write merge unit 255, and built-in (e.g., predetermined) atomic unit 265 may each be implemented as a state machine with other combinational logic circuitry (e.g., adders, shifters, comparators, AND gates, OR gates, XOR gates, or any suitable combination thereof) or other logic circuitry. These components may also include one or more registers or buffers to store operands or other data. PAU 270 may be implemented as one or more processor cores or control circuitry, as well as various state machines with other combinational logic circuitry or other logic circuitry, and may also include one or more registers, buffers, or memories to store addresses, executable instructions, operands, and other data, or may be implemented as a processor.

[0044] The write-merge unit 255 receives the read data and the request data and merges the request data and the read data to create a single unit with the read data and a source address to be used in a response or return packet. The write-merge unit 255 provides the merged data to the write port of the cache 210 (or equivalently, to the cache controller 215 to be written to the cache 210). Optionally, the write-merge unit 255 provides the merged data to the network communication interface 225 to encode and prepare a response or return packet for transmission on the chiplet network 285.

[0045] When the request data is for a built-in atomic operator, the built-in atomic unit 265 receives the request and reads the data from the write-merging unit 255 or directly from the off-die memory controller 220. The atomic operator is executed, and the resulting data is written to the cache 210 using the write-merging unit 255, or provided to the network communication interface 225 to encode and prepare a response or return data packet for transmission over the chiplet network 285.

[0046] The built-in atomic unit 265 handles predefined atomic operators, such as extract and increment or compare and exchange. In an example, these operations perform simple read-modify-write operations on a single memory location of 32 bytes or less in size. Atomic memory operations are initiated from a request packet transmitted via the chiplet network 285. The request packet has a physical address, an atomic operator type, an operand size, and optionally has up to 32 bytes of data. The atomic operator performs a read-modify-write on the cache memory line of the cache 210, thereby filling the cache memory when necessary. The atomic operator response can be a simple completion response, or a response with up to 32 bytes of data. Example atomic memory operators include extract and, extract and or, extract and xor, extract and add, extract and subtract, extract and increment, extract and decrement, extract and minimum, extract and maximum, extract and exchange, and compare and exchange. In various example embodiments, 32-bit and 64-bit operations and operations on 16 or 32 bytes of data are supported. The method disclosed herein is also compatible with hardware that supports larger or smaller operations and more or less data.

[0047] Built-in atomic operators may also involve requests for "standard" atomic operators on the requested data, such as relatively simple single-cycle integer atomics, such as extract and increment or compare and exchange, whose throughput will be the same as a regular memory read or write operation that does not involve atomic operators. For these operations, the cache controller 215 can typically reserve a cache line in the cache 210 by setting a hazard bit (in hardware) so that the cache line cannot be read by another process while it is in transition. The data is obtained from the off-die memory 275 or the cache 210 and provided to the built-in atomic unit 265 to perform the requested atomic operator. After the atomic operator, the built-in atomic unit 265 provides the resulting data to the write merge unit 255, which also writes the resulting data to the cache 210, in addition to providing the resulting data to the packet encoder 240 to encode the output data packet for transmission on the chiplet network 285. After writing the resulting data to the cache 210, the memory hazard unit 260 will clear any corresponding hazard bits that were set.

[0048] The PAU 270 implements high performance (high throughput and low latency) of programmable atomic operators (also referred to as "custom atomic transactions" or "custom atomic operators") that is comparable to the performance of built-in atomic operators. Instead of performing multiple memory accesses, in response to an atomic operator request specifying a programmable atomic operator and a memory address, the circuitry in the memory controller chiplet 205 transmits the atomic operator request to the PAU 270 and sets the hazard bit of the memory address corresponding to the memory row used in the atomic operator stored in the memory hazard register to ensure that no other operations (read, write, or atomic) are performed on the memory row, and then clears the hazard bit after the atomic operator is completed. The additional, direct data path provided to the PAU 270 executing the programmable atomic operator allows additional write operations without being subject to any limitations imposed by the bandwidth of the communication network and without increasing any congestion of the communication network.

[0049] The PAU 270 includes a multithreaded processor having one or more processor cores, such as a multithreaded processor based on the RISC-V ISA, and further having an extended instruction set for executing programmable atomic operators. When provided with an extended instruction set for executing programmable atomic operators, the PAU 270 may be embodied as one or more hybrid threaded processors. In some example embodiments, the PAU 270 provides barrel round-robin instantaneous thread switching to maintain a higher instruction rate per clock.

[0050] Programmable atomic operators may be performed by the PAU 270, which involve requests for programmable atomic operators on requested data. A user may prepare programming code to provide such programmable atomic operators. For example, a programmable atomic operator may be a relatively simple multi-cycle operation, such as a floating point addition, or may be a relatively complex multi-instruction operation, such as a Bloom filter insert. The programmable atomic operator may be the same as or different from the predetermined atomic operator, as long as they are defined by the user rather than the system vendor. For these operations, the cache controller 215 may reserve a cache line in the cache 210 by setting a danger bit (in hardware) so that the cache line cannot be read by another process while it is being converted. Data is obtained from the cache 210 or the off-die memory 275 or 280, and the data is provided to the PAU 270 to perform the requested programmable atomic operator. After the atomic operator, the PAU 270 provides the resulting data to the network communication interface 225 to directly encode an output data packet with the resulting data for transmission on the chiplet network 285. Additionally, PAU 270 provides the resulting data to cache controller 215, which also writes the resulting data to cache 210. After writing the resulting data to cache 210, cache control circuit 215 will clear any corresponding hazard bits that were set.

[0051] In the selected example, the approach taken for programmable atomic operators is to provide a plurality of generic custom atomic request types that can be sent from an originating source such as a processor or other system component to the memory controller chiplet 205 via the chiplet network 285. The cache controller 215 or off-die memory controller 220 recognizes the request as a custom atomic and forwards the request to the PAU 270. In a representative embodiment, the PAU 270: (1) is a programmable processing element capable of efficiently executing user-defined atomic operators, (2) can perform loads and stores on memory, arithmetic and logical operations, and control flow decisions; and (3) utilizes the RISC-V ISA with a new set of specialized instructions to facilitate interaction with such controllers 215, 220 to perform user-defined operations in an atomic manner. In a desirable example, the RISC-V ISA contains a complete instruction set supporting high-level language operators and data types. The PAU 270 can utilize the RISC-V ISA, but will typically support a more limited instruction set and a limited register file size to reduce the die size of the unit when included within the memory controller chiplet 205.

[0052] As mentioned above, the memory hazard clearing unit 260 will clear the set hazard bit of the reserved cache line before writing the read data to the cache 210. Therefore, when the write-merging unit 255 receives the request and the read data, the memory hazard clearing unit 260 may transmit a reset or clear signal to the cache 210 to reset the set memory hazard bit of the reserved cache line. And, resetting this hazard bit will also release the pending read or write request involving the specified (or reserved) cache line, thereby providing the pending read or write request to the inbound request multiplexer for selection and processing.

[0053] Figure 3 1 (eg, in the memory controller 140) and Figure 2 As illustrated, the PAU 300 includes a processor 305, a local memory 310 (eg, SRAM), and a controller 315 for the local memory 310.

[0054] In an example, processor 305 is pipelined so that multiple stages of different instructions are executed together in each clock cycle. Processor 305 is also a barrel multithreaded processor, having a circuit system that switches between different register files (e.g., register groups containing current processing states) after each clock cycle of processor 305. This enables efficient context switching between currently executing threads. In an example, processor 305 supports eight threads, resulting in eight register files. In an example, some or all of the register files are not integrated into processor 305, but reside in local memory 310 (registers 320). This reduces circuit complexity in processor 305 by eliminating traditional flip-flops for these registers 320.

[0055] The local memory 310 may also accommodate a cache 330 and instructions 325 for atomic operators. The atomic instructions 325 include instruction sets for atomic operators that support various application programs to load. When an atomic operator is requested, for example, by an application chiplet 125, the instruction set corresponding to the atomic operator is executed by the processor 305. In an example, the atomic instructions 325 are partitioned to establish an instruction set. In this example, a specific programmable atomic operator requested by a requesting process can identify the programmable atomic operator by a partition number. The partition number can be established when a programmable atomic operator is registered (e.g., loaded onto it) using the PAU 300. Additional metadata for the programmable atomic instruction 325 may also be stored in the local memory 310, such as a partition table.

[0056] The atomic operator manipulates the cache 330, which is typically synchronized (e.g., flushed) when the thread of the atomic operator completes. Thus, latency is reduced for most memory operations during execution of the programmable atomic operator thread, except for the initial load from external memory such as off-die memory 275 or 280.

[0057] The processor 305 is configured with a variable length pipeline to address inefficiencies caused by situations when the processor 305 is lightly loaded (e.g., when less than all available threads are used). To achieve this, the processor 305 is configured to enable instruction completion at one stage in the pipeline before the end of the pipeline. Thus, assuming the pipeline length is eight stages, but an instruction can be completed in two stages (e.g., a register move instruction) or in six stages (e.g., a double precision multiplication), then the instruction can be completed at the second stage and the sixth stage, respectively. Completion in this context indicates that the instruction is ready to be written back to the register. As described above, and below with respect to Figure 4 In the discussion of , when multiple instructions attempt to complete at the same time (e.g., in the same clock cycle), for example, a variable length pipeline can cause complexity. In order to address this complexity, the processor 305 is configured to determine the completion time of the instruction before inserting it into the pipeline. The determination is a search for a specific instruction, or a search for the type of instruction. When the instruction will be completed, the search therefore provides several clock cycles or a processor level. This is the completion time associated with the current clock cycle of the processor 305. Therefore, if the instruction takes five clock cycles to complete, the completion time is five clock cycles from the current clock cycle of the processor. However, other timing elements other than the clock cycle can be used, as described below, and the point of completion time will determine the register write-back conflict with other instructions. Therefore, any metric indicating these metrics can be used.

[0058] In an example, to determine the completion time of an instruction, the processor 305 is configured to determine that the completion time is less than all possible pipeline stages in the pipeline. This condition is similar to the following description of Figure 4 The fixed completion time instructions discussed are consistent. In general, conflict avoidance delay techniques are applicable to fixed completion time instructions but not to variable completion time instructions.

[0059] The processor 305 is configured to detect a conflict between the instruction and a different instruction based on the completion time. Here, the different instruction is in the pipeline and the conflict occurs when the completion time is equal to the second completion time of the different instruction. Therefore, the detection confirms that when a bottleneck of completing instructions, such as a single cycle of register writeback, both the current instruction and the different instruction will reach the bottleneck at the same time.

[0060] To track conflicts, the processor 305 may include a scoreboard (e.g., a register write-back scoreboard). A scoreboard is a structure in which instruction completions can be marked. Thus, for example, when clock cycles are used to determine completion times, the scoreboard has one field for a given future clock cycle, and when an instruction (e.g., a different instruction) in the pipeline is expected to complete after that cycle, the field is marked (e.g., with a logical one). Other structures may be used to indicate that a time will be used, such as a shift structure (e.g., a register) encoded so that each bit represents a number of cycles in the future, the structure shifting down by one at each clock cycle.

[0061] The processor 305 is configured to detect conflicts by finding the clock cycle in which the completion time falls in the scoreboard to obtain a result. This result is then checked by the processor 305 to detect that a different instruction will perform a register writeback at that clock cycle. Therefore, there is a conflict between the instruction and the different instruction.

[0062] The processor 305 is configured to calculate the difference between the completion time and the non-conflicting completion time. In an example, when there is no conflict (e.g., non-conflicting completion time), the processor 305 uses the scoreboard to look forward to future cycles. This difference is the completion delay, which, if enforced, will ensure that the instruction can be written back to the register. If there is no conflict, the difference will be zero. In an example, the processor 305 is configured to write an indication that the instruction will be completed at the second clock cycle in the scoreboard as part of inserting the instruction into the pipeline. Here, the second clock cycle corresponds to the non-conflicting completion time. Therefore, the processor 305 updates the scoreboard with the completion time plus the difference to achieve conflict detection of future instructions.

[0063] The processor 305 is configured to delay the completion of the instruction by the difference. Thus, if an instruction can be completed in the second stage of the pipeline, but conflicts with a different instruction, and a difference of one is given to resolve the conflict, the processor 305 will perform a register writeback of the instruction in the clock cycle after the second stage in the pipeline is completed.

[0064] In an example, to support delays, processor 305 may include a write delay structure (e.g., Figure 4). Here, the processor 305 is configured to detect that an instruction is ready to perform a register writeback at a stage in the pipeline. The processor 305 is then configured to perform a read in the write delay data structure for the record corresponding to the stage in the pipeline. If it is determined that the value of the record is not zero, the instruction is prevented from performing a register writeback. Here, when the record is implemented as a shift register, the value in the register may be decremented at each clock cycle. Therefore, if the second-level instruction is ready to write back with a one-cycle delay, the value in the record is one rather than zero, and therefore the writeback of the instruction will be prevented and another instruction will perform the writeback. However, after the next clock cycle, the value in the second-level record will be decremented to zero, and the instruction will be able to perform the writeback. In an example, the processor 305 is configured to write the difference as a value into the record as part of inserting the instruction into the pipeline.

[0065] Since thread instructions may complete at different times (e.g., clock cycles, pipeline stages, etc.), a flexible technique for rescheduling them may include a buffer of thread IDs currently in the pipeline (e.g., a pipelined thread ID buffer). The processor 305 may be configured to place the thread ID of the instruction into the pipelined thread ID buffer as part of inserting the instruction into the pipeline. Then, when the instruction completes, the processor 305 is configured to move the thread ID from the pipelined thread ID buffer to the thread ready-to-run queue. Here, each thread ID may be extracted in order to schedule the next instruction.

[0066] Figure 4 The process flow through the processor component for variable pipeline length in a barrel multithreaded processor according to an embodiment is described. As described, the thread ID is obtained from the ready-to-run queue. When the next instruction is to be processed, the thread ID is obtained from the thread ready-to-run queue 405, and the state of the thread is obtained (thread state component) 410. The next instruction of the thread is cached (instruction cache component 415). Next, the instruction is decoded (e.g., cracked) into component parts, such as operands, instruction type, etc. at the instruction cracking component 420.

[0067] The instruction write back slot component 425 (e.g., instruction write back circuitry) examines the instruction and determines at which stage in the pipeline 150 the instruction will complete. In this context, instruction completion means the point when the instruction will attempt to write back to the register file 435. For example, a move instruction (e.g., moving data from one register to another) may be very fast and complete at the second stage of the pipeline 450, or complete within two clock cycles of entering the pipeline. In contrast, a double precision addition instruction may complete at the fourth stage of the pipeline 450 or take four clock cycles. These types of instructions have a known or fixed completion within one stage of the pipeline 450, and are therefore referred to herein as fixed completion time instructions. Other instructions (e.g., requests to off-die memory or to components external to the processor (e.g., coprocessors, cryptographic components, or other IP blocks)) may have completion times that exceed pipeline stages, which may also be variable, and are therefore referred to as variable completion time instructions.

[0068] If the instruction write-back slot 425 determines that the instruction is a variable completion time instruction, a form of thread self-scheduling can be used. Here, the processor will hand over the timing of thread rescheduling to an external or long-running component to a certain extent. To achieve this, the thread ID travels with the instruction. Therefore, for example, when a memory request instruction enters the pipeline 450 to process a memory request, the thread ID of the instruction accompanies the memory request. At this time, the thread ID is no longer in the thread ready to run queue 405, nor in any other described structure. Therefore, the thread will not be rescheduled. However, when the memory request is completed, the response from the memory is received by the processor and stored in the buffer 465. A separate buffer 470 can be used for another IP block (e.g., a coprocessor) response, and the buffer 465 can be used for all variable completion time instruction responses. The multiplexer 460 determines when the thread corresponding to the response in the buffer 465 or 470 will be put back into the thread ready to run queue for rescheduling.

[0069] If the instruction is a fixed completion time instruction, the instruction write-back slot component 425 checks the register write-back scoreboard 430 to determine whether any other register write-back can be attempted at the same clock cycle as the current instruction. For example, if two clock cycles ago, the instruction could be written back within four clock cycles, and the current instruction could be written back within two clock cycles, then the two instructions would be able to be written back within the same clock cycle. This potential conflict is tracked in the register write-back scoreboard 430. The register write-back scoreboard 430 tracks which clock cycles do not have potential write-backs. Therefore, when a 4-cycle instruction is processed by the instruction write-back slot component 425, the fourth clock cycle is marked as indicating a write-back of a 4-cycle component. Then, two cycles later, when processing a 2-cycle instruction, the clock cycle when the 2-cycle instruction may be completed is marked by the 4-cycle instruction, indicating a register write-back conflict.

[0070] When the instruction write back slot component 425 detects a register write back conflict, the instruction write back slot component 425 resolves the conflict by calculating the delay of the conflicting instruction based on the non-conflicting cycles from the register write back scoreboard 430. Therefore, if the cycle after the conflicting cycle is idle, a 1-cycle write back delay can be provided for the 2-cycle instruction. If there is no conflict, a 0-cycle write back delay is provided for the instruction.

[0071] Once the instruction write back slot component 425 determines the register write back delay, the instruction write back slot component 425 writes the register write back delay to the write back delay component 445. An example implementation of the write back delay component 445 may be a set of shift registers, one register for each stage in the pipeline 450, or a subset of the stages in the pipeline 450 that may prompt a register write back. As illustrated, the arrows leading from the pipeline 450 and the write back delay component correspond such that the topmost arrow of each arrow corresponds to the write back of the second stage of the pipeline 450, the second topmost arrow corresponds to the fourth stage, and the last arrow corresponds to the sixth stage.

[0072] After each clock cycle, the shift register of the write-back delay component 445 decrements the value stored therein. Thus, if a 2-cycle instruction has a three cycle latency, the value three is stored in the shift register corresponding to the second stage of the pipeline 450. After the first cycle, the value in the register will be two, then one after another cycle, and finally zero after the third cycle.

[0073] When an instruction is ready to be written back from pipeline 450, the stage at which the writeback specifies which register in writeback delay component 445 is located is queried to determine whether the writeback will occur. For example, when the fourth stage of pipeline 450 is completed, a 4-cycle instruction has zeros in writeback delay component 445 and can therefore be written back to register file 435 immediately. However, the register in writeback delay component 445 corresponding to a 2-cycle instruction does not have zeros and therefore no writeback will occur for this instruction. Specifically, the thread of 2-cycle instructions will remain in the second stage of pipeline 450. In the next cycle, the writeback delay component 445 register for the second stage will be decremented to zero, and writeback to register file 435 for the 2-cycle instruction can proceed.

[0074] Instructions with later completion times (e.g., later pipeline stages) have priority. Thus, in a given clock cycle, if instructions at the sixth and fourth stages are ready to be written back to register file 435, the sixth stage instructions will perform the writeback. This ensures that the maximum writeback latency does not cause the writeback to exceed the pipeline length, which is a typical latency imposed on other barrel multithreaded processors. When the latency of an instruction is shorter than the pipeline length, fewer clock cycles are wasted in a lightly loaded processor because the shorter cycle instructions can be completed in fewer cycles than it takes for each stage in pipeline 450 to complete.

[0075] Once the write back to register file 435 is completed, the thread can be rescheduled. This is achieved by pipelined thread ID component 440. Pipelined thread ID component 440 contains the thread ID of the instruction moved through pipeline 450. When an instruction is able to perform a write back, the thread ID of the instruction is removed from pipelined thread ID component 440 and delivered to multiplexer 460 for reinsertion into thread ready to run queue 405. In an example, the multiplexer selects an available thread ID from pipelined thread ID component 440 before any other source (e.g., memory response). Therefore, buffer 465 or 470 maintains the thread ID from the variable completion time instruction until there is no input from pipelined thread ID component 440.

[0076] Figure 5 1 is a flow chart of an example of a method 500 for variable pipeline length in a barrel multithreaded processor according to an embodiment. The operations of the method 500 are performed by computer hardware (eg, processing circuitry).

[0077] In an example, the method is performed by a processor (e.g., processor 305) in a PAU (e.g., PAU 300 or PAU 270) in a memory controller (e.g., memory controller 140 or memory controller 205). In an example, the memory controller is a chiplet (e.g., memory controller 140). In an example, the memory controller chiplet is integrated into a chiplet system (e.g., chiplet system 110).

[0078] At operation 505, the completion time of the instruction is determined before being inserted into the pipeline of the barrel multithreaded processor. In an example, the completion time is the number of clock cycles. In an example, determining the completion time of the instruction includes determining that the completion time is less than all possible pipeline stages in the pipeline.

[0079] At operation 510, a conflict between the instruction and a different instruction is detected based on the completion time. Here, the different instruction is in the pipeline and the conflict occurs when the completion time is equal to a second completion time of the different instruction.

[0080] In an example, detecting a conflict includes looking up the clock cycle in which the completion time falls in the register writeback scoreboard to obtain a result. Next, checking the result to detect that the result indicates that a different instruction will perform a register writeback at a clock cycle. In an example, the operation of method 500 is expanded to include writing an indication that the instruction will complete at a second clock cycle in the register writeback scoreboard as part of inserting the instruction into the pipeline. Here, the second clock cycle corresponds to a non-conflicting completion time.

[0081] At operation 515, a difference between the completion time and the unconflicted completion time is calculated. In an example, when the completion time is measured in clock cycles, the difference is a second number of clock cycles. In an example, the maximum delay (eg, the completion time plus the difference) is eight clock cycles.

[0082] At operation 520, completion of the instruction is delayed by the difference. In an example, delaying completion of the instruction by the difference includes detecting that the instruction is ready to perform a register writeback at a stage in the pipeline, and performing a read of a record corresponding to the stage in the pipeline in a write delay data structure. If it is determined that the value of the record is not zero, the instruction is prevented from performing the register writeback. In an example, the operation of method 500 can be expanded to include writing the difference as a value into the record as part of inserting the instruction into the pipeline. In an example, the operation of method 500 can be expanded to include decrementing the value with each clock cycle.

[0083] In an example, the operation of method 500 can be extended to include moving the thread ID of the instruction from the pipelined thread ID buffer to the thread ready-to-run queue in response to the completion of the instruction. In an example, the thread ID is inserted into the pipelined thread ID buffer as part of inserting the instruction into the pipeline.

[0084] Figure 6A block diagram illustrating an example machine 600, which can be used, implemented in or by the machine to implement any one or more of the techniques (e.g., methods) discussed herein. As described herein, the example may include logic or multiple components or mechanisms in the machine 600, or may be operated by it. A circuit system (e.g., a processing circuit system) is a collection of circuits implemented in a tangible entity of the machine 600, the entity including hardware (e.g., simple circuits, gates, logic, etc.). The membership of the circuit system may become flexible over time. The circuit system includes components that can perform specified operations individually or in combination when operating. In an example, the hardware of the circuit system may be designed to perform specific operations (e.g., hard-wired) in an unchanged manner. In an example, the hardware of the circuit system may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.), including machine-readable media that are physically modified (e.g., magnetic, electrical, movable placement of a large number of particles that are unchanged, etc.) to encode instructions for specific operations. When the physical components are connected, the basic electrical properties of the hardware composition are changed, for example, from an insulator to a conductor, or vice versa. Instructions enable embedded hardware (e.g., an execution unit or loading mechanism) to create components of a circuit system in hardware through variable connections to perform parts of a specific operation when in operation. Therefore, in an example, the machine-readable medium element is part of the circuit system, or is communicatively coupled to other components of the circuit system when the device is in operation. In an example, any of the physical components can be used in more than one component in more than one circuit system. For example, under operation, an execution unit can be used in a first circuit of a first circuit system at one point in time and reused by a second circuit in the first circuit system, or reused by a third circuit in the second circuit system at a different time. The following are additional examples of these components of the machine 600.

[0085] In alternative embodiments, the machine 600 may be operated as a standalone device, or may be connected (e.g., networked) to other machines. In a networked deployment, the machine 600 may operate in the capacity of a server machine, a client machine, or both in a server-client network environment. In an example, the machine 600 may act as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. The machine 600 may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a network appliance, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) instructions specifying actions to be taken by the machine. In addition, although only a single machine is described, the term "machine" should also be deemed to include any machine collection that individually or collectively executes an instruction set (or multiple sets) to perform any one or more of the methods discussed herein (e.g., cloud computing, software as a service (SaaS), other computer cluster configurations).

[0086] The machine (e.g., computer system) 600 may include a hardware processor 602 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof), a main memory 604, a static memory (e.g., a memory or storage device for firmware, microcode, basic input output (BIOS), a unified extensible firmware interface (UEFI), etc.) 606, and a mass storage device 608 (e.g., a hard drive, a tape drive, a flash storage device, or other block device), some or all of which may communicate with each other via an interconnect (e.g., a bus) 630. The machine 600 may further include a display unit 610, an alphanumeric input device 612 (e.g., a keyboard), and a user interface (UI) navigation device 614 (e.g., a mouse). In an example, the display unit 610, the input device 612, and the UI navigation device 614 may be a touch screen display. The machine 600 may further include a storage device (e.g., a drive unit) 608, a signal generating device 618 (e.g., a speaker), a network interface device 620, and one or more sensors 616, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or other sensors. The machine 600 may include an output controller 628, such as a serial (e.g., universal serial bus (USB), parallel or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate with or control one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0087] The registers of the processor 602, main memory 604, static memory 606, or mass storage 608 may be or include a machine-readable medium 622 on which is stored one or more sets of data structures or instructions 624 (e.g., software) that embody or are utilized by any one or more of the techniques or functions described herein. The instructions 624 may also reside, in whole or in part, within any of the registers of the processor 602, main memory 604, static memory 606, or mass storage 608 during execution thereof by the machine 600. In an example, one or any combination of the hardware processor 602, main memory 604, static memory 606, or mass storage 608 may constitute the machine-readable medium 622. Although the machine-readable medium 622 is illustrated as a single medium, the term "machine-readable medium" may include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) configured to store one or more instructions 624.

[0088] The term "machine-readable medium" may include any medium capable of storing, encoding, or carrying instructions for execution by the machine 600 and causing the machine 600 to perform any one or more of the techniques of the present disclosure, or any medium capable of storing, encoding, or carrying data structures used by or associated with such instructions. Non-limiting machine-readable medium examples may include solid-state memory, optical media, magnetic media, and signals (e.g., radio frequency signals, other photon-based signals, sound signals, etc.). In an example, a non-transitory machine-readable medium includes a machine-readable medium having a plurality of particles, the particles having a constant (e.g., stationary) mass, and thus being composed of matter. Therefore, a non-transitory machine-readable medium is a machine-readable medium that does not contain a transient propagating signal. Specific examples of non-transitory machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable magnetic disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0089] In an example, the information stored or otherwise provided on the machine-readable medium 622 may represent instructions 624, such as the instructions 624 themselves or a format from which the instructions 624 may be derived. Such a format from which the instructions 624 may be derived may include source code, encoded instructions (e.g., in compressed or encrypted form), packaged instructions (e.g., split into multiple packages), etc. The information representing the instructions 624 in the machine-readable medium 622 may be processed by the processing circuitry into instructions to implement any of the operations discussed herein. For example, deriving the instructions 624 from the information (e.g., processed by the processing circuitry) may include: compiling (e.g., from source code, object code, etc.), interpreting, loading, organizing (e.g., dynamically or statically linking), encoding, decoding, encrypting, decrypting, packaging, unpacking, or otherwise manipulating the information into instructions 624.

[0090] In an example, the derivation of instructions 624 may include (e.g., by processing circuitry) the assembly, compilation, or interpretation of information to create instructions 624 from some intermediate or pre-processed format provided by machine-readable medium 622. When the information is provided in multiple parts, the information may be combined, unpacked, and modified to create instructions 624. For example, the information may be in multiple compressed source code packages (or object code, or binary executable code, etc.) on one or more remote servers. The source code packages may be encrypted when transmitted over the network, and decrypted, uncompressed, assembled (e.g., linked) as necessary, and compiled or interpreted at the local machine (e.g., into a stand-alone executable library, etc.), and executed by the local machine.

[0091] The instructions 624 may further be transmitted or received over a communication network 626 using a transmission medium via the network interface device 620 using any of a number of transmission protocols (e.g., frame relay, Internet Protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.). Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), a mobile telephone network (e.g., a cellular network), a plain old telephone (POTS) network, and a wireless data network (e.g., a wireless network known as a wireless network). The Institute of Electrical and Electronics Engineers (IEEE) 802.11 series of standards, known as ), IEEE 802.16 family of standards, IEEE 802.15.4 family of standards, peer-to-peer (P2P) networks, etc. In an example, the network interface device 620 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas to connect to the communication network 626. In an example, the network interface device 620 may include multiple antennas to communicate wirelessly using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technology. The term "transmission medium" should be taken to include any intangible medium capable of storing, encoding, or carrying instructions for execution by the machine 600, and includes digital or analog communication signals or other intangible media to facilitate the communication of such software. Transmission media are machine-readable media. To better illustrate the methods and apparatus described herein, a set of non-limiting example embodiments are set forth below as numbered examples.

[0092] Example 1 is a processor comprising: a pipeline; an instruction write-back circuit system configured to: determine a completion time of an instruction before inserting it into the pipeline; detect a conflict between the instruction and a different instruction based on the completion time, wherein the conflict is detected when the completion time is equal to a second completion time of the different instruction in the pipeline; and calculate a difference between the completion time and a non-conflicting completion time; and a write delay circuit system configured to delay completion of the instruction by the difference.

[0093] In example 2, according to the subject matter of example 1, wherein the completion time is a number of clock cycles.

[0094] In example 3, the subject matter of example 2, wherein the difference is a second number of clock cycles.

[0095] In example 4, the subject matter of example 3, wherein to determine the completion time of the instruction, the instruction write-back circuitry is configured to determine that the completion time is less than all possible pipeline stages in the pipeline.

[0096] In example 5, the subject matter of example 4, wherein the maximum delay is eight clock cycles.

[0097] In Example 6, according to the subject matter described in any one of Examples 1 to 5, in order to detect conflicts, the instruction write-back circuit system is configured to: search the clock cycle in which the completion time falls in the register write-back scoreboard to obtain a result; and detect that the result indicates that a different instruction will perform a register write-back at the clock cycle.

[0098] In Example 7, according to the subject matter of Example 6, the instruction write-back circuit system is configured to: write an indication in the register write-back scoreboard that the instruction will be completed at a second clock cycle as part of inserting the instruction into the pipeline, and the second clock cycle corresponds to the non-conflicting completion time.

[0099] In Example 8, according to the subject matter of any one of Examples 1 to 7, wherein, to delay completion of the instruction by the difference, the pipeline is configured to: detect that the instruction is ready to perform a register write back at a stage in the pipeline; perform a read of a record corresponding to the stage in the pipeline in a write delay data structure of the write delay circuit system; determine that the value of the record is not zero; and prevent the instruction from performing a register write back.

[0100] In example 9, according to the subject matter of example 8, wherein the instruction write-back circuitry is configured to write the difference as a value into the record as part of inserting the instruction into the pipeline.

[0101] In Example 10, the subject matter of any of Examples 8-9, wherein the write delay circuitry is configured to decrement the value with each clock cycle.

[0102] In Example 11, the subject matter of any one of Examples 1 to 10, wherein the pipeline is configured to: move a thread identifier (ID) of the instruction from a pipelined thread ID buffer to a thread ready-to-run queue in response to completion of the instruction, wherein the thread ID is inserted into the pipelined thread ID buffer as part of inserting the instruction into the pipeline.

[0103] In example 12, the subject matter of any of examples 1-11, wherein the processor is included in a programmable atomic unit in the memory controller.

[0104] In Example 13, the subject matter of Example 12, wherein the memory controller is a chiplet in a chiplet system.

[0105] Example 14 is a method comprising: determining a completion time of an instruction before inserting it into a pipeline of a processor; detecting a conflict between the instruction and a different instruction based on the completion time, wherein the conflict is detected when the completion time is equal to a second completion time of the different instruction; calculating a difference between the completion time and a non-conflicting completion time; and delaying completion of the instruction by the difference.

[0106] In example 15, the subject matter of example 14, wherein the completion time is a number of clock cycles.

[0107] In Example 16, according to the subject matter of Example 15, wherein the difference is a second number of clock cycles.

[0108] In example 17, the subject matter of example 16, wherein determining a completion time of the instruction comprises determining that the completion time is less than all possible pipeline stages in the pipeline.

[0109] In Example 18, the subject matter of Example 17, wherein the maximum delay is eight clock cycles.

[0110] In Example 19, according to the subject matter of any of Examples 14 to 18, detecting a conflict comprises: looking up a clock cycle in which the completion time falls in a register writeback scoreboard to obtain a result; and detecting that the result indicates that a different instruction will perform a register writeback at the clock cycle.

[0111] In Example 20, the subject matter of Example 19 includes: writing in the register writeback scoreboard an indication that the instruction will complete at a second clock cycle as part of inserting the instruction into the pipeline, the second clock cycle corresponding to the non-conflicting completion time.

[0112] In Example 21, the subject matter of any one of Examples 14 to 20, wherein delaying completion of the instruction by the difference comprises: detecting that the instruction is ready to perform a register writeback at a stage in the pipeline; performing a read of a record corresponding to the stage in the pipeline in a write delay data structure; determining that the value of the record is not zero; and preventing the instruction from performing the register writeback.

[0113] In Example 22, the subject matter of Example 21 includes writing the difference as a value into a record as part of inserting the instruction into the pipeline.

[0114] In Example 23, the subject matter of any of Examples 21-22 includes: decrementing the value with each clock cycle.

[0115] In Example 24, the subject matter of any one of Examples 14 to 23 includes: moving a thread identifier (ID) of the instruction from a pipelined thread ID buffer to a thread ready-to-run queue in response to completion of the instruction, wherein the thread ID is inserted into the pipelined thread ID buffer as part of inserting the instruction into the pipeline.

[0116] In Example 25, the subject matter of any of Examples 14 to 24, wherein the processor is included in a programmable atomic unit in the memory controller.

[0117] In Example 26, the subject matter of Example 25, wherein the memory controller is a chiplet in a chiplet system.

[0118] Example 27 is a machine-readable medium comprising instructions that, when executed by a circuit system of a processor, cause the processor to perform operations including: determining a completion time of an instruction before inserting it into a pipeline of the processor; detecting a conflict between the instruction and a different instruction based on the completion time, wherein the conflict is detected when the completion time is equal to a second completion time of the different instruction; calculating a difference between the completion time and a non-conflicting completion time; and delaying completion of the instruction by the difference.

[0119] In Example 28, the subject matter of Example 27, wherein the completion time is a number of clock cycles.

[0120] In Example 29, the subject matter of Example 28, wherein the difference is a second number of clock cycles.

[0121] In example 30, the subject matter of example 29, wherein determining a completion time of the instruction comprises determining that the completion time is less than all possible pipeline stages in the pipeline.

[0122] In Example 31, the subject matter of Example 30, wherein the maximum delay is eight clock cycles.

[0123] In Example 32, according to the subject matter of any of Examples 27 to 31, detecting a conflict includes: looking up a clock cycle in which a completion time falls in a register writeback scoreboard to obtain a result; and detecting that the result indicates that a different instruction will perform a register writeback at the clock cycle.

[0124] In Example 33, the subject matter of Example 32, wherein the operation includes: writing in the register writeback scoreboard an indication that the instruction will complete at a second clock cycle as part of inserting the instruction into the pipeline, the second clock cycle corresponding to the non-conflicting completion time.

[0125] In Example 34, the subject matter of any one of Examples 27 to 33, wherein delaying completion of the instruction by the difference comprises: detecting that the instruction is ready to perform a register writeback at a stage in the pipeline; performing a read of a record corresponding to the stage in the pipeline in a write delay data structure; determining that the value of the record is not zero; and preventing the instruction from performing the register writeback.

[0126] In Example 35, according to the subject matter of Example 34, wherein the operation includes: writing the difference as a value to a record as part of inserting the instruction into the pipeline.

[0127] In Example 36, the subject matter of any of Examples 34-35, wherein the operation includes: decrementing the value with each clock cycle.

[0128] In Example 37, the subject matter of any one of Examples 27 to 36, wherein the operation includes: moving a thread identifier (ID) of the instruction from a pipelined thread ID buffer to a thread ready-to-run queue in response to completion of the instruction, wherein the thread ID is inserted into the pipelined thread ID buffer as part of inserting the instruction into the pipeline.

[0129] In Example 38, the subject matter of any of Examples 27-37, wherein the processor is included in a programmable atomic unit in the memory controller.

[0130] In Example 39, the subject matter of Example 38, wherein the memory controller is a chiplet in a chiplet system.

[0131] Example 40 is a system comprising: a component for determining a completion time of an instruction before insertion into a pipeline of a processor; a component for detecting a conflict between the instruction and a different instruction based on the completion time, wherein the conflict is detected when the completion time is equal to a second completion time of the different instruction in the pipeline; a component for calculating a difference between the completion time and a non-conflicting completion time; and a component for delaying completion of the instruction by the difference.

[0132] In Example 41, the subject matter of Example 40, wherein the completion time is a number of clock cycles.

[0133] In Example 42, the subject matter of Example 41, wherein the difference is a second number of clock cycles.

[0134] In example 43, according to the subject matter of example 42, wherein the means for determining a completion time of the instruction comprises means for determining that the completion time is less than all possible pipeline stages in the pipeline.

[0135] In Example 44, the subject matter of Example 43, wherein the maximum delay is eight clock cycles.

[0136] In Example 45, according to the subject matter of any one of Examples 40 to 44, the means for detecting a conflict includes: means for finding a clock cycle in which the completion time falls in a register writeback scoreboard to obtain a result; and means for detecting that the result indicates that a different instruction will perform a register writeback at the clock cycle.

[0137] In Example 46, the subject matter of Example 45 includes: means for writing in a register writeback scoreboard an indication that the instruction will complete at a second clock cycle as part of inserting the instruction into the pipeline, the second clock cycle corresponding to a non-conflicting completion time.

[0138] In Example 47, according to the subject matter of any one of Examples 40 to 46, the means for delaying completion of the instruction by the difference includes: means for detecting that the instruction is ready to perform a register writeback at a stage in the pipeline; means for performing a read of a record corresponding to the stage in the pipeline in a write delay data structure; means for determining that the value of the record is not zero; and means for preventing the instruction from performing the register writeback.

[0139] In Example 48, the subject matter of Example 47 includes: means for writing the difference as a value into a record as part of inserting the instruction into the pipeline.

[0140] In Example 49, the subject matter of any of Examples 47-48 comprises: means for decrementing the value with each clock cycle.

[0141] In Example 50, the subject matter of any one of Examples 40 to 49 includes: means for moving a thread identifier (ID) of an instruction from a pipelined thread ID buffer to a thread ready-to-run queue in response to completion of the instruction, the thread ID being inserted into the pipelined thread ID buffer as part of inserting the instruction into the pipeline.

[0142] In Example 51, the subject matter of any of Examples 40 to 50, wherein the processor is included in a programmable atomic unit in the memory controller.

[0143] In Example 52, the subject matter of Example 51, wherein the memory controller is a chiplet in a chiplet system.

[0144] Example 53 is at least one machine-readable medium comprising instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations to implement any of Examples 1-52.

[0145] Example 54 is an apparatus comprising means for implementing any of Examples 1-52.

[0146] Example 55 is a system for implementing any one of Examples 1 to 52.

[0147] Example 56 is a method for implementing any one of Examples 1-52.

[0148] The above detailed description includes reference to the accompanying drawings, which form a part of the detailed description. The drawings show by way of illustration specific embodiments in which the present invention can be practiced. These embodiments are also referred to herein as "examples". Such examples may include elements other than those shown or described. However, the inventors also contemplate examples in which only those elements shown or described are provided. In addition, the inventors also contemplate examples (or one or more aspects thereof) of any combination or arrangement of those elements shown or described with respect to a specific example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0149] In this document, as is common in patent documents, the term "a / an" is used to include one or more than one, which is independent of any other circumstances or uses of "at least one" or "one or more". In this document, the term "or" is used to refer to a non-exclusive or, so that unless otherwise indicated, "A or B" may include "A but not B", "B but not A" and "A and B". In the appended claims, the terms "including" and "in which" are used as the plain English equivalents of the corresponding terms "including" and "wherein". In addition, in the appended claims, the terms "including" and "comprising" are open, that is, systems, devices, objects or processes containing elements other than those listed after such terms in the claims are still considered to be within the scope of the claims. In addition, in the following claims, the terms "first", "second" and "third" etc. are used only as labels and are not intended to impose numerical requirements on their objects.

[0150] The above description is intended to be illustrative and not restrictive. For example, the above examples (or one or more aspects thereof) can be used in combination with each other. For example, a person of ordinary skill in the art can use other embodiments after consulting the above description. It should be understood that the embodiments will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above specific embodiments, various features can be grouped together to simplify the present disclosure. This situation should not be interpreted as intending that the disclosed features that are not claimed are necessary for any claim. In fact, the subject matter of the present invention may be less than all the features of a specific disclosed embodiment. Therefore, the attached claims are hereby incorporated into the specific embodiments, wherein each claim exists independently as a separate embodiment, and it is considered that such embodiments can be combined with each other in various combinations or arrangements. The scope of the present invention should be determined by reference to the attached claims and the full scope of equivalents granted by such claims.

Claims

1. An electronic device, comprising: A pipeline circuit system for implementing a pipeline; An instruction write-back circuit system is configured to: determining a completion time of an instruction prior to insertion into the pipeline; detecting a conflict between the instruction and a different instruction based on the completion time, the different instruction being in the pipeline, the conflict being detected when the completion time is equal to a second completion time of the different instruction; as well as calculating a difference between the completion time and an unconflicted completion time, wherein the difference is less than or equal to a maximum delay defined by a length of the pipeline; and Write delay circuitry is configured to delay completion of the instruction by the difference. The electronic device according to claim 1 , wherein the completion time is the number of clock cycles. The electronic device of claim 2 , wherein the difference is a second number of clock cycles. The electronic device according to claim 1 , wherein the maximum delay is eight clock cycles.

5. The electronic device according to claim 1, wherein: To detect the conflict, the instruction write-back circuit system is configured to: Find the clock cycle where the completion time falls in the register writeback scoreboard to obtain the result; and Detecting the result indicates that the different instruction is to perform a register writeback at the clock cycle.

6. The electronic device according to claim 5, wherein the instruction write-back circuit system is configured to: An indication that the instruction will complete at a second clock cycle is written in the register writeback scoreboard as part of inserting the instruction into the pipeline, the second clock cycle corresponding to the non-conflicting completion time.

7. The electronic device according to claim 1, wherein: To delay completion of the instruction by the difference, the pipeline is configured to: detecting that the instruction is ready to perform a register writeback at a stage in the pipeline; performing a read of a record corresponding to the stage in the pipeline in a write delay data structure of the write delay circuitry; determining that the value of the record is not zero; as well as The instruction is prevented from performing a writeback of the register.

8. The electronic device according to claim 7, wherein the instruction write-back circuit system is configured to: The difference is written as the value to the record as part of inserting the instruction into the pipeline.

9. The electronic device of claim 7, wherein the write delay circuitry is configured to: The value is decremented with each clock cycle.

10. The electronic device according to claim 1, wherein the pipeline is configured as follows: A thread identifier ID of the instruction is moved from a pipelined thread ID buffer into a thread ready-to-run queue in response to completion of the instruction, the thread ID being inserted into the pipelined thread ID buffer as part of inserting the instruction into the pipeline.

11. The electronic device of claim 1, wherein the electronic device is included in a programmable atomic unit in a memory controller.

12. The electronic device of claim 11, wherein the memory controller is a chiplet in a chiplet system.

13. A method performed by an electronic device, the method comprising: determining the completion time of instructions before insertion into the pipeline of the processor; detecting a conflict between the instruction and a different instruction based on the completion time, the different instruction being in the pipeline, the conflict being detected when the completion time is equal to a second completion time of the different instruction; calculating a difference between the completion time and an unconflicted completion time, wherein the difference is less than or equal to a maximum delay defined by a length of the pipeline; and Completion of the instruction is delayed by the difference. The method of claim 13 , wherein the completion time is a number of clock cycles. The method of claim 14 , wherein the difference is a second number of clock cycles. The method of claim 13 , wherein the maximum delay is eight clock cycles.

17. The method of claim 13, wherein detecting the conflict comprises: Find the clock cycle where the completion time falls in the register writeback scoreboard to obtain the result; and Detecting the result indicates that the different instruction is to perform a register writeback at the clock cycle.

18. The method according to claim 17, comprising: An indication that the instruction will complete at a second clock cycle is written in the register writeback scoreboard as part of inserting the instruction into the pipeline, the second clock cycle corresponding to the non-conflicting completion time.

19. The method of claim 13, wherein delaying completion of the instruction by the difference comprises: detecting that the instruction is ready to perform a register writeback at a stage in the pipeline; performing a read in a write latency data structure for a record corresponding to the stage in the pipeline; determining that the value of the record is not zero; as well as The instruction is prevented from performing a writeback of the register.

20. The method according to claim 19, comprising: The difference is written as the value to the record as part of inserting the instruction into the pipeline.

21. The method according to claim 19, comprising: The value is decremented with each clock cycle.

22. The method of claim 13, comprising: A thread identifier ID of the instruction is moved from a pipelined thread ID buffer into a thread ready-to-run queue in response to completion of the instruction, the thread ID being inserted into the pipelined thread ID buffer as part of inserting the instruction into the pipeline.

23. The method of claim 13, wherein the processor is included in a programmable atomic unit in a memory controller.

24. The method of claim 23, wherein the memory controller is a chiplet in a chiplet system.

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