LDPC coding for memory cells with arbitrary levels

Abstract

The present invention is entitled "LDPC Coding for Memory Cells with Arbitrary Ranks." The present disclosure generally relates to applying LDPC coding to memory cells with arbitrary rank. A modulation code is applied to a first portion of user bits. The encoded user data is stored in a first modulation block. Parity bits are then generated for the first portion of user bits. The parity bits are then stored in a second modulation block that is different from the first modulation block. The modulation code is then applied to a second portion of user bits stored in the second modulation block. Parity bits are then generated for the second portion of user bits and stored in a third modulation block. The parity bits are thus embedded in a modulation block separate from the modulation block storing the user data.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 086962, filed on October 2, 2020, which is incorporated herein by reference. Background Art Technical Field

[0003] Embodiments of the present disclosure are generally directed to applying LDPC coding to memory cells having arbitrary levels.

[0004] Description of related art

[0005] Memory devices such as NAND memory cells are multi-state objects that store binary information. To simplify binary arithmetic, the number of levels in a cell is chosen to be an integer power of 2 (e.g., 2, 4, 8, 16, etc.). Efforts have been made to create cells with any number of levels so that non-integer powers of 2 cell levels can be achieved.

[0006] For this non-integer power of 2 scenario, user data can be encoded by converting the user database from 2-ary to L-ary, where L is the number of unit levels. This makes encoding user data easier. However, LDPC parity calculations are binary, not non-integer powers of 2. Therefore, LDPC parity information presents issues with non-integer powers of 2 unit levels.

[0007] Because LDPC parity calculations are binary, there's the problem of how to write binary information into L-level cells without encoding and losing data capacity. LDPC parity checks for non-integer powers of two cell levels require additional storage capacity beyond that required for integer powers of two cell levels. Alternatively, the LDPC parity data could be encoded, which is undesirable.

[0008] Therefore, there is a need in the art for a way to store LDPC parity data for a non-integer power of 2 number of unit levels without encoding the LDPC parity data or using excessive storage capacity. Summary of the Invention

[0009] The present disclosure generally relates to applying LDPC coding to memory cells having arbitrary levels. A modulation code is applied to a first portion of user bits. The encoded user data is stored in a first modulation block. Parity bits are then generated for the first portion of user bits. The parity bits are then stored in a second modulation block that is different from the first modulation block. The modulation code is then applied to a second portion of user bits stored in the second modulation block. Parity bits are then generated for the second portion of user bits and stored in a third modulation block. The parity bits are thus embedded in a modulation block separate from the modulation block storing the user data.

[0010] In one embodiment, a data storage device includes: one or more memory devices; and a controller coupled to the one or more memory devices, wherein the controller is configured to: apply modulation coding to a first group of user data; write the modulated first group of user data to a first modulation block; generate first parity data for the modulated first group of user data; and write the first parity data to a second modulation block.

[0011] In another embodiment, a data storage device includes: one or more memory devices; and a controller coupled to the one or more memory devices, wherein the controller is configured to: generate parity data for a first set of modulated user data; and embed the parity data with a second set of modulated user data different from the first set of modulated user data.

[0012] In another embodiment, a data storage device includes: one or more memory devices; means for storing modulated first user data; and means for storing parity data for the modulated first user data at a location different from the modulated first user data. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Thus, a detailed understanding of the manner in which the above-recited features of the present disclosure are understood, a more particular description of the disclosure, the brief summary above, and the like, may be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical embodiments of the disclosure and are therefore not to be considered limiting of its scope, as the disclosure may admit to other equally effective embodiments.

[0014] Figure 1 is a schematic block diagram illustrating a storage system according to the disclosed embodiments, in which a data storage device can be used as a storage device for a host device.

[0015] Figures 2A to 2L is a schematic diagram of embedding parity in a modulation block according to the disclosed embodiment.

[0016] Figure 3 is a schematic diagram of a triangular LDPC H-matrix according to the disclosed embodiment.

[0017] Figure 4 is a schematic diagram of L-level memory cell encoding according to the disclosed embodiment.

[0018] Figure 5 is a flow chart illustrating a method of applying LDPC encoding to memory cells having arbitrary levels according to the disclosed embodiments.

[0019] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation. DETAILED DESCRIPTION

[0020] Hereinafter, reference is made to embodiments of the present disclosure. However, it should be understood that the present disclosure is not limited to the specifically described embodiments. On the contrary, any combination of the following features and elements (whether or not related to different embodiments) is considered to implement and practice the present disclosure. In addition, although the embodiments of the present disclosure can achieve advantages over other possible solutions and / or advantages over the prior art, whether a specific advantage is achieved by a given embodiment is not a limitation of the present disclosure. Therefore, the following aspects, features, embodiments and advantages are merely illustrative and are not considered to be elements or limitations of the appended claims unless expressly stated in the claims. Similarly, reference to "the present disclosure" should not be interpreted as a summary of any inventive subject matter disclosed herein and should not be considered to be elements or limitations of the appended claims unless expressly stated in the claims.

[0021] The present disclosure generally relates to applying LDPC coding to memory cells having arbitrary levels. A modulation code is applied to a first portion of user bits. The encoded user data is stored in a first modulation block. Parity bits are then generated for the first portion of user bits. The parity bits are then stored in a second modulation block that is different from the first modulation block. The modulation code is then applied to a second portion of user bits stored in the second modulation block. Parity bits are then generated for the second portion of user bits and stored in a third modulation block. The parity bits are thus embedded in a modulation block separate from the modulation block storing the user data.

[0022] Figure 1is a schematic block diagram illustrating a storage system 100 according to the disclosed embodiments, in which a data storage device 106 can be used as a storage device for a host device 104. For example, the host device 104 can utilize non-volatile memory (NVM) 110 included in the data storage device 106 to store and retrieve data. The host device 104 includes a host DRAM 138. In some examples, the storage system 100 can include multiple storage devices, such as the data storage device 106, that can operate as a storage array. For example, the storage system 100 can include multiple data storage devices 106 that are configured as a redundant array of inexpensive / independent disks (RAID) that collectively function as mass storage devices for the host device 104.

[0023] Host device 104 can store data to and / or retrieve data from one or more storage devices, such as data storage device 106. Figure 1 As shown, host device 104 can communicate with data storage device 106 via interface 114. Host device 104 can include any of a variety of devices, including a computer server, a network attached storage (NAS) unit, a desktop computer, a notebook (i.e., laptop) computer, a tablet computer, a set-top box, a telephone handset such as a so-called "smart" phone, a so-called "smart" tablet, a television, a camera, a display device, a digital media player, a video game console, a video streaming device, or other device capable of sending or receiving data from a data storage device.

[0024] The data storage device 106 includes a controller 108, an NVM 110, a power supply 111, a volatile memory 112, an interface 114, and a write buffer 116. In some examples, for clarity, the data storage device 106 may include Figure 1 Additional components not shown in the figure. For example, the data storage device 106 may include a printed circuit board (PCB) to which the components of the data storage device 106 are mechanically attached, and the printed circuit board includes conductive traces that electrically interconnect the components of the data storage device 106, etc. In some examples, the physical size and connector configuration of the data storage device 106 can conform to one or more standard form factors. Some exemplary standard form factors include, but are not limited to, a 3.5" data storage device (e.g., an HDD or SSD), a 2.5" data storage device, a 1.8" data storage device, a peripheral component interconnect (PCI), a PCI extension (PCI-X), a PCI Express (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe Mini Card, MiniPCI, etc.). In some examples, the data storage device 106 can be directly coupled (e.g., directly soldered) to a motherboard of the host device 104.

[0025] The interface 114 of the data storage device 106 may include one or both of a data bus for exchanging data with the host device 104 and a control bus for exchanging commands with the host device 104. The interface 114 may operate according to any suitable protocol. For example, the interface 114 may operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), PCI and PCIe, Non-Volatile Memory Express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD (OCSSD), etc. The electrical connection of the interface 114 (e.g., the data bus, the control bus, or both) is electrically connected to the controller 108, thereby providing an electrical connection between the host device 104 and the controller 108, allowing data to be exchanged between the host device 104 and the controller 108. In some examples, the electrical connection of the interface 114 may also allow the data storage device 106 to receive power from the host device 104. For example, Figure 1 As shown, power supply 111 can receive power from host device 104 via interface 114 .

[0026] NVM 110 may include multiple memory devices. NVM 110 may be configured to store and / or retrieve data. For example, a memory device of NVM 110 may receive data and a message instructing the memory device to store data from controller 108. Similarly, a memory device of NVM 110 may receive a message instructing the memory device to retrieve data from controller 108. In some examples, each memory device in the memory device may be referred to as a die. In some examples, a single physical chip may include multiple dies (i.e., multiple memory cells). In some examples, each memory device may be configured to store a relatively large amount of data (e.g., 128MB, 256MB, 512MB, 1GB, 2GB, 4GB, 8GB, 16GB, 32GB, 64GB, 128GB, 256GB, 512GB, 1TB, etc.).

[0027] In some examples, each memory device of NVM 110 may include any type of non-volatile memory device, such as a flash memory device, a phase change memory (PCM) device, a resistive random access memory (ReRAM) device, a magnetoresistive random access memory (MRAM) device, a ferroelectric random access memory (F-RAM), a holographic memory device, and any other type of non-volatile memory device.

[0028] NVM 110 may include multiple flash memory devices. NVM flash memory devices may include NAND or NOR-based flash memory devices and may store data based on the charge contained in the floating gate of the transistor for each flash memory cell. In an NVM flash memory device, the flash memory device may be divided into multiple dies, wherein each of the multiple dies includes multiple blocks, which may be further divided into multiple pages. Each of the multiple blocks within a particular memory device may include multiple NVM cells. Rows of NVM cells may be electrically connected using word lines to define pages within a plurality of pages. Corresponding cells in each of the multiple pages may be electrically connected to corresponding bit lines. In addition, the NVM flash memory device may be a 2D or 3D device and may be a single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), or quad-level cell (QLC). The controller 108 may write data to and read data from the NVM flash memory device at a page level, and erase data from the NVM flash memory device at a block level.

[0029] Data storage device 106 includes a power supply 111 that can provide power to one or more components of data storage device 106. When operating in standard mode, power supply 111 can use power provided by an external device, such as host device 104, to power one or more components. For example, power supply 111 can use power received from host device 104 via interface 114 to power one or more components. In some examples, power supply 111 can include one or more power storage components configured to provide power to one or more components when operating in shutdown mode, such as when power is no longer received from an external device. In this manner, power supply 111 can serve as an onboard backup power source. Some examples of one or more power storage components include, but are not limited to, capacitors, supercapacitors, batteries, and the like. In some examples, the amount of power that can be stored by one or more power storage components can be a function of the cost and / or size (e.g., area / volume) of the one or more power storage components. In other words, as the amount of power stored by one or more power storage components increases, the cost and / or size of the one or more power storage components also increases.

[0030] The data storage device 106 also includes a volatile memory 112 that can be used by the controller 108 to store information. The volatile memory 112 can include one or more volatile memory devices. Figure 1As shown, the volatile memory 112 can consume power received from the power supply 111. Examples of the volatile memory 112 include, but are not limited to, random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, etc.)).

[0031] The data storage device 106 includes a controller 108 that can manage one or more operations of the data storage device 106. For example, the controller 108 can manage reading data from and / or writing data to the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 can initiate a data storage command to store data in the NVM 110 and monitor the progress of the data storage command. The controller 108 can determine at least one operational characteristic of the storage system 100 and store the at least one operational characteristic in the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 temporarily stores the data associated with the write command in an internal memory or write buffer 116 before sending the data to the NVM 110.

[0032] Figures 2A to 2L FIG is a schematic diagram of embedding parity in a modulation block according to the disclosed embodiment. Figures 2A to 2L In the example of , the term "data" refers to user data, and the term "coded data" refers to modulated data excluding parity data. Modulated data is user data encoded with a modulation code. Data storage devices (such as Figure 1 The data storage device 106 may include a modulation encoder engine and a modulation decoder engine, wherein the modulation encoder engine is configured to encode user data using a modulation code, and the modulation decoder engine is configured to decode the modulated user data so that the user data can be read by a host (such as Figure 1 Host 104) reads.

[0033] In some embodiments, the modulation encoder engine and the modulation decoder engine can be components of the controller. In other embodiments, the modulation encoder engine and the modulation decoder engine can be separate components, where user data passes through the modulation encoder engine when written to the NVM from the controller and passes through the modulation decoder engine when read from the NVM to the controller. In one embodiment, the modulation encoder engine and the modulation decoder engine can be a single unit. In other embodiments, the modulation encoder engine and the modulation decoder engine can be separate units.

[0034] exist Figure 2A In the first set of user data, a controller such as Figure 1 The controller 108 receives the Figure 2B In the embodiment of the present invention, modulation coding is applied to a first set of user data, wherein the first set of user data is a modulated first set of user data. The modulated first set of user data is programmed into a first modulation block in the NVM, such as Figure 1 NVM 110. Figure 2C In the embodiment of the present invention, first parity data for the modulated first set of user data is generated. The first parity data is written to the second modulation block before the second set of user data is stored in the second modulation block. The parity data (such as the first parity data) may include any number of bits corresponding to a set of user data (such as the first set of user data), such as approximately three parity bits, so that the user data can be recovered in the event of a program failure, accumulation of bit errors, etc.

[0035] exist Figure 2D In the embodiment, a second group of user data different from the first group of user data is written into the second modulation block, wherein the second group of user data includes a gap of the first parity data. In addition, the second modulation block includes the second group of user data and the first parity data, wherein the second group of user data is not modulation data, and the first parity data is not encoded. Figure 2E In the embodiment of the present invention, the second set of user data is encoded with the modulation data, such that the second set of user data is a modulated second set of user data. The modulated second set of user data is different from the modulated first set of user data. In addition, the first parity data embedded in the modulated second set of user data may be approximately 30% of the total data of the second modulation block.

[0036] exist Figure 2F In the embodiment of the present invention, second parity data of the modulated second group of user data is generated. Before storing the third group of user data in the third modulation block, the second parity data is written into the third modulation block. Figure 2G In the third modulation block, a third group of user data different from the second group of user data is written, wherein the third group of user data includes a gap of the second parity data. In addition, the third modulation block includes the third group of user data and the second parity data, wherein the third group of user data is not modulation data, and the second parity data is not encoded. Figure 2H In the embodiment of the present invention, the third group of user data is encoded with the modulation data, such that the third group of user data is modulated third group of user data. The modulated third group of user data is different from the modulated second group of user data. In addition, the second parity data embedded in the modulated third group of data may be approximately 30% of the total data of the third modulation block.

[0037] exist Figure 2IIn the embodiment of the present invention, third parity data of the modulated third group of user data is generated. Before the fourth group of user data is stored in the fourth modulation block, the third parity data is written into the fourth modulation block. Figure 2J In the embodiment, a fourth group of user data different from the third group of user data is written into the fourth modulation block, wherein the fourth group of user data includes a gap of the third parity data. In addition, the fourth modulation block includes the fourth group of user data and the third parity data, wherein the fourth group of user data is not modulated data, and the third parity data is not encoded. Figure 2K In the embodiment of the present invention, the fourth group of user data is encoded with the modulation data, such that the fourth group of user data is modulated fourth group of user data. The modulated fourth group of user data is different from the modulated third group of user data. In addition, the third parity data embedded in the modulated fourth group of data may be approximately 30% of the total data of the fourth modulation block.

[0038] exist Figure 2L , fourth parity data for the modulated fourth group of user data is generated. The fourth parity data is written to the fifth modulation block. However, because there is no user data remaining to be programmed into the fifth modulation block, the fourth parity data is not embedded in the user data or the modulation data. The fourth parity data may be approximately 1% of the data available for writing into the fifth modulation block. It should be understood that although the fifth modulation block is illustrated as the last modulation block, and although the fourth parity data is the last parity data written into the last modulation block, additional parity data, user data, and modulation blocks may be between the last modulation block and the previous modulation block. For example, the NVM may have n modulation blocks, where "n" refers to an integer value. In addition, although the fifth modulation block is illustrated as the last modulation block, additional data may be received, wherein the additional parity data and modulation data may be written into the fifth modulation block, the sixth modulation block, and so on.

[0039] Figure 3 is a schematic diagram of a triangular low-density parity-check (LDPC) horizontal (H) matrix 302 in accordance with the disclosed embodiment. Figures 2A to 2L The aspect of embedding parity in the modulation block can be similar to Figure 3 The triangular LDPC H matrix shown in FIG. For example, the group of modulation blocks 304 may be Figure 2L The embodiment shown.

[0040] The triangular LDPC H matrix 302 construction can be implemented to allow for embedded parity in the modulation block encoding of the set of modulation blocks 304. For example, the parity bits (P) can be Figures 2A to 2LThe parity data illustrated in FIG. Parity bits can be calculated sequentially using larger blocks of previously programmed user data. The H matrix construction of the triangular LDPC H matrix 302 can facilitate sequential generation of parity bits and progressive embedding of the generated parity bits in the modulation block.

[0041] User data is represented by the "D" in triangular LDPC H matrix 302. Triangular LDPC H matrix 302 includes a set of rows and a set of columns. Each column has a parity bit or a user data bit, wherein the number of bits per column is approximately 3. The number of bits per column listed is not intended to be limiting, but rather to provide examples of possible implementations. Each row includes at least three user data bits and at least one parity bit. In one embodiment, each row includes up to approximately 30 user data bits.

[0042] The first section "a" of the triangular LDPC H matrix 302 corresponds to the modulated first set of user data 306. The second section "1" of the triangular LDPC H matrix corresponds to the modulated second set of user data 308, wherein the parity bits are parity bands associated with the user data of the modulated first set of user data 306. The third section "2" of the triangular LDPC H matrix 302 corresponds to the modulated third set of user data 310, wherein the parity bits are parity bands associated with the user data of the modulated second set of user data 308. The fourth section "3" of the triangular LDPC H matrix 302 corresponds to the modulated fourth set of user data 312, wherein the parity bits are parity bands associated with the user data of the modulated third set of user data 310.

[0043] Segment "m" of triangular LDPC H matrix 302 includes additional parity bits and user data bits corresponding to an additional modulation block of modulation data and parity data. Segment "n" is the final segment of triangular LDPC H matrix 302, where the final segment includes parity bits. Final segment "n" does not include any modulated user data and corresponds to parity data 314. Therefore, final segment "n" may comprise approximately 1% of the total size of set of modulation blocks 304.

[0044] Figure 4 is a schematic diagram of L-level memory cell encoding according to the disclosed embodiment. Figure 3 Aspects of the triangular LDPC H matrix 302 may be similar to Figure 4 The L-level memory cell encoding. For example, Figure 3 The first segment "a" may be a data segment 408, Figure 3 The second segment "1" may be the first embedded parity segment 410a, Figure 3 The third segment "2" of may be the second embedded parity segment 410b, Figure 3 The fourth segment "3" of may be the third embedded parity segment 410c, and Figure 3 The segment “m” may be the combined fourth embedded parity segment 410d and the fifth embedded parity segment 410e. Figure 3 The final section "n" of may be the parity bit section 412. Furthermore, "D" denotes user data bits and "P" denotes parity bits.

[0045] The data segment 408 is encoded with a modulation code. The data segment 408 can be a 4-bit cell represented by the first segment 402. The embedded parity segments 410a-410e can also be 4-bit cells, where one cell is associated with a parity bit, as shown in the second segment 404. The parity bit segment 412 can be represented by the third segment 406, where the number of bit cells is constrained to n-1 bits of the cell. For example, for a 4-bit cell, as shown in the third segment 406, the parity bit is constrained to 3 bit cells out of the 4-bit cell. In addition, modulation constraints and modulation coding can be implemented on each page of bit cells. The number of bit cells listed is not intended to be limiting, but rather to provide an example of a possible implementation.

[0046] For example, a memory cell (i.e., a bit cell) can be a 5-bit cell, such as a five-level cell (PLC) architecture or even a 3-bit cell. Each memory cell may include multiple levels. The number of levels may be a non-integer power of 2. The number of levels in a cell may be hardware-defined and supported by the modulation code in the binary domain with virtually no code penalty. For example, in the 5-bit cell example, the number of levels is greater than or equal to approximately 20 and less than or equal to approximately 21. For a 20- or 21-level cell including user data bits, the combination of the 20-level cell and the 21-level cell may be approximately 70% of the total data stored on the data storage device or memory cell. Furthermore, when parity data is embedded in the modulation code, such as shown in the second segment 404, approximately 30% of the total data stored on the data storage device may be stored in the second segment 404. Because the parity bit segment 412 does not include user data bits, in the 5-bit cell, the bit cell is constrained to a 4-bit cell, where the data size of the parity bit segment 412 may be approximately 1% of the total data of the data storage device or memory cell.

[0047] It will be appreciated that the first segment 402, corresponding to coded data having no parity data embedded therein, can be modulated most efficiently within the Shannon limit. The second segment 404, corresponding to coded data having parity data embedded therein, can be modulated with a higher code penalty than the first segment 402, but still within the Shannon limit, taking into account the additional constraints imposed by the fixed parity bits. The third segment 406, corresponding to parity data not embedded in any coded data, will have the worst modulation efficiency, but because the third segment 406 (i.e., the last segment) will be very small (i.e., approximately 1% of the data), a higher modulation code penalty can be tolerated.

[0048] Figure 5 is a flow chart illustrating a method 500 of applying LDPC coding to memory cells having arbitrary levels according to the disclosed embodiments. At block 502, a controller (such as Figure 1 The controller 108 of the embodiment of the present invention determines a first segment of user data to which a modulation code is to be applied. The first segment of user data does not include any parity data because the parity data is generated for previously stored data. At block 504, the modulation code is applied to the first segment of user data and the first modulated user data is stored in a first modulation block. For example, the first modulated user data may be Figure 4 Data segment 408.

[0049] At block 506, parity bits are generated for the first modulated user data and stored in the second modulation block. At block 508, the controller determines a second segment of the user data to which modulation coding is to be applied. At block 510, the modulation code is applied to the second segment of the user data, and the second modulated data is stored in the second modulation block. The second modulated data is programmed into the second modulation block such that the parity data generated at block 506 is embedded in the second modulated data. Parity data for the current modulated data in the current modulation block is generated and written to the next modulation block.

[0050] By using a modulation code, user data is encoded in a first modulation block, while the LDPC parity data for the encoded user data is embedded in a different modulation block. The LDPC parity data is not encoded and uses significantly less storage capacity than in a non-modulated case. This allows for storing LDPC parity data for non-integer powers of two unit levels without encoding the LDPC parity data or using excessive storage capacity.

[0051] In one embodiment, a data storage device includes: one or more memory devices; and a controller coupled to the one or more memory devices, wherein the controller is configured to: apply modulation coding to a first set of user data; write the modulated first set of user data into a first modulation block; generate first parity data for the modulated first set of user data; and write the first parity data into a second modulation block. The second modulation block contains a second set of user data different from the modulated first set of user data. Before storing the second set of user data in the second modulation block, the first parity data is written into the second modulation block. The second modulation block does not contain modulation data. The first parity data is not encoded. The first parity data is embedded in the second modulation block, wherein the modulation data does not correspond to the modulated first set of user data. The one or more memory devices include a plurality of levels, wherein the plurality of levels is a non-integer power of 2. The levels are configured as a first portion having first-level cells and a second portion having more second-level cells than the first-level cells, and wherein the total number of levels is a non-integer number, enabling fine-tuning of storage area density. Each cell includes 5 bits. Parity data embedded with user data in the modulation block comprises approximately 30% of the total data and is modulated under the Shannon limit while taking into account fixed parity bit constraints. Parity data not embedded with user data in the modulation block comprises approximately 1% of the total data and is modulated to fit within the I-level cell with embedded blank data. The parity data and blank data have a higher modulation code penalty than the parity data embedded with user data.

[0052] In another embodiment, a data storage device includes: one or more memory devices; and a controller coupled to the one or more memory devices, wherein the controller is configured to: generate parity data for a first set of modulated user data; and embed the parity data with a second set of modulated user data different from the first set of modulated user data. The parity data is not encoded, and the parity data embedded in the second set of modulated user data is positioned adjacent to the first set of modulated user data. The first set of modulated user data does not have parity data embedded therein and is modulated at the Shannon limit. The parity data of the second set of modulated user data does not have any user data embedded therein. The parity data, the first set of modulated user data, and the second set of modulated user data satisfy a triangular H-matrix construction.

[0053] In another embodiment, a data storage device includes: one or more memory devices; means for storing modulated first user data; and means for storing parity data for the modulated first user data at a location different from the modulated first user data. The means for storing the parity data includes means for embedding the parity data with modulation data different from the modulated first user data. The means for storing the modulated first user data includes means for storing the modulated first user data without the embedded parity data. The means for storing the parity data includes means for storing the parity data in a modulated block without any modulated user data.

[0054] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be envisaged without departing from the basic scope thereof, and the scope of the disclosure is determined by the claims that follow.

Claims

1. A data storage device, comprising: one or more memory devices; and a controller coupled to the one or more memory devices, wherein the controller is configured to: applying modulation coding to a first group of user data; Writing the modulated first group of user data into the first modulation block; generating first parity data for the modulated first group of user data; as well as writing the first parity data to a second modulation block, wherein the first modulation block does not include the first parity data, and wherein the second modulation block is configured to store parity data and: User data; or Modulated user data. 2 . The data storage device of claim 1 , wherein the controller is further configured to write a second set of user data different from the modulated first set of user data into the second modulation block. 3 . The data storage device of claim 2 , wherein the first parity data is written to the second modulation block before the second set of user data is stored in the second modulation block. The data storage device of claim 1 , wherein the second modulation block does not contain modulation data. The data storage device of claim 1 , wherein the first parity data is not encoded.

6. The data storage device of claim 1, wherein the first parity data is embedded in the second modulation block, the second modulation block having modulation data that does not correspond to the modulated first group of user data.

7. The data storage device of claim 1, wherein the one or more memory devices comprise a plurality of cells, wherein each cell of the plurality of cells comprises a plurality of levels, and wherein the number of levels of the plurality of levels is a non-integer power of 2.

8. The data storage device according to claim 7, wherein: The plurality of cells includes a first portion having a first number of cells, and a second portion having a second number of cells; the first number of cells comprising a first number of stages and the second number of cells comprising a second number of stages; and The second number of stages is one more than the first number of stages.

9. The data storage device of claim 8, wherein each cell comprises 5 bits.

10. The data storage device of claim 9, wherein the parity data embedded with the user data in the modulation block includes 30% of all data and is modulated under the Shannon limit in consideration of a fixed parity bit constraint.

11. A data storage device according to claim 10, wherein the parity data not embedded with the user data in the modulation block comprises 1% of all data and is modulated to fit into the I-level cell with embedded blank data, wherein the parity data and blank data will have a higher modulation code penalty than the parity data embedded with the user data.

12. A data storage device, comprising: one or more memory devices; and a controller coupled to the one or more memory devices, wherein the controller is configured to: generating first parity data for a first set of modulated user data, wherein the first set of modulated user data is stored in a first modulated block, and wherein the first modulated block does not include the first parity data; as well as embedding the first parity data in a second group of modulated user data different from the first group of modulated user data, wherein the first parity data is not embedded in the first group of modulated user data, and the second group of modulated user data including the embedded first parity data is stored in a second modulation block, and wherein the second modulation block is configured to store the parity data and: User data; or Modulated user data.

13. The data storage device of claim 12, wherein the first parity data is not encoded, and wherein the first parity data embedded in the second group of modulated user data is disposed adjacent to the first group of modulated user data.

14. The data storage device of claim 12, wherein the first set of modulated user data has no parity data embedded therein, and modulated at the Shannon limit.

15. The data storage device of claim 12, wherein the parity data of the second set of modulated user data is not embedded with any user data. 16 . The data storage device of claim 12 , wherein the first parity data, the first group of modulated user data, and the second group of modulated user data satisfy a triangular H-matrix construction.

17. A data storage device, comprising: one or more memory devices; as well as a controller coupled to the one or more memory devices, wherein the controller is configured to: generating modulated first user data and first parity data associated with the modulated first user data, wherein modulation coding is applied to the first user data to generate the modulated first user data; storing the modulated first user data, wherein the modulated first user data is not stored together with the first parity data associated with the modulated first user data, and wherein a first storage location of the modulated first user data does not include the first parity data; as well as storing the first parity data associated with the modulated first user data in a second storage location different from the first storage location of the modulated first user data, wherein the second storage location is used to store the modulated second user data, and wherein the second storage location is configured to store parity data and: User data; or Modulated user data.

18. The data storage device of claim 17, wherein storing the first parity data comprises embedding the first parity data in modulation data different from the modulated first user data.

19. The data storage device of claim 17, wherein storing the modulated first user data comprises storing the modulated first user data without storing embedded parity data.

20. The data storage device of claim 17, wherein storing the first parity data comprises storing the first parity data in a modulated block without any modulated user data.

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