A PROM program storage area expansion EDAC verification circuit and method

Abstract

The present invention provides a PROM program storage area expansion EDAC check circuit and method for resolving the problem of single-bit data errors in the PROM program area of ​​existing spaceborne computers, reducing the risk of single-event upsets in the space environment, and improving product reliability. The circuit comprises a processor with integrated EDAC error correction and detection functions, an SRAM data storage area, and a PROM program storage check area. The SRAM data storage area includes a first SRAM for storing data and a second SRAM for storing the SRAM area EDAC code. The PROM program storage check area includes multiple PROMs for storing programs and a PROM for storing the program area EDAC check code. The processor's data bus is connected to the PROM for storing programs, and the processor's EDAC bus is connected to the PROM for storing the program area EDAC check code.

Description

Technical Field

[0001] The present invention relates to the technical field of space embedded computer applications, in particular to a PROM program storage area expansion EDAC verification circuit and method. Background Art

[0002] Single event upsets (SEUs) are a significant factor affecting the reliability of onboard computer products. A single event upset (SEU) occurs when a single high-energy particle from the universe strikes a sensitive region of a semiconductor device, causing the device's logic state to flip: a stored "0" becomes a "1," or vice versa, leading to system dysfunction and, in severe cases, catastrophic failures. SEUs primarily occur in memory or instruction-related devices. As chip integration increases, the likelihood of SEU errors increases. Typical SEUs are caused by bombardment from high-energy particles in the universe and have become the most common error in onboard computers.

[0003] Currently, the primary SEU protection measure for onboard computer systems is dual (or triple) redundancy. The primary SEU protection measure for program areas is Flash-based triple-module redundancy or direct use of PROM memory. This approach can meet the space environment requirements of general onboard products, but it cannot fully meet the extremely harsh conditions of deep space exploration missions. Because deep space exploration missions involve a high concentration of high-energy particles and long on-orbit time, the Flash memory triple-module redundancy voters themselves lack the ability to withstand space radiation, making voting results unreliable. When two voters experience SEU errors due to the cumulative effect of SEUs, triple-module redundancy becomes ineffective. PROM memory consists of a data area and a logic area. The data area utilizes antifuse technology, making it immune to SEUs. However, the logic area is susceptible to SEUs due to the presence of flip-flops. When data from the PROM data area enters the logic area's flip-flops, bombardment by high-energy particles can cause the flip-flops to flip, potentially causing program execution errors or runaway. Summary of the Invention

[0004] In order to solve the problems existing in the prior art, the present invention provides a PROM program storage area extended EDAC verification circuit and method, which are used to solve the problem of single-bit data errors in the PROM program area of ​​existing onboard computers, reduce the risk of single-event upsets in the space environment, and improve product reliability.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] A PROM program storage area expansion EDAC check circuit includes a processor integrated with an EDAC error correction function, an SRAM data storage area and a PROM program storage check area;

[0007] Wherein, the SRAM data storage area includes a first SRAM for storing data and a second SRAM for storing the EDAC code of the SRAM area, and the PROM program storage and verification area includes multiple PROMs for storing programs and a PROM for storing the EDAC verification code of the program area;

[0008] The address bus A[2:20] of the processor is connected to the address lines A[0:18] of the first SRAM and the second SRAM respectively through a driver, and the address bus A[2:16] of the processor is connected to the address lines A[0:14] of the PROM memory respectively through a driver;

[0009] The data bus of the processor is connected to a PROM for storing programs, and the EDAC bus of the processor is connected to a PROM for storing an EDAC check code in a program area.

[0010] Preferably, the data bus of the first SRAM is connected to the data bus D[0:31] of the processor, and the data bus of the second SRAM is connected to the EDAC bus CB[0:7] of the processor.

[0011] Preferably, the read and write signals of the first SRAM are correspondingly interconnected with the read and write signals of the second SRAM and connected to the global read and write signals of the processor;

[0012] The chip select RAMCS# signals of the first SRAM and the second SRAM are interconnected and connected to the chip select signal of the processor SRAM area.

[0013] Preferably, the PROM program storage check area includes a 32-bit program storage area composed of four 8-bit PROMs and an 8-bit EDAC check area composed of one 8-bit PROM.

[0014] Preferably, the PROM for storing programs includes a first PROM, a second PROM, a third PROM and a fourth PROM, and the PROM for storing the EDAC check code of the program area includes a fifth PROM;

[0015] Among them, the data bus of the first PROM is connected to the data bus D[0:7] of the processor, the data bus of the second PROM is connected to the data bus D[8:15] of the processor, the data bus of the third PROM is connected to the data bus D[16:23] of the processor, the data bus of the fourth PROM is connected to the data bus D[24:31] of the processor, and the data bus of the fifth PROM is connected to the EDAC bus CB[0:7] of the processor.

[0016] Preferably, the read signals of the first PROM, the second PROM, the third PROM, the fourth PROM and the fifth PROM are interconnected and connected to the global read signal of the processor;

[0017] The chip select ROMCS# signals of the first PROM, the second PROM, the third PROM, the fourth PROM and the fifth PROM are interconnected and connected to the chip select signal of the processor PROM area.

[0018] Preferably, the PROM adopts an EEPROM chip during ground simulation verification and adopts a PROM chip in satellite-borne products.

[0019] A PROM program storage area extended EDAC verification method includes the following steps:

[0020] Burn the application program and the EDAC check code into the PROM for storing the program and the PROM for storing the EDAC check code of the program area respectively;

[0021] Insert the PROM into the target product, and connect the data bus of the PROM to the data bus of the processor;

[0022] After the target product is powered on, the program starts running from the PROM. The application program and the EDAC check code are placed on the data bus of the processor. The processor uses its own integrated EDAC error correction function and combines it with the EDAC code on the data bus to check the data in the PROM program area.

[0023] If there is a single bit error in the data, the processor automatically corrects the single bit error;

[0024] If there are two errors in the data, the processor will send a program error signal to complete the verification.

[0025] Preferably, before verifying the application, the process further includes verifying whether the application is loaded normally, specifically:

[0026] Set the application program to not be verified, power on the target product, and observe whether the application program can normally enter the pre-set mark of the main program. If it can enter normally, it means that the application program is loaded normally and proceed to the next step of verification; if it cannot enter normally, it means that the program loading is abnormal.

[0027] Preferably, before performing verification using a processor integrated with an EDAC error correction and detection function, the method further includes verifying whether the processor integrated with an EDAC error correction and detection function can implement the error correction and detection function.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] The present invention provides an EDAC verification circuit for extending a PROM program storage area. When a program is burned, an application program and an EDAC code are respectively burned into a corresponding PROM using a programmer. When a spaceborne computer product is powered on, the program starts to run from the PROM, and a data bus of the PROM is correspondingly connected to a data bus of a processor. A processor with an integrated EDAC error correction and detection function is used in combination with the EDAC code on the data bus to verify application program data in the PROM program area. When a single-bit error occurs, the circuit automatically corrects the error, and when a double-bit error occurs, the program reports an error, thereby realizing a "correct one and check two" function in the program storage area, solving the problem of single-bit data errors in the PROM program storage area of ​​existing spaceborne computers, significantly reducing the risk of single-event upsets in a space environment, enhancing the space-resistant SEU capability of the spaceborne computer product, and improving the space adaptability and reliability of the spaceborne computer. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a block diagram of the EDAC verification circuit for expanding the PROM program storage area of ​​the present invention.

[0031] In the figure, there are a processor 1, a driver 2, a first SRAM 3, a second SRAM 4, a first PROM 5, a second PROM 6, a third PROM 7, a fourth PROM 8, and a fifth PROM 9. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0033] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0034] The present invention is described in further detail below with reference to the accompanying drawings:

[0035] like Figure 1 As shown, the present invention provides a PROM program storage area extended EDAC check circuit, including a processor 1 integrated with an EDAC error correction function, an SRAM data storage area and a PROM program storage check area;

[0036] The SRAM data storage area includes a first SRAM 3 for storing data and a second SRAM 4 for storing the EDAC code of the SRAM area. The PROM program storage and verification area includes multiple PROMs for storing programs and PROMs for storing EDAC verification codes. The PROM for storing programs includes a first PROM 5, a second PROM 6, a third PROM 7, and a fourth PROM 8. The PROM for storing the EDAC verification code of the program area includes a fifth PROM 9.

[0037] The specific connection mode of the SRAM data storage area is as follows: the address bus A[2:20] of the processor 1 is connected to the address lines A[0:18] of the first SRAM 3 and the second SRAM 4 respectively through the driver 2; the data bus of the first SRAM 3 is connected to the data bus D[0:31] of the processor 1; and the data bus of the second SRAM 4 is connected to the EDAC bus CB[0:7] of the processor 1;

[0038] The read signal OE# of the first SRAM3 and the read signal OE# of the second SRAM4 are interconnected, the write signal WR# of the first SRAM3 and the write signal WR# of the second SRAM4 are interconnected, and are connected to the global read and write signals of the processor 1; the chip select RAMCS# signals of the first SRAM3 and the second SRAM4 are interconnected, and are connected to the chip select signal of the SRAM area of ​​the processor 1.

[0039] The specific connection mode of the PROM program storage check area is as follows: the address bus A[2:16] of the processor 1 is connected to the address lines A[0:14] of the PROM memory through the driver 2; the data bus of the processor 1 is connected to the PROM for storing the program, and the EDAC bus of the processor 1 is connected to the PROM for storing the EDAC check code of the program area;

[0040] The data bus of the first PROM 5 is connected to the data bus D[0:7] of the processor 1, the data bus of the second PROM 6 is connected to the data bus D[8:15] of the processor 1, the data bus of the third PROM 7 is connected to the data bus D[16:23] of the processor 1, the data bus of the fourth PROM 8 is connected to the data bus D[24:31] of the processor 1, and the data bus of the fifth PROM 9 is connected to the EDAC bus CB[0:7] of the processor 1;

[0041] The read signals of the first PROM 5, the second PROM 6, the third PROM 7, the fourth PROM 8 and the fifth PROM 9 are interconnected and connected to the global read signal of the processor 1;

[0042] The chip select ROMCS# signals of the first PROM5, the second PROM6, the third PROM7, the fourth PROM8 and the fifth PROM9 are interconnected and connected to the chip select signal of the PROM area of ​​the processor 1.

[0043] Preferably, the PROM adopts an EEPROM chip during ground simulation verification and adopts a PROM chip in satellite-borne products.

[0044] The present invention provides an EDAC check circuit for extending a PROM program storage area. When a program is burned, an application program and an EDAC code are respectively burned into a corresponding PROM using a programmer. When a spaceborne computer product is powered on, the program starts to run from the PROM. A processor integrated with an EDAC error correction and detection function is used in combination with an EDAC check code to check application program data in the PROM program area. When a single-bit error occurs, the circuit automatically corrects the error, and when a double-bit error occurs, the program reports an error. This implements a "correct one, check two" function in the program storage area, solves the problem of single-bit data errors in the PROM program storage area of ​​existing spaceborne computers, significantly reduces the risk of single-event upsets in a space environment, enhances the space resistance to SEUs of the spaceborne computer product, and improves the space adaptability and reliability of the spaceborne computer.

[0045] Specifically, a PROM program storage area extended EDAC verification circuit includes a 32-bit processor 1 with an EDAC verification function, an AC244 driver 2, two SRAMs, one of which is a 32-bit SRAM, the 32-bit SRAM 1 adopts 3DSR16M32CS4084, for storing 32-bit data, and the other is an 8-bit SRAM, the 8-bit SRAM 2 adopts 3DSR4M08CS1271, for storing 8-bit EDAC code; five 32K×8-bit radiation-resistant programmable PROMs all adopt UT28F256, among which four 8-bit PROMs form a 32-bit program storage area for storing boot programs and application programs, and the other 8-bit PROM is used to store the EDAC verification code of the program area. The 32-bit program storage area and the 8-bit EDAC verification area together constitute a PROM program storage area with an EDAC verification circuit.

[0046] The TSC685F processor's read signal OE# is connected to the read signals of two SRAMs and five PROMs. The processor's write signal WR# is connected to the write signals of the two SRAMs. The RAM area chip select signal RAMCS# of the processor is connected to the chip selects of the two SRAMs, and the ROM area chip select signal ROMCS# of the processor is connected to the chip selects of the five PROMs. When the onboard computer product is powered on, the program begins running from the PROM, placing the 32-bit application program and the 8-bit EDAC code on the bus of the processor. The processor uses its integrated EDAC error correction and detection function, combined with the EDAC code on the bus, to verify the data in the PROM program area. If a single-bit error occurs, it will automatically correct it. If a double-bit error occurs, the program will report an error, thus realizing the "correct one, check two" function of the program storage area.

[0047] The specific connection method is as follows: the data bus of the 32-bit SRAM is connected to the data bus D[0:31] of processor 1, and the data bus of the 8-bit SRAM is connected to the EDAC bus CB[0:7] of processor 1; the address bus A[2:20] of processor 1 is connected to the address lines A[0:18] of the two SRAMs after passing through the driver 2AC244; the read signal OE# and write signal WR# of the two SRAMs are interconnected and connected to the global read and write signals of processor 1, and the chip select signal RAMCS# is connected and connected to the chip select of the SRAM area of ​​processor 1;

[0048] The specific connection method is as follows: Five 8-bit PROM memories form a 40-bit program storage area with EDAC function. The data bus of the first PROM is connected to the data bus D[0:7] of processor 1, the data bus of the second PROM is connected to the data bus D[8:15] of processor 1, the data bus of the third PROM is connected to the data bus D[16:23] of processor 1, the data bus of the fourth PROM is connected to the data bus D[24:31] of processor 1, and the data bus of the fifth PROM is connected to the EDAC bus CB[0:7] of processor 1. The address bus A[2:16] of processor 1 is connected to the address lines A[0:14] of the five PROMs through driver 2AC244. The read signal OE# of the five PROMs is connected to the global read signal of processor 1. The chip select signal ROMCS# is connected to the chip select of the PROM area of ​​processor 1.

[0049] It should be noted that the PROM described in the present invention is a read-only memory, which has no write signal and can only be programmed by a programmer. However, the EEPROM used in the functional test of the present invention has a write signal and can be directly programmed.

[0050] The PROM program storage area expansion EDAC verification circuit of the present invention includes the following steps during verification:

[0051] Burn the application program and the EDAC check code into the PROM for storing the program and the PROM for storing the EDAC check code of the program area respectively;

[0052] Insert the PROM into the target product, and connect the data bus of the PROM to the data bus of the processor 1;

[0053] After the target product is powered on, the program starts running from the PROM. The application program and the EDAC check code are placed on the data bus of processor 1. Processor 1 uses its own integrated EDAC error correction function and combines it with the EDAC code on the data bus to check the data in the PROM program area.

[0054] If there is a single bit error in the data, processor 1 automatically corrects the single bit error;

[0055] If there are two errors in the data, processor 1 sends a program error signal to complete the verification.

[0056] Furthermore, before verifying the application, it is also included to verify whether the application is loaded normally, specifically:

[0057] Set the application program to not be verified, power on the target product, and observe whether the application program can normally enter the pre-set mark of the main program. If it can enter normally, it means that the application program is loaded normally and the next step of verification is carried out; if it cannot enter normally, it means that the application program is loaded abnormally.

[0058] Before the PROM program storage area extended EDAC verification circuit of the present invention is put into use, because it is impossible to directly obtain a scenario where high-energy particles disrupt the PROM memory logic area on the ground, and PROM is a read-only memory, single-bit and double-bit errors in the program storage area are simulated on the ground. Verification is performed using an EEPROM with the same function as the PROM. Based on whether the program can be executed normally, it is determined whether the EEPROM program area EDAC "correct one, check two" function is correct and whether it can be implemented. The specific verification method and criteria are as follows:

[0059] A. Verification method of single error correction function:

[0060] (1) Use a dedicated "EDAC generation tool" to generate the 8-bit EDAC code corresponding to the 32-bit application according to the required encoding format, and use a programmer to burn the 32-bit application and the 8-bit EDAC code into the corresponding 5 EEPROMs respectively;

[0061] (2) Insert the four EEPROMs storing the application into the product, set the application to start without verification, power on the product, and observe whether the application can normally enter the pre-set mark of the main program. If it can enter normally, it means that the program is loaded normally;

[0062] Insert the five EEPROMs storing the application and EDAC code into the product, set the application to start and verify, power on the product, and observe whether the application can normally enter the pre-set mark of the main program. If it can enter normally, it means that the program is loaded normally;

[0063] (3) Use the programmer to read the data in the first EEPROM that stores the low byte of the application program, change one bit of a certain 8-bit data from "0" to "1" (or from "1" to "0"), and then re-burn the changed data into the EEPROM. Insert the four EEPROMs that store the application program into the product, set the program startup to not perform verification, power on the product, and observe whether the program can normally enter the pre-set mark of the main program. If it can enter normally, it means that the program is loaded normally. Insert the five EEPROMs that store the application program and EDAC code into the product, set the application startup to perform verification, power on the product, and observe whether the application can normally enter the pre-set mark of the main program. If it can enter normally, it means that the application is loaded normally.

[0064] Correctness criterion for single-error correction function:

[0065] If in step (2), the program is loaded and executed normally to the preset mark regardless of whether EDAC is included or not, and in step (3), the program is loaded abnormally and cannot be executed normally without EDAC verification, but can be loaded and executed normally to the preset mark after EDAC verification, it means that EDAC can realize the single error correction function.

[0066] B. Verification method of double error detection function:

[0067] (1) Use a dedicated "EDAC generation tool" to generate the 8-bit EDAC code corresponding to the 32-bit application according to the required encoding format, and use a programmer to burn the 32-bit application and the 8-bit EDAC code into the corresponding 5 EEPROMs respectively;

[0068] (2) Insert the four EEPROMs storing the application into the product, set the application to start without verification, power on the product, and observe whether the application can normally enter the pre-set mark of the main program. If it can enter normally, it means that the application is loaded normally;

[0069] Insert the five EEPROMs storing the application and EDAC code into the product, set the application to start and verify, power on the product, and observe whether the application can normally enter the pre-set mark of the main program. If it can enter normally, it means that the application is loaded normally;

[0070] (3) Use the programmer to read the data in the first EEPROM that stores the low byte of the application program, change two bits of a certain 8-bit data from "0" to "1" (or from "1" to "0"), and then re-burn the changed data into the EEPROM. Insert the four EEPROMs that store the application program into the product, set the application program to start without verification, power on the product, and observe whether the application program can normally enter the pre-set mark of the main program. If it can enter normally, it means that the application program has loaded normally. Insert the five EEPROMs that store the application program and EDAC code into the product, set the application program to start with verification, power on the product, and observe whether the application program can normally enter the pre-set mark of the main program. If it can enter normally, it means that the application program has loaded normally.

[0071] Correctness criterion of double error detection function:

[0072] If in step (2), the program can be loaded and executed normally to the preset mark regardless of whether EDAC is included or not, and in step (3), the program can be loaded and executed normally without EDAC verification, but cannot be loaded and executed normally with EDAC verification and enters a specific trap, it means that EDAC can realize the double error detection function.

[0073] Example

[0074] The present invention provides an implementation example to further illustrate the verification circuit of the present invention.

[0075] like Figure 1 As shown, the processor used is the Sparc V7 architecture TSC695F. This device features a 32-bit EDAC function. Seven parity bits (CB[6:0]) are used for data bus verification. The DPAR signal is used to verify the 32-bit data bus and generate an odd parity code. Therefore, when the EDAC mechanism is used, the control bus has a total of 40 bits. This device's EDAC mechanism uses a seven-bit Hamming code, which can correct all single-bit errors on the 40-bit bus. It can also detect any double-bit error on the 40-bit bus, but cannot correct the error. The 32-bit SRAM1 uses the 3DSR16M32CS4084, the 8-bit SRAM2 uses the 3DSR4M08CS1271, and the five 32K×8-bit EEPROMs used for test verification use the AT28C256. The address line driver uses the B54AC244.

[0076] The specific connection relationship is as follows: the data bus D[0:31] of the processor TSC685F is directly connected to the data line of SRAM1, and is also divided into 4 groups by byte and connected to the 8-bit data lines of the 4 EEPROMs that store the program; the seven-bit check bits CB[6:0] of the TSC685F and the data bus odd check bit (DPAR) constitute the 8-bit EDAC check bit, which is respectively connected to the 8-bit data lines of SRAM2 and the EEPROM that stores the program EDAC code; after the address bus of the TSC685F passes through the bus driver B54AC244, A[2:20] is directly connected to the address lines A[0:18] of the two SRAMs, and A[2:16] are respectively connected to the address lines A[0:14] of the five EEPROMs. The read signal OE# of TSC685F is connected to the read signals of 2 SRAMs and 5 EEPROMs respectively, the write signal WR# of the processor is connected to the write signals of 2 SRAMs respectively, the processor RAM area chip select RAMCS# is connected to the chip selects of 2 SRAMs respectively, and the processor ROM area chip select ROMCS# is connected to the chip selects of 5 EEPROMs respectively.

[0077] In this embodiment, a ground program is used to simulate single-bit and double-bit errors in the program storage area to verify whether the EDAC "correct one, check two" function of the EEPROM program storage area is correct. The specific verification method and criteria are as follows:

[0078] A. Single error correction function

[0079] Verification method:

[0080] (1) Add a serial port print mark in the main function of the test program. When the program enters the main function normally, it will send 0xA5 through the serial port. Use the "EDAC Generation Tool" to generate the 8-bit EDAC code corresponding to the 32-bit application using Hamming code encoding. Use the programmer to burn the 32-bit application and the 8-bit EDAC code into the corresponding 5 EEPROMs respectively;

[0081] (2) Insert four EEPROMs storing 32-bit application programs into the product and set the program to start without verification. After powering on the product, observe the ground software. If the ground software prints 0xA5, it indicates that the program has been loaded successfully; otherwise, the program has not been loaded successfully.

[0082] Insert the five EEPROMs storing the application program and EDAC code into the product and set the program to start for verification. After powering on the product, observe the ground software. If the ground software prints 0xA5, it indicates that the program has loaded successfully; otherwise, the program has not loaded successfully.

[0083] (3) Use a programmer to read the data from the first EEPROM that stores the low byte of the application program, change the first bit of the third data from "0" to "1", and then re-burn the modified data into the EEPROM. Insert the four EEPROMs that store the application program into the product and set the program to start without verification. After powering on the product, observe the ground software. If the ground software prints 0xA5, it indicates that the program has been loaded successfully; otherwise, the program has not been loaded successfully.

[0084] Insert the five EEPROMs storing the application program and EDAC code into the product and set the program to start for verification. After powering on the product, observe the ground software. If the ground software prints 0xA5, it indicates that the program has loaded successfully; otherwise, the program has not loaded successfully.

[0085] Correctness criteria:

[0086] In step (2), regardless of whether the startup program is set to perform EDAC verification, the ground software can print out 0xA5. In step (3), the startup program is set not to perform EDAC verification, and the ground software does not print out 0xA5. After the startup program is set to perform EDAC verification, the ground software can print out 0xA5. This shows that the EDAC of the PROM can realize the single-error correction function of the program storage area.

[0087] B. Double error detection function

[0088] Verification method:

[0089] (1) Add a serial port print flag to the main function of the test program and enable the double error trap. When the program enters the main function normally, it will send 0xA5 through the serial port. Use the "EDAC Generation Tool" to generate the 8-bit EDAC code corresponding to the 32-bit application using Hamming code encoding. Use the programmer to burn the 32-bit application and the 8-bit EDAC code into the corresponding 5 EEPROMs respectively;

[0090] (2) Insert four EEPROMs storing 32-bit application programs into the product and set the program to start without verification. After powering on the product, observe the ground software. If the ground software prints 0xA5, it indicates that the program loaded successfully. Otherwise, the program loaded unsuccessfully. Use debug commands to check whether the software has entered a specific error trap.

[0091] Insert the five EEPROMs storing the application program and EDAC code into the product and set the program to start for verification. After powering on the product, observe the ground software. If the ground software prints 0xA5, the program loads successfully. Otherwise, the program load fails. Use debug commands to check whether the software has entered a specific error trap.

[0092] (3) Use a programmer to read the data from the first EEPROM that stores the low byte of the application program, change the first bit of the third data from "0" to "1", and change the seventh bit from "1" to "0", and then re-burn the modified data into the EEPROM. Insert the four EEPROMs that store the application program into the product and set the program to start without verification. After the product is powered on, observe the ground software. If the ground software prints 0xA5, it indicates that the program has been loaded successfully; otherwise, the program has not been loaded successfully. Use the debug command to check whether the software has entered a specific error trap.

[0093] Insert the five EEPROMs storing the application program and EDAC code into the product and set the program to start for verification. After powering on the product, observe the ground software. If the ground software prints 0xA5, the program loads successfully. Otherwise, the program load fails. Use debug commands to check whether the software has entered a specific error trap.

[0094] Correctness criteria:

[0095] In step (2), regardless of whether the startup program is set to perform verification, the ground software can print 0xA5. In step (3), the startup program is set not to perform EDAC verification, and the ground software does not print 0xA5. Through software query, the program does not enter the specific error trap. After setting the startup program to perform EDAC verification, the ground software also does not print 0xA5. Through software query, the program enters the specific double error trap. This shows that the EDAC of the PROM can realize the double error detection function of the program storage area.

[0096] In summary, the PROM program storage area extended EDAC check circuit proposed in the present invention can realize the "correct one and check two" function of the program storage area.

[0097] The PROM program storage area expansion EDAC verification circuit proposed in this invention has been put into engineering application. After ground testing, experimental assessment and on-orbit flight verification, it can meet the harsh radiation environment of deep space exploration and ensure the reliability, accuracy and safety of on-board computer products.

[0098] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered by the scope of protection of the claims of the present invention.

Claims

1. A PROM program storage area expansion EDAC verification circuit, characterized in that: It includes a processor (1) with an integrated EDAC error correction function, an SRAM data storage area, and a PROM program storage check area; The SRAM data storage area includes a first SRAM (3) for storing data and a second SRAM (4) for storing an EDAC code of the SRAM area, and the PROM program storage and verification area includes a plurality of PROMs for storing programs and a PROM for storing an EDAC verification code of the program area; The address bus A[2:20] of the processor (1) is connected to the address lines A[0:18] of the first SRAM (3) and the second SRAM (4) respectively through the driver (2); the address bus A[2:16] of the processor (1) is connected to the address lines A[0:14] of the PROM memory respectively through the driver (2); The data bus of the processor (1) is connected to a PROM for storing programs, and the EDAC bus of the processor (1) is connected to a PROM for storing an EDAC check code in a program area; The PROM for storing programs includes a first PROM (5), a second PROM (6), a third PROM (7) and a fourth PROM (8), and the PROM for storing the EDAC check code of the program area includes a fifth PROM (9); The data bus of the first PROM (5) is connected to the data bus D[0:7] of the processor (1), the data bus of the second PROM (6) is connected to the data bus D[8:15] of the processor (1), the data bus of the third PROM (7) is connected to the data bus D[16:23] of the processor (1), the data bus of the fourth PROM (8) is connected to the data bus D[24:31] of the processor (1), and the data bus of the fifth PROM (9) is connected to the EDAC bus CB[0:7] of the processor (1).

2. The PROM program storage area expansion EDAC verification circuit according to claim 1, characterized in that: The data bus of the first SRAM (3) is connected to the data bus D[0:31] of the processor (1), and the data bus of the second SRAM (4) is connected to the EDAC bus CB[0:7] of the processor (1).

3. The PROM program storage area expansion EDAC verification circuit according to claim 1, characterized in that: The read and write signals of the first SRAM (3) and the read and write signals of the second SRAM (4) are correspondingly interconnected and connected to the global read and write signals of the processor (1); The chip select RAMCS# signals of the first SRAM (3) and the second SRAM (4) are interconnected and connected to the chip select signal of the SRAM area of ​​the processor (1).

4. The PROM program storage area expansion EDAC verification circuit according to claim 1, characterized in that: The PROM program storage check area includes a 32-bit program storage area composed of four 8-bit PROMs and an 8-bit EDAC check area composed of one 8-bit PROM.

5. The PROM program storage area expansion EDAC verification circuit according to claim 1, characterized in that: The read signals of the first PROM (5), the second PROM (6), the third PROM (7), the fourth PROM (8) and the fifth PROM (9) are interconnected and connected to the global read signal of the processor (1); The chip select ROMCS# signals of the first PROM (5), the second PROM (6), the third PROM (7), the fourth PROM (8) and the fifth PROM (9) are interconnected and connected to the chip select signal of the PROM area of ​​the processor (1).

6. The PROM program storage area expansion EDAC verification circuit according to claim 1, characterized in that: The PROM adopts EEPROM chip during ground simulation verification and adopts PROM chip in satellite-borne products.

7. A PROM program storage area extended EDAC verification method, characterized in that: The verification circuit according to any one of claims 1 to 6 comprises the following steps: Burn the application program and the EDAC check code into the PROM for storing the program and the PROM for storing the EDAC check code of the program area respectively; Inserting the PROM into the target product, connecting the data bus of the PROM to the data bus of the processor (1); After the target product is powered on, the program starts running from the PROM. The application program and the EDAC check code are placed on the data bus of the processor (1). The processor (1) uses its own integrated EDAC error correction function and combines the EDAC code on the data bus to check the data in the PROM program area. If there is a single bit error in the data, the processor (1) automatically corrects the single bit error; If there are two errors in the data, the processor (1) sends a program error signal to complete the verification.

8. A PROM program storage area expansion EDAC verification method according to claim 7, characterized in that: Before verifying the application, it is also necessary to verify whether the application is loaded normally, specifically: Set the application to not be verified, power on the target product, and observe whether the application can normally enter the pre-set mark of the main program. If it can enter normally, it means that the application is loaded normally and proceed to the next step of verification; If you cannot enter normally, it means that the program loading is abnormal.

9. A PROM program storage area expansion EDAC verification method according to claim 7, characterized in that: Before using the processor (1) integrated with the EDAC error correction and detection function for verification, the process also includes verifying whether the processor (1) integrated with the EDAC error correction and detection function can realize the error correction and detection function.

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