Chip including eFuse module, electronic device and chip burning control method

Abstract

The present invention belongs to the technical field of integrated circuits. In order to solve the technical problem that the existing chip pins including the eFuse module are too many, the present invention provides a chip including the eFuse module, an electronic device and a chip burning control method. The chip includes: an eFuse module, a serial-to-parallel conversion unit, a burning signal analysis unit, a control unit and pins. The pins include a serial input signal pin, a burning reading control signal pin and an output signal pin. The serial-to-parallel conversion unit is used to convert the serial input signal input through the serial input signal pin into a parallel input address signal; the eFuse module is used to burn the corresponding bit of the parallel input address signal converted by the serial-to-parallel conversion unit; the burning signal analysis unit is used to generate a corresponding burning status signal based on the burning signal processed by the eFuse module, and the burning status signal is output through the output signal pin. Therefore, while ensuring the chip information security, the chip pins are reduced and the chip packaging and testing cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a chip including an eFuse module, an electronic device, and a chip burning control method. Background Art

[0002] At present, the security encryption functions of control units such as MCU, MPU, CPU, etc. of various architectures are generally implemented by built-in eFuse modules. The built-in eFuse module can be used to load chip ID, chip production package, key and other information. This type of information sometimes needs to be written by the manufacturer in the CP and FT links, and some needs to be written by the end user, so the pins related to eFuse burning must be brought out in the package. At the same time, it is necessary to meet the requirement that the burned information cannot be read by the non-burning party. With the continuous development and iteration of electronic product technology, customers have higher and higher requirements for security, and the package size is becoming more and more demanding. The existing packaging technology and related substrate and PCB levels are not enough to bring out enough reusable pins in mature mass-produced products. Large-scale compression of test pins on the basis of ensuring customer information security and flexibility has become an inevitable choice for chip design manufacturers. Summary of the invention

[0003] In order to solve the technical problem of excessive chip pins including the existing eFuse module, the present invention provides a chip including the eFuse module, an electronic device and a chip burning control method, which reduces the chip pins while ensuring the chip information security and reduces the chip packaging and testing cost.

[0004] In one aspect, the present invention provides a chip including an eFuse module, characterized in that it includes:

[0005] eFuse module, serial-to-parallel conversion unit, burning signal analysis unit, control unit and pins,

[0006] The pins include a serial input signal pin, a burn-read control signal pin and an output signal pin.

[0007] The control unit is used to set the chip in a programming verification mode when receiving a programming read control signal through the programming read control signal pin;

[0008] The serial-to-parallel conversion unit is used to convert the serial input signal input through the serial input signal pin into a parallel input address signal when receiving the programming and reading control signal through the programming and reading control signal pin;

[0009] The eFuse module is used to burn the corresponding bits of the parallel input address signal converted by the serial-to-parallel conversion unit;

[0010] The burning signal analysis unit is used to generate a corresponding burning status signal based on the burning signal processed by the eFuse module, and the burning status signal is output through the output signal pin; and

[0011] A first multiplexer is located between the serial-to-parallel conversion unit and the eFuse module, and the first multiplexer is connected to the serial-to-parallel conversion unit and the control unit respectively.

[0012] In a preferred embodiment of the present invention, the burning signal analysis unit is a parity check unit, and the parity check unit is used to perform parity check on the multi-bit width Q of the eFuse module. The input signal pin transmits an input signal corresponding to two different parity check results. Based on the change in the parity check result output by the parity check unit before and after the signal burning, it is determined whether the eFuse module is burned successfully.

[0013] In a preferred embodiment of the present invention, the burning signal analysis unit is a burning signal comparison unit, and according to two different input signals, the burning signal comparison unit is used to compare the two read signals before and after burning, and determine whether the eFuse module is burned successfully according to whether the comparison results are different.

[0014] In a further preferred embodiment of the present invention, the serial input signal pin is a two-wire serial communication interface, and the two-wire serial communication interface receives a custom serial protocol and sends a serial address and an address latch signal through a chip burning device; and the first selector is used to switch the address of the burning action and the address of the reading action; wherein the read address is read twice, and the address is the same, but the number of address bits for burning and reading is different.

[0015] In a preferred implementation manner of the present invention, the control unit and the eFuse module are respectively connected to programming and reading control signal pins, and the programming and reading control signal includes a programming signal, a reading signal and / or an action valid signal.

[0016] In a preferred embodiment of the present invention, each time the chip is powered on or reset, each time the chip is switched to a chip burning verification mode, the control unit is also used to check the contents of the eFuse module and record the result; when the chip burning device reads any address for the first time, the control unit sends the check result through the second multiplexer through the output signal pin.

[0017] In a further preferred embodiment of the present invention, the burning signal analysis unit and the control unit are respectively connected to a second multiplexer, and the second multiplexer is connected to the output signal pin; and when any address is read for the first time after power-on or reset, the second multiplexer sends a blank check signal, and in subsequent burning and reading combined operations, the second multiplexer sends a burning bit change flag or a parity check bit.

[0018] A second aspect of the present invention further provides an electronic device, characterized in that it comprises:

[0019] A chip including an eFuse module as described in any one of the first aspects, and

[0020] A peripheral circuit connected to the chip.

[0021] The third aspect of the present invention further provides a chip burning control method, which is applied to a chip, characterized in that the chip is any chip provided in the first aspect, and the method comprises:

[0022] Receive the programming read control signal, and when the chip is switched to the chip programming verification mode, the control unit performs a blank check on the eFuse module content and records the result; when the chip programming device reads any address for the first time, the control unit sends the blank check result through the output signal pin;

[0023] When the control unit receives the burning and reading control signal transmitted by the burning and reading control signal pin, the serial input signal transmitted by the input signal pin is input into the serial-to-parallel conversion unit, and the processed signal converted by the serial-to-parallel conversion unit is input into the eFuse module;

[0024] The burning signal analysis unit outputs a burning status signal based on whether the burning signal processed by the eFuse module meets a predetermined condition, and outputs the burning status signal through the output signal pin.

[0025] A fourth aspect of the present invention further provides a chip burning control method, which is applied to a chip burning device, and is characterized in that the chip is any chip provided in the first aspect, including:

[0026] Input a burning and reading control signal to the chip,

[0027] receiving a burning status signal output by the chip,

[0028] Whether the burning information of the chip is successful is determined according to whether the burning status signal meets a predetermined requirement.

[0029] Therefore, in the above technical solution provided by the present invention, a serial-to-parallel conversion unit electrically connected to the eFuse module is provided inside the chip, which can directly receive the serial input signal pin, and a burning signal analysis unit is provided inside the chip, so that the comparison of whether the burning is successful can be completed directly inside the chip, without transmitting the burning data signal inside the eFuse module to the outside of the chip, thereby reducing the pins of the chip while ensuring the chip information security, thereby reducing the chip packaging and testing cost.

[0030] Other features and advantages of the invention will be described in the following description, and partly become apparent from the description, or understood by implementing the technical solution of the invention. The purpose and other advantages of the invention can be achieved and obtained by the structures and / or processes specifically pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 The present invention is a pin diagram of an eFuse module in a SoC chip in the prior art.

[0032] Figure 2 A connection diagram of a chip including an eFuse module and a chip burning device is provided for an embodiment of the present invention.

[0033] Figure 3 Another connection diagram of a chip including an eFuse module and a chip burning device is provided for an embodiment of the present invention.

[0034] Figure 4 A connection diagram of a chip including an eFuse module and a chip programming device is provided for an embodiment of the present invention.

[0035] Figure 5 A schematic diagram of the principle of data burning of an eFuse module is provided for an embodiment of the present invention.

[0036] Figure 6 A structural block diagram of an electronic device is provided for an embodiment of the present invention.

[0037] Figure 7 A flow chart of a chip burning control method applied to a chip is provided for an embodiment of the present invention.

[0038] Figure 8 A flow chart of a chip programming control method applied to a chip programming device is provided for an embodiment of the present invention.

[0039] Fig. 9 This is a schematic diagram of the data burning principle of the existing eFuse module in the first mode.

[0040] Fig.10This is a schematic diagram of the data burning principle in the first mode of data burning in the existing eFuse module.

[0041] Fig.11 This is a schematic diagram of the data burning principle of the existing eFuse module in the second mode.

[0042] Fig.12 This is a schematic diagram of the data burning principle in the second mode of existing eFuse module data burning. DETAILED DESCRIPTION

[0043] The following will describe the implementation methods of the present invention in detail with reference to the accompanying drawings and embodiments, so that the implementation process of how the present invention applies technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly. It should be noted that these specific descriptions are only to make it easier and clearer for ordinary technicians in the field to understand the present invention, rather than a restrictive interpretation of the present invention; and as long as there is no conflict, the various embodiments of the present invention and the various features in the embodiments can be combined with each other, and the technical solutions formed are all within the protection scope of the present invention.

[0044] Additionally, the steps shown in the flowcharts of the accompanying drawings may be executed in a control system such as a set of controller executable instructions, and although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in an order different from that shown here.

[0045] The technical solution of the present invention is described in detail below through the accompanying drawings and specific embodiments:

[0046] like Figure 1 The figure shows an eFuse module used in the design of an existing chip (for example, a SoC chip, SoC is the abbreviation of System on Chip module, also known as System on Chip). The chip in the following embodiments may also be a chip including but not limited to a SoC type. Figure 1 The figure shows a commonly used 4K eFuse. All related pins need to be connected to the multiplexed GPIO or multiplexed universal serial port pins through PIN_MUX. If the eFuse with other capacity is used, the address line and data line width will be adjusted accordingly. The pin requirements of other control lines and power, ground, and programming power remain unchanged. The description of some ports is as follows:

[0047]

[0048]

[0049] If you want to integrate the eFuse module to burn and verify the package, you need to occupy the following IO resources:

[0050] Address bus: A = 12

[0051] Data bus: Q = 32

[0052] Necessary programming and reading control signals: STROBE+LOAD+PGENB+PS+MR=5

[0053] Burning power supply and multiplexing selection signal: some are not included.

[0054] Excluding power lines, ground lines, programming power supplies and multiplexed configuration pins, a total of 49 multiplexed pin resources are required.

[0055] Different from the read and write mode of Flash or EPROM, eFuse can only program and write 1 bit at a time, and can read 1 to 4 bytes at a time (determined by the Q bit width of eFuse). As shown in the following table, when programming externally, only READ, Margin_Read, and Program modes need to be supported, while Standby and Power-down modes do not need to be supported. Accordingly, CSB and PD pins can be selected within the chip and do not need to be led out to the chip.

[0056] Burning process:

[0057] When CP, FT, or chip programming device performs programming, it is necessary to refer to the following Fig. 9 The address is addressed by combining the high bit A[11:7] and the low bit A[6:0] to directly address the bit to be programmed. Fig.10 The timing waveform shown sends the corresponding signal and burning power to the chip.

[0058] according to Fig.10 After the waveform and programming power are input in the middle timing, the eFuse Bit specified by the address is programmed. After completion, a read operation is required to verify whether the programming is correct.

[0059] Reading process

[0060] When CP, FT, or chip programming device performs a read operation, it is necessary to refer to Fig.11 Content addressing: eFuse modules generally cannot read single bits. Depending on the Q bit width of the eFuse, CP, FT and chip burning devices can generally only read a whole byte, double byte or quad byte at a time. Therefore, only the low address bits A[6:0] are valid, addressing the byte, double byte or quad byte to be read. And according to Fig.12 The timing waveform shown sends the corresponding signal into the chip.

[0061] according to Fig.12After the timing is input into the waveform, the previously programmed content is verified to be successfully written according to the programmed bit correspondence table. The bit correspondence table is shown in the figure below. This table has corresponding changes according to the different types of eFuse modules.

[0062] Therefore, the existing chips including the eFuse module have the following deficiencies:

[0063] Many package pins: When the SOC chip with integrated eFuse module is doing FT testing and customer burning, it is necessary to lead out parallel address lines and parallel data lines in the package, thus occupying a large number of reusable ports. Figure 1 From the schematic diagram, at least 49 additional pins are required in addition to the pins required for testing)

[0064] Poor flexibility in allocating permissions for the eFuse module: The eFuse module integrated in the SoC needs to be loaded with a lot of information and control bits, such as chip ID, key, traceability information for production packaging and testing, chip operating mode control bits, and chip boot and access permission control bits, etc. According to different business cooperation models or sales strategies between manufacturers and customers, the content in the eFuse module needs to meet the flexible allocation of the burning range between manufacturers and customers. Both parties can burn their designated locations in the eFuse module, and at the same time, neither party can read the burning content of the other party.

[0065] The existing general eFuse module burning and reading solutions usually stipulate the burning and reading range of the eFuse module content between manufacturers and customers and protect the specific area through access control bits. This method has poor flexibility in commercial promotion as the burning and reading range of most manufacturers and customers has been determined after the chip is put into production and cannot be modified at will.

[0066] The packaged chip has a physical reading path, and the cracking cost is low: the currently commonly used burning and reading method requires the realization of off-chip burning function, so there is a physical path for data reading (to verify the correctness of burning), and the information written by the manufacturer or customer has the possibility of being illegally read by the other party or a third party. For example, the access control bit modified by the FIB can be obtained by directly reading the corresponding encrypted information in the chip through the off-chip method; therefore, the security is generally low.

[0067] Example

[0068] In order to solve the technical problem of excessive chip pins including the existing eFuse module, the present invention provides a chip including the eFuse module, an electronic device and a chip burning control method, which reduces the chip pins while ensuring the chip information security and reduces the chip packaging and testing cost.

[0069] like Figure 2As shown, this embodiment provides a chip including an eFuse module, and the chip 100 includes:

[0070] eFuse module 140, serial-to-parallel conversion unit 120, burning signal analysis unit 160, control unit 150 and pins,

[0071] The pins include a serial input signal pin 112, programming and reading control signal pins 114 and 118, and an output signal pin 116; pin 114 is a control signal necessary for eFuse programming, such as Figure 1 As shown (STROBE, CSB, LOAD, PGENB, PD and other control signals), pin 118 is the reset and clock signal necessary for working within the SoC, mainly for identifying the first reading of burning after power-on or reset, so as to control the second multiplexer to send a blank check result signal to 116.

[0072] The control unit 150 is used to set the chip 100 in a burning verification mode when receiving a burning read control signal through the burning read control signal pin 118;

[0073] The serial-to-parallel conversion unit 120 is used to convert the serial input signal input through the serial input signal pin 112 into a parallel input address signal when receiving the burn-in read control signal through the burn-in read control signal pin 114;

[0074] The eFuse module 140 is used to burn the corresponding bits of the parallel input address signal converted by the serial-to-parallel conversion unit 120;

[0075] The burning signal analysis unit 160 is used to generate a corresponding burning status signal based on the burning signal processed by the eFuse module 140 , and the burning status signal is output through the output signal pin 116 .

[0076] Specifically, when the control unit 150 receives the burn-read control signal transmitted by the burn-read control signal pin 118, the serial input signal transmitted by the input signal pin 112 is input to the serial-to-parallel conversion unit 120, and the processed signal (e.g., parallel processing signal) converted by the serial-to-parallel conversion unit 120 is input to the eFuse module 140;

[0077] The burning signal analysis unit 160 outputs a burning status signal based on whether the burning signal processed by the eFuse module 140 meets a predetermined condition, and outputs the burning status signal through the output signal pin 116 .

[0078] In a preferred implementation of this embodiment, the control unit 150 and the eFuse module 140 are connected to the programming and reading control signal pins 114 and 118 respectively, and the programming and reading control signal includes a programming signal, a reading signal and / or an action valid signal.

[0079] Therefore, in the above technical solution provided in this embodiment, a serial-to-parallel conversion unit electrically connected to the eFuse module is provided inside the chip, which can directly receive the serial input signal pin, and a burning signal analysis unit is provided inside the chip, so that the comparison of whether the burning is successful can be completed directly inside the chip, without transmitting the burning signal inside the eFuse module to the outside of the chip, thereby reducing the pins of the chip while ensuring the chip information security, thereby reducing the chip packaging and testing costs.

[0080] Regarding the specific implementation of the burning signal analysis unit 160, this embodiment provides two methods:

[0081] 1. Parity check method:

[0082] Specifically, Figure 3 As shown, in this embodiment, the burning signal analysis unit 160 is a parity check unit 162, and the parity check unit 162 performs parity check on the multi-bit width Q of the eFuse module. The input signal pin transmits the input signal corresponding to two different parity check results. Based on the change in the parity check result output by the parity check unit before and after the signal burning, it is determined whether the eFuse module is burned successfully.

[0083] 2. Burning signal comparison method:

[0084] Specifically, Figure 4 As shown, in this embodiment, the burning signal analysis unit 160 is a burning signal comparison unit 164 (for example, a Shift comparison unit), and according to two different output signals, (one reading before burning and one reading after burning), the burning signal comparison unit compares the output data read twice before and after burning, and determines whether the eFuse module is burned successfully according to whether the comparison results are different.

[0085] These two implementation methods are shown in the principle box Figure 3 And principle box Figure 4As shown: The main implementation methods are the same, but there are differences in the logic of outputting serial data. The parity check unit performs parity check on the multi-bit width Q of the eFuse module (for example, if there are an even number of 1s in Q, output 0. If there are an odd number of 1s in Q, output 1), and then sends the check bit to the multiplexer and outputs it. The shift comparison unit compares the multi-bit width Q read out twice in succession (for example, if the current read Q is the same as the last read Q, output 0. If they are not the same, output 1), and the comparison result is sent to the multiplexer and output.

[0086] pass Figure 3 and Figure 4 It can be seen that this embodiment has been greatly simplified based on the complex interface of the existing eFuse module, and the parallel address input and parallel data output have been changed to serial address input and serial data output. As shown in the example above, excluding the power line, ground line, burning power supply and multiplexing configuration pins, the total occupied multiplexing pins are reduced from 49 to 8, that is, 5 necessary burning and reading control signals, 2 address inputs, and 1 data output.

[0087] Specifically: the chip burning device (also called chip burner or off-chip burner) 200 inputs the address through the serial protocol, and converts it into the parallel data line required by the eFuse module through the serial-to-parallel unit 120. The serial protocol can be either a general serial protocol or a custom serial protocol. It can be either a single line, a dual line or a multi-line. This case takes the custom dual-line protocol as an example, such as the chip burning device sends a serial address and an address latch signal. The circuit shown in this embodiment uses the address latch signal to receive the address information, and at the same time converts it into a parallel address and sends it to the multiplexer.

[0088] For example, the serial input signal pin is a two-wire serial communication interface, and the two-wire serial communication interface receives a custom serial protocol and sends a serial address and an address latch signal through the chip burning device; a first multiplexer 130 is provided between the serial-to-parallel conversion unit 120 and the eFuse module 140; the first multiplexer 130 is respectively connected to the serial-to-parallel conversion unit 120 and the control unit 150. Among them, the first multiplexer 130 is used to switch the address of the burning action and the address of the reading action (for example, the reading address will be read twice, the address is the same, and the change of the parameter after burning is checked), and the address bits of the burning and reading are different.

[0089] The eFuse module 140 is an eFuse unit integrated in the SOC chip. The control unit 150 mainly includes the following functions:

[0090] 1. Each time the chip is powered on or reset, once the SoC is switched to the external programmer mode, the control unit 150 will actively check the eFuse module content and record the result. When the chip programmer reads any address for the first time, the control unit 150 will send the check result serially through the second multiplexer through the multiplexer.

[0091] For example, each time the chip is powered on or reset, each time the chip is switched to the chip burning verification mode, the control unit performs a check on the eFuse module content and records the result; when the chip burning device reads any address for the first time. However, the technical solution provided by the present embodiment of the invention is not limited to this. For example, it can also be set so that if the chip burning device does not read any address, it can directly output 0, or 1 or a pulse or a certain level to enable the burning device to obtain the check information; these different implementations all belong to the scope of protection of the present invention. The control unit sends the check result through the output signal pin via the second multiplexer. Specifically, the burning signal analysis unit 160 and the control unit 150 are respectively connected to the second multiplexer 170, and the second multiplexer 170 is connected to the output signal pin. Among them, in the preferred implementation, the check signal is indispensable, because whether it is judged that the burning is successful by reading from the parity check, or judging that the burning is successful by reading once before and after the burning, it can only reflect to the off-chip burner whether the burning bit has changed. The original blank check (eg, defect detection) operation result of the newly produced chip cannot be known by the off-chip programmer, so it needs to be selected and sent out through the second multiplexer; of course, a dedicated pin is not required.

[0092] 2. The two multiplexers 130 and 170 for controlling the address and data are switched to the control unit to provide the eFuse module address (check for empty) when power is turned on to enter the external programming verification mode. When the first arbitrary address is read after entering the external programming verification mode, it is switched to the data output of the control unit 150 (for example, the empty check result is sent via the second multiplexer). During the subsequent programming or reading action, the control unit 150 switches the multiplexers 130 and 170 to the normal working state of the chip programming device (the chip programming device is programmed and verified), the chip programming device provides the eFuse module address, and the chip programming device receives the data output of the parity check unit 162 or the Shift comparison unit 164.

[0093] 3. Parity check unit and shift comparison unit

[0094] The implementation principles of the parity check unit or the shift comparison unit are different, but they can achieve the same result. Therefore, in this embodiment, any parity check or comparison unit can be used, for example:

[0095] 1). It can verify whether the result of a single programming is correct.

[0096] 2). Generate a single-bit result and send it out through a multiplexer; reduce the bit width of the check information and reduce the occupancy of the multiplexed signal.

[0097] 3). The generated verification information cannot be used to reverse the original data contained in the eFuse module.

[0098] 4). Physically, there are no multiple data lines connected from the vicinity of the eFuse module to the vicinity of the PAD unit. Therefore, it is difficult to implement using conventional cracking methods (FIB rewrites the access control bit and then reads it out through the normal path); and the cost is very high and the success rate is very low.

[0099] 5. About the implementation principle of parity check unit and shift comparison unit:

[0100] like Figure 5 As shown, the eFuse module usually adopts a single-bit programming and multi-byte data reading method. During programming, the full address (A[11:0]) is decoded to the bit to be programmed, and programming is implemented through the burning control line. When reading data, the low address (A[6:0]) is decoded to the multiple bytes to be read (in this example, the bit width of Q is 32 bits), and the reading is implemented through the burning control line. In this embodiment, whether the parity check unit or the shift comparison unit is used, the chip burning device must go through the following four steps to burn a certain bit:

[0101] a). Query the read address (such as L1 arrow) corresponding to the programming bit (such as L2 arrow) in the address mapping table of the eFuse module.

[0102] b). Read the Q output containing the programming bit once before programming. (Q[31:0] of the address corresponding to the L1 arrow)

[0103] c). Perform programming on the programming bit (the bit designated by the L2 arrow)

[0104] d). After programming, read the Q output containing the programmed bit. (Q[31:0] of the address corresponding to the L1 arrow)

[0105] Parity check unit principle:

[0106] The difference between the parity check unit and the shift comparison unit when programming a certain bit is that the parity check unit performs parity check on the read data Q[31:0] twice before and after programming, and sends the result to the chip programming device. The chip programming device determines that the programming is successful by discovering the change in the parity check result when reading after programming.

[0107] The Shift comparison unit caches the Q[31:0] output of the previous read operation before and after programming in a programming operation and compares it with the Q[31:0] output of the next read operation. If the comparison results are the same, the comparison result outputs 0 and caches the next Q[31:0]. If the comparison results are different, the comparison result outputs 1 and caches the next Q[31:0]. The chip programming device determines whether the programming is successful by finding out whether the comparison result is 1 when reading after programming.

[0108] The chip burning device 200 includes a signal sending module 210, for example, sending serial signals and burning reading control signals; and a signal receiving module 230, for example, receiving the burning result signal fed back by the chip, and a burning result judgment unit, which determines whether the burning signal is successful according to the signal received by the signal receiving module 230.

[0109] like Figure 8 As shown, this embodiment provides a chip burning control method, which is applied to a chip burning device. The chip is any one of the chips provided above. The chip burning control method includes:

[0110] S210. Input the burning and reading control signal to the chip,

[0111] S220. Receive the burning status signal output by the chip,

[0112] S230. Determine whether the chip programming information is successful based on whether the programming status signal meets a predetermined requirement.

[0113] More specifically, when the chip burning device 200 programs the SoC chip using the eFuse module described in this embodiment, it needs to work according to the following logic:

[0114] 1. Read the burning configuration file, find the address of the bit to be burned, and the corresponding read address.

[0115] 2. Power on the SoC chip to be programmed and enter programming mode.

[0116] 3. Read a specific or unspecified address once (or do not read the address, and directly send the blank check information), and determine whether there is information in the eFuse module based on the output blank check information. All chip burning devices must perform this reading action before burning. This step is mainly used by SoC manufacturers to check whether the eFuse module has manufacturing defects (check whether the eFuse is blown when leaving the factory).

[0117] 4. Program the bits that need to be programmed, and perform the read / program / read actions described above. And determine whether the programming is successful based on the shift comparison result obtained by the last read or the parity check data obtained by the two reads.

[0118] like Figure 7 As shown, this embodiment also provides a chip burning control method, which is applied to a chip, and the chip is any one of the above chips. The method includes:

[0119] S110. Receive the programming read control signal, and when the chip is switched to the chip programming verification mode, the control unit performs a blank check on the eFuse module content and records the result; when the chip programming device reads any address for the first time, the control unit sends the blank check result through the output signal pin (for example, through the second multiplexer through the output signal pin);

[0120] S120. When the control unit receives the burning and reading control signal transmitted by the burning and reading control signal pin, the serial input signal transmitted by the input signal pin is input to the serial-to-parallel conversion unit, and the processed signal converted by the serial-to-parallel conversion unit is input to the eFuse module;

[0121] S130. The burning signal analysis unit outputs a burning status signal based on whether the burning signal processed by the eFuse module meets a predetermined condition, and outputs the burning status signal through an output signal pin.

[0122] like Figure 6 As shown, this embodiment further provides an electronic device 300, which includes:

[0123] A chip 100 including an eFuse module as provided above, and

[0124] The peripheral circuit 310 connected to the chip can be determined in combination with the specific application scenario of the electronic device 300. For example, the electronic device 300 can be a mobile terminal, a PAD, a computer, an Internet of Things terminal (such as a stereo, a household appliance), etc. The peripheral circuit inside the electronic device 300 can be a power supply or a voltage input circuit, and may also include a display, a sound player, etc. according to actual needs.

[0125] By adopting the above technical solution provided by the fundamental embodiment, one or more of the following technical effects can be achieved: less reusable pin resources are required, the package has strong adaptability, and small package chips can also be used for eFuse burning. 2. There is no physical data readout path, and the cost and difficulty of cracking are high. 3. Since the off-chip burner cannot read the data, the control bit and information resource bit allocation in the eFuse module of manufacturers and customers is more flexible, which can open up a wider range of business cooperation models.

[0126] It can be understood by those skilled in the art that the above-mentioned method according to the embodiment of the present invention can be implemented in hardware, firmware, or implemented as software or computer code that can be stored in a recording medium (such as a CD ROM, RAM, floppy disk, hard disk or magneto-optical disk), or implemented as computer code originally stored in a remote recording medium or a non-temporary machine-readable medium downloaded through a network and to be stored in a local recording medium, so that the method described herein can be stored in such software processing on a recording medium using a general-purpose computer, a dedicated processor or programmable or dedicated hardware (such as an ASIC, FPGA or SoC). It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component (e.g., RAM, ROM, flash memory, etc.) that can store or receive software or computer code, and when the software or computer code is accessed and executed by a computer, a processor or hardware, the processing method described herein is implemented. In addition, when a general-purpose computer accesses the code for implementing the processing shown herein, the execution of the code converts the general-purpose computer into a dedicated computer for executing the processing shown herein.

[0127] Those of ordinary skill in the art will appreciate that the units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present invention.

[0128] Finally, it should be noted that the above description is only the best embodiment of the present invention and does not limit the present invention in any form. Any technician familiar with the art can make many possible changes and simple replacements to the technical solution of the present invention by using the above disclosed practices and technical contents without departing from the scope of the technical solution of the present invention, which all belong to the scope of protection of the technical solution of the present invention.

Claims

1. A chip including an eFuse module, characterized in that: include: eFuse module, serial-to-parallel conversion unit, burning signal analysis unit, control unit, first multiplexer and pins, The pins include a serial input signal pin, a burn-read control signal pin and an output signal pin. The control unit is used to set the chip in a programming verification mode when receiving a programming read control signal through the programming read control signal pin; The serial-to-parallel conversion unit is used to convert the serial input signal input through the serial input signal pin into a parallel input address signal when receiving the programming and reading control signal through the programming and reading control signal pin; The eFuse module is used to burn the corresponding bits of the parallel input address signal converted by the serial-to-parallel conversion unit; The burning signal analysis unit is used to generate a corresponding burning status signal based on the burning signal processed by the eFuse module, and the burning status signal is output through the output signal pin; as well as The first multiplexer is located between the serial-to-parallel conversion unit and the eFuse module, and is connected to the serial-to-parallel conversion unit and the control unit respectively. Among them, the serial input signal pin is a two-wire serial communication interface, and the two-wire serial communication interface receives a custom serial protocol and sends a serial address and an address latch signal through a chip burning device; and the first multiplexer is used to switch the address of the burning action and the address of the reading action, wherein the read address is read twice and the address is the same, and the number of address bits for burning and reading is different.

2. The chip according to claim 1, characterized in that: The programming signal analysis unit is a parity check unit, which is used to perform parity check on the multi-bit width Q of the eFuse module. The input signal pin transmits the input signal corresponding to two different parity check results. Based on the change of the parity check result output by the parity check unit before and after the signal is burned, it is determined whether the eFuse module is burned successfully.

3. The chip according to claim 1, characterized in that: The burning signal analysis unit is a burning signal comparison unit, and according to two different input signals, the burning signal comparison unit is used to compare the input signals read twice before and after burning, and determine whether the eFuse module is burned successfully according to whether the comparison results are different.

4. The chip according to claim 1, characterized in that: The control unit and the eFuse module are respectively connected to the programming and reading control signal pins, and the programming and reading control signal includes a programming signal, a reading signal and / or an action valid signal.

5. The chip according to claim 1, characterized in that: Each time the chip is powered on or reset, and each time the chip is switched to the chip burning verification mode, the control unit is also used to check the contents of the eFuse module and record the result; when the chip burning device reads any address for the first time, the control unit sends the check result through the second multiplexer through the output signal pin.

6. The chip according to claim 5, characterized in that: The programming signal analysis unit and the control unit are respectively connected to a second multiplexer, and the second multiplexer is connected to the output signal pin; and when any address is read for the first time after power-on or reset, the second multiplexer sends a blank check signal, and in subsequent programming and reading combined operations, the second multiplexer sends a programming bit change flag or a parity check bit.

7. An electronic device, characterized in that: include: A chip comprising an eFuse module as claimed in any one of claims 1 to 6, and A peripheral circuit connected to the chip.

8. A chip burning control method, applied to a chip, characterized in that: The chip is any one of claims 1 to 6, and the method comprises: Receive the programming read control signal, and when the chip is switched to the chip programming verification mode, the control unit performs a blank check on the eFuse module content and records the result; when the chip programming device reads any address for the first time, the control unit sends the blank check result through the output signal pin; When the control unit receives the burning and reading control signal transmitted by the burning and reading control signal pin, the serial input signal transmitted by the input signal pin is input into the serial-to-parallel conversion unit, and the processed signal converted by the serial-to-parallel conversion unit is input into the eFuse module; The burning signal analysis unit outputs a burning status signal based on whether the burning signal processed by the eFuse module meets a predetermined condition, and outputs the burning status signal through the output signal pin.

9. A chip burning control method, applied to a chip burning device, characterized in that: The chip is any one of claims 1 to 6, comprising: Input a burning and reading control signal to the chip, receiving a burning status signal output by the chip, Whether the burning information of the chip is successful is determined according to whether the burning status signal meets a predetermined requirement.

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