A Network-on-Chip Setting Method and Its Structure

Abstract

The present disclosure proposes a method for setting up an on-chip network, including: constructing an on-chip network, the on-chip network including multiple memory nodes and memory interfaces, each of the memory nodes being provided with a timer; setting the timing length of each of the timers so that the total delay for a data packet to access any of the memory nodes in the on-chip network is a fixed value, wherein the total delay includes a transmission delay and an additional delay, the transmission delay including the time consumed by the data packet when traveling from the memory interface to the memory node, and the time consumed by the data packet when returning from the memory node to the memory interface, and the additional delay being the time when the data packet is inserted by the timer on the memory node.

Description

Technical Field

[0001] The present disclosure relates to the field of memory, and in particular to a method and structure for setting up a network on chip. Background Art

[0002] With the advent of the era of big data and artificial intelligence, the amount of data generated by humanity is growing exponentially. Processing such large amounts of data requires computer system memory to accommodate this increasing volume. Network-on-chip (NOC) memory offers excellent scalability while maintaining performance, and is expected to become a promising memory solution in the era of massive memory.

[0003] Dynamic random access memory (DRAM), the main memory of a computer system, requires uniform access to the DRAM memory. This means that the access time to data stored in any memory node in the DRAM is a fixed constant. However, as the on-chip (NOC) architecture of DRAM continues to expand, the transmission distances of data packets vary further, resulting in a variable transmission delay within the NOC.

[0004] Therefore, the problem of how to unify memory access time in on-chip networks needs to be solved urgently. Summary of the Invention

[0005] In view of this, the present disclosure proposes a method for setting up an on-chip network, including: constructing an on-chip network, the on-chip network including multiple memory nodes and memory interfaces, and each of the memory nodes is provided with a timer; setting the timing length of each timer so that the total delay of a data packet accessing any of the memory nodes in the on-chip network is a fixed value, wherein the total delay includes a transmission delay and an additional delay, the transmission delay includes the time consumed by the data packet when traveling from the memory interface to the memory node, and the time consumed by the data packet when returning from the memory node to the memory interface, and the additional delay is the time when the data packet is inserted by the timer on the memory node.

[0006] Optionally, setting the timing length of each of the timers includes: determining the transmission delay corresponding to each of the memory nodes and determining the total delay; calculating the additional delay of each of the memory nodes based on the difference between the total delay and the transmission delay corresponding to each of the memory nodes; and setting the timing length of each of the timers based on the additional delay of each of the memory nodes.

[0007] Optionally, determining the transmission delay corresponding to each of the memory nodes includes: determining a transmission path for the data packet to access each of the memory nodes based on a deterministic routing algorithm; and determining the transmission delay of the data packet based on the transmission path corresponding to each of the memory nodes.

[0008] Optionally, determining the total delay includes: setting the transmission delay corresponding to the memory node with the longest transmission path as the total delay.

[0009] Optionally, constructing an on-chip network includes: interconnecting the memory nodes to form an on-chip network structure; setting the memory interface on any one of the memory nodes; and setting a timer at the interface of each memory node.

[0010] On the other hand, the present disclosure also proposes an on-chip network, which is suitable for the method as described above, including: multiple memory nodes, each of which is interconnected to form an on-chip network structure; a memory interface, which is set on any one of the memory nodes; and multiple timers, which are respectively set at the interface of each memory node and correspond one-to-one to each memory node, and are used to insert additional delays when the memory node responds to the data packet, so that the total delay of the data packet accessing any memory node in the on-chip network is a fixed value.

[0011] Optionally, the network on chip further includes: a timer time setting unit, configured to calculate the additional delay of each of the memory nodes to set a timing length of each of the timers.

[0012] Optionally, the memory node is a dynamic random access memory node.

[0013] As can be seen from the above technical solution, the present disclosure solves the problem of inconsistent memory access in the current on-chip network by adding additional delays to the memory nodes, making the on-chip network compatible with existing dynamic random access memory protocols and standards and able to be integrated into the existing computer system ecosystem. The core idea of this method is to use a deterministic routing algorithm to determine the transmission path, and by determining the transmission path, the characteristics of the transmission delay can be determined. Before different memory nodes send the returned data packets, a timer is started to add additional delays so that the total delay of all data packets transmitted within the on-chip network is equal. It has the characteristics of simple implementation and strong practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0015] Figure 1A method for setting up a network on chip according to an embodiment of the present disclosure is schematically shown;

[0016] Figure 2 The following schematically illustrates a schematic system architecture of a network on chip according to an embodiment of the present disclosure;

[0017] Figure 3 A schematic diagram of determining a transmission path using a deterministic routing algorithm according to an embodiment of the present disclosure is schematically shown;

[0018] Figure 4 Schematically shows a distribution diagram of additional delay of an on-chip network according to an embodiment of the present disclosure;

[0019] Figure 5 A method for using a network on chip according to an embodiment of the present disclosure is schematically illustrated. DETAILED DESCRIPTION

[0020] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0021] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise," "include," etc. used herein indicate the presence of features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0022] All terms used herein, including technical and scientific terms, have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0023] When using expressions such as "at least one of A, B and C, etc.", they should generally be interpreted according to the meaning of the expression commonly understood by those skilled in the art. For example, "a device having at least one of A, B and C" should include but is not limited to a device having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.

[0024] Figure 1 The diagram schematically illustrates a method for setting up a network on chip based on unified memory access in an embodiment of the present disclosure. Figure 1 As shown, the method for accessing the memory includes steps S110 to S120.

[0025] S110, constructing an on-chip network, the on-chip network including multiple memory nodes and memory interfaces, each memory node being provided with a timer.

[0026] Step S111 : interconnecting the memory nodes to form an on-chip network structure.

[0027] Step S112: Set the memory interface on any memory node.

[0028] Step S113: Set a timer at the interface of each memory node.

[0029] The network-on-chip structure of the embodiment of the present disclosure is described by taking a Mesh network as an example. Figure 2 As shown, the on-chip network includes multiple memory nodes and memory interfaces, and a timer is also set on the interface of each memory node.

[0030] According to an embodiment of the present disclosure, memory nodes are interconnected to form an on-chip network structure, so that data packets can be transmitted to any memory node, where the memory node is a node of a dynamic random access memory.

[0031] According to an embodiment of the present disclosure, a memory interface is provided on any memory node. The memory interface is used to parse command data from a memory controller, generate a data packet, and the destination memory node to be accessed by the data packet. The memory interface is also used to receive returned data packets, parse them, and transmit them to the memory controller.

[0032] The on-chip network structure interconnects all memory nodes within the memory to form a unified whole, establishing a data transmission path from the memory interface to any memory node. Because the memory interface can communicate with any memory node, the external memory controller can complete communication operations with all memory nodes through the memory interface.

[0033] According to an embodiment of the present disclosure, a timer is set at an interface of a memory node to insert an additional delay when the memory node responds to a data packet and generates a return data packet.

[0034] It is understandable that the topology of the on-chip network can be diverse, including but not limited to the Mesh network mentioned in the embodiments of the present disclosure.

[0035] Step S120 sets the timing length of each timer so that the total latency for a data packet accessing any memory node within the on-chip network is the same. The total latency includes transmission latency and additive latency. The transmission latency includes a first transmission latency and a second transmission latency. The first transmission latency is the time it takes for a data packet to travel from the memory interface to the memory node, the second transmission latency is the time it takes for the data packet to return from the memory node to the memory interface, and the additive latency is the time it takes for the data packet to be inserted by the timer on the memory node. The step of setting the timing length of each timer includes steps S121 to S123.

[0036] Step S121 : determining the transmission delay and total delay corresponding to each memory node.

[0037] The method for determining transmission delay includes: determining the transmission path for a data packet to access each memory node based on a deterministic routing algorithm; and determining the transmission delay of the data packet based on the corresponding transmission path of each memory node.

[0038] The method for determining the total delay includes: setting the transmission delay corresponding to the memory node with the longest transmission path as the total delay.

[0039] According to an embodiment of the present disclosure, a deterministic routing algorithm is used to define a transmission path in the on-chip network when a data packet accesses each memory node.

[0040] In the embodiment of the present disclosure, the 2D XY dimensional order routing algorithm is used as an example to determine the transmission path. The 2D XY dimensional order routing algorithm is a simple deterministic routing algorithm that determines the path based on the addresses of the source node and the target node. It is a static deterministic routing algorithm. Figure 3 As shown in the figure, in a 4×4 mesh network, a data packet must travel from the memory node connected to the memory interface in the lower right corner to the memory node marked with an asterisk in the upper left corner. It must first be transmitted along the X direction. When the data packet reaches the same column as the asterisked memory node, it is then transmitted along the Y direction until it reaches the asterisked memory node. When the asterisked memory node responds to the data packet, it is then transmitted from the asterisked memory node along the X direction to the memory node in the same column as the memory interface, and then transmitted along the Y direction again.

[0041] It can be understood that the deterministic routing algorithm includes but is not limited to the 2D XY dimensional order routing algorithm mentioned in the embodiments of the present disclosure.

[0042] According to the embodiment of the present disclosure, after the data packet transmission path is determined, in the absence of congestion, the data packet is transmitted from the memory interface to each memory node. The delay consumed by each memory node in responding and then returning the data packet is determined, that is, the data packet transmission delay is fixed.

[0043] According to an embodiment of the present disclosure, the total delay is set according to the additional delay corresponding to the memory node farthest from the memory interface, that is, the total delay is set according to the additional delay corresponding to the memory node with the longest transmission path.

[0044] like Figure 3 As shown in the figure, in a 4×4 mesh network, a 2D XY-order routing algorithm is used to determine the transmission path. The memory node with the longest transmission path is the memory node with an asterisk in the upper left corner. Assuming that it takes 1ms for a data packet to travel from one memory node to another during transmission, the transmission delay of the memory node in the upper left corner is 12ms, resulting in a total delay of 12ms.

[0045] Step S122 : determining the additional delay of each memory node based on the difference between the total delay and the transmission delay corresponding to each memory node.

[0046] According to the embodiment of the present disclosure, the total delay includes the additional delay and the transmission delay. After obtaining the transmission delay corresponding to each memory node and taking the transmission delay corresponding to the memory node with the longest transmission path as the total delay, the additional delay of each node can be calculated by subtraction.

[0047] According to an embodiment of the present disclosure, a 2D XY dimensional order routing algorithm is used to determine the transmission path in a 4×4 Mesh network, and the memory node with the longest transmission path is the memory node in the upper left corner. Assuming that during the transmission process, it takes 1ms for a data packet to be transmitted from one memory node to another memory node, then the transmission delay of the memory node in the upper left corner is 12ms, and the total delay is 12ms. The transmission delay of the memory node connected to the memory interface in the lower right corner is 0ms, and the additional delay is 12ms. The transmission delay of the memory node in the lower left corner is 6ms, so its additional delay is 6ms. The remaining memory nodes can be calculated in sequence. The final distribution diagram of the additional delay is as follows Figure 4 shown.

[0048] Step S123: Add a delay to set the timing length of each timer.

[0049] The present invention solves the problem of inconsistent memory access in current on-chip networks by adding additional delays to memory nodes, making the on-chip network compatible with existing dynamic random access memory protocols and standards and able to be integrated into the existing computer system ecosystem. The core idea of this method is to use a deterministic routing algorithm to determine the transmission path, and by determining the transmission path, the characteristics of the transmission delay can be determined. Before different memory nodes send back data packets, a timer is started to add additional delays so that the total transmission delay of all data packets within the on-chip network is equal. It has the characteristics of simple implementation and strong practicality.

[0050] The benefits of the disclosed method for configuring the network on a chip are further illustrated by using the disclosed network on a chip. The usage steps include S510 to S550.

[0051] In step S510 , the memory controller sends a data packet containing a command to the memory node to be accessed through the memory interface.

[0052] Data packets carrying commands are transmitted along a path selected by a deterministic routing algorithm in the on-chip network. Taking the XY-dimensional routing algorithm as an example, the command packet will first be transmitted in the X direction until it matches the X dimension of the memory node to be accessed, and then transmitted in the Y direction until it reaches the memory node to be accessed.

[0053] Step S520: The memory node responds to the data packet carrying the command and executes the command.

[0054] Commands can include operations such as reading and writing to memory nodes.

[0055] Step S530: When the storage node needs to return a data packet, a timer is started.

[0056] In step S540 , when the timer reaches the additional delay value, the memory node interface transmits the returned data packet back to the memory interface.

[0057] When data packets access memory nodes within the on-chip network, it can be seen that for memory nodes closer to the memory interface, the data packet transmission path is shorter, resulting in shorter transmission delays. However, memory nodes farther from the memory interface experience longer data packet transmission delays due to their greater distance from the chip port. To address the issue of uneven return data packet delays, a timer inserts a corresponding delay when each memory node sends a return data packet. Memory nodes with shorter transmission distances insert more additional delays, while memory nodes with longer transmission distances insert less additional delays. This ensures that the total delay for data packets accessing memory nodes within the on-chip network is equal to the transmission delay plus the additional delay, and the total delay is equal for all memory nodes.

[0058] In step S550 , the memory interface returns the data to the memory controller.

[0059] On the other hand, the present disclosure further discloses an on-chip network applicable to the above method, including: the on-chip network includes multiple memory nodes and memory interfaces, and a timer is also provided on the interface of each memory node.

[0060] According to an embodiment of the present disclosure, a network on chip (NOC) includes multiple memory nodes, each of which is interconnected to form a NOC structure, wherein the memory nodes are dynamic random access memory (DRAM) nodes.

[0061] According to an embodiment of the present disclosure, a network on chip (NOC) includes a memory interface, which is provided on any memory node. The memory interface is used to parse command data from a memory controller, generate data packets and the addresses of the memory nodes to be accessed by the data packets, and receive returned data packets.

[0062] According to an embodiment of the present disclosure, the on-chip network includes multiple timers, which are respectively set at the interfaces of each memory node and correspond one-to-one to each memory node. They are used to insert additional delays when the memory nodes respond to data packets, so that the total delay of the data packet accessing any memory node in the on-chip network is a fixed value.

[0063] According to an embodiment of the present disclosure, the network on chip further includes: a timer time setting unit, configured to calculate the additional delay of each memory node and set the timing length of each timer.

[0064] Those skilled in the art will appreciate that the features described in the various embodiments and / or claims of this disclosure may be combined and / or coupled in various ways, even if such combinations and / or couplings are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure may be combined and / or coupled in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or couplings are intended to fall within the scope of this disclosure.

[0065] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be used in combination to advantage. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A method for setting up a network on a chip, characterized in that: include: Constructing a network on chip, the network on chip comprising a plurality of memory nodes and a memory interface, each of the memory nodes being provided with a timer; Setting the timing length of each timer so that the total delay of a data packet accessing any memory node in the on-chip network is a fixed value, The total delay includes transmission delay and additional delay. The transmission delay includes the time consumed when the data packet travels from the memory interface to the memory node and the time consumed when the data packet returns from the memory node to the memory interface. The additional delay is the time when the data packet is inserted by the timer on the memory node.

2. The method for setting up a network on chip according to claim 1, wherein: The step of setting the timing length of each timer includes: Determining the transmission delay corresponding to each of the memory nodes, and determining the total delay; Calculating an additional delay of each of the memory nodes based on a difference between the total delay and the transmission delay corresponding to each of the memory nodes; The additional delay of each of the memory nodes sets the timing length of each of the timers.

3. The method for setting up a network on chip according to claim 2, wherein: The determining the transmission delay corresponding to each of the memory nodes includes: Determining, based on a deterministic routing algorithm, a transmission path for the data packet to access each of the memory nodes; The transmission delay of the data packet is determined based on the transmission paths corresponding to the respective memory nodes.

4. The method for setting up a network on chip according to claim 3, wherein: The determining the total delay comprises: The transmission delay corresponding to the memory node with the longest transmission path is set as the total delay.

5. The method for setting up a network on chip according to claim 1, wherein: The construction of the on-chip network includes: interconnecting the memory nodes to form an on-chip network structure; Setting the memory interface on any one of the memory nodes; A timer is set at the interface of each of the memory nodes.

6. A network on chip, applicable to the method according to any one of claims 1 to 5, characterized in that: include: A plurality of memory nodes, each of the memory nodes being interconnected to form an on-chip network structure; A memory interface, provided on any one of the memory nodes; Multiple timers are respectively set at the interface of each memory node, corresponding one-to-one to each memory node, and are used to insert additional delays when the memory node responds to the data packet so that the total delay of the data packet accessing any memory node in the on-chip network is a fixed value.

7. The network on chip according to claim 6, characterized in that Also includes: The timer time setting unit is used to calculate the additional delay of each of the memory nodes to set the timing length of each of the timers.

8. The network on chip according to claim 6, wherein: The memory node is a dynamic random access memory node.

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