A Modeling Method for a Field-Effect Transistor
By constructing a field effect transistor model containing NQS subcircuit and thermal subcircuit, the shortcomings of the existing models in simulating the NQS effect and thermal diffusion of high-frequency field effect transistors are solved, and high-precision simulation in the wide band is achieved.
Patent Information
- Application Number
- CN202011115348.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-10-19
- Publication Date
- 2025-07-01
- Estimated Expiration
- 2040-10-19
AI Technical Summary
The existing field effect transistor models have shortcomings in simulating the NQS effect of high-frequency field effect transistors, which cannot maintain high accuracy in the wide band, and the thermal modeling is not reasonable enough.
A new field effect transistor modeling method is proposed. By constructing a small signal eigenpartial equivalent circuit and a large signal model, NQS sub-circuit and thermal sub-circuit are introduced to ensure the unity and accuracy of the model under small signals and large signals.
This method can maintain high accuracy in a wide band, accurately simulate the NQS effect and thermal diffusion process, improve the robustness and accuracy of the model, and reduce the dependence on high-order sources.
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Figure CN114386347B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to a field effect transistor (FET), and more particularly to a modeling method for a field effect transistor, belonging to the field of integrated circuit design. Background Art
[0002] In the 21st century, the information industry has developed rapidly. In just 20 years, the communication standard has spanned from 2G to 3G, 4G, and now 5G. High capacity and low latency are the cores of 5G communication, and high-frequency high-power amplifiers are one of the keys to achieving these two goals. As is well known, the distributed effects existing in high-frequency chips and the electromagnetic and thermal effects introduced by packaging make chip design and debugging extremely complex. Therefore, the design process based on EDA (Electronic Design Automation) is extremely crucial, and an accurate radio frequency nonlinear model of a transistor is the most complex and important link in this process.
[0003] There are several types of radio frequency transistor models: physical models, physically intensive models, empirical models, look-up table models, neural network models, and behavioral models. Among them, look-up table and neural network models have been widely used in the industry due to their generalization ability for processes. For example, Keysight has developed Root Model, NeuroFET, DynaFET, etc. The Root Model was first developed by David Root, an expert from Keysight. This framework separates DC (static) current and high-frequency current, and the weights of the two are allocated by a frequency selection factor. This modeling method is simple and easy to automate. However, this method does not have a physical interpretation for the modeling of heat and cannot simulate the transient diffusion process of heat. More importantly, the Root Model does not have a corresponding modeling solution for the NQS effect (non-quasi-static effect, that is, the control of the gate voltage on the channel current has a time delay) of high-frequency field effect transistors, resulting in the model's accuracy not meeting the requirements of chip designers in some scenarios. NeuroFET only replaces the mapping relationship between current, charge, and port voltage stored in the look-up table with a neural network in form, so NeuroFET also has the above-mentioned disadvantages of the Root Model. DynaFET has improved the description of the thermal physical process and uses a large amount of time-domain nonlinear data to train model parameters, but the model architecture still does not consider the NQS effect.
[0004] The aforementioned existing models can be classified as technology-independent models. Although the models have been iteratively upgraded and the descriptions of heat and charge traps, etc. are more scientific and accurate, there has never been a good solution for the modeling of NQS. Some literatures use high-order current sources and charge sources to describe the NQS phenomenon, but in actual operation, some problems will be encountered, such as the non-conservation of high-order current and charge sources and incomplete test data. Therefore, this solution has not been widely promoted in the actual commercial environment. Summary of the Invention
[0005] The main purpose of this application is to provide a modeling method for field effect transistors to overcome the deficiencies in the prior art.
[0006] To achieve the above-mentioned invention purpose, this application provides the following technical solutions:
[0007] An embodiment of this application provides a modeling method for field effect transistors, which includes:
[0008] Construct an equivalent circuit for the small-signal intrinsic part of the field effect transistor. The Y parameters of this small-signal intrinsic part equivalent circuit are:
[0009]
[0010] Where Y int is the intrinsic Y parameter, is each element of the two-port Y matrix, i, j = 1 or 2, y g11 is the real part of y g12 is the real part of g m is the transconductance, gds is the output admittance, ω is the angular frequency, C gs is the gate-source capacitance, C gd is the gate-drain capacitance, C ds is the drain-source capacitance;
[0011] Calculate C gs 、C gd 、C ds and the cross capacitance C m 、transconductance g m 、output admittance g ds 、NQS time delay v caused by the NQS effect, where:
[0012]
[0013] Construct a large-signal model of the field effect transistor. This large-signal model includes a gate charge source Q g 、drain charge source Qd 、Gate current source I g 、Drain current source I d and the NQS sub - circuit, where the NQS sub - circuit corresponds to the gate voltage delay circuit and obtains the relationship between the non - linear current source, charge source and port voltage by performing path integration on the port voltage, that is:
[0014]
[0015]
[0016] Among them, V gs 、V ds are the gate - source voltage and source - drain voltage respectively.
[0017] In some embodiments, the NQS sub - circuit is expressed as:
[0018] V gs-delay = V gs × exp(-jwτ).
[0019] In some embodiments, the large - signal model of the field - effect transistor further includes a thermal sub - circuit, and the thermal sub - circuit corresponds to an R - C parallel circuit for simulating thermal diffusion, and it can be expressed as:
[0020] T j = T amb + R th ·P diss .
[0021] Among them, T j is the channel temperature, T amb is the ambient temperature, R th is the thermal resistance, and P diss is the average power of the channel.
[0022] In some embodiments, the modeling method further includes: changing the ambient temperature and introducing a temperature factor α 1d , and obtaining the relationship between the current source, charge source and temperature as:
[0023] Q g (T j ) = (1 - α Id (T j - T0))·Q g (T0)
[0024] Q d (T j ) = (1 - α Id (T j - T0))·Q d (T0)
[0025] I g (T j ) = (1 - αI g (T j - T0))·I g (T0)
[0026] I g (T j ) = (1 - α Id (T j - T0))·I d (T0)
[0027] where T0 is the initial ambient temperature, and T j is the channel temperature of the device. In some embodiments, due to the use of pulse testing, the self-heating effect of the device can be ignored. Therefore, the ambient temperature is consistent with the channel temperature, that is, the channel temperature can be controlled by changing the ambient temperature.
[0028] In some embodiments, the modeling method further includes: after integrating to obtain the relationship between the nonlinear current source, charge source and port voltage, storing it in the form of a look-up table.
[0029] In some embodiments, the modeling method further includes: after integrating to obtain the relationship between the nonlinear current source, charge source and port voltage, training with a neural network to obtain a neural network analysis model.
[0030] In some embodiments, the small-signal performance of the large-signal model of the field-effect transistor is determined by Equation (III):
[0031]
[0032] Equation (III) is obtained by differentiating V gs_delay on both sides of Equation (II).
[0033] In some embodiments, the field-effect transistor includes MOSFET, LDMOS, VDMOS, MESFET, or HEMT, etc., and is not limited thereto.
[0034] Compared with the prior art, the technical solutions provided by the embodiments of the present application have at least the following advantages:
[0035] (1) A new FET model framework is proposed. During the integration process of the current source and the charge source, all NQS effects are eliminated. The NQS effects are simulated by the delay sub-circuit of the gate. This modeling method is consistent with the physical mechanism of NQS and ensures the unity of the small-signal model and the large-signal model. Thus, the accuracy of the model is not affected by the frequency band, and there is no need to use high-order sources. In terms of the robustness, accuracy, and the difficulty of model extraction of the model, it is significantly superior to the existing model frameworks;
[0036] (2) The model generation is fully automated. The model is based on two-dimensional current and charge, and has good simulation convergence. Information of all bias points of the device is recorded in the model, which can well reflect the non-linear performance of the device;
[0037] (3) The model extraction is fully automated. The model is accurate and can save a great deal of manpower and material resources;
[0038] (4) Based on the characteristics of the model constructed in the embodiments of the present application, a radio frequency large-signal model obtained from Tcad process simulation can be obtained on a large scale. It can be used both for evaluating the process and for chip design, and is expected to realize the coordinated development of the process and the design, greatly accelerating the optimization of the process and the process from process to chip design and manufacturing, and reducing the number of chip tape-outs. Brief Description of the Drawings
[0039] Figure 1 Schematic diagram of the small-signal intrinsic part equivalent circuit of a FET in an embodiment of the present application;
[0040] Figure 2-1 Topological diagram of a large-signal model of a FET in an embodiment of the present application;
[0041] Figure 2-2 Schematic diagram of the NQS sub-circuit of a large-signal model of a FET in an embodiment of the present application;
[0042] Figure 2-3 Schematic diagram of the thermal sub-circuit of a large-signal model of a FET in an embodiment of the present application;
[0043] Figure 3 Comparison diagram of the pulsed channel current (circles) obtained by testing and the pulsed channel current (lines) simulated by the model in an embodiment of the present application;
[0044] Figure 4 Relationship diagram of the gate charge obtained by integration and the gate-source voltage in an embodiment of the present application;
[0045] Figure 5 Relationship diagram of the gate charge obtained by integration and the drain-source voltage in an embodiment of the present application;
[0046] Figure 6It is a diagram showing the relationship between the drain charge obtained by integration and the gate-source voltage in an embodiment of the present application;
[0047] Figure 7 It is a diagram showing the relationship between the drain charge obtained by integration and the drain-source voltage in an embodiment of the present application;
[0048] Figure 8 It is a comparison diagram of the gate-source capacitance (line) simulated by the large-signal model and the gate-source capacitance (circle) extracted by testing in an embodiment of the present application;
[0049] Figure 9 It is a comparison diagram of the gate-drain capacitance (line) simulated by the large-signal model and the gate-drain capacitance (circle) extracted by testing in an embodiment of the present application;
[0050] Figure 10 It is a comparison diagram of the drain-source capacitance (line) simulated by the large-signal model and the drain-source capacitance (circle) extracted by testing in an embodiment of the present application;
[0051] Figure 11 It is a comparison diagram of the transcapacitance (line) simulated by the large-signal model and the transcapacitance (circle) extracted by testing in an embodiment of the present application. Detailed implementation manners
[0052] As mentioned above, some existing FET models, such as the Root Model, NeuroFET, etc. developed by Keysight, have covered the first-generation semiconductors to the third-generation semiconductors, such as MOSFET, LDMOS, GaAS pHEMT, and GaN HEMT. These model architectures have nothing to do with the physics of the device. Only by testing the standard S-parameters (scattering parameters), pulse or static I-V curves, the model can be automatically generated without manual intervention. However, their biggest defect is that there is no good modeling solution for NQS. The models proposed by NXP and others use high-order current sources and voltage sources, and can only simulate the NQS effect in a narrow band. Moreover, the charge conservation and simulation convergence of the high-order sources will also be major challenges.
[0053] In view of these deficiencies in the prior art, the inventors of the present application have conducted in-depth analysis on the NQS phenomenon of FETs, and given a set of solutions from the physical mechanism level. Moreover, this solution can be easily integrated into existing models such as RootModel, NeuroFET, DynaFET, etc., which is a breakthrough progress for model theories and methods. The technical solutions of the present application will be described in detail below with reference to the accompanying drawings and embodiments. However, the following embodiments are only explanations of the present application, and they do not limit the present application. Those skilled in the art can make non-creative modifications to the embodiments according to needs after reading this specification, but as long as they are within the scope of the claims of the present application, they are protected by the patent law.
[0054] Please refer to Figure 1 , first construct the small-signal intrinsic part equivalent circuit of the field-effect transistor (FET) (hereinafter referred to as the "small-signal circuit" or "small-signal equivalent circuit"), and its Y-parameters are
[0055]
[0056] where Y int is the intrinsic Y-parameter, is each element of the two-port Y-matrix, y g11 is the real part of y g12 is the real part of g m is the transconductance, gds is the output admittance, ω is the angular frequency, C gs is the gate-source capacitance, C gd is the gate-drain capacitance, C ds is the drain-source capacitance.
[0057] The terms related to the current source in this small-signal equivalent circuit are g m and gds . The NQS effect brings a time delay τ to the voltage control of the gate, and the frequency response of the time delay will reduce the transconductance g m , generating an additional transcapacitance
[0058] g m ·e -jωτ = g m ·cos(ωτ) - j·g m ·sin(ωτ) (2) Taylor expansion of the above formula can obtain
[0059]
[0060] The real part in formula (3) represents the transconductance decreasing with frequency, and the imaginary part represents the transcapacitance C m (commonly used definition in the industry)
[0061] C m = -g m ·sin(ωτ) ≈ -g m ·τ (4)
[0062] In the industry, the Taylor series is conventionally used to construct high-order current sources and charge sources for modeling the NQS effect. However, the Taylor series can only be approximated within a narrow band. For accurate modeling at high frequencies, high-order series approximation is required, which easily leads to non-physical simulation phenomena, and the charge conservation of high-order sources is relatively poor. Looking back at the LDMOS model article published by NXP in 2018, the above method was also used to model the NQS effect. So far, there has been no breakthrough in the NQS modeling theory and method in the industry.
[0063] The embodiment of this application proposes a new model framework (abbreviated as HTFET, also known as the large-signal model or large-signal model circuit, etc.), which elegantly solves the NQS problem. As Figure 2-1 shown, the HTFET model consists of two current sources and two charge sources. Qg is the gate charge source, Qd is the drain charge source, Ig is the gate current source, and Id is the drain current source (I d = Id(V gs_delay , V ds , T j ), V gs-delay = V gs × exp(-jwτ)). Refer to Figure 2-2 、 Figure 2-3 , the HTFET model also includes an NQS sub-circuit (V gs-delay = V gs × exp(-jwτ)) and a thermal sub-circuit (T j = T amb + R th · P diss ), corresponding to the gate voltage delay circuit (voltage-controlled voltage source) and the R-C parallel circuit for simulating heat diffusion respectively.
[0064] In the solution of the embodiment of this application, first, the relationships between parameters such as the intrinsic capacitance and transconductance and the intrinsic Y-parameter Y int are constructed. From Equation (1), it is easy to obtain that the gate-drain capacitance C gd is
[0065]
[0066] The gate-source capacitance C gs is
[0067]
[0068] The drain-source capacitance C ds is
[0069]
[0070] The cross-capacitance C m caused by NQS is
[0071]
[0072] Transconductance g m is
[0073]
[0074] The output admittance is
[0075]
[0076] The NQS time delay τ is
[0077]
[0078] Once the relationship between the internal intrinsic parameters and the external bias is obtained, the nonlinear current source and charge source can be obtained by performing a path integral on the port voltage, that is:
[0079]
[0080]
[0081] To better understand the difference between the above integral formulas of the current source and charge and the commercial model Root Model, the current and charge integral formulas of the Root Model are given here. Since the difference lies only in the drain current and drain charge, only these two sources are listed here:
[0082]
[0083] Carefully observing the differences between Equations (13), (15) and Equations (16), (17), it is obvious that in the Root model, the transcapacitance C m is put into the integral term of Q d , and g m cosωτ is put into the integral term of I d . However, since C m and g m cosωτ vary greatly with frequency, the model accuracy cannot cover a wide frequency band. The integration method proposed in the embodiments of the present application takes the NQS effect into account in the control of the current source gate, and the NQS-related C m and cosωτ are removed from the integral term. Finally, V gs_delay is used to replace V gs , and the NQS sub-circuit shown in Figure 2-2 is combined to complete the modeling of NQS.
[0084] Based on the physical mechanism of the NQS effect, the embodiments of the present application creatively introduce an NQS sub-circuit into the Root model. This method not only has high accuracy but also has no bandwidth limitation.
[0085] Differentiating both sides of the equation in Equation (15) with respect to V gs_delay yields
[0086]
[0087] In fact, for a large-signal circuit ( Figure 2-1 ), the simulated voltage is externally excited. Therefore, from the perspective of the external port, the small-signal behavior of the current source is determined by Equation (19)
[0088]
[0089] Equation (19) theoretically derives the small-signal behavior of the large-signal model framework proposed in the embodiments of the present application. Obviously, Equation (19) is consistent with Equations (2)-(4), that is, all the effects of the NQS effect on transconductance and transcapacitance have been accurately modeled.
[0090] Among them, for the thermal modeling of the model, various solutions known in the industry can be adopted, so it will not be elaborated in this specification.
[0091] The present application proposes a new FET model framework. During the integration process of the current source and the charge source, all NQS effects are eliminated, as shown in Equations (13) and (15). The effect of NQS is simulated by the delay sub-circuit of the gate, as Figure 2-2 shown. This modeling method is consistent with the physical mechanism of NQS, and ensures the unity of the small-signal model and the large-signal model. Thus, the accuracy of the model is not affected by the frequency band, and there is no need to use high-order sources. In terms of the robustness, accuracy of the model, and the difficulty of model extraction, the solution of the embodiments of the present application is significantly superior to the existing Root Model framework, etc.
[0092] Compared with other empirical models (such as MET LDMOS, etc.), the modeling method provided by the embodiments of the present application has the following advantages: fully automated model generation, the model is based on two-dimensional current and charge, good simulation convergence, information of all bias points of the device is recorded in the model, and it can well reflect the non-linear performance of the device.
[0093] Compared with the physical intensive model ASM (such as the gallium nitride physical model, etc.), the modeling method provided by the embodiments of the present application has the following advantages: fully automated model extraction, accurate model, which can save a lot of manpower and material resources of the company, and is very attractive to small and medium-sized chip companies.
[0094] Based on the modeling method provided by the embodiments of the present application, a radio frequency large-signal model can be obtained on a large scale from Tcad process simulation. This model can be used not only to evaluate the process but also for chip design, promising the coordinated development of the process and design, greatly accelerating the process optimization and the process from process to chip design and manufacturing. As radio frequency and millimeter-wave chips evolve towards higher frequencies, higher powers, and higher integration, the chip design process increasingly relies on EDA. The accurate model provided by the embodiments of the present application can reduce the number of chip tape-outs, thereby accelerating the product release time, seizing strategic opportunities, and greatly saving manpower and material resources, bringing huge benefits to society.
[0095] The following uses a specific LDMOS modeling case to illustrate the implementation process and implementation effect of the FET modeling method.
[0096] The following content is the detailed operation steps:
[0097] 1. Test the S-parameters of the LDMOS FET device with multiple biases at different temperatures, including the zero-bias (coldfet) S-parameters and the S-parameters at all other bias points (hotfet). The bias voltage can be static or use a narrow pulse to prevent self-heating;
[0098] 2. Test the S-parameters of the calibration components (Open-Short);
[0099] 3. Test the pulsed I-V curves (current and voltage curves) and static I-V curves at different temperatures;
[0100] 4. Use the S-parameters of the test calibration components to de-embed the GSG PAD (probe contact PAD) and internal connections of the LDMOS FET. Since the Open-Shrot de-embedding method is well-known in the industry, it will not be elaborated here;
[0101] 5. Use the coldfet parameter extraction technology to obtain the parasitic parameters of the LDMOS FET, such as Lg (gate inductance), Ld (drain inductance), Ls (source inductance), Rg (gate resistance), Rd (drain resistance), Rs (source resistance), etc.;
[0102] 6. De-embed the extracted parasitic parameters from the S-parameters at all biases to obtain the intrinsic part of the Y-parameter Y int ;
[0103] 7. According to Figure 1 the small-signal equivalent circuit topology shown, analyze and obtain the following key equivalent circuit parameters, including:
[0104] The gate-drain capacitance C gd is
[0105]
[0106] Gate-source capacitance C gs is
[0107]
[0108] Drain-source capacitance C ds is
[0109]
[0110] Cross capacitance C caused by NQS m is
[0111]
[0112] Transconductance g m is
[0113]
[0114] Output admittance is
[0115]
[0116] The NQS time delay τ is
[0117]
[0118] The average value of the frequencies of the above key parameters is taken to obtain the optimal value under the final broadband;
[0119] 8. Select the time delay constant τ extracted from the bias point of the class AB amplifier as Figure 2-2 the time delay setting of the NQS sub-circuit in;
[0120] 9. Perform path integration on the small-signal equivalent circuit parameters under all biases to obtain non-linear current sources and charge sources, as shown in Eqs. (31)-(34):
[0121]
[0122] In actual operation, the I-V curve of the pulse test can be used to replace the current source obtained by integrating Eq. (34);
[0123] 10. Change the ambient temperature, repeat the operation steps 2 - step 9, introduce the temperature factor, and the relationship between current and charge with temperature can be obtained
[0124] Q g (T j ) = (1 - α Id (T j - T0))·Q g (T0) (35)
[0125] Q d (T j )=(1-α Id (T j -T0))·Q d (T0) ((36)
[0126] I g (T j )=(1-α Id (T j -T0))·I g (T0) (37)
[0127] I d (T j )=(1-α Id (T j -T0))·I d (T0) ((38)
[0128] Regarding temperature modeling, it is known in the industry that there are many ways. This embodiment only lists one of them to illustrate the modeling process, and the specific details are not expanded here.
[0129] 11. After integrating the relationship between the nonlinear current source and charge source and the port voltage, it can be stored in a lookup table or trained using a neural network to obtain a neural network analytical model. Both methods can be used in an EDA simulation environment and will not be described in detail here.
[0130] In this embodiment, the model finally uses a lookup table to store the relationship between the nonlinear current source and the charge source and the port voltage, and the model is implemented in ADS (Advanced Design System).
[0131] in, Figure 3 The figure shows the comparison between the pulse channel current of the test (circle) and the model simulation (line). Since the test data is written into the model faithfully, the channel current of the test and the simulation basically coincide.
[0132] in, Figure 4 , Figure 5 is the gate-source charge obtained by integrating equation (31), Figure 6 , Figure 7 is the drain-source charge obtained by integrating equation (32). Obviously, the charge is two-dimensional, and this method can maximize the retention of device information at all bias points, and the charge conservation can also be satisfied, so the convergence of the model simulation can also be guaranteed.
[0133] in, Figure 8 Comparison of gate-source capacitance Cgs extracted from large signal model simulation and test. Figure 9Comparison of the gate-drain capacitance Cgd extracted for large-signal model simulation and testing Figure 10 Comparison of the gate-drain capacitance Cgd extracted for large-signal model simulation and testing. It can be seen that the non-linear capacitance from the large-signal model simulation is very close to the test result, indicating the accuracy of the model constructed in this embodiment. It is worth mentioning that Figure 10 is the comparison of the transcapacitance Cm between simulation and testing. This capacitance is caused by NQS Figure 10 reflecting that this embodiment accurately models the NQS effect.
[0134] The above are only the preferred embodiments of the present application, and the protection scope of the present application is not limited to the above embodiments. All technical solutions falling within the idea of the present application belong to the protection scope of the present application. It should be noted that for those of ordinary skill in the art, several improvements and refinements made without departing from the principle of the present application should also be regarded as within the protection scope of the present application.
Claims
1. A modeling method for a field effect transistor, characterized in that Including: Constructing a small-signal intrinsic part equivalent circuit of a field-effect transistor, and the Y parameters of the small-signal intrinsic part equivalent circuit are: where Y int is the intrinsic Y parameter, is each element of the two-port Y matrix, i, j = 1 or 2, y g11 is the real part of, y g12 is the real part of, g m is the transconductance, g ds is the output admittance, ω is the angular frequency, C gs is the gate-source capacitance, C gd is the gate-drain capacitance, C ds is the drain-source capacitance; C is calculated by formula (I) gs C gd C ds and the cross capacitance C m the transconductance g m the output admittance g ds and the NQS time delay τ, where: Construct a large-signal model of a field-effect transistor, the large-signal model including a gate charge source Q g , a drain charge source Q d , a gate current source I g , a drain current source I d and an NQS sub-circuit, the NQS sub-circuit corresponding to a gate voltage delay circuit, and obtaining the relationship between a non-linear current source, a charge source and a port voltage by performing a path integral on the port voltage, that is: Among them, V gs and V ds are the gate-source voltage and the source-drain voltage respectively.
2. The modeling method according to claim 1, wherein The NQS sub-circuit is expressed as: V gs-delay = V gs × exp(-jwτ).
3. The modeling method according to claim 1, wherein The large-signal model of the field-effect transistor further includes a thermal sub-circuit, and the thermal sub-circuit corresponds to an R-C parallel circuit for simulating thermal diffusion.
4. The modeling method according to claim 3, wherein Including: Change the environmental temperature and introduce the temperature factor α 1d , and the relationships between the current source, charge source and temperature are obtained as follows: Q g (T j )=(1-α Id (T j -T0))·Q g (T0) Q d (T j ) = (1 - α Id (T j - T0)) · Q d (T0) I g (T j )=(1-α Id (T j -T0))·I g (T0) I d (T j )=(1-α Id (T j -T0))·I d (T0) where, T0 is the initial ambient temperature, and T j is the device channel temperature.
5. The modeling method according to claim 1, characterized in that Further including: after integrating to obtain the relationship between the non-linear current source, charge source and port voltage, storing it in the form of a look-up table.
6. The modeling method according to claim 1, wherein Further including: after integrating to obtain the relationship between the non-linear current source, charge source and port voltage, training with a neural network to obtain a neural network analysis model.
7. The modeling method according to claim 1, characterized in that The small-signal performance of the large-signal model of the field-effect transistor is determined by Equation (III): Formula (III) is obtained by differentiating V on both sides of the equation of Formula (II). gs_delay This is achieved by differentiation.
8. The modeling method according to claim 1, wherein The field-effect transistor includes MOSFET, LDMOS, VDMOS, MESFET or HEMT.