Chip design wiring method and device, equipment, storage medium

Abstract

The embodiments of the present application disclose a wiring method and apparatus, a device, and a storage medium for chip design; wherein the method comprises: performing wiring on a wiring layer according to wiring information required for wiring in chip design to obtain an initial line segment; judging whether the wiring spacing requirement of the wiring layer is satisfied between the initial line segment and a neighboring line segment to obtain a judgment result; and automatically processing the initial line segment according to the judgment result until a target line segment that satisfies the wiring spacing requirement is obtained.

Description

Technical Field

[0001] The embodiments of the present application relate to chip design technology, and relate to but are not limited to wiring methods and devices, equipment, and storage media for chip design. Background Art

[0002] There are always some important clock signals in the chip design process. Non-default routing rules (NDR) need to be set in the chip back-end design to increase the wiring width and wiring spacing to ensure stable signal transmission and reduce wiring delay, thereby improving chip performance. However, these important signal lines used to need to be designed manually by engineers. In recent years, electronic design automation (EDA) tools have also begun to intervene to solve this problem.

[0003] Manual wiring by engineers has the disadvantage of being too time-consuming. Although the quality of manual wiring by engineers is guaranteed, it takes a long time, especially when the number of NDR wiring is hundreds or thousands. This may lead to problems such as long design time and chip tape-out delays in the extremely competitive chip design field, which is difficult to accept.

[0004] Although the existing EDA tool wiring solutions have solved the problem that engineers need a long time to manually wire, these tools deal with NDR wiring, which is very different from the previous normal wiring design solutions. As a result, the metal wire segments customized by the tools may not meet the chip design requirements. In this way, engineers need to manually correct these wire segments later, which leads to a long chip design cycle. Summary of the invention

[0005] In view of this, the wiring method, device, equipment, and storage medium for chip design provided in the embodiments of the present application can automatically obtain target line segments without design rule check (DRC) violations, that is, obtain target line segments that meet the wiring spacing requirements, thereby eliminating the need for later manual corrections and thus shortening the chip design cycle. The wiring method, device, equipment, and storage medium for chip design provided in the embodiments of the present application are implemented as follows:

[0006] The wiring method for chip design provided in an embodiment of the present application includes: performing wiring on a wiring layer according to wiring information required for wiring in the chip design to obtain an initial line segment; judging whether the initial line segment and a neighboring line segment meet the wiring spacing requirement of the wiring layer to obtain a judgment result; and automatically processing the initial line segment according to the judgment result until a target line segment that meets the wiring spacing requirement is obtained.

[0007] A wiring device for chip design provided in an embodiment of the present application includes: a wiring module, which is used to perform wiring on a wiring layer according to the connection information required for wiring in the chip design, and obtain an initial line segment; a judgment module, which is used to judge whether the wiring spacing requirement of the wiring layer is met between the initial line segment and the neighboring line segment, and obtain a judgment result; and a processing module, which is used to automatically process the initial line segment according to the judgment result until a target line segment that meets the wiring spacing requirement is obtained.

[0008] An electronic device provided in an embodiment of the present application includes a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and when the processor executes the program, the wiring method of the chip design described in the embodiment of the present application is implemented.

[0009] An embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the wiring method of the chip design described in the embodiment of the present application is implemented.

[0010] In an embodiment of the present application, a wiring method for chip design is provided. According to the wiring information required for the chip design, wiring is performed on the wiring layer. After the initial line segment is obtained, instead of continuing to generate the next metal line segment, the method automatically checks whether the spacing between the initial line segment and the neighboring line segment meets the wiring spacing requirement. Then, the initial line segment is automatically processed according to the detection result until a target line segment that meets the wiring spacing requirement is obtained. In other words, the wiring method for chip design can automatically generate a target line segment that meets the wiring spacing requirement. In this way, the introduction of a target line segment that does not meet the wiring spacing requirement is avoided, so that engineers do not need to make manual corrections in the later stage, thereby shortening the chip design cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present application and are used together with the specification to illustrate the technical solution of the present application.

[0012] Figure 1 Provide a schematic diagram of the wiring for each layer of the chip;

[0013] Figure 2 A schematic diagram of the implementation flow of the wiring method for chip design provided in an embodiment of the present application;

[0014] Figure 3 A schematic diagram of the implementation flow of the wiring method for chip design provided in an embodiment of the present application;

[0015] Figure 4 A schematic diagram of determining available wiring layers provided in an embodiment of the present application;

[0016] Figure 5 A schematic diagram of the shape of an initial line segment provided in an embodiment of the present application;

[0017] Figure 6 A schematic diagram of an enclosing area provided in an embodiment of the present application;

[0018] Figure 7 A schematic diagram of a target line segment obtained before updating provided in an embodiment of the present application;

[0019] Figure 8 A schematic diagram of the intersection of line segments provided in an embodiment of the present application;

[0020] Fig. 9 A schematic diagram of the implementation flow of the wiring method for chip design provided in an embodiment of the present application;

[0021] Fig.10 A schematic diagram of a Manhattan line provided in an embodiment of the present application;

[0022] Fig.11 A schematic diagram of the coordinates of the starting point and the end point of the line to be connected provided in an embodiment of the present application;

[0023] Fig.12 A schematic diagram of the preliminary planning shape of the wiring provided in the embodiment of the present application;

[0024] Fig.13 A schematic diagram of a wiring DRC check provided in an embodiment of the present application;

[0025] Fig.14 A schematic diagram of the shape of the metalB line segment provided in an embodiment of the present application;

[0026] Fig.15 A schematic diagram of metalC causing DRC in metalB provided in an embodiment of the present application;

[0027] Fig.16 The new metalB shape provided in the embodiment of the present application solves the DRC problem introduced by metalC and determines the schematic diagram of the metalA shape;

[0028] Fig.17 A schematic diagram of the result of completing the wiring shape generation work provided in an embodiment of the present application;

[0029] Fig.18 A schematic diagram of adding through holes to complete wiring provided in an embodiment of the present application;

[0030] Fig.19 A schematic diagram of the structure of a wiring device designed for a chip according to an embodiment of the present application;

[0031] Fig. 20A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the specific technical solution of the present application will be further described in detail below in conjunction with the drawings in the embodiments of the present application. The following embodiments are used to illustrate the present application, but are not used to limit the scope of the present application.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0034] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0035] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present application are used to distinguish similar or different objects, and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present application described here can be implemented in an order other than that illustrated or described here.

[0036] In chip design, the number of wiring metal layers usually ranges from 4 to 15, but is not limited to this. The wiring direction of the same layer is consistent, and the wiring directions of two adjacent layers are perpendicular. For example, Figure 1 As shown, the wiring direction of the Mn-th layer 102 is longitudinal, and the wiring directions of the adjacent upper and lower layers, namely the Mn-1-th layer 101 and the Mn+1-th layer 103, are transverse. This is the basic rule of wiring in chip design.

[0037] The inventors found in the process of research that although EDA and other tools are used for chip design, the wiring results produced by these tools usually have DRC violation problems. For example, some designed line segments cannot meet the wiring spacing requirements. In this way, engineers still need to manually correct them one by one in the later stage. It can be seen that the problem of long chip design cycle has not been effectively improved.

[0038] In view of this, an embodiment of the present application provides a wiring method for chip design, which can automatically complete the wiring in one go, and there is no DRC violation problem in the wiring result, so that engineers do not need to correct the wiring results in the later stage, thereby effectively improving the problem of long chip design cycle.

[0039] The method can be applied to electronic devices, which can be devices with information processing capabilities such as mobile phones, tablet computers, laptops or desktop computers. The functions implemented by the wiring method of the chip design can be implemented by calling program codes by the processor in the electronic device, and of course the program codes can be stored in a computer storage medium. It can be seen that the electronic device at least includes a processor and a storage medium.

[0040] Figure 2 A schematic diagram of the implementation flow of the wiring method for chip design provided in the embodiment of the present application is shown in FIG. Figure 2 As shown, the method may include the following steps 201 to 203:

[0041] Step 201, performing wiring on a wiring layer according to wiring information required for wiring in chip design to obtain an initial line segment.

[0042] The connection information may include one or more sets of coordinates of the starting point and the end point of the to-be-connected line. In some embodiments, the electronic device may implement step 201 through steps 301 to 303 of the following embodiments.

[0043] Step 202, determining whether the initial line segment and the neighboring line segment meet the wiring spacing requirement of the wiring layer, and obtaining a determination result.

[0044] It can be understood that the neighboring line segment refers to an existing metal line segment that is adjacent to the initial line segment on the same wiring layer, that is, there is no other line segment between the neighboring line segment and the initial line segment.

[0045] Different wiring layers may have the same or different wiring spacing requirements. In some embodiments, the electronic device may obtain the wiring spacing requirement corresponding to the wiring layer by a table lookup method according to the identifier of the wiring layer where the initial line segment is located.

[0046] In some embodiments, if the spacing between the initial line segment and any neighboring line segment does not meet the wiring spacing requirement, the judgment result is that the wiring spacing requirement is not met; if the spacing between the initial line segment and each neighboring line segment meets the wiring spacing requirement, the judgment result is that the wiring spacing requirement is met.

[0047] Step 203: automatically process the initial line segment according to the judgment result until a target line segment that meets the wiring spacing requirement is obtained.

[0048] Different judgment results will result in different ways of automatically processing the initial line segment. For example, when the judgment result is that the wiring spacing requirement is not met, the electronic device can process the initial line segment through steps 306 and 307 of the following embodiment until an initial line segment (i.e., a target line segment) that meets the wiring spacing requirement is obtained. For another example, when the judgment result is that the wiring spacing requirement is met, the electronic device can directly determine the initial line segment as the target line segment. In this way, the electronic device can repeat the above steps 201 to 203 until the wiring requirements required for the chip design are completed, that is, the connection between each set of starting points and end points is completed.

[0049] In an embodiment of the present application, a wiring method for chip design is provided. According to the wiring information required for the chip design, wiring is performed on the wiring layer. After the initial line segment is obtained, instead of continuing to generate the next metal line segment, the method automatically checks whether the spacing between the initial line segment and the neighboring line segment meets the wiring spacing requirement. Then, the initial line segment is automatically processed according to the detection result until a target line segment that meets the wiring spacing requirement is obtained. In other words, the wiring method for chip design can automatically generate a target line segment that meets the wiring spacing requirement. In this way, the introduction of a target line segment that does not meet the wiring spacing requirement is avoided, so that engineers do not need to make manual corrections in the later stage, thereby shortening the chip design cycle.

[0050] The present application embodiment further provides a wiring method for chip design. Figure 3 A schematic diagram of the implementation flow of the wiring method for chip design provided in the embodiment of the present application is shown in FIG. Figure 3 As shown, the method may include the following steps 301 to 314:

[0051] Step 301, obtaining the coordinates of the starting point and the end point of the current line to be connected from the connection information required for wiring in chip design;

[0052] Step 302: Determine available wiring layers according to the coordinates of the starting point and the coordinates of the end point.

[0053] The so-called available wiring layer refers to the wiring layer that can meet the connection requirements between the starting point and the end point. Figure 4As shown, assuming that the coordinates of the starting point are (x1, y1), the coordinates of the end point are (x2, y2), x1<x2, y1<y2, the wiring layer 401 and the wiring layer 402 are adjacent, and the wiring spacing requirement of the two is s. At the starting and ending points, you can either wire horizontally on the wiring layer 401 or vertically on the wiring layer 402. However, if you wire horizontally from the starting point (x1, y1) to (x2, y1), since there is already a metal wire segment 403 between (x1, y1) and (x2, y1), it is obvious that the line segment from (x1, y1) to (x2, y1) cannot be generated, and it is necessary to wire vertically at a distance s from the metal wire segment 403, which will increase the wiring complexity and the number of through holes between the starting point and the end point. If the wiring is longitudinally conducted from the starting point (x1, y1) to (x1, y2), since there is neither an existing metal line segment nor other devices between (x1, y1) and (x1, y2), the wiring layer 402 can be used as an available wiring layer. Of course, this is only an example and should not limit the protection scope of the available wiring layer.

[0054] For example, assuming that the coordinates of the starting point are (x1, y1) and the coordinates of the end point are (x2, y1), then wiring layer 401 can be used as an available wiring layer; similarly, assuming that the coordinates of the starting point are (x1, y1) and the coordinates of the end point are (x1, y2), then wiring layer 402 can be used as an available wiring layer.

[0055] Step 303 , performing routing on the available routing layer according to the coordinates of the starting point, the coordinates of the end point and the routing width requirement of the available routing layer to obtain an initial line segment.

[0056] It can be understood that in the embodiment of the present application, wiring is performed on an available wiring layer, so that the introduction of new wiring problems can be avoided, thereby speeding up the wiring speed and shortening the chip design cycle.

[0057] The line segments of the wiring have a certain width. The wiring width requirements of different wiring layers may be the same or different. In some embodiments, the electronic device can obtain the wiring width requirement of the wiring layer by a table lookup method according to the identification of the available wiring layer.

[0058] In some embodiments, if the available wiring layer is horizontal wiring, the length of the initial line segment may be the distance between the horizontal coordinate of the starting point and the horizontal coordinate of the end point. In other embodiments, if the available wiring layer is vertical wiring, the length of the initial line segment may be the distance between the vertical coordinate of the starting point and the vertical coordinate of the end point. Figure 5As shown, the coordinates of the starting point are (x1, y1), the coordinates of the end point are (x2, y2), x1<x2, y1<y2, and the wiring width requirements of the wiring layer 501 of the horizontal wiring and the wiring layer 502 of the vertical wiring are both w. Then, if Figure 5 As shown, the initial line segment can be either line segment 503 or line segment 504 .

[0059] It can be understood that the length of the initial line segment is designed as the distance between the horizontal coordinate of the starting point and the horizontal coordinate of the end point, or as the distance between the vertical coordinate of the starting point and the vertical coordinate of the end point; this wiring rule is relatively simple and can minimize the number of metal segments used to connect the starting point and the end point, thereby speeding up the wiring speed and shortening the chip design cycle.

[0060] Step 304, determining whether the initial line segment and the neighboring line segment meet the wiring spacing requirement of the available wiring layer; if yes, executing step 305; otherwise, executing step 306;

[0061] In some embodiments, the electronic device may implement step 304 as follows: determine the enclosing area of ​​the initial line segment according to the wiring spacing requirement, and the spacing between each boundary of the enclosing area and the boundary of the corresponding parallel initial line segment all meet the wiring spacing requirement; determine whether there is a neighboring line segment crossing the boundary of the enclosing area, and obtain the determination result. For example, if no neighboring line segment crosses the boundary of the enclosing area, the determination result obtained is that the initial line segment and each neighboring line segment meet the wiring spacing requirement; similarly, if a neighboring line segment crosses the boundary of the enclosing area, the determination result obtained is that the initial line segment and the neighboring line segment do not meet the wiring spacing requirement.

[0062] For example, suppose the wiring spacing requirement is that the spacing between two adjacent line segments must be greater than or equal to s. Figure 6 As shown, the enclosing area of ​​the initial line segment 601 (the shaded area in the figure) is 602, and the spacing between each boundary of the enclosing area 602 and the boundary of the corresponding parallel initial line segment is equal to s. It is found through judgment that the line segment 603 crosses the boundary of the enclosing area 602. Therefore, it is determined that the wiring spacing requirements are not met between the initial line segment and the neighboring line segment.

[0063] It should be noted that, for any newly generated line segment, the electronic device can determine whether the line segment and its neighboring line segments meet the wiring spacing requirement according to the above method.

[0064] Step 305, determining the initial line segment as a target line segment that meets the wiring spacing requirement; then proceeding to step 308;

[0065] Step 306: automatically generate a new initial line segment.

[0066] For example, in some embodiments, the electronic device may implement step 306 through steps 908 to 910 of the following embodiments.

[0067] Step 307 , automatically processing the new initial line segment according to the judgment result of whether the new initial line segment and the corresponding neighboring line segment meet the wiring spacing requirement, until a target line segment that meets the wiring spacing requirement is obtained; then proceeding to step 308 .

[0068] It can be understood that in the embodiment of the present application, if the initial line segment does not meet the wiring spacing requirement, a new initial line segment is automatically generated, and it is automatically determined whether the new initial line segment and the corresponding neighboring line segment meet the wiring spacing requirement. Based on this, the new initial line segment is automatically processed until a target line segment that meets the wiring spacing requirement is obtained; in this way, it can be ensured that each line segment automatically drawn by the electronic device will not have a DRC violation problem, so that engineers will no longer need to manually correct it in the later stage, thereby shortening the chip design cycle.

[0069] It should be noted that in the embodiments of the present application, the method for automatically processing each generated line segment is the same, and the ultimate goal is to obtain a target line segment that meets the wiring spacing requirements.

[0070] Step 308 , determining whether the endpoints of the target line segment include the end point; if so, executing step 309 ; otherwise, executing step 310 .

[0071] It can be understood that the purpose of judging whether the endpoints of the currently obtained target line segment include the end point is to determine whether to continue to complete the wiring task between the current starting point and the end point, or to perform the wiring task between the starting point and the end point of the next line to be connected. If the endpoints of the currently obtained target line segment include the end point, adding through holes to both ends of the target line segment can complete the wiring task of the current connection; otherwise, the following step 310 is executed.

[0072] Step 309, adding through holes at both ends of the target line segment, thereby completing the wiring task of the current line to be connected.

[0073] It can be understood that after the electronic device completes the wiring task of the current line to be connected, it continues to complete the wiring task of the next line to be connected according to the wiring information and the wiring method of the chip design described in the embodiment of the present application, until the starting point and end point of each group are connected by metal wire segments.

[0074] Step 310 , using the coordinates of the end point as an end point position, generating a perpendicular line segment of the target line segment on another available wiring layer.

[0075] It can be understood that in the process of connecting the starting point and the end point through wiring, the planning of the next line segment uses the coordinates of the end point as the endpoint position, so that the number of wiring times in the process can be reduced as much as possible, thereby shortening the chip design cycle.

[0076] Step 311, based on the judgment result of whether the vertical line segment and the corresponding neighboring line segment meet the wiring spacing requirement of the other available wiring layer, process the vertical line segment until a target line segment that meets the wiring spacing requirement of the other available wiring layer is obtained.

[0077] It can be understood that the corresponding neighbor line segment in step 311 refers to the neighbor line segment of the vertical line segment. As mentioned above, in the wiring process of chip design, the method of automatically processing each newly generated line segment is the same, and the ultimate goal is to obtain a target line segment that meets the wiring spacing requirements.

[0078] Step 312: Update the target line segment obtained last time according to the currently obtained target line segment, so that the updated target line segment and the currently obtained target line segment are in an L shape.

[0079] It can be understood that the target line segment obtained last time and the target line segment obtained currently are perpendicular to each other, and the target line segment obtained last time is updated along with the target line segment obtained currently, so that the two perpendicular line segments are always L-shaped. In this way, each line segment used to connect the starting point and the end point finally has no redundant part, thereby improving the wiring quality and shortening the total length of the connection between the two points.

[0080] For example, if Figure 7 As shown, assuming that the current target line segment is 701, and the previous target line segment is 702, before updating the target line segment 702, the two line segments are T-shaped; after the update, the two line segments are L-shaped. Obviously, compared with before the update, the length of the target line segment 702 is shortened.

[0081] Step 313, determine whether the endpoint of the target line segment of the other available wiring layer includes the end point; if so, execute step 314; otherwise, repeat the above steps 310 to 313 until the target line segment including the end point is obtained, and enter step 314.

[0082] It should be noted that, based on the target line segment of the other available wiring layer (i.e., the currently obtained target line segment), the target line segment of the available wiring layer (i.e., the target line segment obtained last time) is updated so that the updated target line segment and the target line segment of the other available wiring layer are in an L shape. The execution order of this step (i.e., step 312) and step 313 can be various, and the execution order of these two steps is not limited in this application. Step 312 can be executed first, or step 313 can be executed first, or these two steps can be executed in parallel.

[0083] Step 314, adding through holes at the nodes of each obtained target line segment to complete the connection between the starting point and the end point.

[0084] It can be understood that a node refers to the intersection (convergence) of two mutually perpendicular line segments. Figure 8 As shown, the connection between the starting point 801 and the end point 802 requires target line segments 803 to 805, wherein the target line segment 803 and the target line segment 804 are perpendicular to each other, and the intersection point is 811; the target line segment 804 and the target line segment 805 are perpendicular to each other, and the intersection point is 812; then, the electronic device can add through holes at the intersection points 811 and 812 respectively to connect the target line segment 803 and the target line segment 804, and to connect the target line segment 804 and the target line segment 805.

[0085] The present application embodiment further provides a wiring method for chip design. Fig. 9 A schematic diagram of the implementation flow of the wiring method for chip design provided in the embodiment of the present application is shown in FIG. Fig. 9 As shown, the method may include the following steps 901 to 911:

[0086] Step 901, obtaining the coordinates of the starting point and the end point of the current line to be connected from the connection information required for chip design;

[0087] Step 902, determining an available wiring layer according to the coordinates of the starting point and the coordinates of the end point;

[0088] Step 903, determining a Manhattan line with the least turns between the starting point and the end point according to the coordinates of the starting point and the end point;

[0089] Step 904: determine the rectangular area determined by the Manhattan line as the target area.

[0090] Before describing the Manhattan connection, here is a brief introduction to Manhattan. Manhattan is an extremely prosperous neighborhood with tall buildings and streets that are horizontal and vertical. Fig.10As shown, there is no straight path from point A to point B. You must take a detour, and when taking a detour, you must walk horizontally and vertically to reach point B. For example, the path from point A to point B is Fig.10 The paths a, b, c and d shown in the figure show that the paths a and d have the least turns and only one right angle, so these two paths are Manhattan lines. Similarly, if we consider location A as the starting point and location B as the end point, then in chip design, the area enclosed by these two paths is the target area, which is also the optimal wiring area.

[0091] Step 905 , performing routing on the target area of ​​the available routing layer according to the coordinates of the starting point, the coordinates of the end point and the routing width requirement to obtain an initial line segment.

[0092] It can be understood that routing is performed on a target area of ​​an available routing layer rather than beyond the target area, so that the connection distance between two points can be minimized, thereby effectively improving the utilization rate of the routing layer.

[0093] In some embodiments, the width of the initial line segment meets the wiring width requirement, the length of the initial line segment is the distance between the horizontal coordinate of the starting point and the horizontal coordinate of the end point, or the length of the initial line segment is the distance between the vertical coordinate of the starting point and the vertical coordinate of the end point.

[0094] Step 906, determining whether the initial line segment and the neighboring line segment meet the wiring spacing requirement of the available wiring layer; if yes, executing step 907; otherwise, executing step 908;

[0095] Step 907: determine the initial line segment as a target line segment that meets the wiring spacing requirement.

[0096] It should be noted that after obtaining the target line segment, the electronic device also needs to execute steps such as determining whether the endpoints of the target line segment include the end point, that is, execute steps 308 to 314 as described in the above embodiment to complete the connection between the starting point and the end point, and then perform the wiring task of the next starting point and end point to be connected.

[0097] In some embodiments, when the endpoint of the target line segment does not include the end point, the electronic device can generate a vertical line segment of the target line segment on the target area of ​​another available wiring layer with the coordinates of the end point as an end point position.

[0098] It can be understood that the line segments used to connect the initial point and the end point are all deployed on the target area, which can make the connection distance between the two points the shortest, thereby improving the utilization rate of the wiring layer.

[0099] Step 908: Determine the physical position relationship between the target neighbor line segment that does not meet the wiring spacing requirement and the initial line segment.

[0100] In some embodiments, the electronic device may first obtain shape information of the target neighbor line segment, and then determine the physical position relationship between the two line segments based on the shape information and the shape information of the initial line segment.

[0101] Step 909: Determine the translation direction and translation distance of the initial line segment according to the physical position relationship.

[0102] In some embodiments, step 909 can be implemented as follows: based on the physical position relationship and the target area, the translation distance and the translation direction are determined, so that the electronic device translates the initial line segment according to the translation direction so that the translated initial line segment is within the target area of ​​the available wiring layer.

[0103] It can be understood that when the electronic device automatically processes each newly generated line segment, it can automatically process it according to the above steps. The advantage of this is that the final connection distance between two points can be minimized, thereby improving the wiring quality.

[0104] Step 910: translate the initial line segment according to the translation direction and the translation distance so that the initial line segment after translation and the target neighboring line segment meet the wiring spacing requirement, and use the initial line segment after translation as the new initial line segment.

[0105] Step 911, according to the judgment result of whether the new initial line segment and the corresponding neighboring line segment meet the wiring spacing requirement, automatically process the new initial line segment until a target line segment that meets the wiring spacing requirement is obtained.

[0106] Similarly, here, after obtaining the target line segment, the electronic device also needs to execute steps such as determining whether the endpoints of the target line segment include the end point, that is, execute steps 308 to 314 of the above embodiment to complete the connection between the starting point and the end point, and then perform the wiring task of the next starting point and end point to be connected.

[0107] The following describes an exemplary application of the embodiments of the present application in a practical application scenario.

[0108] In the embodiment of the present application, in order to avoid the problem of long chip design cycle caused by manual wiring, at the same time, make full use of the basic wiring capabilities of EDA tools, such as: using command lines to automatically draw metal segments, punch holes, and judge the physical position relationship of metal segments, etc., to accelerate wiring automation, while avoiding the introduction of additional DRC violation problems, so as to achieve the purpose of completing wiring once and without the need for subsequent corrections. The embodiment of the present application provides a wiring method for chip design, which may include the following steps 1) to 8):

[0109] Step 1) After the back-end design completes the Floorplan phase, the coordinates of the starting point (x1, y1) and the end point (x2, y2) of the current line to be connected are obtained according to the wiring information required for wiring. Fig.11 As shown in the figure, it is assumed that x1≤x2, y1<y2, the required wiring width of NDR is w, and the wiring spacing is s.

[0110] Step 2) Determine the available wiring layers near the starting point under the premise of meeting the NDR spacing requirements.

[0111] Step 3) Fig.11 As shown, the rectangular area 111 determined by the Manhattan line between the coordinates, namely ((x1, y1)(x2+w, y2+w)), is initially used as the optimal wiring area, namely the target area;

[0112] Step 4) Fig.12 As shown, on the optimal routing area 121 of the available routing layer, the initial shape of the planned routing is the line segment metalA (ie, the initial line segment), namely ((x1, y1)(x2+w, y1+w));

[0113] Step 5) Fig.13 As shown, determine whether area 131 (i.e., the enclosing area), i.e., ((x1-s, y1-s)(x2+w+s, y1+w+s)) satisfies DRC, i.e., whether it satisfies the wiring spacing requirement of the wiring layer object; if so, execute step a); if not, execute step b);

[0114] Step a) Determine that the shape of the line segment is metalA (i.e., the target line segment), i.e., ((x1, y1)(x2+w, y1+w)); then, proceed to step 6);

[0115] Step b) generates a new line segment shape according to the DRC feedback information by a method similar to step 6) b) and finally obtains a suitable shape, that is, finally obtains the target line segment.

[0116] Step 6) Fig.14As shown, on another available routing layer, the shape of the line segment metalB perpendicular to the line segment metalA is planned to be ((x2, y1)(x2+w, y2+w)), and it is determined whether the area 141, i.e., ((x2-s, y1-s)(x2+w+s, y2+w+s)) satisfies the DRC; if so, perform the following step a); if not, perform the following step b), for example, Fig.15 As shown, area 151 (i.e. Fig.14 In the area 141), a line segment metalC exists, and the line segment metalC is an example of the target neighbor line segment that does not meet the wiring spacing requirement;

[0117] Step a) Fig.14 As shown, the shape of line segment metalB is determined to be ((x2, y1)(x2+w, y2+w)), which is another target line segment.

[0118] Step b) Fig.15 As shown, the line segment metalC (i.e., an example of the target neighbor line segment) exists in the area 151, then according to the DRC feedback information, as Fig.16 As shown, a new line segment metalB is generated, that is, the shape ((x2-x0, y1)(x2-x0+w, y1+w)), and it is determined whether area 161, that is, ((x2-x0-s, y1-s)(x2-x0+w+s, y1+w+s)) satisfies the DRC. This operation is performed in a loop until a line segment metalB (that is, another target line segment) that satisfies the DRC is found. At the same time, based on the line segment metalB that satisfies the DRC, the shape of the line segment metalA is updated to the final state.

[0119] In some embodiments, the DRC feedback information may include shape information of the line segment metalC. The physical position relationship between the line segment metalB and the line segment metalC is determined based on the DRC feedback information and the shape information of the line segment metalB. The translation distance and translation direction required to translate the line segment metalB may be determined based on the physical position relationship and the optimal routing area, such as Fig.15 As shown, the translation distance is x0, and the translation direction is H to K.

[0120] Step 7) Repeat the operation method of step 6) until the connection from the starting point to the end point is finally completed. The result is as follows Fig.17 As shown;

[0121] Step 8) Fig.18 As shown, each wiring shape node is connected through a through hole to complete the final wiring.

[0122] In an embodiment of the present application, a wiring method is provided, wherein the wiring rules of the method are simple and the tool implementation speed is fast; and the wiring is completed without introducing DRC violations and causing tedious repair work in the later stage.

[0123] In the embodiment of the present application, the shortest Manhattan connection method is combined with DRC inspection to convert it into a routing method that can be recognized by the tool, thereby accelerating the NDR routing speed and improving the routing quality.

[0124] Based on the foregoing embodiments, the embodiments of the present application provide a wiring device for chip design, which includes the modules included and the units included in the modules, and can be implemented by a processor; of course, it can also be implemented by a specific logic circuit; in the implementation process, the processor can be a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP), a field programmable gate array (FPGA) or a graphics processing unit (GPU), etc.

[0125] Fig.19 A schematic diagram of the structure of the wiring device designed for the chip of the embodiment of the present application is shown in FIG. Fig.19 As shown, the device 190 includes a wiring module 191, a judgment module 192 and a processing module 193, wherein:

[0126] A wiring module 191 is used to perform wiring on the wiring layer according to the wiring information required for wiring in the chip design to obtain an initial line segment;

[0127] A judgment module 192, used to judge whether the initial line segment and the neighboring line segment meet the wiring spacing requirement of the wiring layer, and obtain a judgment result;

[0128] The processing module 193 is used to automatically process the initial line segment according to the judgment result until a target line segment that meets the wiring spacing requirement is obtained.

[0129] In some embodiments, the wiring module 191 is used to: obtain the coordinates of the starting point and the end point of the current line to be connected from the connection information; determine the available wiring layer according to the coordinates of the starting point and the coordinates of the end point; perform wiring on the available wiring layer according to the coordinates of the starting point, the coordinates of the end point and the wiring width requirements of the available wiring layer to obtain the initial line segment.

[0130] In some embodiments, the wiring module 191 is used to: determine the Manhattan line with the least turns between the starting point and the end point based on the coordinates of the starting point and the coordinates of the end point; determine the rectangular area determined by the Manhattan line as the target area; and perform wiring on the target area of ​​the available wiring layer based on the coordinates of the starting point, the coordinates of the end point and the wiring width requirements to obtain the initial line segment.

[0131] In some embodiments, the width of the initial line segment meets the wiring width requirement, the length of the initial line segment is the distance between the horizontal coordinate of the starting point and the horizontal coordinate of the end point, or the length of the initial line segment is the distance between the vertical coordinate of the starting point and the vertical coordinate of the end point.

[0132] In some embodiments, the processing module 193 is used to: automatically generate a new initial line segment when the judgment result is that the wiring spacing requirement is not satisfied between the initial line segment and the neighboring line segment; and automatically process the new initial line segment according to the judgment result of whether the wiring spacing requirement is satisfied between the new initial line segment and the corresponding neighboring line segment until the target line segment is obtained.

[0133] In some embodiments, the processing module 193 is used to: determine the physical position relationship between the target neighbor line segment that does not meet the wiring spacing requirement and the initial line segment; determine the translation direction and translation distance of the initial line segment based on the physical position relationship; translate the initial line segment based on the translation direction and translation distance so that the translated initial line segment meets the wiring spacing requirement with the target neighbor line segment, and use the translated initial line segment as the new initial line segment.

[0134] In some embodiments, the processing module 193 is used to: determine the translation distance and the translation direction according to the physical position relationship and the target area, so that the initial line segment after translation is within the target area of ​​the available wiring layer.

[0135] In some embodiments, the wiring module 191 is also used to generate a vertical line segment of the target line segment on another available wiring layer with the coordinates of the end point as an end point position when the endpoint of the target line segment does not include the end point; the processing module 193 is used to: process the vertical line segment according to the judgment result of whether the wiring spacing requirement of the other available wiring layer is satisfied between the vertical line segment and the corresponding neighboring line segment, until a target line segment that satisfies the wiring spacing requirement of the other available wiring layer is obtained; when the endpoint of the target line segment of the other available wiring layer in 190 does not include the end point, the device repeats the above steps until a target line segment including the end point is obtained, and adds through holes at the nodes of each target line segment through the wiring module 191 to complete the connection between the starting point and the end point.

[0136] In some embodiments, the routing module 191 is further used to update the target line segment obtained last time according to the currently obtained target line segment, so that the updated target line segment and the currently obtained target line segment are in an L shape.

[0137] In some embodiments, the processing module 193 is configured to generate a vertical line segment of the target line segment on the target area of ​​the another available routing layer.

[0138] The description of the above device embodiment is similar to the description of the above method embodiment, and has similar beneficial effects as the method embodiment. For technical details not disclosed in the device embodiment of the present application, please refer to the description of the method embodiment of the present application for understanding.

[0139] It should be noted that in the embodiments of this application Fig.19 The division of modules by the wiring device of the chip design shown is schematic and is only a logical function division. There may be other division methods in actual implementation. In addition, each functional unit in each embodiment of the present application may be integrated into a processing unit, or may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of a software functional unit. It may also be implemented in the form of a combination of software and hardware.

[0140] Correspondingly, if Fig. 20 As shown, an electronic device 200 provided in an embodiment of the present application may include: a memory 201 and a processor 202, wherein the memory 201 stores a computer program that can be executed on the processor 202, and the processor 202 implements the steps in the method provided in the above embodiment when executing the program.

[0141] The memory 201 is configured to store instructions and applications executable by the processor 202, and can also cache data to be processed or processed by the processor 202 and various modules in the electronic device 200 (for example, image data, audio data, voice communication data, and video communication data), which can be implemented through flash memory (FLASH) or random access memory (Random Access Memory, RAM).

[0142] It should be noted that in the embodiment of the present application, if the above-mentioned decoding method is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the embodiment of the present application can be essentially or partly embodied in the form of a software product that contributes to the relevant technology. The computer software product is stored in a storage medium, including several instructions to enable an electronic device to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a U disk, a mobile hard disk, a read-only memory (ROM), a magnetic disk or an optical disk. In this way, the embodiment of the present application is not limited to any specific combination of hardware and software.

[0143] An embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps in the wiring method for chip design provided in the above embodiment are implemented.

[0144] An embodiment of the present application provides a computer program product including instructions, which, when executed on a computer, enables the computer to execute the wiring method for chip design provided by the above method embodiment.

[0145] It should be noted here that the description of the above storage medium and device embodiments is similar to the description of the above method embodiments, and has similar beneficial effects as the method embodiments. For technical details not disclosed in the storage medium, chip and terminal device embodiments of this application, please refer to the description of the method embodiments of this application for understanding.

[0146] It should be understood that "one embodiment" or "an embodiment" or "some embodiments" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" or "in some embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned sequence numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0147] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0148] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The embodiments of the touch screen system described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as: multiple modules or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or modules can be electrical, mechanical or other forms.

[0149] The modules described above as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules; they may be located in one place or distributed on multiple network units; some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0150] In addition, all functional modules in the embodiments of the present application may be integrated into one processing unit, or each module may be a separate unit, or two or more modules may be integrated into one unit; the above-mentioned integrated modules may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0151] A person skilled in the art can understand that all or part of the steps of implementing the above method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiment; and the aforementioned storage medium includes: mobile storage devices, read-only memories (ROM), magnetic disks or optical disks, etc., various media that can store program codes.

[0152] Alternatively, if the above-mentioned integrated unit of the present application is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application can essentially or in other words, the part that contributes to the relevant technology can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling an electronic device to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0153] The methods disclosed in several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0154] The features disclosed in several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0155] The features disclosed in several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0156] The above is only an implementation method of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A wiring method for chip design, characterized in that: The method comprises: From the wiring information required for the chip design, obtain the coordinates of the starting point and the end point of the current wiring to be connected; Determining an available wiring layer according to the coordinates of the starting point and the coordinates of the end point; According to the coordinates of the starting point, the coordinates of the end point and the wiring width requirement of the available wiring layer, wiring is performed on the available wiring layer to obtain an initial line segment; Determine whether the initial line segment and the neighboring line segment meet the wiring spacing requirement of the wiring layer, and obtain a determination result; According to the judgment result, the initial line segment is automatically processed until a target line segment that meets the wiring spacing requirement is obtained; The method further comprises: when the endpoint of the target line segment does not include the end point, taking the coordinates of the end point as an end point position, generating a vertical line segment of the target line segment on another available wiring layer; According to the judgment result of whether the vertical line segment and the corresponding neighboring line segment meet the wiring spacing requirement of the other available wiring layer, the vertical line segment is processed until a target line segment that meets the wiring spacing requirement of the other available wiring layer is obtained.

2. The method according to claim 1, characterized in that The step of performing routing on the available routing layer according to the coordinates of the starting point, the coordinates of the end point and the routing width requirement of the available routing layer to obtain an initial line segment comprises: Determine a Manhattan line with the least turns between the starting point and the end point according to the coordinates of the starting point and the coordinates of the end point; Determine the rectangular area determined by the Manhattan line as the target area; According to the coordinates of the starting point, the coordinates of the end point and the wiring width requirement, wiring is performed on the target area of ​​the available wiring layer to obtain the initial line segment.

3. The method according to claim 2, characterized in that The width of the initial line segment meets the wiring width requirement, the length of the initial line segment is the distance between the abscissa of the starting point and the abscissa of the end point, or the length of the initial line segment is the distance between the ordinate of the starting point and the ordinate of the end point.

4. The method according to claim 2, characterized in that The automatically processing the initial line segment according to the judgment result until a target line segment that meets the wiring spacing requirement is obtained includes: When the judgment result is that the wiring spacing requirement is not satisfied between the initial line segment and the neighboring line segment, a new initial line segment is automatically generated; According to the judgment result of whether the wiring spacing requirement is satisfied between the new initial line segment and the corresponding neighboring line segment, the new initial line segment is automatically processed until the target line segment is obtained.

5. The method according to claim 4, characterized in that The automatic generation of a new initial line segment comprises: Determine the physical position relationship between the target neighbor line segment that does not meet the wiring spacing requirement and the initial line segment; Determining the translation direction and translation distance of the initial line segment according to the physical position relationship; The initial line segment is translated according to the translation direction and the translation distance so that the initial line segment after translation and the target neighboring line segment meet the wiring spacing requirement, and the initial line segment after translation is used as the new initial line segment.

6. The method according to claim 5, characterized in that Determining the translation direction and translation distance of the initial line segment according to the physical position relationship includes: The translation distance and the translation direction are determined according to the physical position relationship and the target area, so that the initial line segment after translation is within the target area of ​​the available wiring layer.

7. The method according to any one of claims 2 to 6, characterized in that: The method further comprises: When the endpoint of the target line segment of the other available wiring layer does not include the end point, repeat the above steps until a target line segment including the end point is obtained, and add through holes at the nodes of each target line segment to complete the connection between the starting point and the end point.

8. The method according to claim 7, characterized in that The method further comprises: According to the currently obtained target line segment, the previously obtained target line segment is updated so that the updated target line segment and the currently obtained target line segment are in an L shape.

9. The method according to claim 8, characterized in that Generating a vertical line segment of the target line segment on another available routing layer comprises: A vertical line segment of the target line segment is generated on the target area of ​​the another available wiring layer.

10. A wiring device for chip design, characterized in that: include: A wiring module is used to obtain the coordinates of the starting point and the end point of the current wiring to be connected from the wiring information required for the chip design; and determining an available wiring layer according to the coordinates of the starting point and the coordinates of the end point; and performing routing on the available routing layer according to the coordinates of the starting point, the coordinates of the end point and the routing width requirement of the available routing layer to obtain an initial line segment; A judgment module, used for judging whether the initial line segment and the neighboring line segment meet the wiring spacing requirement of the wiring layer, and obtaining a judgment result; A processing module, used for automatically processing the initial line segment according to the judgment result until a target line segment that meets the wiring spacing requirement is obtained; The routing module is further used to generate a vertical line segment of the target line segment on another available routing layer using the coordinates of the end point as an end point position when the end point of the target line segment does not include the end point; The processing module is further used to process the vertical line segment according to the judgment result of whether the vertical line segment and the corresponding neighboring line segment meet the wiring spacing requirement of the other available wiring layer, until a target line segment that meets the wiring spacing requirement of the other available wiring layer is obtained.

11. An electronic device comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, characterized in that: When the processor executes the program, the method according to any one of claims 1 to 9 is implemented.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 9 is implemented.

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