Artificial neuron

Abstract

Artificial neurons are disclosed. An artificial neuron includes a first capacitance node to which a membrane potential of the neuron is applied. A first transistor is configured to discharge the first capacitance node. A second capacitance node is driven in accordance with the membrane potential and communicates a potential for controlling the first transistor. A second transistor is configured to discharge the second capacitance node. The second transistor is controlled in accordance with a potential present at the second capacitance node.

Description

[0001] CLAIM

[0002] This application claims priority to French Patent Application No. 2010639 filed on October 16, 2020, the contents of which are incorporated herein in its entirety to the maximum extent permitted by law. TECHNICAL FIELD

[0003] The present disclosure relates generally to electronic devices, and more particularly to electronic devices implementing artificial neurons. BACKGROUND

[0004] Among existing artificial neurons, spike neurons capable of generating a spike response in response to an excitation signal applied on their membrane by one or more other neurons are particularly known. However, these spike neurons can fail when strongly excited.

[0005] There is a need to improve existing spike neurons. SUMMARY

[0006] One embodiment overcomes all or part of the drawbacks of known spike neurons.

[0007] In one embodiment, the electronic circuit of an artificial neuron comprises: a first capacitive node to which a membrane potential of the neuron is applied; a first transistor for discharging the first capacitive node; a second capacitive node driven in response to the membrane potential and delivering a potential for controlling the first transistor; and a second transistor for discharging the second capacitive node, wherein the second transistor is controlled in response to a potential present at the second capacitive node.

[0008] According to one embodiment, the circuit further comprises a circuit for controlling the second transistor, the circuit being configured to activate the second transistor in response to a discharge of the second capacitive node below a threshold value.

[0009] According to one embodiment, the control circuit comprises an inverter, an input of the inverter being connected to the second capacitive node and an output of the inverter being connected to a gate of the second transistor.

[0010] According to one embodiment, the second capacitive node is coupled to the first capacitive node by a first inverter and a second inverter.

[0011] According to one embodiment, the circuit further comprises a third transistor connected between a gate of the second transistor and a third node to which a reference potential is applied, the gate of the third transistor being coupled to a fourth node located between the first inverter and the second inverter by a third inverter.

[0012] According to one embodiment, the circuit further comprises a fourth transistor coupled to the first capacitive node and to a fourth node to which a potential for powering the neuron is applied.

[0013] According to an embodiment, the gate of the fourth transistor is connected to an output of a NOR gate, or the NOR gate comprises a first input connected to the gate of the second transistor and a second input connected to the first capacitance node.

[0014] According to an embodiment, the fourth transistor is coupled to the first capacitance node by a fifth transistor, the gate of the fifth transistor being for receiving a potential for exciting the neuron.

[0015] One embodiment provides an artificial neural network comprising at least one circuit as described. BRIEF DESCRIPTION OF DRAWINGS

[0016] The above features and advantages and other will be described in detail below with reference to specific embodiments given by way of illustration and not limitation, wherein:

[0017] Figure 1 An example of an artificial neural network is schematically illustrated in block form;

[0018] Figure 2 is an electronic circuit implementing an example of a spiking neuron;

[0019] Figure 3 is a timing diagram illustrating an example of the operation of the circuit of Figure 2

[0020] Figure 4 is an electronic circuit implementing another example of a spiking neuron;

[0021] Figure 5 is a timing diagram illustrating an example of the operation of the neuron's circuit of Figure 4

[0022] Figure 6 is another example of a timing diagram illustrating the operation of the neuron's circuit of Figure 4

[0023] Figure 7 is an electronic circuit implementing a spiking neuron according to an embodiment;

[0024] Figure 8 is a more detailed embodiment of the neuron's electronic circuit of Figure 7

[0025] Figure 9 is a timing diagram illustrating an example of the operation of the neuron's circuit of Figure 7 and Figure 8

[0026] Figure 10 Figure 7 Figure 8 ​​​​​​​a timing diagram of another example of operation of a circuit of neurons. DETAILED DESCRIPTION

[0027] The same features are designated by the same reference signs in the different drawings. In particular, structural and / or functional features that are common in the various embodiments can have the same reference signs and can be provided with the same structural, dimensional and material properties.

[0028] For the sake of clarity, only the steps and elements useful for an understanding of the embodiments described herein are specified and described in detail. In particular, the architecture of the spiking neuron networks and the processing operations performed by these networks are not specified in detail.

[0029] Unless otherwise stated, when referring to two elements connected together, this means a direct connection without any intermediate element other than a conductor, whereas when referring to two elements coupled together, this means that the two elements can be connected or that the two elements can be coupled via one or more other elements.

[0030] In the following description, when referring to terms defining an absolute position, such as the terms "in front of", "behind", "on top of", "on the bottom of", "on the left of", "on the right of", etc., or terms defining a relative position, such as the terms "on", "under", "upper", "lower", etc., or terms defining a direction, such as the terms "horizontal", "vertical", etc., unless otherwise stated, refer to the orientation of the drawings.

[0031] Unless otherwise stated, the expressions "about", "approximately", "substantially" and "in order" mean within 10% and preferably within 5%.

[0032] Figure 1 An example of a network 100 (neural network) of artificial neurons 101 (neurons) is schematically shown in the form of a block.

[0033] The network 100 generally comprises a plurality of layers of artificial neurons 101. In the example shown, the network 100 more particularly comprises an input layer 103 (input layer) configured to receive one or more input signals (inputs), an intermediate layer or hidden layer 105 (hidden layer) configured to process these input signals, and an output layer 107 (output layer) configured to generate one or more output signals (outputs) resulting from the processing of the hidden layer 105.

[0034] Although a single hidden layer 105 is shown in Figure 1 However, according to the complexity of the network 100, the network 100 of artificial neurons 101 can comprise several tens or even several hundreds of hidden layers 105. Furthermore, although Figure 1The illustrated input layer 103, hidden layer 105, and output layer 107 include three, four, and two neurons 101, respectively, but each layer 103, 105, 107 can include any non-zero integer number of neurons 101.

[0035] The network 100 of artificial neurons 101 is used, for example, for handwriting recognition, speech recognition, or image recognition (e.g., face recognition) applications. In the case of a face recognition application, the neurons 101 of the input layer 103 of the network 100 receive input data originating, for example, from an image that was previously submitted to pre-processing and feature extraction operations. These data are then processed by the hidden layer 105 of the network 100, for example, by comparison with a database of faces. For example, the network 100 indicates at its output whether the image includes one of the faces present in the database.

[0036] In the illustrated example, each neuron 101 of the network 100 includes an integrator module 109 (DPI), an adaptation module 111 (ADAPT), and a core module 113 (CORE). Each neuron 101 of the network 100 can also include one or more other modules. These modules are represented in Figure 1 by a single block 115 (OTHER).

[0037] For example, the integrator module 109 receives synaptic input signals originating from a plurality of other neurons 101 of the network 100. As an example, the integrator module 109 is a differential pair integrator module (“differential pair integrator”). For example, when a linear artificial neuron is excited by a signal having an amplitude less than its firing threshold, the module 109 enables the neuron to generate an exponential response.

[0038] The adaptation module 111 is connected, for example, to the output of the integrator module 109. As an example, the adaptation module 111 enables the simulation of biological adaptation phenomena. For example, the adaptation module 111 enables the determination of whether the neuron 101 is more difficult to fire if it has recently emitted a spike.

[0039] The core module 113 is connected, for example, to the output of the adaptation module 111. As an example, the core module 113 enables the simulation of the operation of the axonal hillock of a real neuron.

[0040] Figure 2 The electronic circuit that is an example of the implementation of the spiking neuron 200 is, for example, similar to the circuit described in Chapter 7 of the book “Event-Based Neuromorphic Systems” (ISBN: 9780470018491), which is incorporated herein by reference. For example, the spiking neuron 200 enables the implementation of all or part of the artificial neuron 101. Figure 1 ​

[0041] In the illustrated example, neuron 200 comprises a current source SI providing a current labeled Iin. Source SI has for example a node connected to a node applying a potential Vdd, for example corresponding to a supply voltage of neuron 200, and another node connected to node 201. The potential of node 201, for example corresponding to a membrane voltage of neuron 200, is labeled Vmem.

[0042] As Figure 1 illustrated, neuron 200 further comprises a capacitive element Cmem. For example, capacitive element Cmem has an electrode connected to node 201 and another electrode connected to a node applying a reference potential, for example ground.

[0043] In the illustrated example, neuron 200 further comprises transistors Ml, M2 and M3. Transistors Ml, M2 and M3 are for example metal-oxide-semiconductor type transistors, more simply called MOS transistors. More specifically, in the illustrated example, transistors Ml and M2 are N-channel MOS transistors or NMOS transistors, while transistor M3 is a P-channel MOS transistor or PMOS transistor.

[0044] In the illustrated example: the source of NMOS transistor Ml is connected to a node applying a reference potential and its drain is connected to node 201; the source of NMOS transistor M2 is connected to a node of current source S2, the other node of source S2 is connected to a node applying a reference potential, and its drain is connected to node 201; and the source of PMOS transistor M3 is connected to a node of current source S3, the other node of source S3 is connected to a node applying potential Vdd, and its drain is connected to node 201.

[0045] For example, current sources S2 and S3 provide currents labeled IK and INa, respectively.

[0046] In the illustrated example, neuron 200 further comprises an operational amplifier 203. For example, operational amplifier 203 receives on its inverting input (-) a potential Vthr and on its non-inverting input (+) a potential Vmem. For example, potential Vthr defines a firing threshold of neuron 200. Amplifier 203 is for example current-limited by a current source Samp connected between operational amplifier 203 and a node applying a reference potential. For example, source Samp provides a maximum current labeled Iamp.

[0047] In the illustrated example, the neuron 200 also comprises two inverting logic gates 205 and 207, or inverters. In this example, the logic gate 205 comprises an input node 209 connected to the output of the operational amplifier 203 and an output node 211 connected to the gate of the transistor M3. The logic gate 207 comprises an input node 213 connected to the output node 211 of the logic gate 205 and an output node 215 connected to the gate of the transistor M2. The potentials of the nodes 211 and 213 are denoted Vretro, and the potential of the node 215 is denoted Vrefra.

[0048] As an example, the inverting logic gate 205 more specifically comprises: an NMOS transistor M4, the source of which is connected to a node of a current source S4, another node of the source S4 being connected to a node at which a reference potential is applied, and the drain of which is connected to the node 211; and a PMOS transistor M5, the source of which is connected to a node at which a potential Vdd is applied, and the drain of which is connected to the node 211.

[0049] As an example, the inverting logic gate 207 more specifically comprises: an NMOS transistor M6, the source of which is connected to a node of a current source S6, another node of the source S6 being connected to a node at which a reference potential is applied, and the drain of which is connected to the node 215; and a PMOS transistor M7, the source of which is connected to a node of a current source S7, another node of the source S7 being connected to a node at which a potential Vdd is applied, and the drain of which is connected to the node 215.

[0050] As an example, the current sources S4, S6 and S7 provide currents denoted IIp, IKdn and IKup, respectively.

[0051] In the illustrated example: the gate of the transistor M1 receives the potential VIK, for example, so as to enable the conduction of a leakage current from the neuron 200 through the transistor M1; the gate of the transistor M2 receives the potential Vrefra of the output node 215 of the gate 207; the respective gates of the transistors M3, M6 and M7 each receive the potential Vretro of the output node 211 of the gate 205; the respective gates of the transistors M4 and M5 each receive the potential present at the output of the operational amplifier 203.

[0052] In the illustrated example, the neuron 200 also comprises another capacitive element CK. The capacitive element CK is for example connected between the output node 215 of the gate 207 and a node at which a reference potential is applied.

[0053] Figure 3 is a timing diagram illustrating an example of the operation of the circuit of Figure 2 . Figure 3 The timing diagram of is more particularly illustrates the variation of the potential Vmem present at the node 201 of the neuron 200 as a function of the time t.

[0054] It is initially assumed that at time tO the potential Vmem at node 201 is substantially zero and less than the firing threshold Vthr of neuron 200. The output of operational amplifier 203 then applies a low voltage close to the reference potential, for example at input node 209 of inverter logic gate 205. In this case, NMOS transistor M4 is turned off, while PMOS transistor M5 is turned on. The potential Vrefra at output node 211 of gate 205, applied to the gate of PMOS transistor M3, is thus substantially equal to the potential Vdd. PMOS transistor M3 is then turned off.

[0055] Still at time tO, the potential Vretro present at input node 213 of inverter logic gate 207 is substantially equal to the potential Vdd. In this case, NMOS transistor M6 is turned on, while PMOS transistor M7 is turned off. This causes output node 215 of gate 207, and thus the gate of NMOS transistor M2, to be taken to the reference potential. NMOS transistor M2 is then turned off.

[0056] At time tO, it is further assumed that the capacitive elements Cmem and CK are empty. Source SI provides a current Iin, which causes the charging of capacitive element Cmem to start. In other words, at time tO the integration of the current Iin provided by source SI by capacitive element Cmem starts. The value of the potential Vmem present at node 201 then increases as capacitive element Cmem charges.

[0057] At time t1, which follows time tO, the value of the potential Vmem present at node 201 exceeds the firing threshold Vthr of neuron 200. This then causes the output of operational amplifier 203 to switch from a low voltage to a positive voltage +Vsat.

[0058] This causes transistors M4 and M7 to turn on, while transistors M5 and M6 turn off. The potential Vretro of node 211 is thus pulled to ground. Transistor M3 then turns on. Starting from time t1, capacitive element Cmem is charged not only by source SI providing current Iin, but also by source S3 providing current INa. This accelerates the charging of capacitive element Cmem, and the potential Vmem then starts to increase faster than between times tO and t1.

[0059] Furthermore, still at time t1, capacitive element CK starts to charge due to the current IKup provided by source S7. This causes the potential Vrefra present at output node 215 of inverter 207 to gradually increase.

[0060] At time t2, which follows time t1, the potential Vmem reaches a maximum value Vmax. The maximum value Vmax reached by the potential Vmem at time t2 is for example regulated by the potential Vdd.

[0061] From time t2, the potential Vmem is substantially constant and equal to Vmax until time t3, which is after time t2.

[0062] It is assumed that at time t3, the potential Vrefra reaches a value sufficient to switch transistor M2 from the off state to the on state. The period separating time t2 from time t3 is regulated, for example, by the value of the capacitive element CK and by the value of the current IKup provided by source S7.

[0063] It is assumed that the current IK delivered by source S2 is greater than the sum of the currents Iin and INa provided respectively by sources S1 and S3. The capacitive element Cmem starts discharging at time t3. This then causes the potential Vmem present at node 201 to decrease.

[0064] At time t4, which is after time t3, the value of the potential Vmem becomes less than the firing threshold Vthr of the neuron 200. This causes, for example, the output of the operational amplifier 203 to switch from the positive voltage +Vsat to a low voltage close to the reference potential.

[0065] This causes transistors M5 and M6 to turn on, while transistors M4 and M7 turn off. The potential Vretro of the output node 211 of the inverter 205 is therefore substantially equal to the potential Vdd. Transistor M3 then turns off, which stops the delivery of the current INa by source S3.

[0066] Still at time t4, source S6 starts delivering the current IKdn. This causes the discharge of the capacitive element CK to start and the potential Vrefra of the output node 215 of the inverter 207 to decrease.

[0067] At time t5, which is after time t4, it is assumed that the potential Vmem reaches a value substantially equal to the reference potential.

[0068] In the example shown, the variation of the potential Vmem between times t1 and t5 corresponds to the generation of a spike by the neuron 200 having a duration equal to t3-t2.

[0069] From time t5, the potential Vmem is substantially constant and equal to the reference potential until time t6, which is after time t5.

[0070] The period separating time t5 from time t6 is called the refractory period of the neuron 200. During this period, the potential Vrefra is sufficient to prevent transistor M2 from switching from the on state to the off state. In the ideal case, the neuron 200 does not emit a spike whatever the current Iin of source S1 during the refractory period.

[0071] At time t6, it is assumed that the potential Vrefra reaches a value low enough to switch transistor M2 from the on state to the off state. The duration separating time t5 from time t6 is for example regulated by the value of the capacitive element CK and by the value of the current IKdn delivered by the source S6.

[0072] In the example shown, time t6 marks the beginning of a new integration phase, similar to the integration phase previously discussed with respect to time t0. This for example corresponds to the case where the neuron 200 is subjected to a sustained excitation.

[0073] Figure 4 is an electronic circuit implementing another example of a spiking neuron 400.

[0074] Figure 4 The neuron 400 of Figure 2 includes elements common to the neuron 200 of These common elements will not be detailed hereinafter. Figure 4 The neuron 400 of Figure 2 differs from the neuron 200 of

[0075] In the neuron 400 of Figure 4 , the current sources S1, S2, S3, S4, S6 and S7 and the operational amplifier 203 are omitted with respect to the neuron 200 of Figure 2 . More specifically, in the example shown: the drain of transistor M1 is connected to the drain of PMOS transistor M8; the source of transistor M8 is connected to the drain of PMOS transistor M9, the source of which is connected to a node at which the potential Vdd is applied; the source of transistor M3 is connected to the drain of PMOS transistor M10, the source of which is connected to a node at which the potential Vdd is applied; the source of transistor M6 is connected to the drain of NMOS transistor M11, the source of which is connected to a node at which the reference potential is applied; and the source of transistor M7 is connected to the drain of PMOS transistor M12, the source of which is connected to a node at which the potential Vdd is applied.

[0076] In the example shown: the gate of transistor M8 receives the potential Vin; the respective gates of transistors M9 and M10 each receive the potential Vrefra of the output node 215 of the inverting logic gate 207; the gate of transistor M11 receives the potential Vtr; and the gate of transistor M12 receives the potential Vts.

[0077] The potential Vin for example corresponds to an input potential of the neuron 400. The potential Vtr for controlling the transistor Ml 1 for example makes it possible to adjust the duration of the refractory period of the neuron 400. The potential Vts for controlling the transistor M12 for example makes it possible to adjust the duration of the spike phase (t1 to t4) of the neuron 400. Figure 3

[0078] The neuron 400 has an operation similar to that of the neuron 200 previously described in connection with the circuit of Fig. 2. Figure 3

[0079] Figure 5 is a timing diagram illustrating an example of the operation of the circuit of the neuron 400. Figure 4 Figure 5 The timing diagram of Fig. 5 illustrates more particularly in the curves 501, 503, 505 and 507 the variations of the input potential Vin applied to the gate of the transistor M8, of the output potential marked Vout, for example as an image of the potential Vretro present at the nodes 211 and 213, of the potential Vmem present at the node 201 and of the potential Vrefra applied to the gate of the transistor M2 as a function of time t.

[0080] In the example illustrated, after an initialization period of the neuron 400, a potential step marked AVin1 is applied to the gate of the transistor M8 at the time t0. From the time t0, the potential Vmem undergoes variations similar to those previously described in connection with the neuron 200 of Fig. 2. Figure 3

[0081] In the example illustrated, the potential Vout is at a high level during the spike phase (for example, when the potential Vretro of the output node 211 of the gate 205 is substantially equal to the potential Vdd). However, the potential Vout is at a low level during the refractory integration phase (for example, when the potential Vretro is substantially equal to the reference potential).

[0082] In the example illustrated, the potential Vrefra of the output node 215 of the gate 207 increases during the spike phase. However, the potential Vrefra decreases during the refractory and integration phases. In the example of operation, the potential Vrefra reaches a value equal to the reference potential before the beginning of each new spike phase, for example the node 215 being completely discharged during each integration phase.

[0083] In the example illustrated, the curve 503 illustrating the variations of the potential Vout comprises pulses having a substantially constant width or duration. Moreover, as illustrated by the curve 505 of the variations of the potential Vmem, the refractory periods are clearly distinct from the integration phases. ​​​​

[0084] Figure 6 is a timing diagram showing another example of operation of the circuit of the neuron 400. Figure 4 Figure 6 The timing diagram of the neuron 400 shows in curves 601, 603, 605 and 607 the variation over time t of the input potential Vin applied to the gate of the transistor M8, the output potential marked as Vout, for example as an image of the potential Vretro present at nodes 211 and 213, the potential Vmem present at node 201 and the potential Vrefra applied to the gate of the transistor M2 as a function of time t.

[0085] Figure 6 The example of operation shown differs from the example of operation shown in Figure 5 The difference between the example of operation shown in

[0086] For example, Figure 6 The timing diagram of the neuron 400 shows the case in which the neuron 400 is subjected to a strong synaptic excitation. This strong synaptic excitation is for example due to the fact that each neuron 400 comprises a large number of synapses or to the fact that a significant weight is assigned to each synapse.

[0087] In the example shown, the curve 603 showing the variation of the potential Vout comprises a first spike followed by a plurality of other spikes having a width or duration smaller than the width or duration of the first spike. This is in particular due to the fact that the potential Vrefra does not reach a value equal to the reference potential before the start of each new spike phase and to the fact that the node 215 does not completely discharge and remains with a residual charge, for example during the integration phase. Therefore, during the next pulse phase, the node 215 is not charged from a value of the potential Vrefra substantially equal to the reference potential, as in the example of Figure 5 Therefore, this causes a reduction in the spike time, which negatively affects the operation of the neuron 400 and the processing performed by the network implementing the neuron 400.

[0088] In addition, as shown by the curve 605 of the variation of the potential Vmem, it is difficult to determine the refractory period from the integration phase. This is in particular due to the fact that the charge present at the node 201 is discharged by the transistor M2, which cannot compensate for the arrival of the charge from the node applying the potential Vdd under the action of the potential Vin.

[0089] To overcome these drawbacks, it is possible to provide for using an NMOS transistor M2 of greater size, for example such as to enable the discharge of a greater quantity of charge. However, this would not solve the problem, for example, of the neuron 400 being subjected to a synaptic excitation greater than the threshold value of the transistor M8. Figure 6 ​The problem of the illustrated synapse to stimulate greater synapse stimulation.

[0090] Figure 7 An electronic circuit implementing the spiking neuron 700 according to the embodiment.

[0091] Figure 7 The neuron 700 comprises elements common to the neuron 400 of Figure 4 These common elements will not be detailed hereinafter.

[0092] In the illustrated example, the neuron 700 comprises a node 201 to apply a membrane potential Vmem. The node 201 is for example a capacitive node. As an example, the node 201 is formed by providing a capacitive element Cl connected between the node 201 and a node to apply a reference potential, for example ground. As a variant, the node 201 is formed by exploiting the stray capacitance of the circuit of the neuron 700.

[0093] In the illustrated example, the neuron 700 further comprises a transistor M2 to discharge the capacitive node 201. In the conductive state, the transistor M2 enables the charge present at the capacitive node 201 to be discharged to ground.

[0094] In the illustrated example, the neuron 700 further comprises an output node 215 of the inverting logic gate 207. The node 215 is for example a capacitive node. As an example, the capacitive node 215 is formed by providing a capacitive element C2 connected between the node 215 and a node to apply a reference potential. As a variant, the node 215 is formed by exploiting the stray capacitance of the circuit of the neuron 700.

[0095] Similarly to the neuron 400 of Figure 4 The capacitive node 215 of the neuron 700 is driven for example as a function of the membrane potential Vmem present at the capacitive node 201. In the illustrated example, the node 215 is separated from the node 201 by two inverting logic gates 205 and 207 connected in series between the node 201 and the node 215. More particularly, in this example, the input of the inverting logic gate 205 is connected to the node 201 and its output is connected to a node 701, the input of the inverting logic gate 207 is connected to the node 701 and its output is connected to the node 215. The node 701 of the neuron 700 is for example equivalent to the nodes 211 and 213 of the neuron 400.

[0096] In the illustrated example, the gate 205 is also connected to a node that applies a potential Vdd, e.g. a power supply potential of the neuron 700, and to a node that applies a reference potential. For example, the power supply nodes of the gate 207 are connected to nodes of a current source 703, another node of the source 703 is connected to a node that applies the potential Vdd and to a node of another current source 705, and another node of the source 705 is connected to a node that applies the reference potential.

[0097] The capacitor node 215 delivers a potential Vrefra for controlling the discharge transistor M2. The node 215 is connected to the gate of the transistor M2, for example.

[0098] In the illustrated example, the neuron 700 further comprises a discharge transistor M20 of the capacitor node 215. The transistor M20 is an N-channel MOS transistor (NMOS), for example. In this example, the source of the transistor M20 is connected to a node that applies a reference potential, and its drain is connected to the capacitor node 215. In the on state, the transistor M20 enables the discharge of the charge present at the capacitor node 215 to ground.

[0099] For example, the neuron 700 comprises a circuit 707 for controlling the discharge transistor M20. The control circuit 707 is configured to activate the transistor M20 in response to the discharge of the capacitor node 215 below a threshold value, for example.

[0100] In the illustrated example, the control circuit 707 comprises an inverting logic gate 709. An input of the inverting logic gate 709 is connected to the node 215, and its output is connected to a capacitor node 711, which is connected to the gate of the transistor M20. In this example, the power supply nodes of the inverting logic gate 709 are connected to nodes of a current source 713, another node of the source 713 is connected to a node that applies the potential Vdd and to a node that applies the reference potential.

[0101] As an example, the capacitor node 711 is formed by providing a capacitive element C3 connected between the node 711 and a node that applies the reference potential. As a variant, the node 711 is formed by exploiting the stray capacitance of the circuit of the neuron 700. The potential present at the capacitor node 711 is denoted Vctrl_refra.

[0102] In the illustrated example, the neuron 700 further comprises an NOR logic gate 715. For example, the logic gate 715 has an input connected to the capacitor node 711 and another input connected to the capacitor node 201. The power supply nodes of the logic gate 715 are connected to a node that applies the potential Vdd and to a node of a current source 717, another node of the source 717 is connected to a node that applies the reference potential. For example, at the output, the logic gate 715 delivers a binary signal denoted Vctrl_in.

[0103] In the illustrated example, the neuron 700 further comprises a transistor M21. The transistor M21 is for example a P-channel MOS transistor (PMOS). In this example, the transistor M21 is inserted between the transistors M8 and M9. More specifically, the source of the transistor M21 is connected to the drain of the transistor M9, and its drain is connected to the source of the transistor M8. As a variant, the transistor M21 can be coupled between the transistor M8 and the node 201, or between the transistor M9 and the node at which the potential Vdd is applied. In the off state, the transistor M21 makes it possible to block or limit the current supplied to the capacitive node 201 independently of the value of the potential Vin applied to the gate of the transistor M8.

[0104] In the illustrated example, the transistor M21 is controlled by the output of the NOR logic gate 715. The gate of the transistor M21 receives for example the signal Vctrl_in.

[0105] In the illustrated example, the neuron 700 further comprises three other inverting logic gates 719, 721 and 723 connected in series between the node 701 and the node at which the output potential Vout of the neuron 700 is delivered. More specifically, in this example: the input of the gate 719 is connected to the node 701, and its output is connected to the node 725; the input of the gate 721 is connected to the node 725, and its output is connected to the node 727; the input of the gate 723 is connected to the node 727, and its output is connected to the node at which the potential Vout is delivered.

[0106] Furthermore, the power supply nodes of each of the inverting logic gates 719, 721, 723 are respectively connected to the node at which the potential Vdd is applied and to the node at which the reference potential is applied.

[0107] In the illustrated example, the neuron 700 comprises a further transistor M22 of discharge of the capacitive node 711. The transistor M22 is for example an N-channel MOS transistor (NMOS). In this example, the source of the transistor M22 is connected to the node at which the reference potential is applied, and its drain is connected to the capacitive node 711. In the on state, the transistor M22 makes it possible to discharge the charge present at the capacitive node 711 to ground.

[0108] The transistor M22 is controlled for example as a function of the potential present at the node 725, denoted Vout_int. The gate of the transistor M22 is for example connected to the node 725.

[0109] Figure 8 is a neuron 700 of electronic circuit according to an embodiment Figure 7 a more detailed embodiment of the electronic circuit of the neuron 700 according to an embodiment.

[0110] In the illustrated example, inverters 205, 207, 709, 719, 721, and 723 are complementary metal-oxide-semiconductor inverters, more simply referred to as CMOS inverters. Each CMOS inverter includes a PMOS transistor and an NMOS transistor connected in series.

[0111] More specifically, in the illustrated example: inverter 205 comprises an NMOS transistor M4 and a PMOS transistor M5, the drains of which are connected to node 701, the source of NMOS transistor M4 is connected to a node at which a reference potential is applied, the source of PMOS transistor M5 is connected to a node Vdd at which a potential is applied, and the gates of NMOS transistor M4 and PMOS transistor M5 are connected to capacitive node 201. Inverter 207 comprises an NMOS transistor M6 and a PMOS transistor M7, the drains of which are connected to node 215, the source of NMOS transistor M6 is connected to current source 705, the source of PMOS transistor M7 is connected to current source 703, and the gates of NMOS transistor M6 and PMOS transistor M7 are connected to node 701. Inverter 709 comprises an NMOS transistor M30 and a PMOS transistor M31, the drains of which are connected to capacitive node 711, the source of NMOS transistor M30 is connected to a node at which a reference potential is applied, the source of PMOS transistor M31 is connected to current source 713, and the gates of NMOS transistor M30 and PMOS transistor M31 are connected to capacitive node 215. Inverter 719 comprises an NMOS transistor M32 and a PMOS transistor M33, the drains of which are connected to node 725, the source of NMOS transistor M32 is connected to a node at which a reference potential is applied, the source of PMOS transistor M33 is connected to a node at which a potential Vdd is applied, and the gates of NMOS transistor M32 and PMOS transistor M33 are connected to node 701. Inverter 721 comprises an NMOS transistor M34 and a PMOS transistor M35, the drains of which are connected to node 727, the source of NMOS transistor M34 is connected to a node at which a reference potential is applied, the source of PMOS transistor M35 is connected to a node at which a potential Vdd is applied, and the gates of NMOS transistor M34 and PMOS transistor M35 are connected to node 725. Finally, inverter 723 comprises an NMOS transistor M36 and a PMOS transistor M37, the drains of which are connected to a node at which a transfer potential Vout is applied, the source of NMOS transistor M36 is connected to a node at which a reference potential is applied, the source of PMOS transistor M37 is connected to a node at which a potential Vdd is applied, and the gates of NMOS transistor M36 and PMOS transistor M37 are connected to node 727.

[0112] In the example shown: Current source 703 includes a PMOS transistor M38, whose source is connected to the node with the applied potential Vdd, whose drain is connected to the source of a PMOS transistor M7, and whose gate receives potential Vts; Current source 705 includes an NMOS transistor M39, whose source is connected to the node with the applied reference potential, whose drain is connected to the source of an NMOS transistor M6, and whose gate receives potential Vtr; Current source 713 includes a PMOS transistor M40, whose source is connected to the node with the applied potential Vdd, whose drain is connected to the source of a PMOS transistor M31, and whose gate receives potential Vts; Current source 717 includes an NMOS transistor M41, whose source is connected to node 729, whose drain is connected to the output node 731 of a NOR gate logic gate 715, and whose gate receives potential Vts.

[0113] Furthermore, in the example shown, the NOR gate logic gate 715 includes: an NMOS transistor M42, whose source is connected to a node with an applied reference potential, whose drain is connected to node 729, and whose gate is connected to capacitor node 711; an NMOS transistor M43, whose source is connected to a node with an applied reference potential, whose drain is connected to node 729, and whose gate is connected to capacitor node 201; a PMOS transistor M44, whose source is connected to a node with an applied potential Vdd, whose drain is connected to node 733, and whose gate is connected to capacitor node 711; and a PMOS transistor M45, whose source is connected to node 733, whose drain is connected to node 731, and whose gate is connected to capacitor node 201.

[0114] In the example shown, the output node 731 of the NOR gate 715 is connected to the gate of the transistor M21.

[0115] Figure 9 It is shown Figure 7 and 8 A timing diagram illustrating an example of the operation of the neuron 700 circuit.

[0116] Figure 9 The timing diagrams, in curves 901, 903, 905, 907, 909, and 911, show in more detail the changes of the input potential Vin, output potential Vout, membrane potential Vmem, potential Vrefra for controlling transistor M2, potential Vctrl_in for controlling transistor M21, and potential Vctrl_refra for controlling transistor M20 over time t.

[0117] In the example shown, after the initialization cycle of neuron 700, a potential step labeled ΔVin3 is applied to the gate of transistor M8 at time t0. For example, Figure 9 The amplitude of the potential step ΔVin3 is similar to Figure 5the amplitude of the potential step AVin1.

[0118] In the following description, it is assumed for simplicity that the reference potential is zero, i.e. substantially equal to OV.

[0119] At time tO, the neuron 700 starts the integration phase. The capacitor node 215 is fully discharged at time tO, the potential Vrefra is zero. At the output of the inverter 709, the potential Vctrl_refra of the capacitor node 711 is in the high state. The transistor M20 is in the off state. At the output of the NOR logic gate 715, the potential Vctrl_in is in the low state. The transistor M21 is in the on state.

[0120] At time t1, after time tO, the inverters 205, 207, 719, 721 and 723 are switched. The neuron 700 then ends the integration phase and starts the spike phase. The signal Vout is switched to the high level. The capacitor node 215 starts charging, which causes the potential Vrefra to increase. The potential Vout_int of the node 725 is switched to the high state, switching the transistor M22 from the off state to the on state. This causes the capacitor node 711 to discharge, and its potential Vctrl_refra becomes zero. The transistor M20 remains in the off state. At the output of the NOR logic gate 715, the potential Vctrl_in remains in the low state. The transistor M21 remains in the on state.

[0121] At time t2, after time t1, the inverters 205, 207, 719, 721 and 723 are switched again. The neuron 700 then ends the spike phase and starts the refractory period. The signal Vout is switched to the low level. The capacitor node 215 starts discharging, which causes the potential Vrefra to decrease. The potential Vout_int of the node 725 is switched to the low state, switching the transistor M22 from the on state to the off state. The capacitor node 711 then charges via the current source 713 of the control circuit 707. Figure 7 ) At the output of the NOR logic gate 715, the potential Vctrl_in is switched from the low state to the high state. The transistor M21 is then switched from the on state to the off state.

[0122] At time t3, after time t2, the potential Vctrl_refra reaches the activation threshold of the transistor M20. The transistor M20 is switched from the off state to the on state, which causes the node 215 to discharge. At time t3, the output potential Vctrl_in of the NOR logic gate 715 is switched from the high state to the low state. The transistor M21 is then on. The neuron 700 then starts a new integration phase similar to that previously discussed with respect to time tO.

[0123] Figure 10 is a schematic diagram showing Figure 7 and 8A timing diagram of another example of the operation of the neuron 700 circuit.

[0124] Figure 10 The timing diagrams, in curves 1001, 1003, 1005, 1007, 1009, and 1011, show in more detail the changes of the input potential Vin, the output potential Vout, the membrane potential Vmem, the potential Vrefra for controlling transistor M2, the potential Vctrl_in for controlling transistor M21, and the potential Vctrl_refra for controlling transistor M20, according to time t.

[0125] Figure 10 Examples of operations shown Figure 9 The difference in the example of operation shown is primarily that a potential step ΔVin4, having an amplitude greater than the potential step ΔVin2, is applied to the gate of transistor M8 at time t0. For example, Figure 10 The timeline diagram illustrates the strong synaptic activation of neuron 700. For example, Figure 10 The amplitude of the potential step ΔVin4 is similar to Figure 6 The amplitude of the potential step ΔVin2.

[0126] In the example shown, curve 1003 illustrating the change in potential Vout includes spikes with a substantially constant width or duration. This is particularly true because capacitor node 215 is fully discharged by transistor M20 before the start of each new spike phase, thus not retaining residual charge, which is consistent with... Figure 6 The circuit 400 in the example operation is different.

[0127] Furthermore, as shown in curve 1005 of the potential Vmem change, the refractory period differs from the integration phase. This is particularly because transistor M21 is able to suppress the excitation of capacitor node 201 by potential Vin. Therefore, regardless of the potential Vin applied to the gate of transistor M8, the potential Vmem of capacitor node 201 is ensured to remain zero during the duration of the refractory period.

[0128] The advantage of the artificial neuron 700 is that the duration of the output potential Vout pulse is unaffected or almost unaffected under conditions of high synaptic excitation. Another advantage of the artificial neuron 700 is that the refractory period is significant even under conditions of high synaptic excitation.

[0129] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to them. Specifically, combining... Figure 8 The embodiments of the neuron 700 discussed are not limiting, and those skilled in the art can use other elements or circuits to obtain equivalent functionality.

[0130] Finally, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art, based on the functional indications given above. In particular, the dimensions of the transistors, capacitive elements, current sources, etc. of the circuit of the neuron 700 are within the capabilities of a person skilled in the art.

Claims

1. An electronic circuit of an artificial neuron comprising: a first capacitance node to apply a membrane potential of the artificial neuron; a first transistor to discharge the first capacitance node; a second capacitance node to be driven in accordance with the membrane potential and to deliver a potential for controlling the first transistor; a second transistor to discharge the second capacitance node, and a fourth transistor coupled to the first capacitance node and to a fifth node to apply a potential for powering the artificial neuron; wherein a gate of the fourth transistor is connected to an output of a NOR gate having a first input and a second input, the first input connected to a gate of the second transistor, the second input connected to the first capacitance node; wherein the second transistor is controlled in accordance with a potential present at the second capacitance node.

2. The circuit of claim 1, further comprising a control circuit configured to activate the second transistor in response to sensing that a discharge of the second capacitance node is below a threshold value.

3. The circuit of claim 2, wherein the control circuit comprises an inverter having an input and an output, the input connected to the second capacitance node, the output connected to the gate of the second transistor.

4. The circuit of claim 1, wherein the second capacitance node is coupled to the first capacitance node by a first inverter and a second inverter, the first and second inverters coupled in series at a fourth node.

5. The circuit of claim 4, further comprising a third transistor connected between the gate of the second transistor and a third node to apply a reference potential, wherein a gate of the third transistor is coupled to the fourth node by a third inverter.

6. The circuit of claim 1, wherein the fourth transistor is coupled to the first capacitance node by a fifth transistor having a gate configured to receive a potential for exciting the artificial neuron.

7. An artificial neural network comprising at least one circuit of claim 1.

8. An electronic circuit of an artificial neuron comprising: a first capacitance node to apply a membrane potential of the artificial neuron; a first transistor to discharge the first capacitance node; a second capacitance node; a first control circuit having an input to receive the membrane potential and an output configured to provide a first control potential to the second capacitance node; a feedback circuit configured to apply the first control potential to control operation of the first transistor to discharge; a second transistor to discharge the second capacitance node; and a second control circuit having an input to receive the control potential and an output configured to provide a second control potential to control operation of the second transistor to discharge; a fourth transistor having a conductive path coupled between a potential node and the first capacitance node; and a fifth transistor having a conductive path coupled between the potential node and the second capacitance node. ​ a fourth control circuit having a first input, a second input, and an output, the first input coupled to receive the second control potential, the second input coupled to receive the membrane potential, the output configured to generate a fourth control signal to control operation of the fourth transistor.

9. The circuit of claim 8, wherein the first control circuit comprises a pair of inverters connected in series.

10. The circuit of claim 8, wherein the second control circuit comprises an inverter.

11. The circuit of claim 8, wherein the second control circuit operates to activate the second transistor with the second control potential in response to sensing that discharge of the first control potential at the second capacitance node is below a threshold.

12. The circuit of claim 8, further comprising: a third transistor to discharge a control terminal of the second transistor; and a third control circuit having an input coupled to receive an intermediate signal from the first control circuit and an output configured to provide a third control potential to control operation of the third transistor to discharge.

13. The circuit of claim 12: wherein the first control circuit comprises a first inverter and a second inverter connected in series at an intermediate node outputting the intermediate signal; and wherein the third control circuit comprises a third inverter configured to generate the third control signal as an inversion of the intermediate signal.

14. The circuit of claim 8, wherein fourth control circuit is a NOR gate.

15. The circuit of claim 8, further comprising a fifth transistor having a conductive path connected in series with the conductive path of the fourth transistor, the conductive path of the fourth transistor coupled between a potential node and the first capacitance node, wherein the fifth transistor has a control node coupled to receive an input voltage potential to excite the neuron, and in response to the input voltage potential, the membrane potential is generated and applied to the first capacitance node.

16. An artificial neural network comprising at least one circuit of claim 8. ​

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