Data driver and display device including the same

Abstract

A data driver and a display apparatus including the same are provided. The data driver includes a multi-channel sample / hold circuit electrically connected between a digital-to-analog converter and a buffer. The multi-channel sample / hold circuit includes a first sample / hold circuit connected to a first channel and a second sample / hold circuit connected to a second channel. The first sample / hold circuit performs a first driving operation and a second driving operation. The first driving operation includes sampling an analog data voltage as a buffer input voltage during an nth horizontal time and maintaining the buffer input voltage. The second driving operation includes inputting the buffer input voltage to an input terminal of the buffer during an (n+1)th horizontal time. The second sample / hold circuit performs the second driving operation during the nth horizontal time and performs the first driving operation during the (n+1)th horizontal time.

Description

Technical Field

[0001] One or more embodiments described herein relate to a data driver and a display device including a data driver. Background Technology

[0002] The display device uses a data driver to control the display panel. The data driver may include a sample / hold circuit that performs sampling and holding operations during the first half of the horizontal time (1 / 2H) and driving operations during the second half of the horizontal time (1 / 2H). In the case of driving a high-speed, high-resolution display, the first half of the horizontal time is relatively short. Therefore, the settling time of the buffer input voltage may be insufficient, or the power consumption of the sample / hold circuit may increase. Summary of the Invention

[0003] One or more embodiments described herein provide a data driver that increases the sample / hold operation time to a horizontal time (1H). This can reduce the operating frequency, which in turn can reduce power consumption.

[0004] These or other embodiments may provide a data driver that includes a source follower at the front end of the sampling capacitor.

[0005] One or more embodiments may also provide a display device including a data driver as described herein.

[0006] According to one or more embodiments, a data driver includes: a digital-to-analog converter configured to convert a digital data signal into an analog data voltage; a buffer configured to output an analog data voltage; and a multi-channel sample-and-hold circuit electrically connected between the digital-to-analog converter and the buffer, the multi-channel sample-and-hold circuit including a first sample-and-hold circuit connected to a first channel and a second sample-and-hold circuit connected to a second channel. The first sample-and-hold circuit performs a first drive operation during a n-th level time period to sample the analog data voltage as a buffer input voltage and maintain the buffer input voltage, and performs a second drive operation during a (n+1)-th level time period to input the buffer input voltage to an input terminal of the buffer. The second sample-and-hold circuit performs the second drive operation during the n-th level time period and performs the first drive operation during the (n+1)-th level time period, where n is an integer greater than or equal to 1.

[0007] According to one or more embodiments, a display device includes: a display panel; a gate driver configured to apply a gate signal to the display panel; a data driver configured to apply an analog data voltage to the display panel; and a timing controller configured to control the gate driver and the data driver. The data driver includes: a digital-to-analog converter configured to convert a digital data signal into an analog data voltage; a buffer configured to output the analog data voltage; and a multi-channel sample-and-hold circuit electrically connected between the digital-to-analog converter and the buffer, the multi-channel sample-and-hold circuit including a first sample-and-hold circuit connected to a first channel and a second sample-and-hold circuit connected to a second channel. The first sample-and-hold circuit is configured to perform a first drive operation during a nth level time period to sample the analog data voltage as a buffer input voltage and maintain the buffer input voltage, and to perform a second drive operation during a (n+1)th level time period to input the buffer input voltage to an input terminal of the buffer. The second sample-and-hold circuit is configured to perform the second drive operation during the nth level time period and to perform the first drive operation during the (n+1)th level time period, where n is an integer greater than or equal to 1.

[0008] In one embodiment, the first sample / hold circuit includes: a first sampling capacitor configured to store a buffer input voltage; a first source follower including an input terminal configured to selectively receive an analog data voltage or a buffer output voltage and an output terminal connected to a first terminal of the first sampling capacitor; a first input switch group configured to selectively apply the analog data voltage or the buffer output voltage to the input terminal of the first source follower; and a first output switch group configured to control the connection between a second terminal of the first sampling capacitor and a first input terminal and a second input terminal of the buffer, wherein the input terminals of the buffer include a first input terminal and a second input terminal of the buffer.

[0009] In one embodiment, the second sample / hold circuit includes: a second sampling capacitor configured to store a buffer input voltage; a second source follower including an input terminal configured to selectively receive an analog data voltage or a buffer output voltage and an output terminal connected to a first terminal of the second sampling capacitor; a second input switch group configured to selectively apply the analog data voltage or the buffer output voltage to the input terminal of the second source follower; and a second output switch group configured to control the connection between a second terminal of the second sampling capacitor and a first input terminal and a second input terminal of the buffer.

[0010] In one embodiment, the output terminal of the buffer and the input terminal of the first source follower are connected to each other via a first feedback line, and the output terminal of the buffer and the input terminal of the second source follower are connected to each other via a second feedback line.

[0011] In one embodiment, the first input switch group includes: a first switch configured to control the connection between the output terminal of the digital-to-analog converter through which it outputs analog data voltage and the input terminal of the first source follower; and a second switch located on the first feedback line and configured to control the connection between the output terminal of the buffer and the input terminal of the first source follower.

[0012] In one embodiment, the first output switch group includes: a fourth switch configured to control the connection between the second terminal of the first sampling capacitor and the first input terminal of the buffer; and a third switch configured to control the connection between the second terminal of the first sampling capacitor and the second input terminal of the buffer.

[0013] In one embodiment, the second input switch group includes: a fifth switch configured to control the connection between the output terminal of the digital-to-analog converter and the input terminal of the second source follower; and a sixth switch located on the second feedback line and configured to control the connection between the output terminal of the buffer and the input terminal of the second source follower.

[0014] In one embodiment, the second output switch group includes: an eighth switch configured to control the connection between the second terminal of the second sampling capacitor and the first input terminal of the buffer; and a seventh switch configured to control the connection between the second terminal of the second sampling capacitor and the second input terminal of the buffer.

[0015] In one embodiment, when the first sample / hold circuit performs the first drive operation, the sixth and eighth switches are turned on, and the second, fourth, fifth, and seventh switches are turned off.

[0016] In an embodiment, when the first sample / hold circuit performs the second drive operation, the second and fourth switches are turned on, and the first, third, sixth, and eighth switches are turned off.

[0017] In an embodiment, the first sample / hold circuit is configured to sample the analog data voltage as a buffer input voltage when the first, third, sixth, and eighth switches are turned on and the second, fourth, fifth, and seventh switches are turned off, and the first sample / hold circuit is configured to maintain the buffer input voltage when the sixth and eighth switches are turned on and the first, second, third, fourth, fifth, and seventh switches are turned off.

[0018] In an embodiment, when the second sample / hold circuit performs the first drive operation, the second switch and the fourth switch are turned on, and the first switch, the third switch, the sixth switch and the eighth switch are turned off.

[0019] In an embodiment, when the second sample / hold circuit performs the second drive operation, the sixth and eighth switches are turned on, and the second, fourth, fifth, and seventh switches are turned off.

[0020] In an embodiment, the second sample / hold circuit is configured to sample the analog data voltage as a buffer input voltage when the second, fourth, fifth, and seventh switches are turned on and the first, third, sixth, and eighth switches are turned off, and the second sample / hold circuit is configured to maintain the buffer input voltage when the second and fourth switches are turned on and the first, third, fifth, sixth, seventh, and eighth switches are turned off.

[0021] In an embodiment of a display device according to the present invention, the display device includes: a display panel; a gate driver configured to apply a gate signal to the display panel; a data driver configured to apply an analog data voltage to the display panel; and a timing controller configured to control the gate driver and the data driver. Here, the data driver includes: a digital-to-analog converter configured to receive a digital data signal and convert the received digital data signal into an analog data voltage; a buffer configured to output an analog data voltage; and a multi-channel sample / hold circuit located between the digital-to-analog converter and the buffer, including a first sample / hold circuit connected to a first channel and a second sample / hold circuit connected to a second channel. The first sample / hold circuit is configured to perform a first drive operation during a nth level time (where n is an integer greater than or equal to 1) to sample the analog data voltage as a buffer input voltage and maintain the buffer input voltage, and to perform a second drive operation during a (n+1)th level time to input the buffer input voltage to the input terminal of the buffer; and the second sample / hold circuit is configured to perform the second drive operation during the nth level time and the first drive operation during the (n+1)th level time.

[0022] In one embodiment, the first sample / hold circuit includes: a first sampling capacitor configured to store a buffer input voltage; a first source follower including an input terminal configured to selectively receive an analog data voltage or a buffer output voltage and an output terminal connected to a first terminal of the first sampling capacitor; a first input switch group configured to selectively apply the analog data voltage or the buffer output voltage to the input terminal of the first source follower; and a first output switch group configured to control the connection between a second terminal of the first sampling capacitor and a first input terminal and a second input terminal of the buffer.

[0023] In one embodiment, the second sample / hold circuit includes: a second sampling capacitor configured to store a buffer input voltage; a second source follower including an input terminal configured to selectively receive an analog data voltage or a buffer output voltage and an output terminal connected to a first terminal of the second sampling capacitor; a second input switch group configured to selectively apply the analog data voltage or the buffer output voltage to the input terminal of the second source follower; and a second output switch group configured to control the connection between a second terminal of the second sampling capacitor and a first input terminal and a second input terminal of the buffer.

[0024] In one embodiment, the output terminal of the buffer and the input terminal of the first source follower are connected to each other via a first feedback line, and the output terminal of the buffer and the input terminal of the second source follower are connected to each other via a second feedback line.

[0025] In one embodiment, the first input switch group includes: a first switch configured to control the connection between the output terminal of the digital-to-analog converter through which it outputs analog data voltage and the input terminal of the first source follower; and a second switch located on the first feedback line and configured to control the connection between the output terminal of the buffer and the input terminal of the first source follower; and the first output switch group includes: a fourth switch configured to control the connection between the second terminal of the first sampling capacitor and the first input terminal of the buffer; and a third switch configured to control the connection between the second terminal of the first sampling capacitor and the second input terminal of the buffer.

[0026] In one embodiment, the second input switch group includes: a fifth switch configured to control the connection between the output terminal of the digital-to-analog converter through its output analog data voltage and the input terminal of the second source follower; and a sixth switch located on the second feedback line and configured to control the connection between the output terminal of the buffer and the input terminal of the second source follower; and the second output switch group includes: an eighth switch configured to control the connection between the second terminal of the second sampling capacitor and the first input terminal of the buffer; and a seventh switch configured to control the connection between the second terminal of the second sampling capacitor and the second input terminal of the buffer.

[0027] According to an embodiment of the present invention, the data driver and the display device including the data driver are driven simultaneously in a time-division multiplexing manner, such that when sampling and holding operations are performed in the first sample / hold circuit, a driving operation is performed in the second sample / hold circuit, and when sampling and holding operations are performed in the second sample / hold circuit, a driving operation is performed in the first sample / hold circuit. This allows the time required for sampling and holding operations to be doubled in high-speed, high-resolution displays. Therefore, the settling time for the buffer input voltage can be increased, preventing signal distortion and signal transmission errors.

[0028] Furthermore, in the data driver and display device including the data driver according to embodiments of the present invention, the source follower inside the multi-channel sample / hold circuit is disposed at the front end of the sampling capacitor to be connected in series with the sampling capacitor, thereby reducing the equivalent capacitance inside the sample / hold circuit and thus solving the problem caused by RC delay.

[0029] Furthermore, according to embodiments of the present invention, the data driver and the display device including the data driver are configured such that the buffer output voltage is fed back to the input terminal of the source follower, so that the analog data voltage input from the digital-to-analog converter can be output to the output terminal of the buffer without voltage drop. Attached Figure Description

[0030] Figure 1 An embodiment of the display device is shown.

[0031] Figure 2 An example of a data drive is shown.

[0032] Figure 3 An embodiment of an analog drive circuit is shown.

[0033] Figure 4 An embodiment of signals used to operate an analog drive circuit is shown.

[0034] Figure 5 The illustration shows a method for describing an embodiment of the invention. Figure 3 The diagram shows the analog driving circuit in which the first sample / hold circuit performs the sampling operation and the second sample / hold circuit performs the driving operation.

[0035] Figure 6 The illustration shows a method for describing an embodiment of the invention. Figure 3 The diagram shows the analog drive circuit in which the first sample / hold circuit performs a hold operation and the second sample / hold circuit performs a drive operation.

[0036] Figure 7 The illustration shows a method for describing an embodiment of the invention. Figure 3The diagram shows a first sample / hold circuit performing a driving operation and a second sample / hold circuit performing a sampling operation in an analog driving circuit.

[0037] Figure 8 The illustration shows a method for describing an embodiment of the invention. Figure 3 The diagram shows a first sample / hold circuit performing a driving operation and a second sample / hold circuit performing a holding operation in an analog driving circuit.

[0038] Figure 9 An embodiment of the electronic device is shown.

[0039] Figure 10 An example of a smartphone is shown. Detailed Implementation

[0040] In the following description, embodiments of the inventive concept will be described in more detail with reference to the accompanying drawings. In the drawings, the same reference numerals will be used for the same elements, and repeated descriptions of the same elements will be omitted.

[0041] Figure 1 This is a block diagram illustrating an embodiment of a display device 10, which may include a display panel 100 and a display panel driver 120. The display panel driver 120 may include a timing controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500.

[0042] The display panel 100 may include a display area for displaying an image and a peripheral area adjacent to the display area. The display panel 100 may include pixels P and may display an image corresponding to input image data IMG based on light emitted from pixels P. Gate lines GL1 to GLj may extend in a first direction D1, and data lines DL1 to DL1 may extend in a second direction D2 intersecting the first direction D1.

[0043] The timing controller 200 can receive input image data IMG and input control signal CONT from an external device. For example, the input image data IMG received from the external device may include image data of multiple colors (e.g., red, green, and blue). In some embodiments, the input image data IMG may further include white image data. In one embodiment, the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT received from the external device may include a master clock signal, a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and / or other signals.

[0044] The timing controller 200 can generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, and a data signal DATA based on the input image data IMG and the input control signal CONT. The timing controller 200 can generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and output the generated first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include, for example, a vertical start signal and a gate clock signal.

[0045] The timing controller 200 can generate a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and output the generated second control signal CONT2 to the data driver 500. The second control signal CONT2 may include, for example, a level start signal and a load signal.

[0046] The timing controller 200 can generate a data signal DATA based on the input image data IMG and output the generated data signal DATA to the data driver 500.

[0047] The timing controller 200 can generate a third control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator 400. The timing controller 200 can output the generated third control signal CONT3 to the gamma reference voltage generator 400.

[0048] The gate driver 300 can generate gate signals for driving gate lines GL1 to GLj in response to a first control signal CONT1 from the timing controller 200. The gate driver 300 can output the generated gate signals to gate lines GL1 to GLj. For example, the gate driver 300 can sequentially output the gate signals to gate lines GL1 to GLj. In some embodiments, the gate driver 300 can be mounted in the peripheral area of ​​the display panel 100.

[0049] The gamma reference voltage generator 400 can generate a gamma reference voltage VGREF in response to a third control signal CONT3 from the timing controller 200. The gamma reference voltage generator 400 can provide the generated gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF can have a value corresponding to each data signal DATA. In some embodiments, the gamma reference voltage generator 400 can be located inside the timing controller 200 or inside the data driver 500.

[0050] The data driver 500 can receive the second control signal CONT2 and the data signal DATA from the timing controller 200, and can receive the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 can use the gamma reference voltage VGREF to convert the digital data signal DATA into an analog data voltage. The data driver 500 can output the analog data voltage to data lines DL1 to DL1. See below for reference. Figures 2 to 4 An embodiment of the data driver 500 is described.

[0051] Figure 2 It is shown Figure 1 A block diagram of an embodiment of the data driver 500 of the display device 10, and Figure 3 It is shown Figure 2 A circuit diagram of an embodiment of the analog drive circuit 520(k) of the data driver 500.

[0052] refer to Figure 2 The data driver 500 may include a digital driver block 510 and an analog driver block 520. The digital driver block 510 may include a shift register (SR) 511, a sample latch (SL) 512, a hold latch (HL) 513, and a level shifter (LS) 514. The shift register 511 can sequentially shift the data signal DATA. The sample latch 512 and the hold latch 513 can receive the data signal DATA to temporarily store it. The level shifter 514 can shift (e.g., increase) the level of the data signal DATA.

[0053] Analog driver block 520 may include first analog driver circuit 520(1) to i-th analog driver circuit 520(i), where i is an integer greater than or equal to 2. An analog driver circuit 520(k) may include a digital-to-analog converter (DAC) 530, a multi-channel sample / hold (S / H) circuit 540, and a buffer (B) 550. The value of k may be an integer greater than or equal to 1 and less than or equal to i.

[0054] The digital-to-analog converter 530 can convert digital data signals DATA into analog data voltages based on a gamma reference voltage VGREF.

[0055] The multi-channel sample-and-hold circuit 540 can sample analog data voltages as buffer input voltages and hold the buffer input voltages.

[0056] The buffer 550 can amplify the buffer input voltage and output the amplified buffer input voltage to the corresponding data line of the display panel 100. The buffers 550 included in the first analog drive circuit 520(1) to the i-th analog drive circuit 520(i) can be connected to the first data line DL1 to the i-th data line DLi, respectively. In this case, the number of buffers 550 in the analog drive block 520 can be equal to the number of data lines DL1 to DLi.

[0057] like Figure 2 As shown, the analog drive circuit 520(k) may include a digital-to-analog converter 530 configured to convert digital data signal DATA into analog data voltage, a buffer 550 configured to amplify and output buffer input voltage, and a multi-channel sample-and-hold circuit 540 located between the digital-to-analog converter 530 and the buffer 550 and including a first sample-and-hold circuit 541 corresponding to the first channel (CH1) and a second sample-and-hold circuit 542 corresponding to the second channel (CH2).

[0058] refer to Figure 2 and Figure 3 The first sample-and-hold circuit 541 and the second sample-and-hold circuit 542 can be connected in parallel in the multi-channel sample-and-hold circuit 540. The output terminal of the digital-to-analog converter 530 can be selectively connected to either the first sample-and-hold circuit 541 or the second sample-and-hold circuit 542. The output terminal of the first sample-and-hold circuit 541 can be selectively connected to either the first input terminal BI1 or the second input terminal BI2 of the buffer 550. For example, the output terminal of the digital-to-analog converter 530 can be connected to the first sample-and-hold circuit 541, the output terminal of the first sample-and-hold circuit 541 can be connected to the second input terminal BI2 of the buffer 550, and the output terminal of the second sample-and-hold circuit 542 can be connected to the first input terminal BI1 of the buffer 550. In one embodiment, the output terminal of the digital-to-analog converter 530 can be connected to the second sample-and-hold circuit 542, the output terminal of the first sample-and-hold circuit 541 can be connected to the first input terminal BI1 of the buffer 550, and the output terminal of the second sample-and-hold circuit 542 can be connected to the second input terminal BI2 of the buffer 550.

[0059] The first sample-and-hold circuit 541 can perform a first drive operation during the nth horizontal time (where n is an integer greater than or equal to 1) to sample the analog data voltage as a buffer input voltage and maintain the buffer input voltage. The first sample-and-hold circuit 541 can also perform a second drive operation during the (n+1)th horizontal time to input the buffer input voltage to the input terminal of the buffer 550. The first drive operation may include sampling the received analog data voltage and maintaining the buffer input voltage in the sampling capacitor. The second drive operation may include amplifying the maintained buffer input voltage and inputting the amplified buffer input voltage to the input terminal of the buffer 550.

[0060] The second sample / hold circuit 542 can perform a second drive operation during the nth level time and a first drive operation during the (n+1)th level time. For example, when the first sample / hold circuit 541 performs the operation of sampling the analog data voltage and maintaining the buffer input voltage during the nth level time, the second sample / hold circuit 542 can perform a drive operation that amplifies the buffer input voltage maintained during the previous level time (e.g., the (n-1)th level time) and inputs the amplified buffer input voltage to the input terminal of the buffer 550.

[0061] The second sample-and-hold circuit 542 can perform a first drive operation during the (n+1)th level time to sample the analog data voltage as a buffer input voltage and maintain the buffer input voltage, and can perform a second drive operation during the (n+2)th level time to input the buffer input voltage to the input terminal of the buffer 550. The first sample-and-hold circuit 541 can perform the second drive operation during the (n+1)th level time and can perform the first drive operation during the (n+2)th level time. For example, when the second sample-and-hold circuit 542 performs the operation of sampling the analog data voltage and maintaining the buffer input voltage during the (n+1)th level time, the first sample-and-hold circuit 541 can perform a drive operation to amplify the buffer input voltage maintained during the previous level time (e.g., the nth level time) and input the amplified buffer input voltage to the input terminal of the buffer 550.

[0062] In other words, when the first sample-and-hold circuit 541 performs the first drive operation, the second sample-and-hold circuit 542 can perform the second drive operation. Conversely, when the second sample-and-hold circuit 542 performs the first drive operation, the first sample-and-hold circuit 541 can perform the second drive operation. Since the operations of the first sample-and-hold circuit 541 and the second sample-and-hold circuit 542 are performed alternately as described above, the multi-channel sample-and-hold circuit 540 can simultaneously perform the first drive operation and the second drive operation.

[0063] Due to the parallel connection structure and time-division simultaneous drive of the multi-channel sample / hold circuit 540 as described above, the time required to perform the first drive operation and the second drive operation can be doubled. For example, according to an embodiment of the present invention, the multi-channel sample / hold circuit 540 can ensure that each channel samples the analog data voltage as the buffer input voltage and maintains the buffer input voltage for a horizontal time (1H). Therefore, the multi-channel sample / hold circuit 540 can ensure sufficient settling time for the output voltage of the buffer 550. As a result, in high-speed, high-resolution displays, data signal transmission errors caused by backlash of the output voltage of the buffer 550 can be prevented. Furthermore, distortion of the output voltage of the buffer 550 caused by RC delay can be reduced.

[0064] refer to Figure 3 The first sample / hold circuit 541 may include a first sampling capacitor (Cs) 541sc configured to store the input voltage of the buffer, a first source follower 541sf including an input terminal configured to selectively receive an analog data voltage or a buffer output voltage Vout and an output terminal connected to a first terminal of the first sampling capacitor 541sc, a first input switch group SW1 and SW2 configured to selectively apply the analog data voltage or the buffer output voltage Vout to the input terminal of the first source follower 541sf, and a first output switch group SW3 and SW4 configured to control the connection between the second terminal of the first sampling capacitor 541sc and the first input terminal BI1 and the second input terminal BI2 of the buffer 550.

[0065] The first sampling capacitor 541sc may include a first terminal and a second terminal. The first terminal of the first sampling capacitor 541sc may be connected to the output terminal of the first source follower 541sf. The second terminal of the first sampling capacitor 541sc may be selectively connected to either the first input terminal BI1 or the second input terminal BI2 of the buffer 550. The first sampling capacitor 541sc may store and maintain the sampled buffer input voltage.

[0066] The first source follower 541sf may include input and output terminals. The input terminal of the first source follower 541sf can be connected to the output terminal of the digital-to-analog converter 530 to receive analog data voltage. The first source follower 541sf can reduce the impact of parasitic capacitance inside the first sample / hold circuit 541 on the buffer output voltage Vout.

[0067] For example, the first source follower 541sf can be positioned at the front end of the first sampling capacitor 541sc and can be connected to the first sampling capacitor 541sc. This connection structure (between the first source follower 541sf and the first sampling capacitor 541sc) can reduce the equivalent capacitance inside the first sample-and-hold circuit 541. Therefore, the RC delay generated during the first drive operation of the first sample-and-hold circuit 541 can be reduced. This can stabilize the buffer output voltage Vout of the first sample-and-hold circuit 541.

[0068] The first input switch groups SW1 and SW2 and the first output switch groups SW3 and SW4 may include multiple switches SW1, SW2, SW3, and SW4. Switches SW1, SW2, SW3, and SW4 may be implemented, for example, by transistors. The first sample-and-hold circuit 541 can selectively execute a first drive operation and a second drive operation based on the connection of the first input switch groups SW1 and SW2 and the first output switch groups SW3 and SW4.

[0069] The second sample / hold circuit 542 may include a second sampling capacitor (Cs) 542sc configured to store the input voltage of the buffer, a second source follower 542sf including an input terminal configured to selectively receive an analog data voltage or a buffer output voltage Vout and an output terminal connected to a first terminal of the second sampling capacitor 542sc, a second input switch group SW5 and SW6 configured to selectively apply the analog data voltage or the buffer output voltage Vout to the input terminal of the second source follower 542sf, and a second output switch group SW7 and SW8 configured to control the connection between the second terminal of the second sampling capacitor 542sc and the first input terminal BI1 and the second input terminal BI2 of the buffer 550.

[0070] The second sampling capacitor 542sc may include a first terminal and a second terminal. The first terminal of the second sampling capacitor 542sc may be connected to the output terminal of the second source follower 542sf. The second terminal of the second sampling capacitor 542sc may be selectively connected to either the first input terminal BI1 or the second input terminal BI2 of the buffer 550. The second sampling capacitor 542sc may be used to store and maintain the sampled buffer input voltage.

[0071] The second source follower 542sf may include input and output terminals. The input terminal of the second source follower 542sf can be connected to the output terminal of the digital-to-analog converter 530 to receive analog data voltages. The second source follower 542sf can reduce the impact of parasitic capacitance within the second sample-and-hold circuit 542 on the buffer output voltage Vout.

[0072] For example, the second source follower 542sf can be positioned at the front end of the second sampling capacitor 542sc and can be connected to the second sampling capacitor 542sc. This connection structure (between the second source follower 542sf and the second sampling capacitor 542sc) can reduce the equivalent capacitance inside the second sample / hold circuit 542. Therefore, the RC delay generated during the first drive operation of the second sample / hold circuit 542 can be reduced, thereby stabilizing the buffer output voltage Vout of the second sample / hold circuit 542.

[0073] The second input switch groups SW5 and SW6 and the second output switch groups SW7 and SW8 may include multiple switches SW5, SW6, SW7, and SW8. In this case, switches SW5, SW6, SW7, and SW8 can be implemented as transistors. The second sample-and-hold circuit 542 can selectively execute the first drive operation and the second drive operation according to the connection of the second input switch groups SW5 and SW6 and the second output switch groups SW7 and SW8.

[0074] The output terminal of buffer 550 and the input terminal of the first source follower 541sf can be connected to each other via the first feedback line FB1. The output terminal of buffer 550 and the input terminal of the second source follower 542sf can be connected to each other via the second feedback line FB2.

[0075] In one embodiment, the first source follower 541sf and the second source follower 542sf can be configured as NMOS transistors. For example, the output terminal of the buffer 550 can be connected to a first feedback line FB1 for feeding back the buffer output voltage Vout to the input terminal of the first source follower 541sf and a second feedback line FB2 for feeding back the buffer output voltage Vout to the input terminal of the second source follower 542sf.

[0076] Due to this buffer output voltage feedback structure, the analog data voltage input from the digital-to-analog converter 530 can be completely output as the buffer output voltage Vout. For example, when the analog data voltage Vgamma is applied from the digital-to-analog converter 530 to the input terminal of the first source follower 541sf, the buffer input voltage output from the output terminal of the first source follower 541sf can have a value obtained by subtracting the gate-source voltage of the first source follower 541sf from the analog data voltage Vgamma. When the buffer output voltage Vout is input to the input terminal of the first source follower 541sf through the first feedback line FB1, the buffer input voltage after the feedback input operation can have a value obtained by subtracting the gate-source voltage from the buffer output voltage Vout obtained by the gamma input operation. Therefore, the buffer output voltage Vout obtained by the gamma input operation can have a value obtained by adding the gate-source voltage to the buffer input voltage after the feedback input operation. The buffer input voltage after the feedback input operation can have a value obtained by subtracting the gate-source voltage from the analog data voltage Vgamma, such that the buffer output voltage Vout can have a value that is substantially the same as the analog data voltage Vgamma (e.g., Vout = Vgamma). Therefore, the gate-source voltage can be canceled out from the buffer output voltage Vout, so that the analog data voltage Vgamma can be completely output as the buffer output voltage Vout.

[0077] In one embodiment, the first source follower 541sf and the second source follower 542sf can be configured as PMOS transistors. For example, the output terminal of the buffer 550 can be connected to a first feedback line FB1 for feeding back the buffer output voltage Vout to the input terminal of the first source follower 541sf and a second feedback line FB2 for feeding back the buffer output voltage Vout to the input terminal of the second source follower 542sf.

[0078] Due to this buffer output voltage feedback structure, the analog data voltage input from the digital-to-analog converter 530 can be completely output as the buffer output voltage Vout. For example, when the analog data voltage Vgamma is applied from the digital-to-analog converter 530 to the input terminal of the first source follower 541sf, the buffer input voltage output from the output terminal of the first source follower 541sf can have a value obtained by adding the gate-source voltage of the first source follower 541sf to the analog data voltage Vgamma.

[0079] In this scenario, when the buffer output voltage Vout is input to the input terminal of the first source follower 541sf via the first feedback line FB1, the buffer input voltage after the feedback input operation can have a value obtained by adding the gate-source voltage to the buffer output voltage Vout obtained by the gamma input application. Therefore, the buffer output voltage Vout obtained by the gamma input application can have a value obtained by subtracting the gate-source voltage from the buffer input voltage after the feedback input operation. The buffer input voltage after the feedback input operation can have a value obtained by adding the gate-source voltage to the analog data voltage Vgamma. As a result, the buffer output voltage Vout can have a value substantially the same as the analog data voltage Vgamma (e.g., Vout = Vgamma). Therefore, the gate-source voltage can be canceled out from the buffer output voltage Vout, allowing the analog data voltage Vgamma to be output completely as the buffer output voltage Vout.

[0080] The first input switch group SW1 and SW2 may include a first switch SW1 and a second switch SW2. The first switch SW1 may be configured to control the connection between the output terminal of the digital-to-analog converter 530 through its output analog data voltage Vgamma and the input terminal of the first source follower 541sf. The second switch SW2 may be located on the first feedback line FB1 and may be configured to control the connection between the output terminal of the buffer 550 and the input terminal of the first source follower 541sf.

[0081] The first output switch group SW3 and SW4 may include a third switch SW3 and a fourth switch SW4. The fourth switch SW4 may be configured to control the connection between the second terminal of the first sampling capacitor 541sc and the first input terminal BI1 of the buffer 550. The third switch SW3 may be configured to control the connection between the second terminal of the first sampling capacitor 541sc and the second input terminal BI2 of the buffer 550.

[0082] The second input switch group SW5 and SW6 may include a fifth switch SW5 and a sixth switch SW6. The fifth switch SW5 may be configured to control the connection between the output terminal of the digital-to-analog converter 530 through its output analog data voltage Vgamma and the input terminal of the second source follower 542sf. The sixth switch SW6 may be located on the second feedback line FB2 and may be configured to control the connection between the output terminal of the buffer 550 and the input terminal of the second source follower 542sf.

[0083] The second output switch groups SW7 and SW8 may include a seventh switch SW7 and an eighth switch SW8. The eighth switch SW8 may be configured to control the connection between the second terminal of the second sampling capacitor 542sc and the first input terminal BI1 of the buffer 550. The seventh switch SW7 may be configured to control the connection between the second terminal of the second sampling capacitor 542sc and the second input terminal BI2 of the buffer 550. (Refer to the following...) Figure 4 An embodiment describing the operation of switches SW1 to SW8.

[0084] Figure 4 It is used for operation Figure 3 An embodiment of the timing diagram of switches SW1 to SW8 included in the analog drive circuit 520(k).

[0085] refer to Figure 3 and Figure 4 Switches SW1 through SW8 can be turned on and off by a switch control signal from the timing controller 200. Switches SW1 through SW8 can be implemented, for example, by transistors, and each switch can be turned on when a first predetermined voltage (e.g., 10V) is applied as an input and turned off when a second predetermined voltage (e.g., 0V) is applied as an input. However, this is an example of switch operation, and in other embodiments, the on / off voltages may differ, for example, depending on the type of transistor used to implement switches SW1 through SW8.

[0086] Each of switches SW1 to SW8 can repeatedly perform a predetermined operation according to a switch control signal at a period of 2H. In one embodiment, the unit interval for repeatedly performing the switch operation (e.g., two horizontal times (2H)) can be divided into the Mth interval, the (M+1)th interval, the (M+2)th interval, and the (M+3)th interval. For example, the sum of the Mth interval and the (M+1)th interval can be a horizontal time (1H), and the sum of the (M+2)th interval and the (M+3)th interval can be a horizontal time (1H).

[0087] The first switch SW1 can be turned on during the Mth interval and turned off during the intervals from M+1 to M+3. The second switch SW2 can be turned off during the Mth and M+1th intervals and turned on during the M+2 and M+3th intervals. The third switch SW3 can be turned on during the Mth interval and turned off during the intervals from M+1 to M+3. The fourth switch SW4 can be turned off during the Mth and M+1th intervals and turned on during the M+2 and M+3th intervals. The fifth switch SW5 can be turned off during the Mth and M+1th intervals, turned on during the M+2th interval, and turned off during the M+3th interval. The sixth switch SW6 can be turned on during the Mth and M+1th intervals and turned off during the M+2 and M+3th intervals. The seventh switch SW7 can be turned off during the Mth and M+1th intervals, turned on during the M+2th interval, and turned off during the M+3th interval. The eighth switch SW8 can be turned on during the Mth and M+1th intervals and turned off during the M+2 and M+3th intervals.

[0088] In one embodiment, the first sample / hold circuit 541 can perform a sampling operation during the Mth interval, a holding operation during the M+1th interval, and a driving operation during the M+2th and M+3th intervals. For example, during the Mth interval, the first switch SW1 can be turned on, the second switch SW2 can be turned off, the third switch SW3 can be turned on, and the fourth switch SW4 can be turned off. As a result, the first sample / hold circuit 541 can perform a sampling operation.

[0089] During the (M+1)th interval, the first switch SW1 can be turned off, the second switch SW2 can be turned off, the third switch SW3 can be turned off, and the fourth switch SW4 can be turned off. As a result, the first sample / hold circuit 541 can perform a hold operation.

[0090] During the M+2 and M+3 intervals, the first switch SW1 can be turned off, the second switch SW2 can be turned on, the third switch SW3 can be turned off, and the fourth switch SW4 can be turned on. As a result, the first sample / hold circuit 541 can perform a drive operation.

[0091] The second sample-and-hold circuit 542 can perform a drive operation during the Mth and M+1th intervals, a sampling operation during the M+2th interval, and a hold operation during the M+3th interval. For example, during the Mth and M+1th intervals, the fifth switch SW5 can be open, the sixth switch SW6 can be closed, the seventh switch SW7 can be open, and the eighth switch SW8 can be closed. As a result, the second sample-and-hold circuit 542 can perform a drive operation.

[0092] During the M+2th interval, the fifth switch SW5 can be turned on, the sixth switch SW6 can be turned off, the seventh switch SW7 can be turned on, and the eighth switch SW8 can be turned off. As a result, the second sample / hold circuit 542 can perform a sampling operation.

[0093] During the M+3 interval, the fifth switch SW5 can be turned off, the sixth switch SW6 can be turned off, the seventh switch SW7 can be turned off, and the eighth switch SW8 can be turned off. As a result, the second sample / hold circuit 542 can perform a hold operation.

[0094] The buffer input voltage can be divided into a first buffer input voltage driven by the first sample / hold circuit 541 and a second buffer input voltage driven by the second sample / hold circuit 542. For example, when the first sample / hold circuit 541 performs a first drive operation, the first buffer input voltage can be stored and maintained in the first sampling capacitor 541sc. When the first sample / hold circuit 541 performs a second drive operation, the first buffer input voltage can be input to the first input terminal BI1 of the buffer 550. When the second sample / hold circuit 542 performs a first drive operation, the second buffer input voltage can be stored and maintained in the second sampling capacitor 542sc. When the second sample / hold circuit 542 performs a second drive operation, the second buffer input voltage can be input to the first input terminal BI1 of the buffer 550.

[0095] As described above, the first buffer input voltage and the second buffer input voltage are alternately input to the first input terminal BI1 of the buffer 550, so that the buffer output voltage Vout can be maintained at a predetermined level. For example, when the second sample / hold circuit 542 performs a drive operation during the Mth interval and the M+1th interval, the second buffer input voltage can be input to the first input terminal BI1 of the buffer 550 to maintain the buffer output voltage Vout. When the first sample / hold circuit 541 performs a drive operation during the M+2th interval and the M+3th interval, the first buffer input voltage can be input to the first input terminal BI1 of the buffer 550 to maintain the buffer output voltage Vout.

[0096] Figure 5 It is used to describe where Figure 3 The figure shows an embodiment of the analog drive circuit 520(k) in which the first sample / hold circuit 541 performs a sampling operation and the second sample / hold circuit 542 performs a driving operation.

[0097] refer to Figure 5When the first sample / hold circuit 541 performs a sampling operation and the second sample / hold circuit 542 performs a driving operation, the first switch SW1 can be turned on, the second switch SW2 can be turned off, the third switch SW3 can be turned on, the fourth switch SW4 can be turned off, the fifth switch SW5 can be turned off, the sixth switch SW6 can be turned on, the seventh switch SW7 can be turned off and the eighth switch SW8 can be turned on.

[0098] For example, when the first sample-and-hold circuit 541 performs a sampling operation, the output terminal of the digital-to-analog converter 530 through its output analog data voltage Vgamma can be connected to the input terminal of the first source follower 541sf, and the second terminal of the first sampling capacitor 541sc can be connected to the second input terminal BI2 of the buffer 550. When the second sample-and-hold circuit 542 performs a drive operation, the second terminal of the second sampling capacitor 542sc can be connected to the first input terminal BI1 of the buffer 550, and the output terminal of the buffer 550 can be connected to the input terminal of the second source follower 542sf through the second feedback line FB2.

[0099] For example, when the first switch SW1 is on, the second switch SW2 is off, the third switch SW3 is on, and the fourth switch SW4 is off, the output terminal of the digital-to-analog converter 530 through its output analog data voltage Vgamma can be connected to the input terminal of the first source follower 541sf, and the second terminal of the first sampling capacitor 541sc can be connected to the second input terminal BI2 of the buffer 550. As a result, the analog data voltage Vgamma can be sampled as the input voltage of the first buffer.

[0100] When the fifth switch SW5 is open, the sixth switch SW6 is closed, the seventh switch SW7 is open, and the eighth switch SW8 is closed, the second terminal of the second sampling capacitor 542sc can be connected to the first input terminal BI1 of the buffer 550, and the output terminal of the buffer 550 can be connected to the input terminal of the second source follower 542sf through the second feedback line FB2. As a result, the second buffer input voltage can be input to the first input terminal BI1 of the buffer 550.

[0101] Figure 6 It is used to describe where Figure 3 The figure shows an embodiment of the analog drive circuit 520(k) in which the first sample / hold circuit 541 performs a hold operation and the second sample / hold circuit 542 performs a drive operation.

[0102] refer to Figure 6When the first sample / hold circuit 541 performs a hold operation and the second sample / hold circuit 542 performs a drive operation, the first switch SW1 can be turned off, the second switch SW2 can be turned off, the third switch SW3 can be turned off, the fourth switch SW4 can be turned off, the fifth switch SW5 can be turned off, the sixth switch SW6 can be turned on, the seventh switch SW7 can be turned off and the eighth switch SW8 can be turned on.

[0103] For example, when the first sample-and-hold circuit 541 performs a hold operation, the input terminal of the first source follower 541sf and the second terminal of the first sampling capacitor 541sc can be disconnected from the multi-channel sample-and-hold circuit 540. When the second sample-and-hold circuit 542 performs a drive operation, the second terminal of the second sampling capacitor 542sc can be connected to the first input terminal BI1 of the buffer 550, and the output terminal of the buffer 550 can be connected to the input terminal of the second source follower 542sf through the second feedback line FB2.

[0104] For example, when the first switch SW1 is open, the second switch SW2 is open, the third switch SW3 is open, and the fourth switch SW4 is open, the input terminal of the first source follower 541sf and the second terminal of the first sampling capacitor 541sc can be disconnected from the multichannel sample / hold circuit 540. As a result, the input voltage of the first buffer can be maintained in the first sampling capacitor 541sc.

[0105] When the fifth switch SW5 is open, the sixth switch SW6 is closed, the seventh switch SW7 is open, and the eighth switch SW8 is closed, the second terminal of the second sampling capacitor 542sc can be connected to the first input terminal BI1 of the buffer 550, and the output terminal of the buffer 550 can be connected to the input terminal of the second source follower 542sf through the second feedback line FB2. As a result, the second buffer input voltage can be input to the first input terminal BI1 of the buffer 550.

[0106] Figure 7 It is used to describe where Figure 3 The figure shows an embodiment of the analog drive circuit 520(k) in which the first sample / hold circuit 541 performs a drive operation and the second sample / hold circuit 542 performs a sampling operation.

[0107] refer to Figure 7 When the first sample / hold circuit 541 performs a drive operation and the second sample / hold circuit 542 performs a sampling operation, the first switch SW1 can be turned off, the second switch SW2 can be turned on, the third switch SW3 can be turned off, the fourth switch SW4 can be turned on, the fifth switch SW5 can be turned on, the sixth switch SW6 can be turned off, the seventh switch SW7 can be turned on and the eighth switch SW8 can be turned off.

[0108] For example, when the first sample / hold circuit 541 performs a drive operation, the second terminal of the first sampling capacitor 541sc can be connected to the first input terminal BI1 of the buffer 550, and the output terminal of the buffer 550 can be connected to the input terminal of the first source follower 541sf through the first feedback line FB1.

[0109] When the second sample / hold circuit 542 performs a sampling operation, the output terminal of the digital-to-analog converter 530 through its output analog data voltage Vgamma can be connected to the input terminal of the second source follower 542sf, and the second terminal of the second sampling capacitor 542sc can be connected to the second input terminal BI2 of the buffer 550.

[0110] For example, when the first switch SW1 is open, the second switch SW2 is closed, the third switch SW3 is open, and the fourth switch SW4 is closed, the second terminal of the first sampling capacitor 541sc can be connected to the first input terminal BI1 of the buffer 550, and the output terminal of the buffer 550 can be connected to the input terminal of the first source follower 541sf through the first feedback line FB1. As a result, the first buffer input voltage can be input to the first input terminal BI1 of the buffer 550.

[0111] When the fifth switch SW5 is on, the sixth switch SW6 is off, the seventh switch SW7 is on, and the eighth switch SW8 is off, the output terminal of the digital-to-analog converter 530 through its output analog data voltage Vgamma can be connected to the input terminal of the second source follower 542sf, and the second terminal of the second sampling capacitor 542sc can be connected to the second input terminal BI2 of the buffer 550. As a result, the analog data voltage Vgamma can be sampled as the input voltage of the second buffer.

[0112] Figure 8 It is used to describe where Figure 3 The figure shows an embodiment of the analog drive circuit 520(k) in which the first sample / hold circuit 541 performs a drive operation and the second sample / hold circuit 542 performs a hold operation.

[0113] refer to Figure 8 When the first sample / hold circuit 541 performs a drive operation and the second sample / hold circuit 542 performs a hold operation, the first switch SW1 can be turned off, the second switch SW2 can be turned on, the third switch SW3 can be turned off, the fourth switch SW4 can be turned on, the fifth switch SW5 can be turned off, the sixth switch SW6 can be turned off, the seventh switch SW7 can be turned off and the eighth switch SW8 can be turned off.

[0114] For example, when the first sample / hold circuit 541 performs a drive operation, the second terminal of the first sampling capacitor 541sc can be connected to the first input terminal BI1 of the buffer 550, and the output terminal of the buffer 550 can be connected to the input terminal of the first source follower 541sf through the first feedback line FB1.

[0115] When the second sample / hold circuit 542 performs a hold operation, the input terminal of the second source follower 542sf and the second terminal of the second sampling capacitor 542sc can be disconnected from the multichannel sample / hold circuit 540.

[0116] For example, when the first switch SW1 is open, the second switch SW2 is closed, the third switch SW3 is open, and the fourth switch SW4 is closed, the second terminal of the first sampling capacitor 541sc can be connected to the first input terminal BI1 of the buffer 550, and the output terminal of the buffer 550 can be connected to the input terminal of the first source follower 541sf through the first feedback line FB1. As a result, the first buffer input voltage can be input to the first input terminal BI1 of the buffer 550.

[0117] When the fifth switch SW5, the sixth switch SW6, the seventh switch SW7, and the eighth switch SW8 are open, the input terminal of the second source follower 542sf and the second terminal of the second sampling capacitor 542sc can be disconnected from the multichannel sample-and-hold circuit 540. As a result, the input voltage of the second buffer can be maintained in the second sampling capacitor 542sc.

[0118] As described above, according to the control of switches SW1 to SW8, when the first sample / hold circuit 541 performs sampling and holding operations, the second sample / hold circuit 542 can perform a drive operation. Furthermore, when the second sample / hold circuit 542 performs sampling and holding operations, the first sample / hold circuit 541 can perform a drive operation. Due to the parallel connection structure of the first sample / hold circuit 541 and the second sample / hold circuit 542 and the time-division simultaneous drive, as described above, the time for performing the first and second drive operations can be doubled. For example, according to an embodiment of the present invention, the multi-channel sample / hold circuit 540 can ensure that each channel samples the analog data voltage as the buffer input voltage and maintains the buffer input voltage for a horizontal time (1H). Therefore, the multi-channel sample / hold circuit 540 can ensure sufficient settling time for the output voltage of the buffer 550. As a result, in high-speed, high-resolution displays, data signal transmission errors caused by backlash of the output voltage of the buffer 550 can be prevented. Furthermore, distortion of the output voltage of the buffer 550 caused by RC delay can be reduced.

[0119] Figure 9 This is a block diagram illustrating an electronic device 1000 according to an embodiment of the concept of the present invention. Figure 10 It is shown that Figure 9 The diagram shows an example of an electronic device 1000 implemented as a smartphone.

[0120] refer to Figure 9 and Figure 10 Electronic device 1000 may include a processor 1010, a storage device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. Furthermore, electronic device 1000 may include multiple ports for communicating with video cards, sound cards, memory cards, Universal Serial Bus (USB) devices, and other electronic devices. In embodiments, such as... Figure 10 As shown, electronic device 1000 can be implemented as a smartphone. However, electronic device 1000 is not limited to this. For example, electronic device 1000 can be implemented as a cellular phone, video phone, smart tablet, smartwatch, tablet PC, car navigation system, computer monitor, laptop computer, head-mounted display (HMD) device or other device.

[0121] Processor 1010 can perform various computing functions. Processor 1010 can be a microprocessor, central processing unit (CPU), application processor (AP), or other types of processor. Processor 1010 can be coupled to other components via address bus, control bus, and data bus, etc. In addition, processor 1010 can be coupled to an expansion bus such as the peripheral component interconnect (PCI) bus.

[0122] Storage device 1020 can store data for the operation of electronic device 1000. For example, storage device 1020 may include at least one non-volatile memory device such as erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, phase-change random access memory (PRAM), resistive random access memory (RRAM), nanofloating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), or ferroelectric random access memory (FRAM) and / or at least one volatile memory device such as dynamic random access memory (DRAM), static random access memory (SRAM), or mobile DRAM.

[0123] Storage device 1030 may include solid-state drive (SSD) device, hard disk drive (HDD) device, CD-ROM device or other types of device.

[0124] I / O device 1040 may include input devices such as a keyboard, keypad, mouse, touchpad, or touchscreen, or output devices such as a printer or speaker. In some embodiments, I / O device 1040 may include display device 1060.

[0125] Power supply 1050 can provide power for the operation of electronic device 1000.

[0126] The display device 1060 can display an image corresponding to the visual information of the electronic device 1000. The display device 1060 may include a data driver configured to apply an analog data voltage to the display panel. The data driver may include a digital-to-analog converter configured to convert a digital data signal into an analog data voltage, a buffer configured to output an analog data voltage, and a multi-channel sample-and-hold circuit located between the digital-to-analog converter and the buffer, including a first sample-and-hold circuit connected to a first channel and a second sample-and-hold circuit connected to a second channel.

[0127] According to one or more embodiments, the first sample / hold circuit is configured to perform a first drive operation during a nth level time (where n is an integer greater than or equal to 1) to sample the analog data voltage as a buffer input voltage and maintain the buffer input voltage. The first sample / hold circuit is further configured to perform a second drive operation during a (n+1)th level time to input the buffer input voltage to the input terminal of the buffer.

[0128] The second sample / hold circuit is configured to perform a second drive operation during the nth level time and a first drive operation during the (n+1)th level time.

[0129] The display device 1060, including a data driver, can perform time-division simultaneous driving, such that when sampling and holding operations are performed in the first sample / hold circuit, a driving operation is performed in the second sample / hold circuit, and vice versa. Therefore, in a high-speed, high-resolution display, the time used for sampling and holding operations can be doubled. Consequently, the settling time for the buffer input voltage can be increased, preventing signal distortion and signal transmission errors. However, since these have been described above, related repetitive descriptions will not be repeated.

[0130] According to one embodiment, a multi-channel sample-and-hold circuit includes a first sample-and-hold circuit connected to a first channel and a second sample-and-hold circuit connected to a second channel. The first sample-and-hold circuit performs a first drive operation and a second drive operation. The first drive operation includes sampling an analog data voltage as a buffer input voltage during an nth level time and maintaining the buffer input voltage. The second drive operation includes inputting the buffer input voltage to the input terminal of the buffer during an (n+1)th level time. The second sample-and-hold circuit is configured to perform the second drive operation during the nth level time and the first drive operation during the (n+1)th level time, where n is an integer greater than or equal to 1. This multi-channel sample-and-hold circuit can be used to display image data in a display device or for any other application in which data sampling and holding operations are performed.

[0131] The methods, processes, and / or operations described herein can be executed by code or instructions that are run by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device can be the elements described herein or other elements besides those described herein. Because the algorithms underlying the methods (or the operation of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions used to implement the operations of the method embodiments can transform a computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0132] In addition, another embodiment may include a computer-readable medium (e.g., a non-transitory computer-readable medium) for storing the code or instructions described above. The computer-readable medium may be a volatile or non-volatile memory or other storage device that is removably or permanently coupled to a computer, processor, controller, or other signal processing apparatus that will execute code or instructions for performing operations of the method or apparatus embodiments described herein.

[0133] The controllers, processors, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, converters, drivers, and other signal generation and signal processing features disclosed in the embodiments herein can be implemented, for example, in non-transitory logic that may include hardware, software, or both. When implemented at least partially in hardware, the controllers, processors, devices, modules, converters, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features can be any of a variety of integrated circuits, including but not limited to application-specific integrated circuits, field-programmable gate arrays, combinations of logic gates, systems-on-a-chip, microprocessors, or other types of processing or control circuitry.

[0134] When implemented at least partially in software, controllers, processors, devices, modules, units, multiplexers, generators, logic, converters, interfaces, decoders, drivers, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be the elements described herein or elements other than those described herein. Because the algorithms underlying the formation of the methods (or the operation of the computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method embodiments can transform the computer, processor, controller, or other signal processing device into a dedicated processor for performing the methods described herein.

[0135] The foregoing is illustrative of the inventive concept and should not be construed as limiting it. Although some embodiments of the inventive concept have been described, those skilled in the art will readily understand that many modifications are possible to the embodiments without substantially departing from the novel teachings of the inventive concept. Accordingly, these modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, the means plus function clause is intended to cover structures described herein as performing the detailed functions, and not only structural equivalents but also equivalent structures. Therefore, it should be understood that the foregoing is illustrative of the inventive concept and should not be construed as limiting it to the specific embodiments disclosed, and is intended to include modifications to the disclosed embodiments and other embodiments within the scope of the appended claims. The inventive concept is defined by the appended claims, including equivalents of the claims. Embodiments may be combined to form additional embodiments.

Claims

1. A data driver, comprising: A digital-to-analog converter is configured to convert digital data signals into analog data voltages. A buffer is configured to output the analog data voltage; as well as A multi-channel sample-and-hold circuit is electrically connected between the digital-to-analog converter and the buffer. The multi-channel sample-and-hold circuit includes a first sample-and-hold circuit connected to a first channel and a second sample-and-hold circuit connected to a second channel, wherein: The first sample-and-hold circuit is configured to perform a first drive operation during the nth level time period to sample the analog data voltage as a buffer input voltage and maintain the buffer input voltage, and to perform a second drive operation during the (n+1)th level time period to input the buffer input voltage to the input terminal of the buffer. The second sample / hold circuit is configured to perform the second drive operation during the nth level time and the first drive operation during the (n+1)th level time, where n is an integer greater than or equal to 1. The output terminal of the buffer is selectively connected to the first sample / hold circuit via a first feedback line and selectively connected to the second sample / hold circuit via a second feedback line.

2. The data driver according to claim 1, wherein, The first sample / hold circuit includes: The first sampling capacitor is configured to store the input voltage of the buffer; The first source follower includes an input terminal configured to selectively receive the analog data voltage or the buffer output voltage and an output terminal connected to a first terminal of the first sampling capacitor. A first input switch group is configured to selectively apply either the analog data voltage or the buffer output voltage to the input terminals of the first source follower; and A first output switch group is configured to control the connection between the second terminal of the first sampling capacitor and the first and second input terminals of the buffer, wherein the input terminals of the buffer include the first and second input terminals of the buffer.

3. The data driver according to claim 2, wherein, The second sample / hold circuit includes: The second sampling capacitor is configured to store the input voltage of the buffer. The second source follower includes an input terminal configured to selectively receive the analog data voltage or the buffer output voltage and an output terminal connected to a first terminal of the second sampling capacitor. The second input switch group is configured to selectively apply either the analog data voltage or the buffer output voltage to the input terminals of the second source follower; and The second output switch group is configured to control the connection between the second terminal of the second sampling capacitor and the first and second input terminals of the buffer.

4. The data driver according to claim 3, wherein: The output terminal of the buffer is connected to the input terminal of the first source follower via the first feedback line, and The output terminal of the buffer is connected to the input terminal of the second source follower via the second feedback line.

5. The data driver according to claim 4, wherein, The first input switch group includes: A first switch is configured to control the connection between the output terminal of the digital-to-analog converter and the input terminal of the first source follower, wherein the analog data voltage is output through the output terminal of the digital-to-analog converter; and A second switch is located on the first feedback line and is configured to control the connection between the output terminal of the buffer and the input terminal of the first source follower.

6. The data driver according to claim 5, wherein, The first output switch group includes: A fourth switch is configured to control the connection between the second terminal of the first sampling capacitor and the first input terminal of the buffer; and A third switch is configured to control the connection between the second terminal of the first sampling capacitor and the second input terminal of the buffer.

7. The data driver according to claim 6, wherein, The second input switch group includes: A fifth switch is configured to control the connection between the output terminal of the digital-to-analog converter and the input terminal of the second source follower; and A sixth switch, located on the second feedback line and configured to control the connection between the output terminal of the buffer and the input terminal of the second source follower.

8. The data driver according to claim 7, wherein, The second output switch group includes: An eighth switch is configured to control the connection between the second terminal of the second sampling capacitor and the first input terminal of the buffer; and A seventh switch is configured to control the connection between the second terminal of the second sampling capacitor and the second input terminal of the buffer.

9. The data driver according to claim 8, wherein: When the first sample / hold circuit performs the first drive operation, the sixth switch and the eighth switch are turned on, and the second switch, the fourth switch, the fifth switch and the seventh switch are turned off.

10. The data driver according to claim 8, wherein: When the first sample / hold circuit performs the second drive operation, the second switch and the fourth switch are turned on, and the first switch, the third switch, the sixth switch and the eighth switch are turned off.

11. The data driver according to claim 8, wherein: The first sample / hold circuit is configured to sample the analog data voltage as the buffer input voltage when the first switch, the third switch, the sixth switch, and the eighth switch are on and the second switch, the fourth switch, the fifth switch, and the seventh switch are off. The first sample / hold circuit is configured to maintain the buffer input voltage when the sixth and eighth switches are turned on and the first, second, third, fourth, fifth, and seventh switches are turned off.

12. The data driver according to claim 8, wherein: When the second sample / hold circuit performs the first drive operation, the second switch and the fourth switch are turned on, and the first switch, the third switch, the sixth switch and the eighth switch are turned off.

13. The data driver according to claim 8, wherein: When the second sample / hold circuit performs the second drive operation, the sixth switch and the eighth switch are turned on, and the second switch, the fourth switch, the fifth switch and the seventh switch are turned off.

14. The data driver according to claim 8, wherein: The second sample / hold circuit is configured to sample the analog data voltage as the buffer input voltage when the second switch, the fourth switch, the fifth switch, and the seventh switch are turned on and the first switch, the third switch, the sixth switch, and the eighth switch are turned off; and The second sample / hold circuit is configured to maintain the buffer input voltage when the second switch and the fourth switch are turned on and the first switch, the third switch, the fifth switch, the sixth switch, the seventh switch, and the eighth switch are turned off.

15. A display device, comprising: Display panel; A gate driver is configured to apply gate signals to the display panel; A data driver is configured to apply analog data voltages to the display panel; as well as A timing controller is configured to control the gate driver and the data driver. The data driver includes: A digital-to-analog converter is configured to convert digital data signals into said analog data voltages; A buffer is configured to output the analog data voltage; and A multi-channel sample-and-hold circuit is electrically connected between the digital-to-analog converter and the buffer. The multi-channel sample-and-hold circuit includes a first sample-and-hold circuit connected to a first channel and a second sample-and-hold circuit connected to a second channel, wherein: The first sample-and-hold circuit is configured to perform a first drive operation during the nth level time period to sample the analog data voltage as a buffer input voltage and maintain the buffer input voltage, and to perform a second drive operation during the (n+1)th level time period to input the buffer input voltage to the input terminal of the buffer. The second sample / hold circuit is configured to perform the second drive operation during the nth level time and the first drive operation during the (n+1)th level time, where n is an integer greater than or equal to 1. The output terminal of the buffer is selectively connected to the first sample / hold circuit via a first feedback line and selectively connected to the second sample / hold circuit via a second feedback line.

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