Output buffer circuit

Abstract

An output buffer circuit is provided, including an operational amplifier configured to generate an amplifier output voltage signal based on an input voltage signal and a compensation current, a slew rate compensation circuit configured to generate the compensation current based on a difference between the input voltage signal and a feedback voltage signal to increase a slew rate of the amplifier output voltage signal, an output path circuit connected between the operational amplifier and an output pad, the output path circuit configured to transmit the amplifier output voltage signal to generate a pad output voltage signal through the output pad, and a feedback path circuit connected between the slew rate compensation circuit and a feedback input node on the output path circuit, the feedback path circuit configured to generate the feedback voltage signal.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0128520, filed on October 6, 2020, with the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Some example embodiments generally relate to semiconductor integrated circuits, and more specifically, to an output buffer circuit and / or a source driver for a display device including an output buffer circuit. Background Technology

[0004] The power consumption of a display device increases with its resolution, size, and / or operating speed. Recently, 120Hz frame rates have been adopted in mobile devices such as smartphones, leading to a significant increase in the power consumption of the display driver integrated circuit (DDI). A DDI can be divided into analog and digital sections. For example, in Wide Quad High Definition (WQHD) products, the analog section accounts for approximately 66% of the total power consumption of the DDI. The power consumption of the analog section can be further divided into the power consumption of the source drivers and the power consumption of other components such as voltage regulators, charge pumps, and low-temperature polysilicon (LTPS) drivers. For instance, the source drivers of a DDI include a large number of source amplifiers or output buffers; in WQHD products, there are 2880 output buffers, and the power consumption of the source drivers accounts for 46% of the power consumption of the analog section. Summary of the Invention

[0005] Some example embodiments may provide an output buffer circuit that can reduce power consumption.

[0006] Alternatively or additionally, some example embodiments may provide a source driver for a display device that includes an output buffer circuit capable of reducing power consumption.

[0007] According to some example embodiments, an output buffer circuit includes: an operational amplifier configured to generate an amplifier output voltage signal based on an input voltage signal and a compensation current; a slew rate compensation circuit configured to generate a compensation current based on the difference between the input voltage signal and a feedback voltage signal to increase the slew rate of the amplifier output voltage signal; an output path circuit connected between the operational amplifier and an output pad, the output path circuit being configured to transmit the amplifier output voltage signal to generate a pad output voltage signal through the output pad; and a feedback path circuit connected between the slew rate compensation circuit and a feedback input node on the output path circuit, the feedback path circuit being configured to generate a feedback voltage signal.

[0008] According to some example embodiments, a source driver for a display device includes: a plurality of output buffer circuits configured to drive the source lines of a display panel, each of the plurality of output buffer circuits being configured to generate an amplifier output voltage signal based on an input voltage signal and a compensation current to generate a feedback voltage signal with a slew rate less than that of the amplifier output voltage signal, and to generate a compensation current to increase the slew rate of the amplifier output voltage signal, thereby increasing the slew rate of the amplifier output voltage signal based on the difference between the input voltage signal and the feedback voltage signal.

[0009] According to some example embodiments, a source driver for a display device includes: a shift register configured to generate a plurality of latching clock signals based on a clock signal and an input-output control signal; a data latch configured to store data in response to the plurality of latching clock signals and to output a plurality of digital input signals corresponding to the data in response to a load signal; a digital-to-analog converter configured to generate a plurality of input voltage signals corresponding to the plurality of digital input signals, and to generate the plurality of input voltage signals using grayscale voltage; and a plurality of output buffer circuits configured to buffer the plurality of input voltage signals to drive the source lines of a display panel. Each of the buffer circuits includes: an operational amplifier configured to generate an amplifier output voltage signal based on each of an input voltage signal and a compensation current; a slew rate compensation circuit configured to generate a compensation current based on the difference between each of the input voltage signals and a feedback voltage signal to increase the slew rate of the amplifier output voltage signal; an output path circuit connected between the operational amplifier and an output pad, configured to transmit the amplifier output voltage signal to generate a pad output voltage signal through the output pad; and a feedback path circuit connected between the slew rate compensation circuit and a feedback input node on the output path circuit, configured to generate a feedback voltage signal.

[0010] According to some example embodiments, the output buffer circuit and the source driver of the display device can utilize a feedback voltage signal with a slew rate lower than that of the amplifier output voltage signal to increase the supply time of the compensation current. By increasing the supply time of the compensation current, power consumption can be reduced and / or the performance of the output buffer circuit and the source driver can be improved. Attached Figure Description

[0011] Some exemplary embodiments of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0012] Figure 1 This is a block diagram illustrating an output buffer circuit according to some example embodiments.

[0013] Figure 2 This is a waveform diagram showing the voltage signal of an output buffer circuit according to some example embodiments.

[0014] Figure 3 This is a flowchart illustrating a method for improving the slew rate of an output buffer circuit according to some example embodiments.

[0015] Figure 4 It is shown Figure 1 Block diagrams of some example embodiments of operational amplifiers included in the output buffer circuit.

[0016] Figure 5 It is shown Figure 4 Circuit diagrams of some example embodiments of the input stage and bias circuitry included in the operational amplifier.

[0017] Figure 6 It is shown Figure 4 Circuit diagrams of some example embodiments of the load stage and output stage included in the operational amplifier.

[0018] Figure 7 It is shown Figure 1 Block diagrams of some example embodiments of the slew rate compensation circuit included in the output buffer circuit.

[0019] Figure 8 It is shown Figure 7 Circuit diagrams of some example embodiments of the slew rate compensation circuit.

[0020] Figure 9 It is a waveform diagram used to describe the compensation time of the output buffer circuit according to some example embodiments.

[0021] Figure 10 , Figure 11 and Figure 12 This is a diagram illustrating an output buffer circuit according to some example embodiments.

[0022] Figure 13 This is a diagram illustrating an output buffer circuit according to some example embodiments. Figure 14 It is shown Figure 13 The timing diagram for the operation of the output buffer circuit.

[0023] Figure 15 This is a block diagram illustrating a display system according to some example embodiments.

[0024] Figure 16 This is a block diagram illustrating a display device according to some example embodiments.

[0025] Figure 17 This is a block diagram illustrating the source driver of a display device according to some example embodiments.

[0026] Figure 18This is a diagram illustrating a general output buffer circuit and an output buffer circuit according to some example embodiments.

[0027] Figure 19 It is shown Figure 18 The timing diagram for the operation of the output buffer circuit.

[0028] Figure 20 It is shown Figure 18 A diagram showing the transition time and power consumption of the output buffer circuit.

[0029] Figure 21 This is a block diagram illustrating a mobile device according to some example embodiments.

[0030] Figure 22 This is a block diagram illustrating a computing system according to some example embodiments. Detailed Implementation

[0031] Various non-limiting exemplary embodiments will be described more fully below with reference to the accompanying drawings, in which some exemplary embodiments are illustrated. In the drawings, the same reference numerals always refer to the same elements. Repeated descriptions may be omitted.

[0032] Figure 1 This is a block diagram illustrating an output buffer circuit according to some example embodiments.

[0033] Reference Figure 1 The output buffer circuit 10 includes an operational amplifier AMP 100, a slew rate compensation circuit SRCC 200, an output path circuit OPC 300, and a feedback path circuit FPC 400.

[0034] Operational amplifier 100 can generate an amplifier output voltage signal VAO based on an input voltage signal VIN and a compensation current. The compensation current may include a pull-up compensation current ICU and a pull-down compensation current ICD. Operational amplifier 100 can receive the input voltage signal VIN through a positive terminal (+), receive the amplifier output voltage signal VAO through a negative terminal (-), and output the amplifier output voltage signal VAO through an output terminal (e.g., through the amplifier output node NAO). The following will refer to... Figure 4 , Figure 5 and Figure 6 Some example embodiments of the operational amplifier 100 are described.

[0035] The slew rate compensation circuit 200 can generate compensation currents ICU and ICD based on the difference between the input voltage signal VIN and the feedback voltage signal VFB to increase the slew rate of the amplifier output voltage signal VAO, for example, the larger or maximum rate of change of the output voltage per unit time. The compensation currents ICU and ICD may include a pull-up compensation current ICU to increase the slew rate at the rising edge of the amplifier output voltage signal VAO, and / or may include a pull-down compensation current ICD to increase the slew rate at the falling edge of the amplifier output voltage signal VAO. The following will refer to... Figure 7 and Figure 8 Some example embodiments of the slew rate compensation circuit 200 are described.

[0036] The output path circuit 300 can be connected between the operational amplifier 100 and the output pad PDO. The output path circuit 300 can transmit the amplifier output voltage signal VAO to generate a pad output voltage signal VPO through the output pad PDO (e.g., on the output pad PDO).

[0037] The feedback path circuit 400 can be connected between the slew rate compensation circuit 200 and the feedback input node NFI on the output path circuit 300. The feedback path circuit 400 can generate a feedback voltage signal VFB.

[0038] Below, we will refer to Figures 10 to 14 Some example embodiments of the output path circuit 300 and the feedback path circuit 400 are described. As will be described, each of the output path circuit 300 and the feedback path circuit 400 may have a corresponding impedance, and the slew rate of the voltage signal may decrease as it passes through at least a portion of the output path circuit 300 and the feedback path circuit 400. Here, "decrease in the slew rate of the voltage signal" may mean, correspond to, or indicate "increase in the delay time of the voltage signal" and / or "increase in the settling time of the voltage signal".

[0039] Figure 2 This is a waveform diagram showing the voltage signal of an output buffer circuit according to some example embodiments.

[0040] Figure 2 The waveforms of the amplifier output voltage signal VAO at the amplifier output node NAO, the voltage signal VFBI at the feedback input node NFI, and the feedback voltage signal VFB at the feedback output node NFO are shown. For example, Figure 2The diagram illustrates that the input voltage signal VIN transitions from a first voltage V1 to a second voltage V2, which is higher than the first voltage V1, at a first time point Tr, and then transitions from the second voltage V2 to a third voltage V3, which is lower than the second voltage V2, at a second time point Tf. For ease of description and illustration, it is assumed that the input voltage signal VIN is an ideal square wave; however, the example embodiment is not limited to this.

[0041] Reference Figure 1 and Figure 2 The rise time tr2 of the voltage signal VFBI at the feedback input node NFI can be increased due to the impedance of the output path circuit 300 to be longer than the rise time tr1 of the amplifier output voltage signal VAO, and the rise time tr3 of the feedback voltage signal VFB can be increased due to the impedance of the feedback path circuit 400 to be longer than the rise time tr2 of the voltage signal VFBI at the feedback input node NFI. For example, the slew rate (V2-V1) / tr2 of the rising edge of the voltage signal VFBI at the feedback input node NFI can be reduced to be less than the slew rate (V2-V1) / tr1 of the rising edge of the amplifier output voltage signal VAO, and the slew rate (V2-V1) / tr3 of the rising edge of the feedback voltage signal VFB can be reduced to be less than the slew rate (V2-V1) / tr2 of the rising edge of the voltage signal VFBI at the feedback input node NFI.

[0042] Alternatively or additionally, the fall time tr2 of the voltage signal VFBI at the feedback input node NFI may be increased due to the impedance of the output path circuit 300 to be longer than the fall time tr1 of the amplifier output voltage signal VAO, and the fall time tr3 of the feedback voltage signal VFB may be increased due to the impedance of the feedback path circuit 400 to be longer than the fall time tr2 of the voltage signal VFBI at the feedback input node NFI. For example, the slew rate (V2-V1) / tr2 at the falling edge of the voltage signal VFBI at the feedback input node NFI may be reduced to be less than the slew rate (V2-V1) / tr1 at the falling edge of the amplifier output voltage signal VAO, and the slew rate (V2-V1) / tr3 at the falling edge of the feedback voltage signal VFB may be reduced to be less than the slew rate (V2-V1) / tr2 at the falling edge of the voltage signal VFBI at the feedback input node NFI.

[0043] Thus, according to some example embodiments, the output buffer circuit 10 can utilize a feedback voltage signal VFB with a slew rate less than that of the amplifier output voltage signal VAO to increase the supply time of the compensation current ICU and ICD. In devices and systems including the output buffer circuit 10, power consumption can be reduced and / or performance can be improved by increasing the supply time of the compensation current ICU and ICD.

[0044] Figure 3This is a flowchart illustrating a method for improving the slew rate of an output buffer circuit according to some example embodiments.

[0045] Reference Figure 1 and Figure 3 The operational amplifier 100 can be used to generate the amplifier output voltage signal VAO (S100) based on the input voltage signal VIN and the compensation currents ICU and ICD.

[0046] The output path circuit 300 and the feedback path circuit 400 can be used to generate a feedback voltage signal VFB (S200) with a slew rate less than that of the amplifier output voltage signal.

[0047] The slew rate compensation circuit 200 can be used to generate compensation currents ICU and ICD (S300) to increase the slew rate of the amplifier output voltage signal VAO based on the difference between the input voltage signal VIN and the feedback voltage signal VFB.

[0048] In the following text, reference will be made to Figures 4 to 8 This section describes some example embodiments of the operational amplifier 100 and slew rate compensation circuit included in the output buffer circuit. According to some example embodiments, the supply time of the compensation current ICU and ICD can be increased using a feedback voltage signal VFB with a slew rate less than that of the amplifier output voltage signal VAO. The configuration of the operational amplifier and slew rate compensation circuit is not limited to... Figures 4 to 8 The configurations of the operational amplifiers and slew rate compensation circuits shown can be implemented differently.

[0049] Figure 4 It is shown Figure 1 Block diagrams of some example embodiments of operational amplifiers included in the output buffer circuit.

[0050] Reference Figure 4 The operational amplifier 100 may include an input stage 110, a load stage 130, an output stage 150, an upper bias circuit 170, and a lower bias circuit 180. In some example embodiments, Figure 4 The operational amplifier 100 shown may have a rail-to-rail configuration including dual input stages.

[0051] Operational amplifier 100 amplifies the input voltage signal VIN to generate the amplifier output voltage signal VAO. Figure 1 The slew rate compensation circuit 200 generates a compensation current based on the voltage difference between the input voltage signal VIN and the amplifier output voltage signal VAO, provides the compensation current to the load stage 130 of the operational amplifier 100, and reduces the transition time of the amplifier output voltage signal VAO, for example, by increasing the slew rate of the amplifier output voltage signal VAO.

[0052] Input stage 110 receives the input voltage signal VIN and the amplifier output voltage signal VAO, and determines the voltage difference between them. Load stage 130 performs slew rate compensation using pull-up compensation current ICU and pull-down compensation current ICD, generating load currents ILU, ILUB, ILD, and ILDB corresponding to the voltage difference between VIN and VAO, and provides these currents to input stage 110. Up bias circuit 170 and down bias circuit 180 provide bias current to input stage 110. Output stage 150 generates the amplifier output voltage signal VAO based on the signal provided from load stage 130 through amplifier output node NAO.

[0053] Figure 5 It is shown Figure 4 Circuit diagrams of some example embodiments of the input stage and bias circuitry included in the operational amplifier.

[0054] Reference Figure 4 and Figure 5 Input stage 110 may include a first input stage and a second input stage. The first input stage may include P-channel metal-oxide-semiconductor (hereinafter referred to as "PMOS") transistors MP1 and MP2, and may provide pull-down load currents ILD and ILDB to load stage 130. The second input stage may include N-channel metal-oxide-semiconductor (hereinafter referred to as "NMOS") transistors MN1 and MN2, and may receive pull-up load currents ILU and ILUB from load stage 130. Input voltage signal VIN is applied to the gates of transistors MP1 and MN1, and amplifier output voltage signal VAO is applied to the gates of transistors MP2 and MN2.

[0055] The upper bias circuit 170 can generate a first bias current based on a first bias voltage VB1 and can provide the first bias current to the first input stage. The lower bias circuit 180 can generate a second bias current based on a second bias voltage VB2 and can provide the second bias current to the second input stage. The upper bias circuit 170 can be implemented using a PMOS transistor MP3, and the lower bias circuit 180 can be implemented using an NMOS transistor MN3.

[0056] Figure 6 It is shown Figure 4 Circuit diagrams of some example embodiments of the load stage and output stage included in the operational amplifier.

[0057] Reference Figure 6 The load stage 130 may include an upper current mirror circuit, a lower current mirror circuit, a first connection circuit, a second connection circuit, a first capacitor C1, and a second capacitor C2.

[0058] The upper current mirror circuit may include PMOS transistors MP4 and MP5 connected to each other in a current mirror configuration and connected to a power supply such as VDD, and similarly, the lower current mirror circuit may include NMOS transistors MN4 and MN5 connected to each other in a current mirror configuration and connected to a power supply such as ground. The first connection circuit may include PMOS transistor MP7 and NMOS transistor MN7. PMOS transistor MP7 and NMOS transistor MN7 operate in response to a third bias voltage VB3 and a fourth bias voltage VB4, respectively. The second connection circuit may include PMOS transistor MP6 and NMOS transistor MN6. PMOS transistor MP6 and NMOS transistor MN6 operate in response to a third bias voltage VB3 and a fourth bias voltage VB4, respectively.

[0059] The upper current mirror circuit is electrically connected to the second input stage and provides current to the load stage 130. The lower current mirror circuit is electrically connected to the first input stage and provides current to the load stage 130. A first connection circuit electrically connects the first output terminal NCU of the upper current mirror circuit to the first output terminal NCD of the lower current mirror circuit. A second connection circuit electrically connects the second output terminal NCSP of the upper current mirror circuit to the second output terminal NCSN of the lower current mirror circuit. A first capacitor C1 is connected between the first output terminal NCU of the upper current mirror circuit and the amplifier output node NAO of the output stage 150. A second capacitor C2 is connected between the first output terminal NCD of the lower current mirror circuit and the amplifier output node NAO of the output stage 150.

[0060] Output stage 150 may include a PMOS transistor MP8. The gate of PMOS transistor MP8 is connected to the first output terminal NCU of the upper current mirror circuit, and PMOS transistor MP8 is connected between the power supply voltage VDD and the amplifier output node NAO. Output stage 150 may also include an NMOS transistor MN8. The gate of NMOS transistor MN8 is connected to the first output terminal NCD of the lower current mirror circuit, and NMOS transistor MN8 is connected between the amplifier output node NAO and ground.

[0061] The pull-down compensation current ICD can be provided to the first output terminal NCU of the upper current mirror circuit, and the pull-up compensation current ICU can be provided to the first output terminal NCD of the lower current mirror circuit.

[0062] The pull-up load current ILU can flow from the first output terminal NCU of the current mirror circuit to the second input stage of input stage 110, which includes NMOS transistors MN1 and MN2. The pull-up load current ILUB can flow from the second output terminal NCSP of the current mirror circuit to the second input stage included in input stage 110.

[0063] The pull-down load current ILD can flow from the first input stage of input stage 110, which includes PMOS transistors MP1 and MP2, to the first output terminal NCD of the pull-down current mirror circuit. The pull-down load current ILDB can flow from the first input stage included in input stage 110 to the second output terminal NCSN of the pull-down current mirror circuit.

[0064] Figure 7 It is shown Figure 1 Block diagrams of some example embodiments of the slew rate compensation circuit included in the output buffer circuit.

[0065] Reference Figure 7 The slew rate compensation circuit 200 may include a comparator 220, a pull-up compensation current generator 240, and a pull-down compensation current generator 260.

[0066] Comparator 220 compares the input voltage signal VIN with the amplifier output voltage signal VAO to generate a first current I_VDIFF corresponding to the difference between the input voltage signal VIN and the amplifier output voltage signal VAO. Pull-up compensation current generator 240 performs a current mirror operation on the first current I_VDIFF to generate a pull-up compensation current ICU. Pull-down compensation current generator 260 performs a current mirror operation on the first current I_VDIFF to generate a pull-down compensation current ICD.

[0067] Figure 8 It is shown Figure 7 Circuit diagrams of some example embodiments of the slew rate compensation circuit.

[0068] Reference Figure 8 The slew rate compensation circuit 200 includes a comparator 220, a pull-up compensation current generator 240, and a pull-down compensation current generator 260.

[0069] Comparator 220 may include an NMOS transistor MN16 and a PMOS transistor MP16. The gate of the NMOS transistor MN16 is supplied with an input voltage signal VIN, its source is supplied with a feedback voltage signal VFB, and its drain is connected to a first node N11. The gate of the PMOS transistor MP16 is supplied with an input voltage signal VIN, its source is supplied with a feedback voltage signal VFB, and its drain is connected to a second node N12.

[0070] The pull-up compensation current generator 240 may include PMOS transistors MP12, MP13, MP14 and NMOS transistors MN14_1 and MN15.

[0071] The source of PMOS transistor MP12 is connected to the power supply voltage VDD, and its gate is connected to the output terminal NCSP of the current mirror circuit included in the load stage 130 of operational amplifier 100. The source of PMOS transistor MP13 is connected to the drain of PMOS transistor MP12, and its gate and drain are connected to the first node N11. The source of PMOS transistor MP14 is connected to the power supply voltage VDD, and its gate is connected to the gate of PMOS transistor MP13. The drain and gate of NMOS transistor MN14_1 are connected to the drain of PMOS transistor MP14, and its source is connected to ground. The gate of NMOS transistor MN15 is connected to the gate of NMOS transistor MN14_1, its source is connected to ground, and it outputs a pull-up compensation current ICU from its drain.

[0072] The pull-down compensation current generator 260 may include NMOS transistors MN12, MN13, MN14 and PMOS transistors MP14_1 and MP15.

[0073] The source of NMOS transistor MN12 is connected to ground, and its gate is connected to the output terminal NCSN of the current mirror circuit included in the load stage 130 of operational amplifier 100. The source of NMOS transistor MN13 is connected to the drain of the first NMOS transistor MN12, and its drain and gate are connected together to the second node N12. The source of NMOS transistor MN14 is connected to ground, and its gate is connected to the gate of NMOS transistor MN13. The drain and gate of PMOS transistor MP14_1 are connected together to the drain of NMOS transistor MN14, and its source is connected to the power supply voltage VDD. The gate of PMOS transistor MP15 is connected to the gate of PMOS transistor MP14_1, its source is connected to the power supply voltage VDD, and it outputs a pull-down compensation current ICD from its drain.

[0074] The NMOS transistor MN16 and PMOS transistor MP16 included in comparator 220 may have corresponding threshold voltages. In some example embodiments, the body of NMOS transistor MN16 may be electrically connected to the source of NMOS transistor MN16, and the body of PMOS transistor MP16 may be electrically connected to the source of PMOS transistor MP16. Furthermore, the body of NMOS transistor MN16 may be electrically connected to the body of PMOS transistor MP16. When the body (e.g., main block) of the NMOS transistor and / or the body (e.g., main block) of the PMOS transistor are electrically connected to the source of the NMOS transistor or the PMOS transistor, the threshold voltage of the NMOS transistor and / or the PMOS transistor may have a constant value, even if the reverse bias voltage of the NMOS transistor and / or the PMOS transistor changes.

[0075] In the following text, refer to Figures 4 to 8 The example configuration describes the operation of the operational amplifier 100 and slew rate compensation circuit included in the output buffer circuit according to some example embodiments.

[0076] The input voltage signal VIN is applied to the NMOS transistor MN16 and PMOS transistor MP16 of comparator 220, and the feedback voltage signal VFB is applied to the feedback output node NFO corresponding to the source of the NMOS transistor MN16 and PMOS transistor MP16.

[0077] When the input voltage signal VIN transitions from a low voltage level to a high voltage level, NMOS transistor MN16 turns on, NMOS transistor MN15 turns on, and the voltage of the second capacitor C2 is pulled down by the pull-up compensation current ICU. Here, the gate voltage of PMOS transistor MP8 decreases rapidly to cause a transient current in the output buffer circuit, and thus the amplifier output voltage signal VAO can be quickly set. This operation continues until the gate-source voltage VIN-VFB of NMOS transistor MN16 becomes equal to the threshold voltage VTHN of NMOS transistor MN16. At the point when the gate-source voltage VIN-VFB becomes equal to the threshold voltage VTHN, NMOS transistor MN16 turns off, and the pull-up compensation operation (e.g., the generation of the pull-up compensation current ICU) ends.

[0078] Conversely, when the input voltage signal VIN transitions from a high voltage level to a low voltage level, PMOS transistor MP16 turns on, PMOS transistor MP15 turns on, and the voltage of the first capacitor C1 is pulled up through the pull-down compensation current ICD. Here, the gate voltage of NMOS transistor MN8 increases rapidly to cause a transient current in the output buffer circuit, and thus the amplifier output voltage signal VAO can be quickly set. This operation continues until the gate-source voltage VFB-VIN of PMOS transistor MP16 becomes equal to the threshold voltage VTHP of PMOS transistor MP16. At the point when the gate-source voltage VFB-VIN becomes equal to the threshold voltage VTHP, PMOS transistor MP16 turns off, and the pull-down compensation operation (e.g., the generation of the pull-down compensation current ICD) ends.

[0079] Factors, such as the supply time of the compensation current ICU and ICD, are the main factors affecting the performance of the slew rate compensation circuit 200. The supply time is determined by the point at which the gate-source voltage VIN-VFB or VFB-VIN becomes equal to the threshold voltages VTHN and VTHP, respectively. The voltage level of the input voltage signal VIN and the threshold voltages VTHN and VTHP are not adjustable factors. Instead, refer to the following... Figure 9The supply time of the adjustable compensation current will be described.

[0080] Figure 9 It is a waveform diagram used to describe the compensation time of the output buffer circuit according to some example embodiments.

[0081] Figure 9 The waveform of the feedback voltage signal at the feedback output node NFO is shown. The input voltage signal VIN changes from a first voltage V1 to a second voltage V2, which is greater than the first voltage V1, at a first time point Tr, and changes from the second voltage V2 to a third voltage V3, which is less than the second voltage V2 and may be the same as or different from the first voltage V1, at a second time point Tf. For ease of description and illustration, it is assumed that the input voltage signal VIN is an ideal square wave. Figure 1 The first feedback voltage signal VFB1, the second feedback voltage signal VFB2, and the third feedback voltage signal VFB3 shown have different slew rates. The slew rate of the second feedback voltage signal VFB2 may be less than that of the first feedback voltage signal VFB1, and the slew rate of the third feedback voltage signal VFB3 may be less than that of the second feedback voltage signal VFB2.

[0082] For reference Figures 4 to 8 The pull-up compensation time (and / or supply time) is described as corresponding to the time interval from the first time point Tr to the point when the gate-source voltage VIN-VFB=V2-VFB of the NMOS transistor MN16 becomes equal to the threshold voltage VTHN of the NMOS transistor MN16, and the pull-down compensation time is corresponding to the time interval from the second time point Tf to the point when the gate-source voltage VFB-VIN=VFB-V3 of the PMOS transistor MP16 becomes equal to the threshold voltage VTHP of the PMOS transistor MP16.

[0083] like Figure 9 As shown, the pull-up compensation time tcr2 corresponding to the second feedback voltage signal VFB2 is longer than the pull-up compensation time tcr3 corresponding to the third feedback voltage signal VFB3, and the pull-up compensation time tcr1 corresponding to the first feedback voltage signal VFB1 is longer than the pull-up compensation time tcr2 corresponding to the second feedback voltage signal VFB2. Furthermore, the pull-down compensation time tcf2 corresponding to the second feedback voltage signal VFB2 is longer than the pull-down compensation time tcf3 corresponding to the third feedback voltage signal VFB3, and the pull-down compensation time tcf1 corresponding to the first feedback voltage signal VFB1 is longer than the pull-down compensation time tcf2 corresponding to the second feedback voltage signal VFB2. As a result, the pull-up compensation time and / or pull-down compensation time can increase as the slew rate of the feedback voltage signal applied to the comparator 220 decreases.

[0084] In conventional schemes, slew rate compensation is performed based on the amplifier output voltage signal VAO. Conversely, according to some example embodiments, slew rate compensation is performed based on a feedback voltage signal VFB whose slew rate is less than that of the amplifier output voltage signal VAO, thereby increasing the compensation time. By increasing the compensation time or supply time of the compensation current, the slew rate of the output voltage signal can be further increased, and the performance of the apparatus and system including the output buffer circuit can be improved and / or power consumption can be reduced.

[0085] Figure 10 , Figure 11 and Figure 12 This is a diagram illustrating an output buffer circuit according to some example embodiments.

[0086] Figure 10 The diagram shows some example embodiments of the feedback input node NFI corresponding to the output pad PDO, and the feedback path circuit generating the feedback voltage signal VFB1 based on the pad output voltage signal VPO on the output pad PDO. Figure 11 and Figure 12 The diagram shows some example embodiments where the feedback input node NFI corresponds to an output intermediate node within the output path circuit, and the feedback path circuit generates a feedback voltage signal VFB based on the voltage signal at the output intermediate node.

[0087] Reference Figure 10 The output buffer circuit 11 may include an output path circuit 301 and a feedback path circuit 401. Figure 10 The operational amplifier 100 and slew rate compensation circuit 200 mentioned above are omitted. The output buffer circuit 11 may or may not include the operational amplifier 100 and / or the slew rate compensation circuit 200.

[0088] The output path circuit 301 may include an output switch SWO, an output conductive path OCP, and an output electrostatic discharge (ESD) resistor Resdo.

[0089] The output switch SWO is connected between the amplifier output node NAO, which generates the amplifier output voltage signal VAO, and the first output intermediate node NO1, and the output switch SWO is turned on in response to the output enable signal SOEN. The output switch SWO and the output enable signal SOEN can be used to control the electrical connection between the amplifier output node NAO and the output pad PDO.

[0090] The output conductive path OCP connects the first output intermediate node NO1 and the second output intermediate node NO2. The output conductive path OCP may include conductive patterns in a conductive layer formed on a semiconductor substrate and vertical direct contacts connecting the conductive patterns. The output conductive path OCP may have impedance due to parasitic resistance and parasitic capacitance.

[0091] The output ESD resistor Resdo is connected between the second output intermediate node NO1 and the output pad PDO. The output ESD resistor Resdo can protect the internal circuitry from electrostatic discharge (ESD) such as triboelectric discharge through the output pad PDO.

[0092] The output switch SWO, the output conductive path OCP, and the output ESD resistor Resdo may each have their own impedance. For example, the output switch may have an on-resistance value, the output conductive path OCP may have a parasitic resistance value, and the output ESD resistor Resdo may have a specific (or, alternatively, predetermined) resistance value.

[0093] The feedback path circuit 401 may include a feedback ESD resistor Resdf, a feedback conductive path FCP, and a feedback switch SWF.

[0094] The feedback ESD resistor Resdf is connected between the output pad PDO and the first feedback intermediate node NF1. The feedback ESD resistor Resdf can protect the internal circuitry from electrostatic discharge through the output pad PDO.

[0095] The feedback conductive path FCP connects the first feedback intermediate node NF1 and the second feedback intermediate node NF2. The feedback conductive path FCP may include conductive patterns formed in a conductive layer on a semiconductor substrate and vertical direct contacts connecting the conductive patterns. The feedback conductive path FCP may have impedance due to its parasitic resistance and / or parasitic capacitance.

[0096] The feedback switch SWF is connected between the second feedback intermediate node NF2 and the feedback output node NFO that generates the feedback voltage signal VFB1. The feedback switch SWF is turned on in response to the output enable signal SOEN. The feedback switch SWF and the output enable signal SOEN can be used to control the electrical connection between the feedback output node NFO and the output pad PDO.

[0097] In, for example, Figure 10 In some example embodiments shown, the output pad PDO corresponds to a feedback point, such as the feedback input node NFI. Thus, the feedback path circuit 401 can generate a feedback voltage signal VFB based on the voltage signal VFBI (e.g., the pad output voltage signal VPO on the output pad PDO), such that the slew rate of the feedback voltage signal VFB1 is less than the slew rate of the amplifier output voltage signal VAO.

[0098] Reference Figure 11 The output buffer circuit 12 may include an output path circuit 302 and a feedback path circuit 402. Figure 11The operational amplifier 100 and slew rate compensation circuit 200 mentioned above are omitted. The output buffer circuit 12 may or may not include the operational amplifier 100 and / or the slew rate compensation circuit 200.

[0099] The output path circuit 302 may include an output switch SWO, an output conductive path OCP, and an output electrostatic discharge (ESD) resistor Resdo. Figure 11 The output path circuit 302 in the middle and Figure 10 The output path circuit 301 is the same as that in the previous example, and repeated descriptions are omitted.

[0100] The feedback path circuit 402 may include a feedback conductive path FCP and a feedback switch SWF.

[0101] The feedback conductive path FCP connects the second output intermediate node NO2 and the feedback intermediate node NF. The feedback conductive path FCP may include conductive patterns formed in a conductive layer on a semiconductor substrate and / or vertical direct contacts and / or vias connecting the conductive patterns. The feedback conductive path FCP may have impedance due to its parasitic resistance and / or parasitic capacitance.

[0102] The feedback switch SWF is connected between the feedback intermediate node NF and the feedback output node NFO that generates the feedback voltage signal VFB2. The feedback switch SWF turns on in response to the output enable signal SOEN.

[0103] The electrical connection between the feedback output node NFO and the output pad PDO can be controlled using the feedback switch SWF and the output enable signal SOEN.

[0104] In some example embodiments, such as, Figure 11 As shown, the second output intermediate node NO2 corresponds to the feedback point, for example, the feedback input node NFI. Thus, the feedback path circuit 402 can generate a feedback voltage signal VFB2 based on the voltage signal VFBI on the second output intermediate node NO2, such that the slew rate VFB2 of the feedback voltage signal is less than the slew rate of the amplifier output voltage signal VAO.

[0105] Reference Figure 12 The output buffer circuit 13 may include an output path circuit 303 and a feedback path circuit 403. Figure 12 The operational amplifier 100 and slew rate compensation circuit 200 mentioned above are omitted. The output buffer 13 may or may not include the operational amplifier 100 and / or the slew rate compensation circuit 200.

[0106] The output path circuit 303 may include an output switch SWO, an output conductive path OCP, and an output electrostatic discharge (ESD) resistor Resdo. Figure 12 The output path circuit 303 in the middle and Figure 10 The output path circuit 301 is the same as that in the previous example, and repeated descriptions are omitted.

[0107] The feedback path circuit 402 may include a feedback switch SWF.

[0108] The feedback switch SWF is connected between the first output intermediate node NO1 and the feedback output node NFO that generates the feedback voltage signal VFB3. The feedback switch SWF is turned on in response to the output enable signal SOEN. The feedback switch SWF and the output enable signal SOEN can be used to control the electrical connection between the feedback output node NFO and the output pad PDO.

[0109] In some example embodiments, such as, Figure 12 As shown, the first output intermediate node NO1 corresponds to the feedback point, for example, the feedback input node NFI. Thus, the feedback path circuit 403 can generate a feedback voltage signal VFB3 based on the voltage signal VFBI on the first output intermediate node NO1, such that the slew rate of the feedback voltage signal VFB3 is less than the slew rate of the amplifier output voltage signal VAO.

[0110] For reference Figure 10 , Figure 11 and Figure 12 The description can be generated based on the selection of the feedback point (e.g., the feedback input node NFI). Figure 9 One of the feedback signals VFB1, VFB2, and VFB3 is shown. As described above, due to the decrease in the slew rate of the feedback voltage signal VFB, the compensation time can be increased, the slew rates of the output signals VAO and VPO can be increased, and the power consumption can be reduced. Conversely, the size of the feedback path circuit can be increased as the slew rate of the feedback voltage signal VFB decreases. A suitable configuration of the feedback path circuit to generate the feedback voltage signal VFB with an appropriate slew rate can be selected considering requirements or expected performance and / or design margins.

[0111] Figure 13 This is a diagram illustrating an output buffer circuit according to some example embodiments. Figure 14 It is shown Figure 13 The timing diagram for the operation of the output buffer circuit.

[0112] Reference Figure 13 The output buffer circuit 14 may include an output path circuit 304 and a feedback path circuit 404. Figure 13 The operational amplifier 100 and slew rate compensation circuit 200 mentioned above are omitted. The output buffer circuit 14 may or may not include the operational amplifier 100 and / or the slew rate compensation circuit 200.

[0113] The output path circuit 304 may include an output switch SWO, and the feedback path circuit 404 may include a feedback switch SWF and a feedback control switch SWC. Figure 13 The specific configurations of the output path circuit 304 and the feedback path circuit 404, which can be implemented differently, are omitted here.

[0114] The output switch SWO is connected between the amplifier output node NAO, which generates the amplifier output voltage signal VAO, and the output pad PDO. The output switch SWO is turned on in response to the output enable signal SOEN.

[0115] The feedback switch SWF is connected between the feedback output node NFO that generates the feedback voltage signal VFB and the output pad PDO. The feedback switch SWF is turned on in response to the output enable signal SOEN.

[0116] The feedback control switch SWC is connected between the amplifier output node NAO and the feedback output node NFO. The feedback control switch SWC is turned on in response to the inverted signal SOENB of the output enable signal SOEN.

[0117] Reference Figure 14 Based on the changes in the voltage levels Vi1, Vi2, and Vi3 of the input voltage signal VIN, the voltage levels Vo1, Vo2, and Vo3 of the pad output voltage signal VPO can change sequentially every unit period 1H. When the output buffer circuit is a source amplifier circuit included in the source driver of the display device, the unit period 1H can correspond to the row scan period used to apply the source voltage or the pad output voltage signal VPO to each pixel of the selected row.

[0118] The output enable signal SOEN can be deactivated during the pre-latch period tPL corresponding to the second part of the unit period 1H, and can be activated during the output period corresponding to the first part of the unit period 1H. Conversely, the inverting signal SOENB can be activated during the pre-latch period tPL, and can be deactivated during the output period. Figure 14 An example is shown where the output enable signal SOEN and the inverted signal SOENB are activated at a logic high level, but the activation logic level is not limited to this.

[0119] Reference Figure 13 and Figure 14 During the output period when the output enable signal SOEN is activated, the output switch SWO is turned on, causing the output path circuit 304 to electrically connect the amplifier output node NAO to the output pad PDO. The feedback control switch SWC is turned off and the feedback switch SWF is turned on, causing the feedback path circuit 404 to electrically connect the output pad PDO to the feedback output node NFO.

[0120] Conversely, during the pre-latch period tPL when the output enable signal SOEN is deactivated, the output switch SWO is turned off, causing the output path circuit 304 to electrically disconnect the amplifier output node NAO from the output pad PDO. The feedback switch SWF is turned off and the feedback control switch SWC is turned on, causing the feedback path circuit 404 to electrically connect the amplifier output node NAO to the feedback output node NFO.

[0121] As a result, the feedback path circuit 404 can generate a feedback voltage signal VFB based on the voltage signal VFBI on the feedback input node NFI when the output enable signal SOEN is activated, and the feedback path circuit 404 can generate a feedback voltage signal VFB based on the amplifier output voltage signal VAO on the amplifier output node NAO when the output enable signal SOEN is deactivated.

[0122] During the pre-latch period tPL, the output buffer circuit can output a pad output voltage signal VPO corresponding to the previous data (e.g., voltage level) of the input voltage signal VIN, and simultaneously preload the next data of the input voltage signal VIN to the input terminal of the operational amplifier of the output buffer circuit. The output switch SWO and feedback switch SWF can be turned off during the pre-latch period tPL, so that the next data of the input voltage signal VIN does not affect the voltage level of the output pad PDO. Conversely, the feedback control switch SWC can be turned on during the pre-latch period tPL to reduce the settling time of the amplifier output voltage signal VAO by providing it to the slew rate compensation circuit.

[0123] Figure 15 This is a block diagram illustrating a display system according to some example embodiments.

[0124] Figure 15 The display system 500 can be at least one of various electronic devices with image display capabilities, such as mobile phones, smartphones, tablet PCs, personal digital assistants (PDAs), wearable devices, portable multimedia players (PMPs), handheld devices, and handheld computers.

[0125] Reference Figure 15 The display system 500 may include a host device 520 and a display device 530. The display device 530 may include a display driver integrated circuit (DDI) 540 and a display panel 550.

[0126] The host device 520 controls the overall operation of the display system 500. The host device 500 may be or may include an application processor (AP), a baseband processor (BBP), a microprocessor (MPU), etc. The host device 500 can provide image data IMG, clock signal CLK, and control signal CTRL to the display device 530. For example, the image data IMG may include RGB pixel values ​​and has a resolution of w×h, where w is the number of pixels in the horizontal direction and h is the number of pixels in the vertical direction.

[0127] The control signal CTRL may include at least one of a command signal, a horizontal synchronization signal, a vertical synchronization signal, a data enable signal, etc. For example, image data IMG and the control signal CTRL may be provided to DDI 540 in display device 530 in a grouped manner. The command signal may include control information, image information, and / or display setting information. For example, image information may include the resolution of the input image data IMG. For example, display setting information may include panel information, brightness setting values, etc. For example, the host device 520 may provide information based on user input or predetermined setting values ​​as display setting information.

[0128] The DDI 540 can drive the display panel 550 based on image data (IMG) and control signal (CTRL). The DDI 540 can convert the digital image signal (IMG) into an analog signal and drive the display panel 550 based on the analog signal.

[0129] The DDI 540 may include multiple output buffer circuits OBF, such as those referenced above. Figures 1 to 14 At least one of those described above. According to some example embodiments, each buffer circuit OBF may utilize a feedback voltage signal VFB with a slew rate less than that of the amplifier output voltage signal VAO to increase the supply time of the compensation current.

[0130] Figure 16 This is a block diagram illustrating a display device according to some example embodiments. Figure 16 An electroluminescent display device, such as an OLED display device, is shown as an example, and the example embodiment is not limited to a particular type of display device.

[0131] Reference Figure 16 The electroluminescent display device 530 may include a display panel 550, which includes a plurality of pixel rows 511 and a DDI 540 for driving the display panel 550. The DDI 540 may include a data driver or source driver 600, a scan driver 544, a timing controller 545, a power supply 546, and a gamma circuit 547.

[0132] Display panel 550 can be connected to source driver 600 of DDI 540 via multiple source lines, and can be connected to scan driver 544 of DDI 540 via multiple scan lines. Display panel 550 may include pixel rows 511. For example, display panel 550 may include multiple pixels PX arranged in a matrix with multiple rows and columns. A row of pixels PX connected to the same scan line may be referred to as a pixel row 511. In some example embodiments, display panel 550 may be or may include a self-emissive display panel that does not use a backlight unit to emit light. For example, display panel 550 may be or may include an organic light-emitting diode (OLED) display panel.

[0133] Each pixel PX included in the display panel 550 may have various configurations depending on the driving mechanism of the display device 530. For example, the electroluminescent display device 530 may be driven by analog and / or digital driving methods. Analog driving methods generate grayscale using variable voltage levels corresponding to input data, while digital driving methods generate grayscale using variable durations of LED emission. Analog driving methods may be difficult to implement because they require complex manufacturing / production of DDIs if the display is large and / or has high resolution. However, digital driving methods can easily achieve high resolution with simpler circuit structures. As the size of the display panel increases and the resolution increases, digital driving methods may have more advantageous characteristics than analog driving methods. The display device according to some example embodiments may be applicable to both analog and digital driving methods.

[0134] The source driver 600 can apply a data signal to the display panel 550 via the source line based on the display data DDT. The scan driver 544 can apply a scan signal to the display panel 550 via the scan line.

[0135] See below for reference. Figure 17 As will be described, the source driver 600 may include multiple output buffer circuits OBF, such as those referenced above. Figures 1 to 14 At least one described. According to some example embodiments, each buffer circuit OBF may utilize a feedback voltage signal VFB with a slew rate less than that of the amplifier output voltage signal VAO to increase the supply time of the compensation current.

[0136] Timing controller 545 controls the operation of display device 530. Timing controller 545 provides control signals to source driver 600 and scan driver 544 to control the operation of display device 543. In some example embodiments, source driver 600, scan driver 544, and timing controller 545 may be implemented as a single integrated circuit (IC). In some example embodiments, source driver 600, scan driver 544, and timing controller 545 may be implemented as two or more integrated circuits. The driving module includes at least timing controller 545, and source driver 600 may be referred to as a timing controller-embedded data driver (TED).

[0137] The timing controller 545 can be obtained from Figure 15 The host device 520 receives image data IMG and input control signals. For example, the image data IMG may include red (R) image data, green (G) image data, and blue (B) image data. According to some example embodiments, the image data IMG may include white image data, magenta image data, yellow image data, cyan image data, etc. The input control signals may include a master clock signal, a data enable signal, a horizontal synchronization signal, a vertical synchronization signal, etc.

[0138] Power supply 546 can supply a high power supply voltage ELVDD and a low power supply voltage ELVSS to display panel 550. Alternatively or additionally, power supply 546 can supply a regulator voltage to gamma circuit 547. Gamma circuit 547 can generate a gamma reference voltage GRV based on regulator voltage VREG. For example, regulator voltage VREG can be or correspond to the high power supply voltage ELVDD or another voltage generated based on the high power supply voltage ELVDD.

[0139] Figure 17 This is a block diagram illustrating the source driver of a display device according to some example embodiments.

[0140] Reference Figure 17 The source driver 600 may include a shift register 610, a data latch 630, a digital-to-analog converter (DAC) 650, and an output buffer block 670.

[0141] The shift register 610 can receive a clock signal CLK and an input / output control signal DIO, and can generate multiple latch clock signals LCLK0 to LCLKn-1 based on the clock signal CLK. Each of the latch clock signals LCLK0 to LCLKn-1 can determine the latching time point of the data latch 630, serving as a clock signal for a specific time period.

[0142] Data latch 630 can store data DDT in response to latch clock signals LCLK0 to LCLKn-1 provided by shift register 610. Data latch 630 can output the stored data to DAC 650 in response to load signal TP. Data latch 630 can provide output signals D0 to Dn-1 in response to load signal TP. DAC 650 can generate input voltage signals VIN0 to VINn-1 using grayscale voltage GMA, which are analog signals corresponding to the output signals D0 to Dn-1 of data latch 630.

[0143] Output buffer block 670 buffers input voltage signals VIN0 to VINn-1 and generates source drive signals, such as pad output voltage signals VPO0 to VPOn-1. Output buffer block 670 may include multiple output buffer circuits OBF that drive the source lines respectively. As described above, each output buffer circuit OBF may include an operational amplifier, a slew rate compensation circuit, an output path circuit, and a feedback path circuit.

[0144] According to some example embodiments, the output buffer circuit OBF and source driver 600 of the display device can increase the supply time of the compensation current by utilizing a feedback voltage signal with a slew rate lower than that of the amplifier output voltage signal. By increasing the supply time of the compensation current, power consumption can be reduced, and the performance of the output buffer circuit OBF and source driver 600 can be improved.

[0145] Figure 18 This is a diagram illustrating a general output buffer circuit and an output buffer circuit according to some example embodiments.

[0146] Figure 18 A general-purpose output buffer OBFc and an output buffer OBFp are shown. The general-purpose output buffer OBFc includes a slew rate compensation circuit SRCC' configured to generate a compensation current Ic by performing a slew rate compensation operation based on the amplifier output voltage signal VAO'. The output buffer OBFp, according to some example embodiments, includes a slew rate compensation circuit SRCC' configured to generate a compensation current Ic by performing a slew rate compensation operation based on a feedback voltage signal VFB whose slew rate is less than that of the amplifier output voltage signal VAO. The operational amplifier AMP, the slew rate compensation circuits SRCC and SRCC', the output path circuit OPC, and the feedback path circuit FPC are the same as described above, and repeated descriptions are omitted.

[0147] like Figure 18 As shown, the panel load PLD, including resistor RP and capacitor CP, can be connected to the output pad PDO. The panel load PLD can generate load output voltage signals VLO and VLO' by filtering the pad output voltage signals VPO and VPO', respectively.

[0148] Figure 19 It is shown Figure 18 The timing diagram of the operation of the output buffer circuit. Figure 20 It is shown Figure 18 A diagram showing the transition time and power consumption of the output buffer circuit.

[0149] Figure 19 The waveforms of the horizontal synchronization signal HSYNC, the amplifier output voltage signals VAO and VAO', the pad output voltage signals VPO and VPO', and the load output voltage signals VLO and VLO', corresponding to a line scan period of approximately 3 μm (microseconds) 1H, are shown. They are measured relative to the input voltage signal VIN, which is switched between higher and lower voltage levels per line scan period 1H.

[0150] like Figure 19 As shown, compared with the voltage signals VAO', VPO', and VLO' of the ordinary output buffer circuit OBFc, the voltage signals VAO, VPO, and VLO of the output buffer circuit OBFp according to some example embodiments may have increased slew rate and reduced transition time.

[0151] Figure 20 The diagram shows the transition time (i.e., rise time and fall time) of the voltage signal measured for a general output buffer circuit OBFc and an output buffer circuit OBFp according to some example embodiments, the power consumption PWC1 of the source driver, and the overall power consumption PWC2 of the display driver integrated circuit. Figure 20 As shown, compared to a conventional output buffer circuit OBFc, the transition time can be reduced by about 5% and the power consumption can be reduced by about 5.5% in the output buffer circuit OBFp according to some example embodiments.

[0152] Figure 21 This is a block diagram illustrating a mobile device according to some example embodiments.

[0153] Reference Figure 21 The mobile device 700 includes a system-on-a-chip (“SoC”) 710 and multiple functional modules 740, 750, 760 and 770. The mobile device 700 may also include a memory device 720, a storage device 730 and a power management device 780.

[0154] SoC 710 controls the overall operation of mobile device 700. In some example embodiments, for example, SoC 710 controls memory device 720, storage device 730, and multiple functional modules 740, 750, 760, and 770. SoC 710 may be an application processor (“AP”) included in mobile device 700.

[0155] SoC 710 may include CPU 712 and power management system (PM system) 714. Memory device 720 and storage device 730 may store data for operation of mobile device 700. In some example embodiments, memory device 720 may include at least one of volatile memory devices, such as dynamic random access memory (“DRAM”), static random access memory (“SRAM”), and mobile DRAM. In some example embodiments, storage device 730 may include at least one of non-volatile memory devices, such as erasable programmable read-only memory (“EPROM”), electrical EPROM (“EEPROM”), flash memory, phase-change random access memory (“PRAM”), resistive random access memory (“RRAM”), nano-floating gate memory (“NFGM”), polymer random access memory (“PoRAM”), magnetic random access memory (“MRAM”), ferroelectric random access memory (“FRAM”), etc. In some example embodiments, the storage device 730 may also include at least one of a solid-state drive (“SSD”), a hard disk drive (“HDD”), a CD-ROM, etc.

[0156] Functional modules 740, 750, 760, and 770 perform various functions of the mobile device 700. In some example embodiments, the mobile device 700 may include, for example, a communication module 740 performing communication functions (e.g., at least one of a Code Division Multiple Access (“CDMA”) module, a Long Term Evolution (“LTE”) module, a Radio Frequency (RF) module, an Ultra Wideband (“UWB”) module, a Wireless Local Area Network (WLAN) module, a Global Microwave Access Interoperability (“WIMAX”) module, etc.), a camera module 750 performing camera functions, a display module 760 performing display functions, a touch panel module 770 performing touch sensing functions, etc. In some example embodiments, the mobile device 700 may also include, for example, at least one of a Global Positioning System (“GPS”) module, a microphone (“MIC”) module, a speaker module, a gyroscope module, etc. However, the functional modules 740, 750, 760, and 770 in the mobile device 700 are not limited thereto.

[0157] The power management device 780 can provide operating voltage to the SoC 710, memory device 720, storage device 730, and functional modules 740, 750, 760, and 770.

[0158] According to some example embodiments, the display module 760 includes an output buffer block 762, which may include multiple output buffer circuits OBF to drive the source lines of the display panel. Each output buffer circuit OBF may include the aforementioned operational amplifier, slew rate compensation circuit, output path circuit, and feedback path circuit.

[0159] Figure 22 This is a block diagram illustrating a computing system according to some example embodiments.

[0160] Reference Figure 22 The computing system 1100 may employ or support a MIPI interface and may include an application processor 1110, an image sensor 1140, and a display 1150. The CSI host 1112 of the application processor 1110 may perform serial communication with the CSI device 1141 of the image sensor 1140 using a Camera Serial Interface (CSI). In some example embodiments, the CSI host 1112 may include a deserializer (DES), and the CSI device 1141 may include a serializer (SER). The DSI host 1111 of the application processor 1110 may perform serial communication with the DSI device 1151 of the display 1150 using a Display Serial Interface (DSI). In some example embodiments, the DSI host 1111 may include a serializer (SER), and the DSI device 1151 may include a deserializer (DES).

[0161] The computing system 1100 may also include a radio frequency (RF) chip 1160, which may include a physical layer PHY 1161 and a DigRF slave device 1162. The physical layer PHY 1113 of the application processor 1110 may perform data transmission with the physical layer PHY 1161 of the RF chip 1160 using MIPI DigRF. The PHY 1113 of the application processor 1110 may interact and / or communicate with a DigRF master device 1114 for controlling data transmission with the PHY 1161 of the RF chip 1160.

[0162] The computing system 1100 may also include a Global Positioning System (GPS) 1120, a storage device 1170, a microphone 1180, DRAM 1185, and / or a speaker 1190. The computing system 1100 may communicate with external devices using an Ultra-Wideband (UWB) communication interface 1210, a Wireless Local Area Network (WLAN) communication interface 1220, a Global Microwave Access Interoperability (WIMAX) communication interface 1230, etc. However, the exemplary embodiments are not limited to this. Figure 22 The configuration or interface of computing systems 1000 and 1100 are shown.

[0163] According to some example embodiments, the source driver of the display device 1150 includes a plurality of output buffer circuits OBF for driving the source lines of the display panel. Each output buffer circuit OBF may include the aforementioned operational amplifier, slew rate compensation circuit, output path circuit, and feedback path circuit.

[0164] As described above, the output buffer circuit and source driver of the display device according to some example embodiments can increase the supply time of the compensation current by utilizing a feedback voltage signal with a slew rate lower than that of the amplifier output voltage signal. By increasing the supply time of the compensation current, power consumption can be reduced, and the performance of the output buffer circuit and source driver can be improved.

[0165] This invention concept can be applied to any electronic device and system. For example, it can be applied to at least one system such as mobile phones, smartphones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, camcorders, personal computers (PCs), server computers, workstations, laptop computers, digital TVs, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, vehicle navigation systems, video phones, monitoring systems, autofocus systems, tracking systems, motion monitoring systems, etc.

[0166] As used herein, terms such as “circuit” may mean and / or refer to at least one electrical component, such as at least one active device and / or at least one passive device. Any or all of the elements disclosed above may include or be implemented in processing circuitry, which includes active devices such as transistors and / or diodes and / or passive devices including at least one of resistors, capacitors, inductors, or memristors, and / or may include hardware (including logic circuitry) or be implemented in hardware; may include a hardware / software combination (such as a processor executing software) or be implemented in a hardware / software combination; or may include a combination thereof or be implemented in a combination thereof. For example, processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0167] The foregoing are descriptions of some exemplary embodiments and should not be construed as limiting them. Although some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the exemplary embodiments without substantially departing from the inventive concept.

Claims

1. An output buffer circuit, comprising: An operational amplifier configured to generate an amplifier output voltage signal based on an input voltage signal and a compensation current; A slew rate compensation circuit is configured to generate a compensation current based on the difference between the input voltage signal and the feedback voltage signal to increase the slew rate of the amplifier output voltage signal. An output path circuit is connected between the operational amplifier and the output pad, and the output path circuit is configured to transmit the amplifier output voltage signal to generate a pad output voltage signal through the output pad. as well as A feedback path circuit, connected between the slew rate compensation circuit and the feedback input node of the output path circuit, is configured to generate the feedback voltage signal. The slew rate of the feedback voltage signal is less than the slew rate of the amplifier output voltage signal.

2. The output buffer circuit according to claim 1, wherein, The feedback input node corresponds to the output pad, and the feedback path circuit is configured to generate the feedback voltage signal on the output pad based on the output voltage signal of the pad.

3. The output buffer circuit according to claim 1, wherein, The feedback input node corresponds to the output intermediate node inside the output path circuit, and the feedback path circuit is configured to generate the feedback voltage signal at the output intermediate node based on the voltage signal.

4. The output buffer circuit according to claim 1, wherein, The output path circuit includes: An output switch is connected between an amplifier output node configured to generate the amplifier output voltage signal and a first output intermediate node, the output switch being configured to turn on in response to an output enable signal; An output conductive path is provided, connecting the first output intermediate node and the second output intermediate node; and An output electrostatic discharge resistor is connected between the second output intermediate node and the output pad.

5. The output buffer circuit according to claim 4, wherein, The feedback path circuit is configured to generate the feedback voltage signal based on the pad output voltage signal on the output pad, such that the slew rate of the feedback voltage signal is less than the slew rate of the amplifier output voltage signal.

6. The output buffer circuit according to claim 4, wherein, The feedback path circuit includes: A feedback electrostatic discharge resistor is connected between the output pad and the first feedback intermediate node; A feedback conductive path, connecting the first feedback intermediate node and the second feedback intermediate node; and A feedback switch is connected between the second feedback intermediate node and the feedback output node configured to generate the feedback voltage signal, the feedback switch being configured to turn on in response to the output enable signal.

7. The output buffer circuit according to claim 4, wherein, The feedback path circuit is configured to generate the feedback voltage signal based on the voltage signal at the second output intermediate node, such that the slew rate of the feedback voltage signal is less than the slew rate of the amplifier output voltage signal.

8. The output buffer circuit according to claim 4, wherein, The feedback path circuit includes: A feedback conductive path, which connects the second output intermediate node and the feedback intermediate node; and A feedback switch is connected between the feedback intermediate node and the feedback output node configured to generate the feedback voltage signal, the feedback switch being configured to turn on in response to the output enable signal.

9. The output buffer circuit according to claim 4, wherein, The feedback path circuit is configured to generate the feedback voltage signal based on the voltage signal at the first output intermediate node, such that the slew rate of the feedback voltage signal is less than the slew rate of the amplifier output voltage signal.

10. The output buffer circuit according to claim 4, wherein, The feedback path circuit includes: A feedback switch is connected between the first output intermediate node and a feedback output node configured to generate the feedback voltage signal, the feedback switch being configured to turn on in response to the output enable signal.

11. The output buffer circuit according to claim 1, wherein, The output path circuit includes: An output switch, connected between the output pad and an amplifier output node configured to generate the amplifier output voltage signal, is configured to turn on in response to an output enable signal. The feedback path circuit includes: A feedback switch, connected between the output pad and a feedback output node configured to generate the feedback voltage signal, is configured to turn on in response to the output enable signal. A feedback control switch, connected between the amplifier output node and the feedback output node, is configured to turn on in response to the inverted signal of the output enable signal.

12. The output buffer circuit according to claim 11, wherein, The feedback path circuit is configured to generate the feedback voltage signal based on the voltage signal on the feedback input node when the output enable signal is activated, and the feedback path circuit is configured to generate the feedback voltage signal based on the amplifier output voltage signal on the amplifier output node when the output enable signal is deactivated.

13. The output buffer circuit according to claim 11, wherein, When the output enable signal is activated, the output switch is configured to be turned on, such that the output path circuit electrically connects the amplifier output node to the output pad, and When the output enable signal is activated, the feedback control switch is configured to be off and the feedback switch is configured to be on, such that the feedback path circuit electrically connects the output pad to the feedback output node.

14. The output buffer circuit according to claim 11, wherein, When the output enable signal is deactivated, the output switch is configured to open, causing the output path circuit to electrically disconnect the amplifier output node from the output pad, and When the output enable signal is deactivated, the feedback switch is configured to be off and the feedback control switch is configured to be on, such that the feedback path circuit electrically connects the amplifier output node to the feedback output node.

15. The output buffer circuit according to claim 1, wherein, The slew rate compensation circuit includes: A comparator circuit is configured to compare the input voltage signal with the feedback voltage signal to generate a first current corresponding to the difference between the input voltage signal and the feedback voltage signal; A pull-up compensation current generating circuit is configured to perform a current mirror operation on the first current to generate a pull-up compensation current that reduces the transition time of the rise edge of the amplifier output voltage signal; and A pull-down compensation current generating circuit is configured to perform a current mirror operation on the first current to generate a pull-down compensation current that reduces the transition time of the falling edge of the amplifier output voltage signal.

16. The output buffer circuit according to claim 15, wherein, The comparator circuit includes: An NMOS transistor, wherein the input voltage signal is applied to the gate of the NMOS transistor, the feedback voltage signal is applied to the source of the NMOS transistor, and the drain of the NMOS transistor is connected to the pull-up compensation current generation circuit; and The PMOS transistor has an input voltage signal applied to its gate, a feedback voltage signal applied to its source, and its drain connected to the pull-down compensation current generation circuit.

17. The output buffer circuit according to claim 16, wherein, When the difference between the input voltage signal and the feedback voltage signal is greater than the threshold voltage of the NMOS transistor, the NMOS transistor turns on and the PMOS transistor turns off, causing the slew rate compensation circuit to provide the pull-up compensation current to the operational amplifier. Specifically, when the difference between the input voltage signal and the feedback voltage signal is less than the threshold voltage of the PMOS transistor, the PMOS transistor is turned on and the NMOS transistor is turned off, so that the slew rate compensation circuit provides the pull-down compensation current to the operational amplifier.

18. A source driver for a display device, comprising: A plurality of output buffer circuits according to any one of claims 1 to 17, configured to drive the source line of a display panel, each of the plurality of output buffer circuits being configured to generate an amplifier output voltage signal based on an input voltage signal and a compensation current to generate a feedback voltage signal with a slew rate less than that of the amplifier output voltage signal, and to generate a compensation current to increase the slew rate of the amplifier output voltage signal, thereby increasing the slew rate of the amplifier output voltage signal based on the difference between the input voltage signal and the feedback voltage signal.

19. A source driver for a display device, comprising: A shift register, which is configured to generate multiple latching clock signals based on a clock signal and input-output control signals; A data latch is configured to store data in response to the plurality of latch clock signals and to output a plurality of digital input signals corresponding to the data in response to a load signal; A digital-to-analog converter configured to generate a plurality of input voltage signals corresponding to the plurality of digital input signals, wherein the plurality of input voltage signals are generated using grayscale voltage; as well as Multiple output buffer circuits are configured to buffer the multiple input voltage signals to drive the source lines of the display panel, each of the buffer circuits comprising: An operational amplifier configured to generate an amplifier output voltage signal based on each of the input voltage signal and the compensation current. A slew rate compensation circuit is configured to generate the compensation current based on the difference between each of the input voltage signals and the feedback voltage signal, thereby increasing the slew rate of the amplifier output voltage signal. An output path circuit, connected between the operational amplifier and the output pad, is configured to transmit the amplifier output voltage signal to generate a pad output voltage signal via the output pad. A feedback path circuit, connected between the slew rate compensation circuit and the feedback input node of the output path circuit, is configured to generate the feedback voltage signal. The slew rate of the feedback voltage signal is less than the slew rate of the amplifier output voltage signal.

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