Memory devices and their operation methods

Abstract

A memory device includes: a memory cell array including a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device. Embodiments of the invention also provide a method for operating the memory device.

Description

Technical Field

[0001] The embodiments of the present invention relate to memory devices and methods of operating the same. Background Technology

[0002] Memory devices are used to store information in semiconductor devices and systems. Non-volatile memory devices retain data even after power is lost. Examples of non-volatile memory devices include flash memory, ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), and phase-change memory (PCM). MRAM, RRAM, FRAM, and PCM are sometimes referred to as emerging memory devices. Summary of the Invention

[0003] According to one aspect of the present invention, a method for operating a memory device is provided, comprising: detecting a temperature of the memory device; determining a target write pulse width based on the detected temperature of the memory device; and writing data into the memory device using the target write pulse width.

[0004] According to another aspect of the present invention, a method for operating a memory device is provided, comprising: detecting a write error rate of the memory device; comparing the detected write error rate with a threshold write error rate; increasing the write pulse width if the detected write error rate is higher than the threshold write error rate; and decreasing the write pulse width if the detected write error rate is not higher than the threshold write error rate.

[0005] According to another aspect of the present invention, a memory device is provided, comprising: a memory cell array including a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion. Furthermore, the drawings are illustrative, serving as examples of embodiments of the invention, and are not intended to be limiting.

[0007] Figure 1 This is a block diagram illustrating an exemplary memory device incorporating write pulse trimming according to some embodiments.

[0008] Figure 2 This is a flowchart illustrating a method for write pulse trimming according to some embodiments.

[0009] Figure 3A This illustrates, according to some embodiments, in Figure 2 The example temperature correlation table used in the method is a graph.

[0010] Figure 3B This illustrates, according to some embodiments, in Figure 2 Another example of a temperature-related table used in the method is a graph.

[0011] Figure 3C This is a flowchart illustrating a method for generating a temperature correlation table according to some embodiments.

[0012] Figure 4 This is a flowchart illustrating another method of write pulse trimming according to some embodiments. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0015] Manufacturing processes for emerging memory devices are still immature. The write error rate (WER) of emerging memory devices such as ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), and phase-change memory (PCM) is temperature-dependent. Specifically, the difficulty of programming during a write operation is affected by the temperature of the emerging memory device. When the temperature is relatively high, programming data into the memory cells of the emerging memory device is relatively easy, thus requiring relatively fewer write pulses (i.e., lower write pulse width); when the temperature is relatively low, programming data into the memory cells of the emerging memory device is relatively difficult, thus requiring relatively more write pulses (i.e., higher write pulse width). Typical normal temperature ranges for memory devices are between 25°C and 85°C. However, sometimes memory devices may operate under extreme temperature conditions, such as a minimum of -25°C or a maximum of 125°C. In one example, the number of write pulses required at 125°C is approximately six times that required at -50°C. Therefore, a fixed number of write pulses is not suitable for all write operations under all conditions. In other words, when fixed programming conditions are set, it may only be suitable for or optimized for writing operations at a specified temperature, and the write error rate may increase when the actual temperature deviates from the specified temperature.

[0016] According to some aspects of this disclosure, the write pulse width of the memory device is adjusted (i.e., write pulse trimming) based on the temperature of the memory cell array or the write error rate of the memory device. This adjustment allows the memory device to operate under appropriate conditions to reduce the write error rate. Specifically, the write pulse width of the memory is adjusted based on the temperature of the memory and a temperature-dependent table. Alternatively, the write pulse width is adjusted based on the write error rate of the memory device.

[0017] Figure 1 This is a block diagram illustrating an exemplary memory device 100 incorporating write pulse trimming according to some embodiments. In the illustrated example, the exemplary memory device 100 includes: a memory cell array 102, a controller 106, a voltage generation circuit 116, a row decoder 118, a word line control circuit 120, a column decoder 122, a bit line control circuit 124, a read circuit 126, a write circuit 130, an input / output (I / O) circuit 132, an optional temperature sensor 134, and an optional error monitor 136. In one example, the memory device 100 includes a temperature sensor 134. In another example, the memory device 100 includes an error monitor 136. In yet another example, the memory device 100 includes both a temperature sensor 134 and an error monitor 136.

[0018] The memory cell array 102 includes a plurality of memory cells 104 arranged in rows and columns. The memory cells 104 are emerging memory cells, such as MRAM cells, RRAM cells, FRAM cells and PCM cells, but other types of memory cells may also be used.

[0019] The controller 106 specifically includes a control circuit 108, a command address latch circuit 110, a pulse generator circuit 112, and a memory bank 114. The command address latch circuit 110 temporarily holds the command and address, which are received as input by the memory device 100. The command address latch circuit 110 sends the address to the row decoder 118 and the column decoder 122.

[0020] The row decoder 118 decodes the row address included in the address and sends the row address to the word line control circuit 120. Based on the decoded row address, the word line control circuit 120 selects the word line (corresponding to a specific row) 102 of the memory cell array 102. Specifically, it accesses the memory cell 104 in that specific row.

[0021] On the other hand, the column decoder 120 decodes the column address included in the address and sends the column address to the bit line control circuit 124. Based on the decoded column address, the bit line control circuit 124 selects the bit line of the memory cell array 102 (corresponding to a specific column). Specifically, the memory cell 104 in a specific row of that specific column (among all memory cells 104) is accessed, and data can be written to or read from the memory cell 104 in that specific row and column.

[0022] During a write operation, write circuit 130 provides various voltages and currents to write data to memory cell 104 selected based on the decoded row address and decoded column address. A pulse generator circuit 112 generates the write pulses (i.e., the write pulse width) required for the write operation. Figure 1 In the example shown, the pulse generator circuit 112 is located within the controller 106, although the pulse generator circuit 112 may be a separate component external to the controller 106. Among other things, the write circuit 130 includes a write driver, not shown.

[0023] During a read operation, read circuit 126 provides various voltages and currents for reading data from memory cell 104 selected based on the decoded row address and decoded column address. Among other things, read circuit 126 includes a read driver (not shown) and a sense amplifier 128. The sense amplifier 128 senses a relatively small difference between the voltages of two complementary bit lines (i.e., BL and BLB) and amplifies the difference at the output of read amplifier 128.

[0024] I / O circuit 132 is coupled to both write circuit 130 and read circuit 126. During a write operation, I / O circuit 132 temporarily holds the data to be written and sends the data to be written to write circuit 130. On the other hand, during a read operation, I / O temporarily holds the data read by read circuit 126.

[0025] By using an external power supply voltage, the voltage generation circuit 116 generates various voltages for the operation of the memory device 100. These voltages generated by the voltage generation circuit 116 can be applied to components of the memory device 199, such as the controller 110, row decoder 118, word line control circuit 120, column decoder 122, bit line control circuit 124, read circuit 126, write circuit 130, I / O circuit 132, and optionally a temperature sensor 134 and / or an error monitor 136.

[0026] Control circuit 108 receives commands from command address latch circuit 110. In response to the command, control circuit 108 controls the operation of components of memory device 100, such as controller 110, row decoder 118, word line control circuit 120, column decoder 122, bit line control circuit 124, read circuit 126, write circuit 130, I / O circuit 132, pulse generator circuit 112, memory bank 114, command address latch circuit 110, memory voltage generation circuit 116, and optional temperature sensor 134 and / or error monitor 136.

[0027] Temperature sensor 134 measures the temperature of memory cell array 102. In one example, temperature sensor 134 is an analog temperature sensor that generates an output current proportional to the absolute temperature of temperature sensor 134 and has a wide temperature range of -55°C to 150°C. In another example, temperature sensor 134 is a digital temperature sensor that compares the voltage generated by an onboard temperature sensor with an internal reference voltage and digitizes it by an analog-to-digital converter (ADC). It should be noted that other types of temperature sensors can also be used. Temperature sensor 134 can be, for example, Figure 1 The individual components shown. Temperature sensor 134 can also be embedded in controller 106.

[0028] Error monitor 136 monitors the write error rate (WER) of memory device 100. The write error rate is the number of write bit errors per unit of time. The more write bit errors within a given time interval, the higher the write error rate. During a write operation, some bits are not written as expected after the first write operation; these bits are called incomplete bits. Because of the incomplete bits, a second write operation is required. If there are still any incomplete bits after the second write operation, a third write operation is required. This process continues until there are no more incomplete bits. Error monitor 136 is coupled to I / O circuitry 132 to monitor the write error rate of memory device 100.

[0029] While other methods may be used, the error monitor 136 can employ various write error rate detection methods, such as error-correcting codes (ECC). ECC schemes are used to detect and correct bit errors stored in memory. ECC encodes data by generating ECC check bits (e.g., redundancy bits or parity bits), which are stored in the memory device along with the data. Data bits and check (e.g., parity) bits together form a codeword. For example, an ECC that generates 8 parity bits for 64-bit data can typically detect two errors and correct one error in the 64-bit data; this is called a DED / SEC code, representing Double Error Detection (DED) and Single Error Correction (SEC). In another example, a DED / DEC scheme can be used, which means Double Error Detection (DED) and Double Error Correction (DEC). In yet another example, a SED / SEC scheme can be used, which means Single Error Detection (SED) and Single Error Correction (SEC). In one embodiment, the error monitor 136 can be an ECC circuit utilizing an ECC scheme. The ECC circuit can detect errors and correct them during memory device operation. Specifically, the ECC circuit may include an ECC encoder and an ECC decoder. The ECC encoder is configured to generate parity bits and form a codeword, while the ECC decoder is configured to decode the codeword and provide corrected data. Therefore, the ECC circuit can determine the write error rate by utilizing the error detection function of the ECC circuit.

[0030] Among other things, storage unit 114 specifically stores temperature-related tables and / or threshold write error rates, which will be referenced below. Figure 2 and Figure 4 A detailed description is provided. In one example, memory 114 is read-only memory (ROM). In another example, memory 114 is random access memory (RAM). It should be noted that other types of memory may also be used.

[0031] Figure 2 This is a flowchart illustrating a method for write pulse trimming according to some embodiments. Figure 3AThis illustrates, according to some embodiments, in Figure 2 The example temperature correlation table used in the method is a graph. Figure 3B This illustrates, according to some embodiments, in Figure 2 Another example of a temperature-related table used in the method is a graph. Figure 3C This is a flowchart illustrating a method for generating a temperature-related table according to some embodiments. Typically, the write pulse width of the memory device 100 is adjusted based on the temperature of the memory cell array 102 to perform write operations under suitable conditions to reduce the write error rate.

[0032] like Figure 2 As shown, the method begins at step 202, where temperature sensor 134 detects the temperature of memory cell array 102. Since temperature sensor 134 is coupled to controller 106, the controller can make decisions based on the temperature of memory array 102. At step 204, the target write pulse width is determined based on the detected temperature of the memory devices, as referenced below. Figures 3A-3C As explained. Typically, the target write pulse width is determined by referring to, for example... Figure 3A or Figure 3B The temperature correlation table shown indicates that this was determined. Figure 3A or Figure 3B Used as a lookup table. Various temperatures of the memory device correspond to various target write pulse widths.

[0033] exist Figure 3A In the example shown, example temperature-dependent table 302a is used as a lookup table. Temperature-dependent table 302a provides the target write pulse width 306 based on the temperature 304 of the memory cell array 102. Specifically, at a temperature of 125°C, the target write pulse width is 1 unit. At 105°C, the target write pulse width is 1.2 units; at 85°C, it is 1.5 units; at 60°C, it is 2 units; at 45°C, it is 2.2 units; at 25°C, it is 2.7 units; at 0°C, it is 3.5 units; and at -25°C, it is 5 units. In other words, the lower the temperature 304, the larger the target write pulse width 306 becomes.

[0034] exist Figure 3BIn the example shown, another example temperature-dependent table 302b is used as another lookup table. Temperature-dependent table 302b also provides a target write pulse width 306 based on the temperature 304 of the memory cell array 102. Specifically, the target write pulse width is 1 unit at 125°C; 1 unit at 105°C; 2 units at 85°C; 2 units at 60°C; 3 units at 45°C; 3 units at 25°C; 5 units at 0°C; and 5 units at -25°C. In other words, the lower the temperature 304, the larger the target write pulse width 306 becomes. Unlike temperature-dependent table 302a, temperature-dependent table 302b has a lower resolution. For example, for 25°C and 45°C, based on temperature correlation table 302b, the target write pulse width is 3 times. It should be noted that temperature correlation tables with higher or lower resolution than temperature correlation tables 302a and 203b can be used as needed.

[0035] Figure 3C This is a flowchart illustrating a method 300 for generating a temperature correlation table according to some embodiments. Typically, temperature correlation tables are generated during initial testing before the memory device leaves the factory (e.g., in...). Figure 3A or Figure 3B The temperature-related tables 302a or 302b are shown in the table. Method 300 begins at step 332, in which a memory device (e.g., Figure 1 The diagram illustrates a memory device 100 and a testing system. In one embodiment, the testing system is a memory tester used to test the memory device during an initial testing process prior to shipment. The memory tester can test whether the memory device is functioning correctly. To test the memory device, the memory tester can send various signals to the memory device and control the operation of the memory device. These signals may include, for example, address signals, data, command signals, and clock signals. In some examples, to store data in the memory device or retrieve data stored in the memory device, the memory tester can send command signals, address signals, and data. In some examples, the memory tester can store write data at a specific address on the memory device and can read data from the address where the write data is stored. The memory tester can then compare the written data and the read data to determine whether the write operation failed. Based on the results, the memory tester can calculate the write error rate of the memory device.

[0036] Then, method 300 proceeds to step 334. In step 334, the memory tester scans the temperature, write pulse width, and voltage of the memory device. This provides various combinations of conditions (e.g., at temperature T1, at voltage V1, and with a write pulse width WPW1). Then, method 300 proceeds to step 336. In step 336, the write error rate under different conditions is calculated. The write error rate can be calculated by counting write bit errors and dividing the write bit errors by the unit time. Then, method 300 proceeds to step 338. In step 338, a temperature-dependent table is generated based on the write error rates calculated under different conditions. Specifically, at a specific temperature Ti, the minimum write pulse width WPWi that can achieve an acceptable write error rate (e.g., below a threshold write error rate) is determined. In other words, at a specific temperature Ti, if the write pulse width is less than the minimum write pulse width WPWi, the write error rate will be higher than the threshold write error rate. Thus, the minimum write pulse width WPWi is the target write pulse width 306 corresponding to the specific temperature Ti. Because the memory tester scans the temperature of the memory, a temperature correlation table is generated covering a temperature range (e.g., -25°C to 125°C). Then, method 300 proceeds to step 340. In step 340, the temperature correlation table is stored in the memory bank of the memory device (e.g., ...). Figure 1 This is shown in memory cell 114. This allows for reference to temperature-related tables after the memory device leaves the factory.

[0037] Temperature correlation tables 302a and / or 302b are stored in the memory bank 114 of the controller 106. It should be noted that temperature correlation tables 302a and / or 302b are examples, and other temperature correlation tables can be used. Different temperature correlation tables can be used for different applications, such as mobile phones, smartwatches, tablets, and digital cameras. As mentioned above, different applications may have different acceptable write error rates. Thus, different temperature correlation tables can be used due to the different acceptable write error rates. In one example, the temperature correlation tables can be configured after the memory device leaves the factory. The memory device manufacturer provides temperature correlation tables generated during initial testing, which correspond to different applications. After shipment, the user can configure / select a suitable temperature correlation table for a specific application as needed.

[0038] Return to Figure 2In step 206, data is written to the memory device using the target write pulse width. The pulse generator circuit 112 of the controller 106 generates a write pulse with the target write pulse width 306, which is then used by the write circuit 130 in the write operation. Then, in one example, after a certain interval, the method loops back to step 202 to detect the temperature 304. In one example, the interval is configurable. In some applications (e.g., when used in industrial applications), the interval is relatively short, allowing the write pulse width to be adjusted relatively frequently. On the other hand (e.g., when used in consumer electronics such as mobile phones and smartwatches), the interval is relatively long, allowing the write pulse width to be adjusted relatively infrequently. Users can flexibly configure the time interval after the memory device leaves the factory. Thus, the write pulse width is adjusted based on the temperature 304 of the memory cell array 102 and temperature-related tables 302a or 302b. This adjustment allows the memory device 100 to operate under appropriate conditions to reduce the write error rate.

[0039] Figure 4 This is a flowchart illustrating another method of write pulse trimming according to some embodiments. Typically, the write pulse width of the memory device 100 is dynamically adjusted based on the write error rate of the memory device 100, thereby performing write operations under appropriate conditions to reduce the write error rate.

[0040] like Figure 4 As shown, the method begins at step 402, where an error monitor 136 detects the write error rate of the memory device 100. Since the error monitor 136 is coupled to the controller 106, the controller can make decisions based on the write error rate. At step 404, the controller 106 compares the detected write error rate to a threshold write error rate. The threshold write error rate is stored in memory 114 of the controller 106. In one example, the threshold write error rate is associated with the number of data bits written in a second write operation. During a write operation, some bits are not written as expected after the first write operation; these bits are called incomplete bits. Due to the incomplete bits, a second write operation is required. If there are still any incomplete bits after the second write operation, a third write operation is required. This process continues until there are no incomplete bits. Therefore, the number of data bits written in the second write operation can be used as a benchmark for the write error rate. In other words, if the number of write errors is greater than the number of data bits written in the second write operation, the number of write errors is generally considered relatively high. Other threshold write error rates can be used for different applications, such as mobile phones, smartwatches, tablets, and digital cameras. In one example, the threshold write error rate can be configurable. Depending on the result of step 404, the method proceeds to either step 406 or step 408.

[0041] When controller 106 determines that the write error rate is higher than a threshold write error rate, the write pulse width is increased at step 406. When controller 106 determines that the write error rate is not higher than the threshold write error rate, the write pulse width is decreased at that rate. The write pulse width is increased or decreased by pulse generator circuit 112 of controller 106. In one example, the write pulse width is increased or decreased by an amount proportional to the difference between the write error rate and the threshold write error rate. In other words, the larger the difference between the write error rate and the threshold write error rate, the larger the increase or decrease. Specifically, controller 106 determines the difference between the write error rate and the threshold write error rate. Then, pulse generator circuit 112 increases or decreases the write pulse width based on the deviation determined by controller 106. The larger the determined difference, the larger the increase or decrease step size. Thus, when the deviation between the write error rate and the threshold write error rate is large, the increase or decrease step size of the write pulse width is relatively large (i.e., similar to coarse adjustment). As the write error rate deviation decreases, the increment or decrement of the write pulse width becomes relatively small (i.e., like fine-tuning). This allows for relatively rapid write pulse width adjustment while avoiding over-adjustment due to increasing or decreasing the increment. In another example, the write pulse width is increased or decreased by a fixed amount. In other words, the fixed amount is predetermined. This fixed amount can be configured based on different applications such as mobile phones, smartwatches, tablets, and digital cameras. Specifically, the pulse generator circuit 112 increases or decreases the write pulse width regardless of the difference between the write error rate and the threshold write error rate. The predetermined increment or decrement simplifies the associated circuitry.

[0042] Following step 406 or 408, in one example, after a certain interval, the method loops back to step 402 to re-detect the write error rate of memory device 100. In one example, the interval is configurable. In some applications (e.g., when used in industrial applications), the interval is relatively short, allowing for relatively more frequent adjustments to the write pulse width. On the other hand (e.g., when used in consumer electronics such as mobile phones and smartwatches), the interval is relatively long, allowing for relatively infrequent adjustments to the write pulse width. Users can flexibly configure the time interval after the memory device leaves the factory. Thus, the write pulse width is adjusted based on the write error rate of memory device 100. This adjustment allows memory device 100 to operate under appropriate conditions to reduce the write error rate.

[0043] It should be noted that, Figure 2 Methods and Figure 4 The methods can be combined. In other words, the memory device 100 can employ... Figure 2 Methods and Figure 4In this case, the memory device 100 includes a temperature sensor 134 and an error monitor 136.

[0044] According to some disclosed embodiments, a method is provided. The method includes: detecting the temperature of a memory device; determining a target write pulse width based on the detected temperature of the memory device; and writing data to the memory device using the target write pulse width.

[0045] In the above method, the memory device is one of the following: ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), and phase change memory (PCM).

[0046] In the above method, determining the target write pulse width based on the detected temperature of the memory device includes: reading a temperature correlation table; identifying the temperature of the memory device in the temperature correlation table; and identifying the target write pulse width related to the temperature of the memory device.

[0047] In the above method, the memory device includes a memory cell array, and the temperature of the memory device is the temperature of the memory cell array.

[0048] In the above method, the temperature correlation table is generated during the initial testing process.

[0049] The above method also includes storing the unit temperature correlation table in the memory of the memory device.

[0050] In the above method, the temperature correlation table includes multiple temperature correlation tables corresponding to multiple applications.

[0051] In the above method, writing data to the memory device using a target write pulse width includes: generating a write pulse having a target write pulse width; and using the write pulse to write data to the memory device.

[0052] According to a further disclosed embodiment, a method includes: detecting a write error rate of a memory device; comparing the detected write error rate with a threshold write error rate; increasing the write pulse width if the detected write error rate is higher than the threshold write error rate; and decreasing the write pulse width if the detected write error rate is not higher than the threshold write error rate.

[0053] In the above method, the memory device is one of the following: ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), and phase change memory (PCM).

[0054] In the above method, the write pulse width is increased or decreased by a predetermined amount.

[0055] The above method also includes storing the threshold write error rate in the memory of the memory device.

[0056] In the above method, increasing the write pulse width includes: generating a first write pulse with an increased write pulse width; and using the first write pulse to write data to the memory device.

[0057] In the above method, reducing the write pulse width includes: generating a second write pulse with a reduced write pulse width; and using the second write pulse to write data to the memory device.

[0058] According to a further disclosed embodiment, a memory device is provided. The memory device includes: a memory cell array including a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device.

[0059] Among the aforementioned memory devices, the memory device is one of the following: ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), and phase change memory (PCM).

[0060] The aforementioned memory device further includes: an error monitor coupled to a controller, configured to detect a write error rate of the memory device; and wherein the controller is further configured to: compare the detected write error rate with a threshold write error rate; increase a target write pulse width if the detected write error rate is higher than the threshold write error rate; and decrease the target write pulse width if the detected write error rate is not higher than the threshold write error rate.

[0061] The memory device described above also includes a storage cell that stores a temperature correlation table, wherein the target write pulse width used by the write circuit is determined based on the detected temperature of the memory device using the temperature correlation table.

[0062] In the aforementioned memory devices, the temperature correlation table includes multiple temperature correlation tables corresponding to multiple applications.

[0063] The memory device described above also includes a pulse generator circuit coupled to the write circuit and configured to generate a write pulse having a target write pulse width used by the write circuit.

[0064] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made within the invention without departing from its spirit and scope.

Claims

1. A method for operating a memory device, comprising: Generate a temperature-related table; Detecting the temperature of memory devices; Detect the write error rate of the memory device; The target write pulse width is determined based on the detected temperature of the memory device; as well as Data is written to the memory device using the target write pulse width. Generating the temperature correlation table includes: Provide the memory device and the test system; Scan the temperature, write pulse width, and voltage of the memory device; Calculate the write error rate at different temperatures, write pulse widths, and voltages; The temperature correlation table is generated based on the write error rate calculated under different conditions. The temperature correlation table is stored in the memory of the memory device.

2. The method according to claim 1, wherein, The memory device is one of the following: ferroelectric random access memory, magnetic random access memory, resistive random access memory, and phase change memory.

3. The method according to claim 1, wherein, Determining the target write pulse width based on the detected temperature of the memory device includes: Read the temperature correlation table; Identify the temperature of the memory device in the temperature correlation table; and Identify the target write pulse width in relation to the temperature of the memory device.

4. The method according to claim 1, wherein, The memory device includes a memory cell array, and the temperature of the memory device is the temperature of the memory cell array.

5. The method according to claim 3, wherein, The temperature correlation table was generated during the initial testing process.

6. The method according to claim 3, further comprising: The temperature correlation table is stored in the memory of the memory device.

7. The method according to claim 3, wherein, The temperature correlation table includes multiple temperature correlation tables corresponding to multiple applications.

8. The method according to claim 1, wherein, Writing data to the memory device using the target write pulse width includes: Generate a write pulse having the target write pulse width; and The data is written to the memory device using the write pulse.

9. A method of operating a memory device, comprising: Generate a temperature-related table; Detect the write error rate of the memory device; The detected write error rate is compared with the threshold write error rate; If the detected write error rate is higher than the threshold write error rate, then increase the write pulse width; as well as If the detected write error rate is not higher than the threshold write error rate, then the write pulse width is reduced. Generating the temperature correlation table includes: Provide the memory device and the test system; Scan the temperature, write pulse width, and voltage of the memory device; Calculate the write error rate at different temperatures, write pulse widths, and voltages; The temperature-related table is generated based on the write error rate calculated under different conditions. The temperature correlation table is stored in the memory of the memory device.

10. The method according to claim 9, wherein, The memory device is one of the following: ferroelectric random access memory, magnetic random access memory, resistive random access memory, and phase change memory.

11. The method according to claim 9, wherein, The write pulse width is increased or decreased by a predetermined amount.

12. The method according to claim 9, further comprising: The threshold write error rate is stored in the memory of the memory device.

13. The method according to claim 9, wherein, Increasing the write pulse width includes: Generate a first write pulse with an increased write pulse width; and The first write pulse is used to write data to the memory device.

14. The method according to claim 9, wherein, The reduction of the write pulse width includes: Generate a second write pulse with a reduced write pulse width; and The second write pulse is used to write data to the memory device.

15. A memory device, comprising: A memory cell array, comprising multiple memory cells; A temperature sensor is configured to detect the temperature of the memory cell array; The write circuit is configured to write data into the plurality of memory cells; as well as A controller, coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory cell array; An error monitor, coupled to the controller, is configured to detect the write error rate of the memory device; A storage medium storing a temperature-dependent table, wherein the temperature-dependent table is generated based on the write error rate calculated under different temperatures, write pulse widths, and voltages of the memory device.

16. The memory device according to claim 15, wherein, The memory device is one of the following: ferroelectric random access memory, magnetic random access memory, resistive random access memory, and phase change memory.

17. The memory device according to claim 15, in, The controller is also configured to: The detected write error rate is compared with the threshold write error rate; If the detected write error rate is higher than the threshold write error rate, then the target write pulse width is increased; and If the detected write error rate is not higher than the threshold write error rate, then the target write pulse width is reduced.

18. The memory device according to claim 15, in, The target write pulse width used by the write circuit is determined based on the detected temperature of the memory device using the temperature correlation table.

19. The memory device according to claim 18, wherein, The temperature correlation table includes multiple temperature correlation tables corresponding to multiple applications.

20. The memory device of claim 17, further comprising: A pulse generator circuit, coupled to the write circuit, is configured to generate a write pulse having the target write pulse width used by the write circuit.

Images