Improved mr am cross-point memory with inverted mr am element vertical orientation

Abstract

The invention is entitled "Improved MRAM cross-point memory with inverted MRAM element vertical orientation." In a memory array having a cross-point structure, at each cross-point junction, a programmable resistive memory element such as an MRAM device is connected in series with a threshold switch selector such as a bidirectional threshold switch. In a two-layer cross-point structure having such memory cells, the MRAM devices in one layer are inverted relative to the MRAM devices in the other layer. This can allow a transient voltage spike to be applied across the MRAM device when the threshold switch selector is first turned on in a sensing operation to dissipate more quickly, thereby reducing the risk of changing the stored data state before the stored data state can be sensed.

Description

Technical Field

[0001] The present application relates to memory, and more particularly, to magnetoresistive random access memory. Background Art

[0002] Memory is widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, non-mobile computing devices, and data servers. Memory can include nonvolatile memory or volatile memory. Nonvolatile memory allows information to be stored and retained even when it is not connected to a power source (e.g., a battery).

[0003] An example of non-volatile memory is magnetoresistive random access memory (MRAM), which uses magnetization to represent stored data, as opposed to some other memory technologies that use charge to store data. Generally speaking, MRAM includes a large number of magnetic memory cells formed on a semiconductor substrate, where each memory cell represents (at least) one data bit. Data bits are written to the memory cell by changing the magnetization direction of a magnetic element within the memory cell, and the bit is read by measuring the resistance of the memory cell (low resistance typically represents a "0" bit and high resistance typically represents a "1" bit). As used herein, magnetization direction is the direction in which the magnetic moment is oriented.

[0004] Although MRAM is a promising technology, achieving high bit density and high endurance for fast write operations has been challenging for previous MRAM memory cell designs. Summary of the Invention

[0005] One embodiment of the present invention provides a memory device, which includes a non-volatile memory, the non-volatile memory including: a substrate; one or more memory arrays, the one or more memory arrays being formed on the substrate, each of the arrays including: a first group of conductive lines, the first group of conductive lines extending along a first direction parallel to a surface of the substrate; a second group of conductive lines, the second group of conductive lines being formed above the first group of conductive lines and extending along a second direction parallel to the surface of the substrate; a third group of conductive lines, the third group of conductive lines being formed above the second group of conductive lines and extending along the first direction; a first plurality of memory cells and a second plurality of memory cells, each of the first plurality of memory cells being connected between a corresponding one of the first group of conductive lines and a corresponding one of the second group of conductive lines, each of the first plurality of memory cells including a magnetoresistive resistor. A threshold switch selector is provided for connecting a first plurality of memory cells to a first memory cell and a second plurality of memory cells. The MRAM device includes a reference layer having a fixed magnetic field polarity and a free layer, the free layer being connected in series with the reference layer and having a programmable magnetic field polarity, wherein the free layer is formed below the reference layer. The second plurality of memory cells are each connected between a corresponding one of the second group of conductive lines and a corresponding one of the third group of conductive lines. Each of the second plurality of memory cells includes a threshold switch selector connected in series with the MRAM device. The MRAM device includes a reference layer having a fixed magnetic field polarity and a free layer, the free layer being connected in series with the reference layer and having a programmable magnetic field polarity, wherein the free layer is formed above the reference layer.

[0006] Another embodiment of the present invention provides a method for a memory cell, comprising: sensing a data state of a selected one of a first plurality of memory cells by forcing a read current to flow from a corresponding second conductive line to a corresponding first conductive line, wherein the selected one of the first plurality of memory cells is part of an array including a first plurality of memory cells and a second plurality of memory cells, wherein each of the first plurality of memory cells and the second plurality of memory cells includes a threshold switch selector connected in series with a magnetoresistive random access memory (MRAM) device; sensing a data state of a selected one of the second plurality of memory cells by forcing the read current to flow from the corresponding second conductive line to a corresponding third conductive line; sensing a data state of a selected one of the second plurality of memory cells by forcing the write current to flow from the corresponding second conductive line to a corresponding third conductive line; A conductive line is forced to the corresponding first conductive line to write a selected one of the first plurality of memory cells from the first state to the second state; a conductive line is forced to the corresponding first conductive line to write a selected one of the first plurality of memory cells from the first state to the second state; a conductive line is forced to the corresponding second conductive line to write a selected one of the first plurality of memory cells from the second state to the first state; a conductive line is forced to the corresponding third conductive line to write a selected one of the second plurality of memory cells from the first state to the second state; and a conductive line is forced to write a selected one of the second plurality of memory cells from the second state to the first state.

[0007] Yet another embodiment of the present invention provides a memory device, comprising: a controller circuit configured to be connected to an array of memory cells, wherein each memory cell has a threshold switch selector connected in series with a magnetoresistive random access memory (MRAM) device, the array comprising a first plurality of memory cells and a second plurality of memory cells, wherein each of the first plurality of memory cells is connected between a corresponding one of a first group of conductive lines and a corresponding one of a second group of conductive lines, and each of the second plurality of memory cells is connected between a corresponding one of a third group of conductive lines and a corresponding one of the second group of conductive lines, the controller circuit being configured to:

[0008] reading a selected memory cell of the first plurality of memory cells by biasing a corresponding one of the first set of conductive lines to a lower voltage than a corresponding one of the second set of conductive lines;

[0009] reading a selected memory cell of the second plurality of memory cells by biasing a corresponding one of the third set of conductive lines to a lower voltage than a corresponding one of the second set of conductive lines;

[0010] writing a selected one of the first plurality of memory cells from a first state to a second state by biasing a corresponding one of the first set of conductive lines to a lower voltage than a corresponding one of the second set of conductive lines;

[0011] writing a selected one of the first plurality of memory cells from the second state to the first state by biasing a corresponding one of the first set of conductive lines to a higher voltage than a corresponding one of the second set of conductive lines;

[0012] writing a selected one of the second plurality of memory cells from the first state to the second state by biasing a corresponding one of the third set of conductive lines to a lower voltage than a corresponding one of the second set of conductive lines; and

[0013] A selected memory cell of the second plurality of memory cells is written from the second state to the first state by biasing a corresponding one of the third set of conductive lines to a higher voltage than a corresponding one of the second set of conductive lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Like numbered elements refer to common parts in different figures.

[0015] Figure 1 is a block diagram of one embodiment of a memory system connected to a host.

[0016] Figure 2 is a block diagram of one embodiment of a front-end processor circuit. In some embodiments, the front-end processor circuit is part of a controller.

[0017] Figure 3 is a block diagram of one embodiment of a back-end processor circuit. In some embodiments, the back-end processor circuit is part of a controller.

[0018] Figure 4 is a block diagram of one embodiment of a memory package.

[0019] Figure 5 is a block diagram of one embodiment of a memory die.

[0020] Figure 6A and Figure 6B An example of a control circuit coupled to a memory structure via wafer-to-wafer bonding is shown.

[0021] Figure 7A One embodiment of a portion of a memory array forming a cross-point architecture is depicted in oblique view.

[0022] Figure 7B and Figure 7C They presented Figure 7A Side and top views of the junction structure in .

[0023] Figure 7D One embodiment of a portion of a two-level memory array forming a cross-point architecture is depicted in oblique view.

[0024] Figure 8A and Figure 8B One embodiment of the structure of an MRAM memory cell is shown.

[0025] Figure 9 One embodiment of an MRAM memory cell design to be implemented in a cross-point array is shown in greater detail.

[0026] Figure 10A and Figure 10B Writing to an MRAM memory cell by using a spin torque transfer (STT) mechanism is demonstrated.

[0027] Figure 11A and Figure 11B An embodiment for incorporating a threshold switch selector into an MRAM memory array having a cross-point architecture is presented.

[0028] Figure 12 An embodiment of a memory array having a cross-point architecture in which multiple memory cells are accessed simultaneously is depicted.

[0029] Figure 13 Depicted is an embodiment of a memory array having a cross-point architecture, showing the locations of contacts from the drivers to the bit lines and word lines.

[0030] Figure 14 is a flow chart of one embodiment of a process for simultaneously accessing multiple memory cells in a cross-point array.

[0031] Figure 15 is a flow chart depicting one embodiment of a process for simultaneously accessing multiple memory cells in a cross-point array including performing SSR.

[0032] Figure 16A Plotted is the current versus time relationship of the access current driven through the selected word line during SRR.

[0033] Figure 16BThe voltage across the selected MRAM cell during the SRR is plotted versus time and corresponds to Figure 16A .

[0034] Figure 17 Depicted is a flow chart of a process for writing data to an MRAM cell after a destructive SRR.

[0035] Figure 18 A flow chart depicting the process of the second stage of writing data into an MRAM cell.

[0036] Figure 19A The write current provided to the selected word line is plotted versus time.

[0037] Figure 19B The voltage across the MRAM cell versus time is plotted and corresponds to Figure 19A .

[0038] Figure 20 is a flow chart of a process for simultaneously writing MRAM cells, wherein all selected MRAM cells are first written to one of an AP state or a P state.

[0039] Figure 21A and Figure 21B are used in read operations respectively Figure 11A and Figure 11B One embodiment of a set of waveforms for the current and voltage of a layer 1 cell.

[0040] Figure 22 An example of the voltage of an MRAM device when a threshold switch selector switches from an off state to an on state is shown.

[0041] Figure 23 A two-tier implementation of a cross-point memory architecture is shown, where the MRAM devices in the lower tier are inverted relative to the upper tier in order to minimize capacitance in read operations.

[0042] Figure 24 is used Figure 23 Flowchart of an embodiment of a structure for performing self-reference reading.

[0043] Figure 25 is used to form Figure 23 Flowchart of an implementation scheme of the structure. DETAILED DESCRIPTION

[0044] In a memory array having a cross-point architecture, a first set of conductive lines extends across the surface of a substrate, and a second set of conductive lines is formed above the first set of conductive lines, extending above the substrate in a direction perpendicular to the first set of conductive lines. A memory cell is located at the intersection junction of the two sets of conductive lines. An embodiment of the memory cell may include a programmable resistive element, such as an MRAM memory device, connected in series with a selector switch. One type of selector switch is a threshold switch selector, such as a bidirectional threshold switch (OTS), which can be implemented in a small amount of area relative to other switching elements, such as transistors, and does not require additional control lines. If the voltage or current is above a certain level, a threshold voltage (V 阈值 ) or the threshold current (I 阈值 ) through the threshold switch selector, which switches to the on state, V in series with the resistor 保持 When the threshold switch selector is initially turned on, a transient voltage spike is applied across the series-connected MRAM devices because V 保持 Can be less than V 阈值 , especially since a higher V threshold (by thickening the selector) results in lower leakage. And a lower V 保持 This results in more available write current for a given power supply, such as 3.3 V. This transient current may be briefly greater than the I that can change the state of the memory cell before being sensed. 读取 or I 写入 By dissipating transient voltage spikes more quickly, such as by reducing the cell, line, and transistor select and driver capacitances connected to the selected memory bit, the risk of such disturbances can be reduced and the sensing operation can be performed faster.

[0045] In a cross-point architecture with two or more layers of memory cells, the MRAM devices in each layer are typically formed with the same vertical orientation as the layers of the MRAM devices. MRAM devices exhibit directionality, whereby when writing to the memory cells using spin transfer torque, current applied in one direction writes the MRAM device from a high-resistance anti-parallel state (HRS or AP) to a low-resistance parallel state (LRS or P), while current applied in the opposite direction writes the MRAM device from a low-resistance state to a high-resistance state. Due to this directionality, there is also typically a preferred direction for applying the read current when sensing the memory cells, as more current may be required over a longer time to write a bit from P to AP. In cases where memory cells in different layers have the same orientation, when the threshold switch selector is turned on for a read operation, one of the layers can discharge a transient voltage spike more quickly because the driver capacitance of the threshold switch selector may be smaller. By inverting the MRAM structure of one layer relative to the other, both layers can be given an orientation that allows this spike to dissipate more quickly, thereby reducing the likelihood that the stored data state will change before it is sensed. This can also result in improved read latency access times.

[0046] Figure 1 1 is a block diagram of one embodiment of a memory system 100 connected to a host 120. Memory system 100 can implement the techniques presented herein for operating a cross-point memory array that has experienced excessive drift. Many different types of memory systems can be used with the techniques presented herein. Exemplary memory systems include: solid-state drives ("SSDs"); memory cards including dual in-line memory modules (DIMMs) for DRAM replacement; and embedded memory devices; however, other types of memory systems can also be used.

[0047] Figure 1Memory system 100 includes a controller 102, non-volatile memory 104 for storing data, and local memory (e.g., DRAM / ReRAM) 106. Controller 102 includes a front-end processor (FEP) circuit 110 and one or more back-end processor (BEP) circuits 112. In one embodiment, FEP circuit 110 is implemented on an application-specific integrated circuit (ASIC). In one embodiment, each BEP circuit 112 is implemented on a separate ASIC. In other embodiments, a unified controller ASIC may combine both front-end and back-end functions. The ASICs for each of BEP circuit 112 and FEP circuit 110 are implemented on the same semiconductor, allowing controller 102 to be manufactured as a system on a chip ("SoC"). Each of FEP circuit 110 and BEP circuit 112 includes its own processor. In one embodiment, FEP circuit 110 and BEP circuit 112 are configured as a master-slave configuration, with FEP circuit 110 being the master device and each BEP circuit 112 being a slave device. For example, FEP circuitry 110 implements a flash translation layer (FTL) or media management layer (MML), which performs memory management (e.g., garbage collection, wear leveling, etc.), logical-to-physical address translation, communication with the host, DRAM (local volatile memory) management, and overall operation management of the SSD (or other non-volatile storage system). BEP circuitry 112 manages memory operations within the memory package / die based on requests from FEP circuitry 110. For example, BEP circuitry 112 can implement read, erase, and program processes. Additionally, BEP circuitry 112 can perform buffer management, set specific voltage levels required by FEP circuitry 110, perform error correction (ECC), control the switch-mode interface to the memory package, and more. In one embodiment, each BEP circuitry 112 is responsible for its own set of memory packages.

[0048] In one embodiment, the non-volatile memory 104 includes a plurality of memory packages. Each memory package includes one or more memory dies. Thus, the controller 102 is connected to one or more non-volatile memory dies. In one embodiment, each memory die in the memory package 104 utilizes NAND flash memory (including two-dimensional NAND flash memory and / or three-dimensional NAND flash memory). In other embodiments, the memory package may include other types of memory, such as storage class memory (SCM) or phase change memory (PCM) based on resistive random access memory (such as ReRAM, MRAM, FeRAM, or RRAM). In another embodiment, a BEP or FEP is included on the memory die.

[0049] Controller 102 communicates with host 120 via interface 130, which implements a protocol such as PCI Express (PCIe) or NVM Express (NVMe) using a JEDEC standard double data rate (DDR) or low power double data rate (LPDDR) interface (such as DDR5 or LPDDR5). To work with memory system 100, host 120 includes a host processor 122, host memory 124, and PCIe interface 126 connected along bus 128. Host memory 124 is the host's physical memory and can be DRAM, SRAM, non-volatile memory, or another type of storage device. Host 120 is external to and separate from memory system 100. In one embodiment, memory system 100 is embedded in host 120.

[0050] Figure 2 is a block diagram of one embodiment of the FEP circuit 110 . Figure 2 A PCIe interface 150 is shown communicating with a host 120, along with a host processor 152 communicating with the PCIe interface. Host processor 152 can be any type of processor known in the art and suitable for implementation. Host processor 152 communicates with a network-on-chip (NOC) 154. A NOC is a communication subsystem on an integrated circuit, typically between cores in a SoC. A NOC can span synchronous and asynchronous clock domains, or utilize unclocked asynchronous logic. NOC technology applies network theory and methods to on-chip communication, offering significant improvements over conventional bus and crossbar interconnects. Compared to other designs, NOCs improve the scalability of SoCs and the power efficiency of complex SoCs. The wires and links in a NOC are shared by many signals. Because all links in a NOC can operate simultaneously on different data packets, a high degree of parallelism is achieved. Consequently, as the complexity of integrated subsystems continues to increase, NOCs offer enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges). Connected to and in communication with the NOC 154 are a memory processor 156, SRAM 160, and a DRAM controller 162. The DRAM controller 162 is used to operate and communicate with DRAM (e.g., DRAM 106). The SRAM 160 is a local RAM memory used by the memory processor 156. The memory processor 156 is used to run the FEP circuitry and perform various memory operations. Also in communication with the NOC are two PCIe interfaces 164 and 166. Figure 2In an embodiment, the SSD controller will include two BEP circuits 112; therefore, there are two PCIe interfaces 164 / 166. Each PCIe interface communicates with one of the BEP circuits 112. In other embodiments, there may be more or less than two BEP circuits 112; therefore, there may be more than two PCIe interfaces.

[0051] The FEP circuit 110 may also include a flash translation layer (FTL), or more generally a media management layer (MML) 158, which performs memory management (e.g., garbage collection, wear leveling, load balancing, etc.), logical to physical address translation, communication with the host, management of DRAM (local volatile memory), and management of the overall operation of the SSD or other non-volatile storage system. The media management layer (MML) 158 may be integrated as part of the memory management that can handle memory errors and interact with the host interface. Specifically, the MML may be a module in the FEP circuit 110 and may be responsible for the internals of memory management. Specifically, the MML 158 may include algorithms in the memory device firmware that convert writes from the host to memory structures on the die (e.g., downlinks). Figure 5 and Figure 6A 502 / 602). MML 158 may be required because: 1) the memory may have limited endurance; 2) the memory structure may only be written to a number of pages; and / or 3) the memory structure may not be written to unless it is block erased. MML 158 understands these potential limitations of the memory structure, which may not be visible to the host. Therefore, MML 158 attempts to convert writes from the host into writes to the memory structure.

[0052] Figure 3 is a block diagram of one embodiment of the BEP circuit 112 . Figure 3 A circuit for communicating with the FEP circuit 110 (e.g., Figure 2The PCIe interface 200 communicates with one of the PCIe interfaces 164 and 166 of the processor. The PCIe interface 200 communicates with two NOCs 202 and 204. In one embodiment, the two NOCs can be combined into a large NOC. Each NOC (202 / 204) is connected to the SRAM (230 / 260), buffers (232 / 262), processors (220 / 250) and data path controllers (222 / 252) through an XOR engine (224 / 254) and an ECC engine (226 / 256). The ECC engine 226 / 256 is used to perform error correction, as is known in the art. The XOR engine 224 / 254 is used to perform XOR on the data so that the data can be combined and stored in a recoverable manner in the presence of programming errors. The data path controller 222 is connected to the interface module for communicating with the memory package via four channels. Thus, the top NOC 202 is associated with an interface 228 for four channels for communicating with the memory package, and the bottom NOC 204 is associated with an interface 258 for four additional channels for communicating with the memory package. Each interface 228 / 258 includes four switch mode interfaces (TM interfaces), four buffers, and four schedulers. There is a scheduler, buffer, and TM interface for each of the channels. The processor can be any standard processor known in the art. The data path controller 222 / 252 can be a processor, FPGA, microprocessor, or other type of controller. The XOR engine 224 / 254 and the ECC engine 226 / 256 are dedicated hardware circuits, referred to as hardware accelerators. In other embodiments, the XOR engine 224 / 254 and the ECC engine 226 / 256 can be implemented in software. The scheduler, buffer, and TM interface are hardware circuits.

[0053] Figure 4 is a block diagram of one embodiment of a memory package 104 including multiple memory dies 292 connected to a memory bus (data lines and chip enable lines) 294. The memory bus 294 is connected to a switch mode interface 296 for communicating with the TM interface of the BEP circuit 112 (see, e.g., Figure 3 ). In some embodiments, the memory package may include a small controller connected to the memory bus and the TM interface. The memory package may have one or more memory dies. In one embodiment, each memory package includes eight or 16 memory dies; however, other numbers of memory dies may also be implemented. In another embodiment, the switching interface is changed to JEDEC standard DDR or LPDDR, with or without variations such as relaxed timing settings or smaller page sizes. The technology described herein is not limited to any particular number of memory dies.

[0054] Figure 5 is a block diagram depicting one example of a memory die 500 that may implement the techniques described herein. Figure 4 Memory die 500, one of the memory dies 292, includes a memory array 502, which may include any of the memory cells described below. The array terminal lines of memory array 502 include various word line layers organized into rows, and various bit line layers organized into columns. However, other orientations may also be implemented. Memory die 500 includes row control circuitry 520, whose outputs 508 are connected to corresponding word lines of memory array 502. Row control circuitry 520 receives a set of M row address signals and one or more various control signals from system control logic circuitry 560 and may generally include circuitry such as a row decoder 522, array terminal drivers 524, and block select circuitry 526 for both read and write operations. Row control circuitry 520 may also include read / write circuitry. In one embodiment, row control circuitry 520 includes sense amplifiers 528, each of which includes circuitry for sensing the condition (e.g., voltage) of a word line of memory array 502. In one embodiment, the condition of a memory cell in the cross-point array is determined by sensing the word line voltage. Memory die 500 also includes column control circuitry 510, whose inputs / outputs 506 are connected to corresponding bit lines of memory array 502. Although only a single block is shown for array 502, the memory die may include multiple arrays or "tiles" that can be accessed individually. Column control circuitry 510 receives a set of N column address signals and one or more various control signals from system control logic 560 and may generally include circuitry such as a column decoder 512, array terminal receivers or drivers 514, block select circuitry 516, as well as read / write circuitry and I / O multiplexers.

[0055] The system control logic 560 receives data and commands from the host and provides output data and status to the host. In other embodiments, the system control logic 560 receives data and commands from a separate controller circuit and provides output data to the controller circuit, wherein the controller circuit communicates with the host. In some embodiments, the system control logic 560 may include a state machine 562 that provides die-level control of memory operations. In one embodiment, the state machine 562 is programmable by software. In other embodiments, the state machine 562 does not use software and is implemented entirely in hardware (e.g., circuitry). In another embodiment, the state machine 562 is replaced by a microcontroller or microprocessor, wherein the microcontroller or microprocessor is on or off the memory chip. The system control logic 560 may also include a power control module 564, which controls the power and voltage supplied to the rows and columns of the memory 502 during memory operations and may include a charge pump and regulator circuit for generating regulated voltages. The system control logic 560 includes a storage device 566, which can be used to store parameters for operating the memory array 502.

[0056] Commands and data are transmitted between the controller 102 and the memory die 500 via the memory controller interface 568 (also referred to as the "communication interface"). The memory controller interface 568 is an electrical interface for communicating with the memory controller 102. Examples of the memory controller interface 568 include a switch-mode interface and an open NAND Flash interface (ONFI). Other I / O interfaces may also be used. For example, the memory controller interface 568 may implement a switch-mode interface that connects to the switch-mode interface of the memory interface 228 / 258 of the memory controller 102. In one embodiment, the memory controller interface 568 includes a set of input and / or output (I / O) pins connected to the controller 102.

[0057] In some embodiments, all elements of memory die 500, including system control logic 560, can be formed as part of a single die. In other embodiments, some or all of system control logic 560 can be formed on different dies.

[0058] For purposes of this document, the phrase "one or more control circuits" may include the controller, state machine, microcontroller, and / or other control circuitry represented by system control logic 560, or other similar circuitry for controlling non-volatile memory.

[0059] In one embodiment, memory structure 502 includes a three-dimensional memory array of non-volatile memory cells, wherein multiple memory levels are formed above a single substrate (such as a wafer). The memory structure can include any type of non-volatile memory formed integrally in one or more physical levels of memory cells having active regions disposed above a silicon (or other type) substrate. In one example, the non-volatile memory cells include vertical NAND strings having charge-trapping material.

[0060] In another embodiment, the memory structure 502 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells that utilize floating gates. Other types of memory cells (e.g., NOR-type flash memory) may also be used.

[0061] The exact type of memory array architecture or memory cells included in the memory structure 502 is not limited to the examples described above. Many different types of memory array architectures or memory technologies can be used to form the memory structure 326. No specific non-volatile memory technology is required to implement the claimed novel embodiments presented herein. Other examples of suitable technologies for the memory cells of the memory structure 502 include ReRAM memory (resistive random access memory), magnetoresistive memory (e.g., MRAM, spin transfer torque MRAM, spin orbit torque MRAM), FeRAM, phase change memory (e.g., PCM), and the like. Examples of suitable technologies for the memory cell architecture of the memory structure 502 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, and the like.

[0062] One example of a ReRAM crosspoint memory includes a reversible resistance switching element arranged in a crosspoint array accessed by an X line and a Y line (e.g., a word line and a bit line). In another embodiment, the memory cell may include a conductive bridge memory element. The conductive bridge memory element may also be referred to as a programmable metallization unit. Based on the physical repositioning of ions within a solid electrolyte, the conductive bridge memory element may be used as a state-changing element. In some cases, the conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between the two electrodes. As the temperature increases, the mobility of the ions also increases, which causes the programming threshold of the conductive bridge memory cell to decrease. Therefore, the conductive bridge memory element may have a wide range of programming thresholds over the entire temperature range.

[0063] Another example is magnetoresistive random access memory (MRAM), which stores data via magnetic storage elements. These elements are formed by two ferromagnetic layers separated by a thin insulating layer, each of which can maintain magnetization. One of the two layers is a permanent magnet set to a specific polarity; the magnetization of the other layer can be changed to match the magnetization of the storage memory by an external magnetic field. The memory device is constructed from a grid of such memory cells. In one embodiment for programming, each memory cell is located between a pair of write wires that are arranged at right angles to each other, parallel to the cell, one above the cell and one below the cell. When current passes through them, an induced magnetic field is generated. Memory embodiments based on MRAM will be discussed in more detail below.

[0064] Phase change memory (PCM) takes advantage of the unique properties of chalcogenide glasses. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve non-thermal phase changes by changing the coordination state of the germanium atoms using only laser pulses (or light pulses from another source). Therefore, the programming dose is the laser pulse. The memory cell can be inhibited by preventing the memory cell from receiving light. In other PCM embodiments, the memory cell is programmed by current pulses. It should be noted that the use of "pulse" in this document does not require a rectangular pulse, but includes (continuous or discontinuous) vibrations or pulse trains of sound, current, voltage light or other waves. These memory elements within each selectable memory cell or bit can include additional series elements as selectors, such as a bidirectional threshold switch or a metal insulator substrate.

[0065] Those skilled in the art will recognize that the technology described herein is not limited to a single particular memory structure, memory configuration, or material composition, but encompasses many related memory structures within the spirit and scope of the technology as described herein and as understood by those skilled in the art.

[0066] You can Figure 5The components of the memory system 500 are grouped into two parts: the memory structure 502 of the memory cells; and the peripheral circuitry, which includes all other components. An important characteristic of a memory circuit is its capacity, which can be increased by increasing the area of ​​the memory die of the memory system 500 that is reserved for specific uses of the memory structure 502; however, this reduces the area of ​​the memory die available for the peripheral circuitry. This can place quite severe constraints on these peripheral components. For example, the need to fit sense amplifier circuitry within the available area can be a significant constraint on the sense amplifier design architecture. The reduction in available area can limit the available functionality that can be implemented on the chip relative to the system control logic 560. Therefore, in the design of the memory die of the memory system 500, a fundamental trade-off needs to be made between the amount of area dedicated to the memory structure 502 and the amount of area dedicated to the peripheral circuitry.

[0067] Another area where the memory structure 502 and the peripheral circuitry are often at odds is in the processing involved in forming these areas, as these areas often involve different processing technologies and the trade-offs when implementing different technologies on a single die. For example, when the memory structure 502 is NAND flash memory, it is an NMOS structure, while the peripheral circuitry is typically CMOS-based. For example, elements such as sense amplifier circuits, charge pumps, logic elements in the state machine, and other peripheral circuitry in the system control logic 560 often utilize PMOS devices. The processing operations used to manufacture a CMOS die will differ in many respects from those optimized for NMOS flash, NAND memory, or other memory cell technologies.

[0068] To improve these limitations, the following embodiments may Figure 5The components are separated onto separately formed dies, which are then bonded together. More specifically, the memory structure 502 can be formed on one die, and some or all of the peripheral circuit elements (including one or more control circuits) can be formed on a separate die. For example, a memory die can be formed solely of memory elements, such as a memory cell array of flash NAND memory, MRAM memory, PCM memory, ReRAM memory, or other memory types. Some or all of the peripheral circuitry (even including elements such as decoders and sense amplifiers) can then be moved to a separate die. This allows each die in the memory die to be optimized individually based on its technology. For example, a NAND memory die can be optimized for an NMOS-based memory array structure without having to worry about CMOS elements that have now been moved to a separate peripheral circuitry die that can be optimized for CMOS processing. This provides more space for peripheral elements, allowing for the integration of additional capabilities that might not be easily incorporated if the peripheral elements were confined to the edge of the same die housing the memory cell array. Two dies can then be bonded together in a bonded multi-die memory circuit, with the array on one die connected to the peripheral elements on the other memory circuit. For example, although the following description will focus on bonded memory circuits with one memory die and one peripheral circuit die, other embodiments may use more dies, such as two memory dies and one peripheral circuit die.

[0069] Figure 6A and Figure 6B Shown Figure 5 An alternative arrangement to the arrangement of , which can be implemented using wafer-to-wafer bonding to provide bonded die pairs for memory system 600. Figure 6A An example of peripheral circuitry is shown, including control circuits formed in a peripheral circuit or control die 611 coupled to a memory structure 602 formed in a memory die 601. Figure 5 Like 502, memory die 601 may include multiple independently accessible arrays or "tiles." Common components and Figure 5 Similarly labeled (e.g., 502 is now 602, 510 is now 610, and so on). As can be seen, system control logic 660, row control circuitry 620, and column control circuitry 610 are located in control die 611. In some embodiments, all or a portion of column control circuitry 610 and all or a portion of row control circuitry 620 are located on memory structures die 601. In some embodiments, some circuitry in system control logic 660 is located on memory structures die 601.

[0070] The system control logic 660, row control circuitry 620, and column control circuitry 610 can be formed using conventional processes (e.g., CMOS processes), so that adding elements and functionality more commonly found on the memory controller 102, such as ECC, may require few or no additional process steps (i.e., the same process steps used to manufacture the controller 102 can also be used to manufacture the system control logic 660, row control circuitry 620, and column control circuitry 610). Thus, while moving such circuitry off a die (such as the memory die 292) may reduce the number of steps required to manufacture such a die, adding such circuitry to a die (such as the control die 611) may not require any additional process steps.

[0071] Figure 6A Column control circuitry 610 on control die 611 is shown coupled to memory structure 602 on memory structure die 601 via electrical paths 606. For example, electrical paths 606 can provide electrical connections between column decoders 612, driver circuitry 614, block selects 616, and bit lines of memory structure 602. Electrical paths can extend from column control circuitry 610 in control die 611 through pads on control die 611 that are bonded to corresponding pads on memory structure die 601 that are connected to bit lines of memory structure 602. Each bit line of memory structure 602 can have a corresponding electrical path in electrical paths 606, including a pair of bond pads connected to column control circuitry 610. Similarly, row control circuitry 620 (including row decoders 622, array drivers 624, block selectors 626, and sense amplifiers 628) is coupled to memory structure 602 via electrical paths 608. Each of the electrical paths 608 may correspond to a word line, a dummy word line, or a selected gate line.Additional electrical paths may also be provided between the control die 611 and the memory die 601 .

[0072] For the purposes of this document, the phrase "control circuitry" may include one or more of the controller 102, the system control logic 660, the column control circuitry 610, the row control circuitry 620, a microcontroller, a state machine, and / or other control circuitry, or other similar circuitry for controlling non-volatile memory. The control circuitry may include only hardware or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. The control circuitry may include a processor, an FGA, an ASIC, an integrated circuit, or other types of circuitry.

[0073] In the following discussion, Figure 5 and Figure 6AThe memory array 502 / 602 will be discussed in the context of a cross-point architecture. In a cross-point architecture, a first set of conductive lines or conductors (such as word lines) extend in a first direction relative to an underlying substrate, and a second set of conductive lines or conductors (such as bit lines) extend in a second direction relative to the underlying substrate. Memory cells are located at the intersections of the word lines and the bit lines. The memory cells at these intersections can be formed according to any of a variety of technologies, including those described above. The following discussion will primarily focus on embodiments based on a cross-point architecture using MRAM memory cells.

[0074] Figure 6B 6 is a block diagram showing more details of the arrangement of one embodiment of an integrated memory component for a bonded die pair 600. Memory die 601 contains a plane or array 602 of memory cells. Memory die 601 may have additional planes or arrays. A representative bit line (BL) and a representative word line (WL) 666 are depicted for each plane or array 602. There may be thousands or tens of thousands of such bit lines per plane or array 602. In one embodiment, an array or plane represents a group of connected memory cells that share a common set of continuous word lines and continuous bit lines.

[0075] The control die 611 includes a plurality of bit line drivers 614. In some embodiments, each bit line driver 614 is connected to one bit line or can be connected to multiple bit lines. The control die 611 includes a plurality of word line drivers 624(1) to 624(n). The word line driver 660 is configured to provide voltages to the word lines. In this example, there are "n" word lines per array or plane of memory cells. In one embodiment, if the memory operation is programming or reading, one word line within the selected block is selected for the memory operation. In one embodiment, if the memory operation is erasing, all word lines within the selected block are selected for erasing. The word line driver 660 provides voltages to the word lines in the memory die 601. As described above with respect to Figure 6A As discussed, the control die 611 may also include a charge pump, a voltage generator, and Figure 6B Similar components not shown in FIG. 6A may be used to provide voltages for the word line driver 660 and / or the bit line driver 614 .

[0076] The memory die 601 has a plurality of bonding pads 670a, 670b on a first major surface 682 of the memory die 601. There may be "n" bonding pads 670a to receive voltages from corresponding "n" word line drivers 624(1) through 624(n). There may be one bonding pad 670b for each bit line associated with the array 602. The reference numeral 670 will be used to generally refer to the bonding pads on the major surface 682.

[0077] In some embodiments, each data bit and each parity bit of a codeword is transmitted via a different pair of bonding pads 670b, 674b. The bits of the codeword can be transmitted in parallel via the bonding pad pairs 670b, 674b. This provides for very efficient data transmission relative to, for example, transmitting data between the memory controller 102 and the integrated memory component 600. For example, the data bus between the memory controller 102 and the integrated memory component 600 can, for example, provide 8 bits, 16 bits, or possibly 32 bits to be transmitted simultaneously. However, the data bus between the memory controller 102 and the integrated memory component 600 is not limited to these examples.

[0078] The control die 611 has a plurality of bonding pads 674a, 674b on a first major surface 684 of the control die 611. There can be "n" bonding pads 674a to deliver voltages from corresponding "n" word line drivers 624(1) to 624(n) to the memory die 601. There can be one bonding pad 674b for each bit line associated with the array 602. The reference numeral 674 will be used to generally refer to the bonding pads on the major surface 682. Note that there can be bonding pad pairs 670a / 674a and bonding pad pairs 670b / 674b. In some embodiments, the bonding pads 670 and / or 674 are flip chip bonding pads.

[0079] In one embodiment, the pattern of the bonding pads 670 matches the pattern of the bonding pads 674. The bonding pads 670 are bonded (e.g., flip-chip bonded) to the bonding pads 674. Thus, the bonding pads 670, 674 electrically and physically couple the memory die 601 to the control die 611. Additionally, the bonding pads 670, 674 permit internal signal transmission between the memory die 601 and the control die 611. Thus, the memory die 601 and the control die 611 are bonded together using the bonding pads. Although Figure 6A One control die 611 is depicted bonded to one memory die 601 , but in another embodiment, one control die 611 is bonded to multiple memory dies 601 .

[0080] As used herein, "internal signaling" refers to signaling between the control die 611 and the memory die 601. Internal signaling allows circuitry on the control die 611 to control memory operations in the memory die 601. Therefore, the bonding pads 670 and 674 can be used for memory operation signaling. As used herein, "memory operation signaling" refers to any signal related to memory operations in the memory die 601. Memory operation signaling can include, but is not limited to, providing voltage, providing current, receiving voltage, receiving current, sensing voltage, and / or sensing current.

[0081] The bonding pads 670, 674 can be formed of, for example, copper, aluminum, and alloys thereof. A liner can be present between the bonding pads 670, 674 and the main surface (682, 684). The liner can be formed of, for example, a titanium / titanium nitride stack. The bonding pads 670, 674 and the liner can be applied by vapor deposition and / or electroplating techniques. The bonding pad and liner together can have a thickness of 720 nm, but in other embodiments, the thickness can be greater or less.

[0082] Metal interconnects and / or vias can be used to electrically connect various components in the die to bonding pads 670, 674. Several conductive paths that can be implemented with metal interconnects and / or vias are described. For example, a sense amplifier can be electrically connected to bonding pad 674b via via 664. Figure 6A , electrical path 606 may correspond to via 664, bonding pad 674b, and bonding pad 670b. There may be thousands of such sense amplifiers, vias, and bonding pads. Note that the BL does not necessarily connect directly to bonding pad 670b. The word line driver 660 may be electrically connected to bonding pad 674a via via 662. Figure 6A , electrical path 608 can correspond to via 662, bonding pad 674a, and bonding pad 670a. Note that via 662 can include a separate conductive path for each word line driver 624(1) to 624(n). Likewise, there can be a separate bonding pad 674a for each word line driver 624(1) to 624(n). The word lines in block 2 of memory die 601 can be electrically connected to bonding pad 670a via via 664. Figure 6B , for the corresponding "n" word lines in a block, there are "n" vias 664. For each via 664, there may be a separate pair of bonding pads 670a, 674a.

[0083] Relative to Figure 5 , Figure 6A The on-die control circuitry may also include additional functionality within its logic elements, including both more general capabilities commonly found in memory controller 102 and some CPU capabilities, as well as application-specific features.

[0084] Hereinafter, the system control logic 560 / 660, the column control circuitry 510 / 610, the row control circuitry 520 / 620 and / or the controller 102 (or circuitry of equivalent functionality), in combination with Figure 5 Depicted in or Figure 6A All or a subset of the other circuitry on the control die 611 in Figure 5Similar elements in the examples may be considered to be part of one or more control circuits that perform the functions described herein. The control circuitry may include only hardware or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. The control circuitry may include a processor, FGA, ASIC, integrated circuit, or other types of circuitry.

[0085] In the following discussion, Figure 5 and Figure 6A The memory array 502 / 602 will be discussed primarily in the context of a cross-point architecture, but much of the discussion can be applied more generally. In a cross-point architecture, a first set of conductive lines or conductors (such as word lines) extend in a first direction relative to an underlying substrate, and a second set of conductive lines or conductors (such as bit lines) extend in a second direction relative to the underlying substrate. Memory cells are located at the intersections of the word lines and the bit lines. The memory cells at these intersections can be formed according to any of a variety of technologies, including those described above. The following discussion will primarily focus on embodiments based on a cross-point architecture using MRAM memory cells.

[0086] Figure 7A One embodiment of a portion of a memory array forming a cross-point architecture is depicted in oblique view. Figure 7A The memory array 502 / 602 is Figure 5 Memory array 502 or Figure 6A FIG. 6 is an example of a specific implementation of a memory array 602 in FIG. 6 , wherein a memory die may include multiple such array structures. Bit lines BL1-BL5 are arranged along a first direction (shown as extending into the page) relative to an underlying substrate (not shown) of the die, while word lines WL1-WL5 are arranged along a second direction perpendicular to the first direction. Figure 7A is an example of a horizontal cross-point structure in which both word lines WL1-WL5 and BL1-BL5 extend in a horizontal direction relative to the substrate, and memory cells (two of which are indicated at 701) are oriented so that current through the memory cells (such as indicated by I 单元 In a memory array having additional layers of memory cells, such as described below with respect to Figure 7D As discussed, there will be corresponding additional layers of bit lines and word lines.

[0087] like Figure 7AAs depicted, the memory array 502 / 602 includes a plurality of memory cells 701. The memory cells 701 may include rewritable memory cells, such as may be implemented using ReRAM, MRAM, PCM, or other materials with programmable resistance. The following discussion will focus on MRAM memory cells, but much of the discussion may apply more generally. The current in the memory cells of the first memory level is shown as arrows I 单元 Upward flow is indicated, but current can flow in either direction, as discussed in more detail below.

[0088] Figure 7B and Figure 7C They presented Figure 7A Side and top views of the junction structure in . Figure 7B The side view shows a bottom line or word line WL1, and a top line or bit line BL1-BL n An MRAM memory cell 1201 is located at the intersection between each top and bottom line, but PCM, ReRAM, or other technologies could be used. Figure 7C Is to show M bottom lines WL1-WL M and N top lines BL1-BL N A top view of a cross-point structure. In a binary implementation, the MRAM cell at each cross-point can be programmed to one of at least two resistance states—a high resistance state and a low resistance state. Further details on embodiments of MRAM memory cell design and their programming techniques are provided below.

[0089] Figure 7A The cross-point array of FIG shows an embodiment with one layer of word lines and bit lines, where the MRAM or other memory cells are located at the intersection of two sets of conductive lines. To increase the storage density of the memory tube die, multiple layers of such memory cells and conductive lines can be formed. The double layer example in Figure 7D In display.

[0090] Figure 7D One embodiment of a portion of a two-level memory array forming a cross-point architecture is depicted in oblique view. Figure 7A As shown, Figure 7D The first layer 718 memory cells 701 of the array 502 / 602 are shown, connected to the first layer word lines WL 1,1 -WL 1,4 The second layer of memory cells 720 is formed above the bit lines BL1-BL5 and at the intersections of these bit lines and the second set of word lines WL 2,1 -WL 2,4 Between. Although Figure 7DTwo layers of memory cells 718 and 720 are shown, but the structure can be extended upwards by additional alternating layers of word lines and bit lines. Depending on the embodiment, Figure 7D The word lines and bit lines of the array can be biased for read or program operations so that current in each layer flows from the word line layer to the bit line layer or vice versa. For a given operation, the two layers can be configured to have current in each layer in the same direction or in opposite directions.

[0091] The use of a cross point architecture allows for arrays with a small footprint, and several such arrays can be formed on a single die. The memory cells formed at each cross point can be resistive type memory cells, where the data value is encoded as a different resistance level. Depending on the embodiment, the memory cells can be binary valued, having a low resistance state or a high resistance state, or multi-level cells (MLCs), which can have additional resistance intermediate between the low resistance state and the high resistance state. The cross point arrays described herein can be used as Figure 4 The memory die 292 may be used to replace the local memory 106, or both. The resistive memory cells may be formed according to many of the technologies mentioned above, such as ReRAM, FeRAM, PCM, or MRAM. The following discussion is primarily presented in the context of a memory array using a cross-point architecture with binary-valued MRAM memory cells, but much of the discussion is applicable more generally.

[0092] Figure 8A and Figure 8B One embodiment of the structure of an MRAM memory cell is shown. Figure 8A In the example, the voltage applied across the memory cell (between the corresponding word line and bit line of the memory cell) is represented as the voltage source V 施加 813. The memory cell includes a bottom electrode 801, a pair of magnetic layers (reference layer 803 and free layer 807) separated by a separation layer or tunneling layer (in this example, magnesium oxide (MgO) 805), and then a top electrode 811 separated from the free layer 807 by a spacer 809. The state of the memory cell is based on the relative orientation of the magnetization of the reference layer 803 and the free layer 807: if the two layers are magnetized in the same direction, the memory cell will be in a parallel (P) low resistance state (LRS); and if they have opposite orientations, the memory cell will be in an antiparallel (AP) high resistance state (HRS). MLC implementations will include additional intermediate states. The orientation of the reference layer 803 is fixed, and Figure 15 The reference layer 803 is also referred to as a fixed layer or a pinned layer.

[0093] Data is written to the MRAM memory cell by programming the free layer 807 to have the same orientation or the opposite orientation. The reference layer 803 is formed so that it will maintain its orientation when programming the free layer 807. The reference layer 803 can have a more complex design including a synthetic antiferromagnetic layer and additional reference layers. For simplicity, the figures and discussion omit these additional layers and focus only on the fixed magnetic layer, which is primarily responsible for the tunneling magnetoresistance in the cell.

[0094] exist Figure 8B In an embodiment of the present invention, a forced current method is used to access the MRAM cell. The forced current method can be used to read or write the MRAM cell. In the forced current method, the current source 823 drives the access current (e.g., I 读取 I 写入 ) through the bottom electrode 801. The current source 823 is part of the drive circuit for the bottom electrode 801. A voltage (e.g., V 选 ). In this document, the terms "read current" (Iread) and "write current" (Iwrite) will be used in conjunction with the access current driven through the MRAM cell. The write current is the current driven through the first conductive line (e.g., word line) that, combined with the voltage applied to the second conductive line (e.g., bit line), will change the state of the MRAM cell. A write current flowing through the MRAM cell in one direction will cause the AP state MRAM cell to change from the AP state to the P state. A write current flowing through the MRAM cell in the other direction will cause the P state MRAM cell to change from the P state to the AP state. Generally speaking, if applied for a limited time, such as less than 30ns, the read current will not change the state of the MRAM cell from the P state to the AP state or vice versa.

[0095] As defined herein, an access current can have a positive or negative magnitude. A positive access current driven through a first conductive line (e.g., a word line) at a given point will flow in a direction opposite to a negative access current driven through the first conductive line at the given point. Thus, depending on whether the access current is defined as having a positive or negative magnitude, the access current can flow through the MRAM cell in either direction. In one embodiment, the MRAM cell is read by applying, for example, 0V to the top electrode 811 while driving, for example, a 15 microampere (μA) current through the bottom electrode 801. This read current will flow from the bottom electrode 801 to the top electrode 811. In one embodiment, the MRAM cell is written from the AP state to the P state by applying, for example, 3V to the top electrode 811 while driving, for example, a -30 μA write current through the bottom electrode 801. This write current will flow from the top electrode 811 to the bottom electrode 801. In one embodiment, the MRAM cell is written from the P state to the AP state by applying, for example, 0V to the top electrode 811 while driving, for example, a 30 μA current through the bottom electrode 801. The write current will flow from the bottom electrode 801 to the top electrode 811 .

[0096] Figure 9 One embodiment of an MRAM memory cell design to be implemented in a cross point array is shown in more detail. When placed in a cross point array, the top and bottom electrodes of the MRAM memory cell will be two layers of adjacent conductive layers of the array, such as the top and bottom conductive layers of a two-level array or a dual layer array. In the embodiment shown here, the bottom electrode is the word line (WL) 901 of the memory cell and the top electrode is the bit line (BL) 911 of the memory cell, but in some embodiments these can be reversed by reversing the orientation of the memory element. Between the word line 901 and the bit line 911 are a reference layer 903 and a free layer 907, which are also separated by a MgO barrier 905. In Figure 9 In the embodiment shown, an MgO capping layer 908 is also formed on top of the free layer 907, and a conductive spacer 909 is formed between the bit line 911 and the MgO capping layer 908. The reference layer 903 is separated from the word line 901 by another conductive spacer 902. On either side of the memory cell structure are liners 921 and 923, where these liners can be part of the same structure, but in a Figure 9 A portion of filler material 925, 927 is shown on either side of the liners 921, 923 to fill the otherwise empty areas of the cross-point structure.

[0097] Regarding the free layer design 907, embodiments include a CoFe or CoFeB alloy with a thickness of approximately 1 nm to 2 nm, wherein an Ir layer may be interspersed in the free layer near the MgO barrier 905, and the free layer 907 may be doped with Ta, W, or Mo. Embodiments of the reference layer 903 may include a bilayer of CoFeB and CoPt multilayers coupled to an Ir or Ru spacer 902. The MgO capping layer 908 is optional but may be used to increase the anisotropy of the free layer 907. The conductive spacer may be a conductive metal such as Ta, W, Ru, CN, TiN, and TaN, among others.

[0098] To sense the data state stored in an MRAM, a voltage V is applied across the memory cell. 施加 To read an MRAM memory cell, the voltage difference V 施加 can be applied in either direction; however, MRAM memory cells have directionality, so in some cases, reading in one direction is preferred over reading in the other direction. For example, the optimal current amplitude to write a bit to AP (high resistance state, HRS) can be about 20% higher than the optimal current amplitude to write to P (low resistance state), so if AP (2AP) is read, the bit error rate (read disturb) is less likely. Some of these cases and the resulting directionality of the read are discussed below. The directionality of the bias specifically enters some embodiments of MRAM memory cell programming, such as with respect to Figure 10A and Figure 10B Further discussion.

[0099] The following discussion will focus on the vertical spin-transfer torque MRAM memory cell, where Figure 8A and Figure 9 The free layer 807 / 907 includes a switchable magnetization direction perpendicular to the plane of the free layer. Spin transfer torque ("STT") is an effect that can modify the orientation of the magnetic layers in a magnetic tunnel junction using a spin-polarized current. Charge carriers (such as electrons) have a property called spin, which is a small amount of angular momentum inherent to the carrier. Electric current is generally unpolarized (for example, consisting of 50% spin-up and 50% spin-down electrons). A spin-polarized current is a current in which electrons of either spin are more numerous (for example, a majority of spin-up electrons or a majority of spin-down electrons). A spin-polarized current can be generated by passing an electric current through a thick magnetic layer (a reference layer). If this spin-polarized current is directed into a second magnetic layer (the free layer), the angular momentum can be transferred to the second magnetic layer, thereby changing the magnetization direction of the second magnetic layer. This is called spin transfer torque. Figure 10A and Figure 10BThe use of spin transfer torque to program or write to MRAM memory is demonstrated. The advantages of spin transfer torque magnetic random access memory (STT MRAM) are lower power consumption and better scalability compared to other MRAM variants. Compared to other MRAM implementations, STT switching technology requires relatively low power, which virtually eliminates the problem of adjacent bit interference and has more favorable scaling for higher memory cell densities (MRAM cell size reduction). The latter problem also benefits STT MRAM, where the free layer magnetization and the reference layer magnetization are oriented perpendicular to the film plane, rather than oriented in the plane.

[0100] Since the STT phenomenon is easier to describe based on the behavior of electrons, Figure 10A and Figure 10B and its discussion is given in terms of electron current, where the direction of the written current is defined as the direction of electron flow. Figure 10A and Figure 10B The term "write current" refers to electron current. When electrons are negatively charged, the electron current will be in the opposite direction of the conventionally defined current, so that the electron current will flow from a lower voltage level to a higher voltage level, rather than the conventional current flow from a higher voltage level to a lower voltage level.

[0101] Figure 10A and Figure 10B Writing to an MRAM memory cell using the STT mechanism is illustrated, depicting a simplified schematic representation of an example of an STT-switched MRAM memory cell 1000, in which the reference layer magnetization and the free layer magnetization are both in perpendicular directions. Memory cell 1000 includes a magnetic tunnel junction (MTJ) 1002, which includes an upper ferromagnetic layer 1010, a lower ferromagnetic layer 1012, and a tunnel barrier (TB) 1014, which acts as an insulating layer between the two ferromagnetic layers. In this example, upper ferromagnetic layer 1010 is the free layer FL, and its magnetization direction can be switched. Lower ferromagnetic layer 1012 is the reference (or fixed) layer RL, and its magnetization direction cannot be switched. When the magnetization in free layer 1010 is parallel to the magnetization in reference layer RL 1012, the resistance across memory cell 1000 is relatively low. When the magnetization in the free layer FL 1010 is antiparallel to the magnetization in the reference layer RL 1012, the resistance across the memory cell 1000 is relatively high. The data ("0" or "1") in the memory cell 1000 is read by measuring the resistance of the memory cell 1000. In this regard, the electrical conductors 1006 / 1008 attached to the memory cell 1000 are used to read the MRAM data. Through process and circuit design, both the parallel and antiparallel configurations remain stable in the quiescent state and / or during a read operation (at sufficiently low read currents).

[0102] For both the reference layer RL 1012 and the free layer FL 1010, the magnetization directions are in perpendicular directions (ie, perpendicular to the plane defined by the free layer and perpendicular to the plane defined by the reference layer). Figure 10A and Figure 10B As shown, the magnetization direction of the reference layer RL 1012 is up, and the magnetization direction of the free layer FL 1010 is switchable between up and down, which is also perpendicular to the plane.

[0103] In one embodiment, tunnel barrier 1014 is made of magnesium oxide (MgO); however, other materials may also be used. Free layer 1010 is a ferromagnetic metal that has the ability to change / switch its magnetization direction. Multilayers based on transition metals such as Co, Fe, and their alloys can be used to form free layer 1010. In one embodiment, free layer 1010 comprises an alloy of cobalt, iron, and boron. Reference layer 1012 can be made of many different types of materials, including (but not limited to) multilayers of cobalt and platinum and / or cobalt and iron alloys.

[0104] To "set" the MRAM memory cell bit value (ie, select the direction of the free layer magnetization), an electron write current 1050 is applied from conductor 1008 to conductor 1006, as shown in FIG. Figure 10A To generate electron write current 1050, top conductor 1006 is placed at a higher voltage level than bottom conductor 1008 due to the negative charge of electrons. The electrons in electron write current 1050 become spin-polarized as they pass through reference layer 1012, which is a ferromagnetic metal. As the spin-polarized electrons tunnel through tunnel barrier 1014, conservation of angular momentum can result in a spin transfer torque being exerted on both free layer 1010 and reference layer 1012, but this transfer torque is not sufficient (by design) to affect the magnetization orientation of reference layer 1012. Conversely, if the initial magnetization orientation of free layer 1010 is antiparallel (AP) to that of reference layer 1012, the spin transfer torque is sufficient (by design) to switch the magnetization orientation of free layer 1010 to parallel (P) with that of reference layer 1012, a process known as antiparallel-to-parallel (AP2P) writing. The parallel magnetization then remains stable before and after the electron write current is turned off.

[0105] In contrast, if the magnetization of the free layer 1010 and the magnetization of the reference layer 1012 are initially parallel, the magnetization direction of the free layer 1010 can be switched to be antiparallel to the reference layer 1012 by applying an electron write current in the opposite direction to that in the previous case. Figure 10BAs depicted, an electron write current 1052 is applied from conductor 1006 to conductor 1008 by applying a higher voltage level on the lower conductor 1008. This writes the free layer 1010, which is in the P state, to the AP state, known as parallel to antiparallel (P2AP) writing. Thus, via the same STT physics, the magnetization direction of the free layer 1010 can be deterministically set to either of two stable orientations by judiciously choosing the direction (polarity) of the electron write current.

[0106] The data ("0" or "1") in memory cell 1000 can be read by measuring the resistance of memory cell 1000. Low resistance typically represents a "0" bit, and high resistance typically represents a "1" bit, although alternative conventions sometimes occur. The data is read by applying an electron read current (e.g., from conductor 1008 to conductor 1006) Figure 10A For the flow shown in 1050 ("AP2P direction"), a read current can be applied across the memory cell (e.g., across the magnetic tunnel junction 1002); alternatively, an electron read current can be applied from conductor 1006 to conductor 1008, as shown in FIG. Figure 10B In a read operation, if the electron write current is too high, this may disturb the data stored in the memory cell and change its state. For example, if the electron read current is too high, the data may be disturbed. Figure 10B If the P2AP direction is selected, then excessively high current levels or voltage levels can switch any memory cell in the low resistance P state to the high resistance AP state. Thus, while the MRAM memory cells can be read in either direction, in various embodiments, the directional nature of the write operation can prioritize one read direction over another, such as when the required write current is higher; for example, P2AP, so reading in that direction can result in reduced BER (read disturb).

[0107] although Figure 10A and Figure 10B The discussion is made in the context of electron currents for read current and write current, but unless otherwise indicated, subsequent discussion will be in the context of conventional currents.

[0108] Whether reading or writing 7A to 7D A selected memory cell in an array structure of FIG, a bit line and a word line corresponding to the selected memory cell (bit) are biased to apply a voltage across the selected memory cell and induce electron flow, as described with respect to FIG. Figure 10A or Figure 10BThis will also apply a voltage across the unselected memory cells of the array, which can induce current in the unselected memory cells. Although this wasteful power consumption can be mitigated to some extent by designing the memory cells to have relatively high resistance levels for both the high and low resistance states, this will still result in increased current and power consumption and impose additional design constraints on the design of the memory cells and array.

[0109] One approach to addressing this undesirable current leakage is to place a selector element in series with each MRAM or other resistive (e.g., ReRAM, PCM) memory cell. 7A to 7D In

[15] , a select transistor can be placed in series with each resistive memory cell element, so that element 701 is now a combination of a selector and a programmable resistor. However, the use of transistors requires the introduction of additional control lines to enable the corresponding transistor of the selected memory cell to be turned on. Additionally, transistors generally do not scale in the same way as resistive memory elements, making the use of transistor-based selectors potentially a limiting factor as memory arrays move to smaller sizes.

[0110] An alternative approach to selector elements is to use a threshold switch selector element in series with a programmable resistive element to comprise individual memory cells or bits. The threshold switch selector is biased below its threshold voltage (V 阈值 ) voltage and current below its threshold (I 阈值 ) has a high resistance (in the off or non-conducting state) when a current is applied to it, and has a low resistance (in the on or conducting state) when it is biased to a current above its threshold current and holds the current. The threshold switch selector remains on until its current drops below the holding current, or the voltage drops below the holding voltage. When this happens, the threshold switch selector returns to the off state. Therefore, to program the memory cell at the intersection, a voltage or current sufficient to turn on the associated threshold switch selector is applied, and if the magnitude is sufficient to write, for example, if the resistance-area product (RA) is 10Ω-μm 2 For a 20nm critical dimension (CD) MRAM with a current greater than 35μA, the resulting state determined by the current direction is used to set or reset the memory cell; and in order to read the memory cell, similarly, the threshold switch selector must be activated by turning on before the resistance state of the memory cell can be determined. One example of a threshold switch selector is the bidirectional threshold switch material of a bidirectional threshold switch (OTS). As shown below Figure 14Examples shown include Ge-Se, Ge-Se-N, Ge-Se-As, Ge-Se-Sb-N, Ge58Se42, GeTe6, Si-Te, Zn-Te, C-Te, B-Te, Ge-As-Te-Si-N, Ge-As-Se-Te-Si, and Ge-Se-As-Te.

[0111] Figure 11A and Figure 11B An embodiment for incorporating a threshold switch selector into an MRAM memory array having a cross-point architecture is presented. Figure 11A and Figure 11B The example shows two MRAM cells in a two-layer cross-point array, such as Figure 7D shown, however, in a side view. Figure 11A and Figure 11B The bottom first conductive line, word line 1 1100, the top first conductive line, word line 2 1120, and the middle second conductive line, bit line 1110 are shown. In these figures, for ease of presentation, all of these lines are shown extending from left to right across the page, through the cross-point array, which would be more accurately represented as Figure 7D , wherein the word line or first conductive line or wire extends in one direction parallel to the surface of the underlying substrate, and the bit line or second conductive line or wire extends in a second direction parallel to the surface of the substrate, the second direction being substantially orthogonal to the first direction. The MRAM memory cell is also shown in simplified form, showing only the reference layer, free layer and the intermediate tunnel barrier, but in actual implementation, it will generally include the above-mentioned Figure 9 The additional structure.

[0112] An MRAM cell 1102 including a free layer 1101, a tunnel barrier 1103, and a reference layer 1105 is formed above a threshold switch selector 1109, wherein this series combination of the MRAM device 1102 and the threshold switch selector 1109 together forms a layer 1 cell between a bit line 1110 and a word line 1 1100. Aside from some voltage drop across the threshold switch selector 1109, the series combination of the MRAM device 1102 and the threshold switch selector 1109 operates largely as described above with respect to the embodiment of the present invention when the threshold switch selector 1109 is turned on. Figure 10A and Figure 10B However, the threshold switch selector 1109 initially needs to be turned on by applying a voltage or current above the threshold of the threshold switch selector 1109, and then the bias current or voltage needs to be maintained high enough to be above the holding current or holding voltage of the threshold switch selector 1109 so that it remains turned on during subsequent read or write operations.

[0113] On the second tier, an MRAM cell 1112 including a free layer 1111, a tunnel barrier 1113, and a reference layer 1115 is formed above a threshold switch selector 1119, wherein the series combination of the MRAM device 1112 and the threshold switch selector 1119 together form a tier 2 cell between the bit line 1110 and the word line 2 1120. The tier 2 cell will operate like the tier 1 cell, but the lower conductor now corresponds to the bit line 1110, and the upper conductor is now the word line, i.e., word line 2 1120.

[0114] exist Figure 11A In the embodiment of the present invention, the threshold switch selector 1109 / 1119 is formed below the MRAM device 1102 / 1112, but in alternative embodiments, the threshold switch selector can be formed above the MRAM device for one or both layers. Figure 10A and Figure 10B As discussed, MRAM memory cells have directionality. Figure 11A In FIG, MRAM devices 1102 and 1112 have the same orientation, with free layers 1101 / 1111 above reference layers 1105 / 1115 (relative to a substrate not shown). Forming these layers between conductive lines having the same structure can have many advantages, particularly with respect to processing, because each of the two layers, and subsequent layers in embodiments having more layers, can be formed according to the same processing sequence.

[0115] Figure 11B Shown with Figure 11A An alternative embodiment is similarly arranged, except that in the layer 2 unit, the positions of the reference layer and the free layer are reversed. More specifically, as Figure 11A As shown, between word line 1 1150 and bit line 1160, layer unit 1 includes an MRAM structure 1152 having a free layer 1151 formed over a tunnel barrier 1153, which in turn is formed over a reference layer 1155, wherein the MRAM structure 1152 is formed over a threshold switch selector 1159. Figure 11B The second layer of the embodiment also has an MRAM device 1162 formed above the threshold switch selector 1169 between the bit line 1160 and the word line 2 1170, but with respect to Figure 11A , the MRAM device 1162 is inverted such that the reference layer 1161 is now formed above the tunnel barrier 1163 and the free layer 1165 is now formed below the tunnel barrier 1163 .

[0116] Although Figure 11B The embodiment of the invention requires a different processing sequence for forming these layers, but in some embodiments, it can have advantages. In particular, the directionality of the MRAM structure can make Figure 11B The embodiment is attractive because when writing or reading in the same direction (relative to the reference and free layers), the bit line will be biased the same amount for both the lower and upper layers, and both word lines will also be biased the same amount. For example, if both a layer 1 memory cell and a layer 2 memory cell are sensed in the P2AP direction (relative to the reference and free layers), the bit line layer 1160 will be biased, such as in the P2AP direction, with the bit line 1160 biased low (e.g., 0V) for both the upper and lower cells, and both word line 1 1150 and word line 2 1170 biased to a higher voltage level. Similarly, with respect to writing, to write the high resistance AP state, bit line 1160 is biased low (e.g., 0V) for both the upper and lower cells, and word line 1 1150 and word line 2 1170 are both biased to a higher voltage level; and to write the low resistance P state, bit line 1160 is biased to a high voltage level, and word line 1 1150 and word line 2 1170 are both biased to a low voltage level. In contrast, for Figure 11A In an embodiment of the present invention, the bit lines and word lines will need to have their bias levels reversed in order to perform any of these operations on a higher level relative to a lower level.

[0117] Reading data from or writing data to an MRAM memory cell involves passing current through the memory cell. In embodiments where a threshold switch selector is placed in series with the MRAM element, the threshold switch selector needs to be turned on by applying a sufficient voltage across the series combination of the threshold switch selector and the MRAM element before current can pass through the MRAM element.

[0118] Accessing more than one bit in a cross-point memory array simultaneously can be quite difficult. This article discloses a technique for simultaneously accessing multiple memory cells in a cross-point array. In one embodiment, multiple memory cells in a cross-point array are read simultaneously. In another embodiment, multiple memory cells in a cross-point array are written simultaneously.

[0119] Figure 12An embodiment of a memory array 1202 having a cross-point architecture is depicted, in which multiple memory cells are accessed simultaneously. Array 1202 has a set of first conductive lines 1206a-1206h and a set of second conductive lines 1208a-1208d. In one embodiment, the set of first conductive lines 1206a-1206h are word lines, and the set of second conductive lines 1208a-1208b are bit lines. For ease of discussion, the set of first conductive lines 1206a-1206h may be referred to as word lines, and the set of second conductive lines 1208a-1208b may be referred to as bit lines. However, the set of first conductive lines 1206a-1206h may be bit lines, and the set of second conductive lines 1208a-1208b may be word lines.

[0120] Array 1202 includes a plurality of memory cells 701. Each memory cell 701 is connected between one of first conductive lines 1206 and a corresponding one of second conductive lines 1208. Each memory cell 701 includes a magnetoresistive random access memory (MRAM) element 1202 connected in series with a threshold switch selector 1204. Therefore, each memory cell 701 can be referred to as an MRAM cell. The threshold switch selector 1204 is configured to become conductive in response to application of a voltage or current level exceeding a threshold of the threshold switch selector 1204.

[0121] Each first conductive line 1206 is driven by one of the current drivers 1210a to 1210h. For example, the first conductive line 1206a is driven by the current driver 1210a, the first conductive line 1206b is driven by the current driver 1210b, and so on. Each second conductive line 1208 is driven by one of the voltage drivers 1212a to 1212d. For example, the second conductive line 1208a is driven by the voltage driver 1212a, the second conductive line 1208b is driven by the voltage driver 1212b, and so on. The current driver 1210b drives the access current (I 访问 ) through the selected word line 1206b. Similarly, the current driver 1210g drives I 访问 The current driver 1210 is configured to source current or sink current through the selected word line 1206b. 访问Current can flow through the selected word line in either direction. Regardless of whether the current driver 1210 sources or sinks current, this will be referred to herein as driving current through the word line. In one embodiment, a relatively low current is driven through the unselected word lines (e.g., 1206a, 1206c, 1206d, 1206e, 1206f, and 1206h). Note that, as used herein, "selected word line" means a word line connected to a selected memory cell. "Unselected word line" means a word line not connected to any selected memory cell. In other words, all memory cells connected to an unselected word line are unselected memory cells. Note that, as used herein, "selected bit line" means a bit line connected to at least one selected memory cell. "Unselected bit line" means a bit line not connected to any selected memory cell. In other words, all memory cells connected to an unselected bit line or unselected word line are unselected memory cells.

[0122] Two memory cells 701b, 701e are selected for simultaneous access. The selected memory cell 701b is located at the intersection of the selected word line 1206b and the selected bit line 1208b. The other memory cells are not selected for access (i.e., unselected memory cells). For example, memory cells 701a, 701c, 701d, and memory cells not specifically labeled with reference numbers are not selected for access. The selected memory cell 701e is located at the intersection of the selected word line 1206g and the selected bit line 1208. All other word lines and all other bit lines are unselected. To select memory cell 701, a select voltage (V 选择 ) and drives the access current through the selected word line (e.g., word lines 1206b, 1206g). The unselected voltage (V 未选择 ) is provided to unselected bit lines (e.g., bit lines 1208a, 1208c, 1208d). In one embodiment, V 选择 has a magnitude such that the threshold switch selector 1204 in the selected memory cell will turn on. On the other hand, V 未选择 The magnitude of is such that the threshold switch selectors 1204 in the unselected memory cells will not turn on.

[0123] One of sense amplifiers (SA) 1228a to 1228h is connected to each word line. For example, SA 1228a is connected to word line 1206a, SA 1228b is connected to word line 1206b, and so on. Each sense amplifier is configured to sense the voltage on the word line 1206 to which the SA is connected.

[0124] exist Figure 12In one embodiment, there are more word lines than bit lines in the cross-point array. In one embodiment, there are more bit lines than word lines in the cross-point array. In one embodiment, the number of bit lines in the cross-point array is equal to the number of word lines. Figure 12 In the example shown, there are twice as many word lines as bit lines in the cross-point array; however, different ratios can be used.

[0125] In some implementations, voltage drivers 1212 are connected to corresponding bit lines 1208 at strategic locations. In some implementations, current drivers 1210 are connected to corresponding word lines 1206 at strategic locations. Figure 13 An embodiment of a memory array 1202 having a cross-point architecture is depicted, showing the locations of contacts from the drivers to the bit lines and word lines. Figure 13 The corresponding Figure 5 or Figure 6A The memory array 1202 of the array 502 / 602 depicts the Figure 12 The same word lines 1206a to 1206h and bit lines 1208a to 1208d are used in the array. Figure 13 The memory unit 701 is not shown.

[0126] Each current driver 1210a through 1210h is connected to one of word lines 1206 via a corresponding one of word line contacts 1302a through 1302h. In one embodiment, the current drivers are connected to their corresponding word lines through vias. Thus, the current drivers can reside at a different level of the cross point array than the word lines they drive. Current drivers 1210 can be located outside the cross point array, such as on control die 611. Each word line contact 1302 is connected to word line 1206 at a location that divides the corresponding word line 1206 into a first portion and a second portion. For example, word line contact 1302c is connected to word line 1206c at a location that divides word line 1206c into a first portion 1312a and a second portion 1312b. In some embodiments, half of a bit line 1208 is positioned so that it intersects word line 1206 somewhere in the corresponding first portion, and the other half of the bit line is positioned so that it intersects word line 1206 somewhere in the corresponding second portion. For example, bit lines 1208a and 1208b intersect first portion 1312a of word line 1206c, while bit lines 1208c and 1208d intersect second portion 1312b of word line 1206c. In some embodiments, word line contacts 1302 are located at the midpoint of the respective word lines 1206. Thus, in some embodiments, the first and second portions of the respective word lines have approximately the same length.

[0127] Each voltage driver 1212a through 1212d is connected to one of the bit lines 1208 via a corresponding one of the bit line contacts 1304a through 1304d. In one embodiment, the voltage drivers are connected to their corresponding bit lines through vias. Thus, the voltage drivers can reside at a different level in the cross point array than the bit lines they drive. Voltage drivers 1212 can be located outside the cross point array, such as on the control die 611. Each bit line contact 1304 is connected to bit line 1208 at a location that divides the corresponding bit line 1208 into a first portion and a second portion. For example, bit line contact 1304a is connected to bit line 1208a at a location that divides bit line 1208a into a first portion 1314a and a second portion 1314b. In some embodiments, half of word line 1206 is positioned so that it intersects a bit line somewhere in the corresponding first portion, and the other half of word line 1206 is positioned so that it intersects a bit line somewhere in the corresponding second portion. For example, word lines 1206a-1206d intersect a first portion 1314a of bit line 1208a, while word lines 1206e-1206h intersect a second portion 1314b of bit line 1208a. In some embodiments, bit line contact 1304 is located at the midpoint of the corresponding bit line 1208. Thus, in some embodiments, the first and second portions of the corresponding bit line 1208 have approximately the same length.

[0128] Figure 14 is a flow chart of one embodiment of a process 1400 for simultaneously accessing multiple memory cells in a cross-point array. In one embodiment, the memory cells are MRAM cells. In one embodiment, process 1400 is performed to simultaneously read one or more memory cells in a cross-point array. In one embodiment, process 1400 is performed to simultaneously write to multiple memory cells in a cross-point array. In one embodiment, process 1400 is performed by control circuitry in memory die 500. In one embodiment, process 1400 is performed by control circuitry in control die 611. Figure 13 The process 1400 is discussed with reference to the cross-point array depicted in FIG; however, the process 1400 is not limited to Figure 13 The array depicted in .

[0129] Step 1402 includes applying a select voltage to the selected second conductive line 1208. Figure 13 , the voltage driver 1212b converts V 选择 is applied to the second conductive line 1208b. Step 1402 may also include applying an unselected voltage to the unselected second conductive line 1208. Figure 13 , V 未选择A voltage is applied to second conductive line 1208a by voltage driver 1212a, to second conductive line 1208c by voltage driver 1212c, and to second conductive line 1208d by voltage driver 1212d. In some implementations, the second conductive line is a bit line.

[0130] Step 1404 includes driving an access current individually through each selected first conductive line 1206 to simultaneously drive an access current individually through each selected memory cell. Note that the access current can flow through the first conductive line 1206 in either direction, depending on whether the access current is defined as having a positive or negative magnitude. When a select voltage is applied to the selected second conductive line, the access current is driven through the memory cell. Figure 13 , current driver 1210b drives I 访问 Through the selected first conductive line 1206b, I 访问 At approximately the same time, current driver 1210g drives I 访问 By selecting the first conductive line 1206g, I 访问 Therefore, the current I 访问 A plurality of selected memory cells in the cross-point array are driven individually.

[0131] In one embodiment, the access current in step 1404 is sufficient to exceed I 保持 For example, if the MRAM has a 20nm CD and a RA of 10Ω-μm 2 , then it is 15 μA. Therefore, the access current can be referred to as the read current. In this case, process 1500 can also include sensing the voltage on each corresponding selected first conductive line 1206 to read each memory cell simultaneously.

[0132] In one embodiment, the access current in step 1404 is used to write to the memory cells simultaneously. Therefore, the access current may be referred to as a write current. In one embodiment, the access current changes the MRAM cell from the P state to the AP state. Therefore, multiple MRAM cells in the cross-point array can be programmed from the P state to the AP state at the same time. In one embodiment, the access current changes the MRAM cell from the AP state to the P state. Therefore, multiple MRAM cells in the cross-point array can be programmed from the AP state to the P state at the same time. In some embodiments, the write operation is a two-phase operation. In one embodiment of the MRAM two-phase write operation, the first phase places all selected memory cells in the AP state. The second phase writes the appropriate or selected MRAM cells from the AP state to the P state. Alternatively, the first phase can be programmed to the P state and the second phase can be programmed to the AP state. In another embodiment, the cell is first read in the P2AP direction with a read current, such as 15 μA, and a resulting voltage is generated on the global decode node that enters the sense amplifier, bit line decoder, bit line, memory cell, word line, word line decoder (above the bit line is driven to approximately 0V), where the global node is driven by a read current sufficient to turn on and keep the bit selector in the on state. The resulting voltage can be temporarily stored on a capacitor and adjusted by coupling charge from another capacitor into the storage capacitor, the other terminal of which is switched from a low voltage to a high voltage, for example, moving the stored voltage by 150 mV. Next, the current P2AP is increased to a write current, such as 35 μA, for about 50 ns. Next, a read is performed again, but the resulting voltage is compared to the earlier stored and adjusted voltage by a comparator. If the voltage change is sufficient (e.g., greater than 150 mV), the bit is in the LRS state. If the change is less than 150 mV, the bit is in the HRS state. Next, the bit can be written back to the LRS state by reversing the direction of the write current, or it can be left in the HRS state.

[0133] A variety of different strategies can be used to select which memory cells in a cross-point array are accessed simultaneously. Figure 13, in some embodiments, the selected memory cell is selected relative to its position relative to the bit line contact 1304. In one embodiment of simultaneous access, there is one selected bit line and one or more pairs of selected word lines. For purposes of illustration, some examples will be discussed in which there is one selected bit line and one pair of selected word lines. In one embodiment, the selected word line pair is selected based on the distance from the bit line contact 1304 of the selected bit line to the point where the selected word line intersects the selected bit line. In one embodiment, the distance from the bit line contact 1304 of the selected bit line to the aforementioned intersection point is approximately the same for both components of a pair of selected word lines. In other words, the two components of the pair of selected word lines are equidistant from the connection point of the bit line contact to the corresponding point where each component intersects the selected bit line. As used herein, "equidistant" means "approximately the same distance." In one embodiment, the difference in distance is less than five percent. For example, with reference to Figure 14 , the pair may include word line 1206b and word line 1206g. Alternatively, the pair may include word line 1206d and word line 1206e. This strategy results in approximately the same IR drop between the location where the bit line contact 1304 is connected to the selected bit line and the location where the selected bit line will be connected to each corresponding selected memory cell. This strategy helps improve read margin, thereby providing accurate sensing of each selected memory cell.

[0134] A strategy similar to the distance-based example described above is based on the number of word lines between the selected word line and the location where the bit line contact 1304 connects to the selected bit line. In one embodiment, each component of the pair of word lines is "n" word lines away from the connection point where the bit line contact 1304 connects to the selected bit line. For example, word line 1206b and word line 1206g are each three word lines away from the location where the bit line contact 1304 connects to the bit line 1208 (this example counts word line 1206b and word line 1206g as one word line out of three). Note that in some embodiments, the word lines can be symmetrically spaced relative to the location of the bit line contacts, so that this strategy also results in approximately the same IR drop between the location where the bit line contact 1304 connects to the selected bit line and the location where the selected bit line will connect to each corresponding selected memory cell. Thus, this strategy helps improve read margins, thereby providing accurate sensing of each selected memory cell.

[0135] In another distance-based embodiment, the location of the selected word line is selected so as to maintain approximately the same total distance between the location where the bit line contact 1304 connects to the selected bit line and the location where the corresponding selected word line crosses the selected bit line. This will be explained by way of example. Figure 13, the word line pairs may be: word line 1206a and word line 1206e; word line 1206b and word line 1206f; word line 1206c and word line 1206f; and word line 1206d and word line 1206h. This strategy may facilitate error correction. In some cases, the location of the selected memory cell (and therefore the location of the selected word line) affects the reliability of the data stored in the memory cell. As an example, data stored in a memory cell along word line 1206a may not be as reliable as data stored in a memory cell along word line 1206d. Similarly, data stored in a memory cell along word line 1206h may not be as reliable as data stored in a memory cell along word line 1206e. Therefore, this strategy reads lower reliability data while reading higher reliability data. In some embodiments, both data bits are part of the same ECC code word. In contrast, if the memory cells along word line 1206a and the memory cells along word line 1206b are read simultaneously, two lower reliability bits will be read together, increasing the likelihood of codeword decoding failure. However, by mixing lower reliability bits with higher reliability bits, codeword decoding is less likely to fail. Therefore, this strategy improves the decoding of codewords stored in memory cells.

[0136] A strategy similar to the previous example based on total distance is based on the total number of word lines between the corresponding components of a pair of selected word lines and the location where the bit line contact 1304 is connected to the selected bit line. In one embodiment, the total number of word lines is the same for each pair of selected word lines. Figure 13 , if the word line pairs are word line 1206a and word line 1206e, word line 1206b and word line 1206f, word line 1206c and word line 1206f, and word line 1206d and word line 1206h, then, in each case, there are a total of three word lines between the respective components of the pair of selected word lines and the location where the bit line contact 1304 is connected to the selected bit line (this example does not count the selected word line as one of the word lines "between" the respective components of the pair of selected word lines and the location where the bit line contact 1304 is connected to the selected bit line).

[0137] In some embodiments, simultaneous access of multiple memory cells in a cross-point array includes performing a self-referencing read (SRR). In one embodiment, an SRR read is used during a simultaneous read of multiple memory cells in a cross-point array. In one embodiment, an SRR read is used during a simultaneous write of multiple memory cells in a cross-point array. In one embodiment, an SRR read is used to simultaneously place multiple MRAM cells into an AP state.

[0138] Figure 151 is a flow chart depicting one embodiment of a process 1500 for simultaneously accessing multiple memory cells in a cross-point array including performing an SRR. The SRR may be referred to as a destructive SRR, meaning that the initial state of the memory cells may be changed during the SRR. In one embodiment, process 1500 is performed to simultaneously read multiple memory cells in a cross-point array. In one embodiment, process 1500 is performed during a simultaneous write to multiple memory cells in a cross-point array. In one embodiment, process 1500 is performed by control circuitry in memory die 500. In one embodiment, process 1500 is performed by control circuitry in control die 611.

[0139] Will refer to Figure 13 Process 1500 is discussed with reference to the crosspoint array depicted in FIG; however, process 1500 is not limited to Figure 13 In the process 1500, the memory cells are described as MRAM cells. However, the process 1500 can be used with other types of memory cells in a cross-point array. Figure 16A and Figure 16B Discussion process 1500. Figure 16A The access current driven through the selected word line is plotted versus time. Figure 16B The voltage across a selected MRAM cell is depicted versus time.

[0140] Step 1502 includes driving a first read current through each selected word line while applying a select voltage to the selected bit line to drive a first access current through each selected MRAM cell. Figure 13 , current driver 1210b drives I 访问 Through the selected first conductive line 1206b, I 访问 At approximately the same time, current driver 1210g drives I 访问 By selecting the first conductive line 1206g, I 访问 By memory unit 701e. Figure 13 , the voltage driver 1212b converts V 选择 Applied to the second conductive line 1208b. In one embodiment, I 访问 is 15μA, and V 选择 is 0V.

[0141] Now we will discuss an MRAM cell 701. Figure 16A and Figure 16B , for further details on step 1502. Figure 16A , the access current increases to I at time t1 读取, and keep it at I 读取 Until t3. Figure 16B , the voltage across the memory cell 701 increases from t1 to t2. The threshold switch selector 1204 is disconnected between t1 and t2. Between t1 and t2, the access current causes the word line voltage to increase. The access current also supports any leakage in the path. Once the voltage across the threshold switch selector 1204 reaches the threshold voltage V of the threshold switch selector 1204, the word line voltage increases. 阈值 , the threshold switch selector will turn on and switch to the low resistance state (at t2). Therefore, when the threshold switch selector 1204 is in the off state, the voltage across the series combination of the threshold switch selector and the resistive MRAM element 1202 ramps up.

[0142] Once the threshold switch selector 1204 is in the on state (at t2), I 读取 Current will flow through the selected memory cell 701. When the access current is kept fixed at I 读取 When I is on, the voltage across the memory cell will drop to a level that depends on the series resistance of the MRAM element 1202 and the on-state resistance of the threshold switch selector 1204. For a binary implementation, the memory cell will have a high resistance AP state and a low resistance P state. 读取 The resulting voltage across the series-connected MRAM element 1202 and threshold switch selector 1204 is shown as lines 1610 and 1612, respectively. While the discussion here is in the context of an MRAM-based memory cell placed in series with a threshold switch selector, the reading technique can be similarly applied to other programmable resistive memory cells, such as PCM or ReRAM devices.

[0143] Return again Figure 15 , step 1504 includes driving a write current through each selected word line while applying a select voltage to the selected bit line to simultaneously drive a write current through each selected MRAM cell. Figure 13 , current driver 1210b drives I 访问 Through the selected first conductive line 1206b, I 访问 At approximately the same time, current driver 1210g drives I 访问 By selecting the first conductive line 1206g to drive I 访问 By memory unit 701e. Figure 13 , the voltage driver 1212b converts V 选择 Applied to the second conductive line 1208b. In one embodiment, I 访问 is 30μA, and V选择 is 0V.

[0144] Now we will discuss an MRAM cell 701. Figure 16A and Figure 16B , for further details on step 1504. Figure 16A , the access current increases to I at time t3 写入 , and keep it at I 写入 Until t5. Figure 16B At t3, the voltage across the MRAM cell 701 increases at t3. If the MRAM cell 701 is in HRS (line 1610), the voltage across the MRAM cell will increase to the level indicated by line 1620 at t3 and remain at that level until t5. Recall that HRS is the AP state. Therefore, the MRAM cell will remain in the AP state.

[0145] If the MRAM cell 701 is in the LRS state (line 1612), the voltage across the MRAM cell will increase to the level indicated by line 1622 at t3. Recall that the LRS state is the P state. If the MRAM cell 701 is in the P state, it will switch to the AP state. Figure 16B Line 1622 is shown increasing at t4 to intersect line 1620. This indicates that the MRAM cell has been switched from the P state (LRS) to the AP state (HRS). It will be understood by those skilled in the art that the actual voltage sensed passes through the cell and decoder to the so-called global decode node of the sense amplifier. Current is applied to this global node to drive the memory cell through the word line decoder to the memory bit, and the other side of the memory bit is held near ground by the bit line decoder driver N-channel transistor (source grounded).

[0146] Return again Figure 15 , step 1506 includes driving a second read current through each selected word line while applying a select voltage to the selected bit line to drive a second access current through each selected MRAM cell. In one embodiment, the second access current has the same direction and substantially the same magnitude as the first access current. Figure 13 , current driver 1210b drives I 访问 Through the selected first conductive line 1206b, I 访问 At approximately the same time, current driver 1210g drives I 访问 By selecting the first conductive line 1206g, I 访问 By memory unit 701e. Figure 13 , the voltage driver 1212b converts V 选择Applied to the second conductive line 1208b. In one embodiment, I 访问 is 15μA, and V 选择 is 0V.

[0147] Now we will discuss an MRAM cell 701. Figure 16A and Figure 16B , for further details on step 1506. Figure 16A , the access current at time t5 is from I 写入 Reduce to I 读取 , and keep it at I 读取 Until t6. Figure 16B , the voltage across memory cell 701 decreases to a level indicated by 1630 at t5 and remains at that level until t6. Note that line 1630 is at the HRS level. Also recall that, regardless of the initial state of the MRAM cell, the MRAM cell is placed in the HRS state (AP state) in step 1504.

[0148] Return again Figure 15 , step 1508 includes determining a pre-read state of each selected MRAM cell based on a comparison of a first voltage on each selected word line from driving a first read current through the selected word line to a second voltage on each selected word line from driving a second read current through the selected word line.

[0149] Now we will discuss an MRAM cell 701. Figure 16A and Figure 16B , which is further detailed at step 1508. The first voltage on the selected word line resulting from the application of the first read current will be a voltage between t2 and t3. Therefore, the first voltage is either an HRS level 1610 or an LRS level 1612. Note that this first voltage may have been stored in step 1504, for example, by charging the sense capacitor using the word line voltage. The second voltage on the selected word line resulting from the application of the second read current will be a voltage between t5 and t6. This second voltage will typically be at approximately an HRS level 1610. However, the second voltage may vary slightly from the HRS level 1610. Therefore, comparing the first voltage to the second voltage can be used to determine whether the MRAM cell is at an HRS level 1610 or an LRS level 1612 between t2 and t3.

[0150] Return again Figure 15After step 1508, process 1500 has two options. Step 1510a is a read option. If necessary, step 1510a includes driving a write current through the selected word line 1206 to write back the initial state of the memory cells. Recall that step 1504 placed all MRAM cells in the AP state. Therefore, in step 1510a, all MRAM cells that were originally in the P state are written back to the P state. In step 1510a, all MRAM cells that were originally in the AP state remain in the AP state.

[0151] Step 1510b is the write option. If desired, step 1510b includes driving a write current through the selected word line 1206 to write the new state of the memory cell. As described above, step 1504 places all MRAM cells in the AP state. Therefore, in step 1510b, all MRAM cells that were to be written to the P state are written to the P state, regardless of their initial state. In step 1510b, all MRAM cells that were to be written to the AP state remain in the AP state.

[0152] Figure 17 A flow chart of process 1700 for writing data to an MRAM cell after a destructive SRR is depicted. Process 1700 provides further details of one embodiment of step 1510a. Step 1702 includes performing ECC on the data read from the MRAM cell. Process 1500 can simultaneously read multiple bits of a codeword from a single cross-point array. In some cases, other bits of the codeword are stored in other cross-point arrays. In one embodiment, the system control logic 560 / 660 on the memory die 500 or the control die 611 reads multiple cross-point arrays to obtain all bits of the codeword. In one embodiment, the system control logic 560 / 660 sends the bits of the codeword to the memory controller 102, which decodes the codeword. In some embodiments, the control die 611 decodes the codeword. Regardless of where the decoding is performed, any errors in the data are corrected.

[0153] Step 1704 includes identifying a group of MRAM cells that were in the P state before the destructive SRR. In one embodiment, step 1704 is performed by the system control logic 560 / 660 on the memory die 500 or the control die 611. This identification can be performed based on the results of step 1508 of process 1500.

[0154] Step 1706 includes applying a select voltage to the selected bit line. Step 1708 includes driving a write current through the word lines connected to the identified group of MRAM cells. In one embodiment, I 访问 is -30μA, and V 选择is 0 V. In step 1708, current flows through the MRAM cell in a direction opposite to the direction of current flow in step 1504 of process 1500. Thus, while step 1504 is used to place the MRAM cell in the AP state, step 1708 is used to place the MRAM cell in the P state.

[0155] Figure 18 A flow chart depicts process 1800 for the second phase of writing data to MRAM cells. Process 1800 provides further details of one embodiment of step 1510b. Step 1802 includes identifying a set of MRAM cells that will be programmed to the P state after the destructive SRR. In one embodiment, step 1802 is performed by the system control logic 560 / 660 on the memory die 500 or the control die 611. This identification can be based on data sent to the system control logic 560 / 660 by the memory controller 102. For example, the system control logic 560 / 660 can determine that the MRAM cells to store a "0" will be programmed to the AP state, and the memory cells to store a "1" will be programmed to the P state.

[0156] Step 1804 includes applying a select voltage to the selected bit line. Step 1806 includes driving a write current through the word lines connected to the identified group of MRAM cells. In one embodiment, I 访问 is -30μA, and V 选择 is 0 V. In step 1806, current flows through the MRAM cell in a direction opposite to the direction of current flow in step 1504 of process 1500. Thus, while step 1504 is used to place the MRAM cell in the AP state, step 1806 is used to place the MRAM cell in the P state.

[0157] Figure 19A and Figure 19B Depicted is a timing diagram used during writing to an MRAM cell. The timing diagram may be applicable to process 1700 or process 1800. Figure 19A The current driven through the selected word line is plotted versus time. Figure 19B The relationship between voltage and time across the MRAM cell is depicted. The timing diagram is similar to Figure 16A and Figure 16B and, in some embodiments, represents a timing diagram that follows the SRR timing diagram. Figure 19A and Figure 19B , assuming that the MRAM cell is in the AP state at time t1. At time t1, the current supplied to the selected word line drops from 0A to I 写入 Level. Figure 19A middle, I 写入 is represented as a negative value. For example, although Figure 16A Middle I 写入 can be 30μA, but Figure 19A Middle I 写入 The access current is kept at I 写入 , from t1 until t5. Note that, as defined herein, this negative magnitude access current can flow from the selected word line 1206 to the current driver 1210. In other words, Figure 19A In the example of , current driver 1210 sinks the access current. As defined herein, this is an example of driving a negative current through a word line.

[0158] refer to Figure 19B , between t1 and t3, the voltage across the MRAM drops from 0V to V ss The threshold switch selector 1204 is disconnected between t1 and t2. Once the voltage across the threshold switch selector 1204 reaches the threshold voltage V 阈值 , the threshold switch selector will turn on and switch to the low resistance state (at t2). After the threshold switch selector 1204 turns on, the voltage across the MRAM cell can continue to decrease. By time t3, the voltage across the MRAM cell is at a steady state value (V ss ). In addition, after time t2, all I 写入 All pass through the MRAM cell. At time t4, the MRAM cell switches from the AP state to the P state. Because the P state is a lower resistance state than the AP state, the absolute magnitude of the voltage across the MRAM cell decreases at t4. In other words, at t4, the voltage across the MRAM cell moves closer to 0V.

[0159] In one embodiment, the MRAM cells in a cross-point array are written simultaneously by first writing all selected MRAM cells in the cross-point array to the AP state simultaneously. Then, a group of selected MRAM cells are written to the P state simultaneously from the AP state. This technique can be modified to first write all selected MRAM cells in the cross-point array to the P state simultaneously. Then, a group of selected MRAM cells are written to the AP state simultaneously from the P state.

[0160] Figure 20 FIG2 is a flow chart of a process 2000 for simultaneously writing to MRAM cells, wherein all selected MRAM cells are first written to one of the AP state or the P state. In one embodiment, the process 2000 is performed by control circuitry in the memory die 500. In one embodiment, the process 2000 is performed by control circuitry in the control die 611.

[0161] Step 2002 includes receiving data to be stored in the non-volatile storage device over the communication interface 568 / 668. In one embodiment, the memory die 500 receives the data from the memory controller 102. In one embodiment, the control die 611 receives the data from the memory controller 102.

[0162] Step 2004 includes identifying a first group of MRAM cells 701 in the cross-point array to store a first bit value and identifying a second group of MRAM cells 701 in the cross-point array to store a second bit value for storing data. The first group of MRAM cells 701 and the second group of MRAM cells 701 represent all selected MRAM cells 701 in the cross-point array. In one embodiment, the first bit value is "1" and the second bit value is "0." In one embodiment, the first bit value is represented by the AP state and the second bit value is represented by the P state. Thus, "1" can be represented by the AP state and "0" can be represented by the P state; however, this mapping can be reversed.

[0163] Step 2006 includes placing all MRAM cells 701 in the first and second groups in one of an AP state or a P state. Thus, all selected MRAM cells 701 in the cross-point array are placed in one of an AP state or a P state. This means that all selected MRAM cells 701 in the cross-point array are placed in the AP state, or alternatively, all selected MRAM cells 701 in the cross-point array are placed in the P state. In one embodiment, step 2006 includes performing at least a portion of an SRR. For example, step 2006 may include performing at least steps 1502 through 1504 of process 1500. In one embodiment, steps 1502 through 1506 are performed. In one embodiment, steps 1502 through 1508 are performed.

[0164] Step 2008 includes simultaneously placing the first group of MRAM cells in either the AP state or the P state, while placing the second group of MRAM cells in either the AP state or the P state. In one embodiment, the first group of MRAM cells has two or more cells, and the second group of MRAM cells has zero or more cells. In one embodiment, the first group of MRAM cells has zero or more cells, and the second group of MRAM cells has two or more cells. In one embodiment, the first group of MRAM cells has one or more cells, and the second group of MRAM cells has one or more cells.

[0165] The following two examples will be used to extend step 2006 to step 2008. As one example, in step 2006, both the first and second groups of MRAM cells 701 in the cross-point array are placed in the AP state. In step 2008 of the first example, the first group of MRAM cells are written from the AP state to the P state while the second group of MRAM cells is in the AP state. As a second example, in step 2006, both the first and second groups of MRAM cells 701 in the cross-point array are placed in the P state. In step 2008 of the second example, the first group of MRAM cells are written from the P state to the AP state while the second group of MRAM cells is in the P state.

[0166] As described above, reading data from or writing data to an MRAM memory cell involves passing current through the memory cell. In embodiments where a threshold switch selector is placed in series with the MRAM device, the threshold switch selector needs to be turned on by applying a sufficient voltage across the series combination of the threshold switch selector and the MRAM device before current can pass through the MRAM device. Figure 21A 、 Figure 21B and Figure 22 This activation of the threshold switch selector is considered in more detail in the context of a read operation.

[0167] Figure 21A and Figure 21B are used in read operations respectively Figure 11A and Figure 11B One embodiment of a set of waveforms of current and voltage of a layer 1 unit, wherein Figure 21A and Figure 21B The time axes are aligned and on the same scale. Figure 16A and Figure 16B , Figure 21A and Figure 21B Consider the interval until time t3. In this embodiment for a read operation, the read is performed in the P2AP direction, where word line 1 1100 / 1150 is biased high and bit line 1110 / 1160 is set low (e.g., 0V), so that the (conventional) current flows upward, first through the reference layer 1105 / 1155 and then through the free layer 1101 / 1151. (In terms of electron current, the electron flow will be opposite to the conventional current as shown in FIG. Figure 10B As shown.)

[0168] exist Figure 21A and Figure 21B In an embodiment, a forced current method is used, in which the memory is read from the reference layer side with a read current I from a current source in a driver circuit for the line. 读取 Driver. Figure 21A As shown by the solid line 2101, the current increases to I读取 value and maintains that value for the duration of the current read operation. This current will move the line that supplies current to the selected memory cell, such as Figure 11A Word line 1 1100 / 1150 of the layer 1 memory cells in / B and also supports any leakage in the path. Figure 21B As shown at 2151 in FIG, when the threshold switch selector is in the off state, the current across the parallel combination of the threshold switch selector and the resistive MRAM element ramps up. Once the voltage across the threshold switch selector reaches the threshold voltage V of the threshold switch selector at 2153 阈值 , the threshold switch selector will turn on and switch to the low resistance state.

[0169] Once the threshold switch selector is in the on state, I 读取 Current will flow through the selected memory cell. Figure 21A The dashed line 2103 shows that when the threshold switch selector is turned on at 2153, it reroutes the current flowing through the memory cell from zero to I 读取 When the current level is kept fixed at I 读取 When the voltage across the memory cell drops to a level that depends on the series resistance of the MRAM device and the on-state resistance of the threshold switch selector. For a binary implementation, the memory cell will have a high resistance antiparallel state and a low resistance parallel state. The response to the high resistance state (HRS) and low resistance state (LRS) is 读取 The resulting voltage across the series-connected MRAM device and threshold switch selector is shown as 2155 and 2153, respectively. The resulting voltage difference can then be measured by a sense amplifier to determine the data state stored in the memory cell. While the discussion here is in the context of an MRAM-based memory cell placed in series with a threshold switch selector, the reading technique can be similarly applied to other programmable resistive memory cells, such as PCM or ReRAM devices.

[0170] Figure 21B The voltage is shown to be applied at 2151 and ramped up until it reaches V at 2153. 阈值 , and then drops to the high resistance state level at 2155 or the low resistance state at 2153. In a real device, due to resistance and capacitance, there will be some delay when the voltage spike at 2153 drops to 2155 or 2153. This is caused by Figure 22 Example display for low resistance state.

[0171] Figure 22 An example of the voltage across the MRAM device when the threshold switch selector switches from the off state to the on state is shown. Figure 21B , Figure 22 shows the voltage V across the MRAM device only. MRAM ,and Figure 21B represents the voltage across the series combination of the threshold switch selector and the MRAM device. Initially, before the threshold switch selector turns on, as the applied voltage ramps to V 阈值 voltage, the voltage across the MRAM device will be zero. Once the threshold switch selector is turned on, current begins to flow through the MRAM device, and the voltage across the MRAM device will reach V in the form of a spike. 阈值 level minus the voltage V dropped across the threshold switch selector 保持 Therefore, V MRAM will jump from 0V to ΔV=(V 阈值 –V 保持 ), which will then respond to the applied I 读取 decays to the voltage drop across the MRAM device in the resistive state; for example, I 读取 ×R MRAM For a 25KΩ LRS and a 15μA read current, the voltage V across the MRAM device MRAM will be 375mV. For a 50KΩ HRS, V mram will be 750 mV (unless compliance V is reached which limits the voltage to the clamping voltage). A difference of 375 mV can be sensed, for example, by adjusting the stored level by a threshold amount, such as by 150 mV.

[0172] V MRAM The voltage drops to asymptotically close to V MRAM The rate of the level is determined by the "snapback voltage" ΔV (ie (V 阈值 -V 保持 and V MRAM The size of the spike (the difference between the values ​​of the spiking voltage and the spiking voltage), and the rate at which charge can flow out of the device, depends on the RC characteristics of the memory cell and the wire it is connected to. This behavior has some practical implications for the operation of the memory cell.

[0173] The first effect is that both the low resistance state and the high resistance state will decay, e.g. Figure 22 As shown, Figure 22 The low resistance state is shown. The high resistance state will show similar behavior, but with a higher asymptotic state. In order to distinguish between the two states, they need to be separated by a sufficient margin so that a sensing operation cannot be performed until sufficient time has passed so that the two states have well-defined and distinguishable voltage levels.

[0174] Another effect is that the overcurrent spike may disturb the data stored in the memory cell. Figure 10A and Figure 10BAs discussed, the state of an MRAM memory can be changed by passing a current through the memory cell such that if the voltage across the memory cell and / or the current through the memory cell is high enough for a long enough time, it will change from a parallel state to an antiparallel state (P2AP write), depending on the direction of the current flow, as shown in FIG. Figure 10B As shown, or changing the antiparallel state to a parallel state (AP2P write), as Figure 10A For example, Figure 21A and Figure 21B The reading process of is described as being performed along the P2AP direction, such that Figure 22 The disturbance caused by the waveform of can switch a low resistance state memory cell to a high resistance state before the stored data state can be determined.

[0175] As described above, the threshold switch selector controls access to the memory cell. Specifically, in order to apply a voltage or current to a memory cell to read or change its resistance state, the corresponding selector must first be activated by applying a sufficiently high voltage (e.g., a magnitude higher than the operating threshold voltage V 阈值 When the selector is in the non-conductive state, for example, when the voltage across the selector is below the operational threshold voltage, the memory cell is isolated and maintains its existing resistance state because the MRAM voltage is [R MRAM / (R MRAM +R 选择器 )]×V 施加 =V MRAM The ratio of the non-conductive R 选择器 (e.g. >1MΩ) much larger than R MRAM (For example, <100Ω), V MRAM Low enough, until the selector switches on and its resistance drops to, for example, 1 KΩ.

[0176] Therefore, selecting an MRAM memory cell to read its data content involves turning on the corresponding threshold switch selector with a threshold value from V 阈值 to V 保持 Since the OTS turns on for less than 1 nanosecond, for example, this transient is sensed quickly, and V 选择器 The difference is applied across the MRAM device and decays within a time determined by the internal resistance of the threshold switch selector and the MRAM, as well as the capacitance across the array nodes (e.g., line-to-line capacitance and capacitance of other components in the transistors and drivers) and the series resistance of these capacitive components. Since this transient can cause a disturbance to the data state stored in the memory cell, and since the memory cell cannot be sensed until the transient has sufficiently decayed, the faster this overvoltage can be discharged, the lower the amount of read disturb, and the faster the read operation can be completed.

[0177] If in a Figure 7D In the multi-layer cross-point array structure shown, the orientation of the MRAM devices in the upper layer 720 is the same as that in the lower layer 718 (such as Figure 11A During reading along the P2AP direction as described above for the self-referenced read (SRR) process, the current will flow in different directions in the two layers. More specifically, when Figure 11A When reading in the P2AP direction with the orientation of MRAM 1102 and MRAM 1112 as shown, the current flows in the upward direction for both the layer 1 cells and the layer 2 cells. Therefore, when reading in the P2AP direction for the layer 1 memory cells, word line 1 1100 will be set to a high voltage level and bit line 1110 will be set to a low voltage level, while when reading in the P2AP direction for the layer 2 memory cells, bit line 1110 will be set to a high voltage and word line 2 1120 will be set to a low voltage. Note that when reading layer 1 in the SRR process, this requires Figure 11A The bit line 1110 is biased low to act as a current sink; however, when reading in layer 2 during the SRR process, the bit line 1110 is biased high to act as a current source. This prevents reading layer 1 memory cells and layer 2 memory cells at the same time.

[0178] When forming Figure 7D or Figure 11A When a multi-layer memory structure is shown, from a processing perspective, it is preferable that each layer is formed in the same manner, so only one module is required. For example, see Figure 11A After forming a first set of conductive lines (word lines 11100) above a substrate (not shown), the processing module can sequentially form a threshold switch selector, a reference layer, a tunnel barrier, and a free layer (1109, 1105, 1103, and 1101, respectively). After subsequently forming a second set of conductive lines (bit lines 1110), the memory cell processing module can then be repeated to form a threshold switch selector, a reference layer, a tunnel barrier, and a free layer (1119, 1115, 1113, and 1111, respectively). Repeating the same set of steps for each subsequent layer simplifies processing, particularly when the MRAM structures 1102 and 1112 are represented in simplified form and more information is provided about the actual processing modules used for these elements.

[0179] While forming all MRAM layers with the same orientation is generally preferred, reversing the orientation of an MRAM device with alternating layers can provide a number of advantages. Figure 11B An embodiment is shown in which the layer 2 memory cells have been compared to Figure 11AThe current is reversed so that in SRR operation, the current is forced from word line 1 1150 to bit line 1160 when reading tier 1 memory cells, and from word line 2 1170 to bit line 1160 when reading tier 2 memory cells. This allows the same bias level to be used on bit line 1160 when reading from either level, and also allows the same bias level to be used as described above with respect to Figure 14 、 Figure 15 Alternatively, Figure 11A The layer 1 memory cells may have an inverted orientation, where current is forced from bit line 1110 to word line 1 1100 and / or word line 2 1120 during an SRR read operation. Although inverting the orientation of either layer may allow the same biasing of bit line 1110 when reading memory cells of either level, which of the two layers is inverted may affect the Figure 22 The type of transient voltage exhibited can be dissipated quickly.

[0180] As mentioned above, how fast the transient spike generated across the MRAM element when the threshold switch selector turns on depends on the resistance and capacitance of the path through which the voltage spike is discharged. Figure 11A , where the orientation is the same in layers 1 and 2, word line 1 1100 is pulled high for SRR reads in layer 1, and word line 2 is pulled low for SRR reads in layer 2. Figure 12 or Figure 13 The wordline drivers 1210a to 1210h can pull the wordline up to a lower level by using P-channel devices, while they can pull the wordline down to a higher level by using N-channel devices. Whether based on PMOS pull-up transistors or NMOS pull-down transistors, the capacitance of such drivers is largely proportional to their size. For a given amount of drive resistor requirements, NMOS devices can be formed with a smaller size than PMOS devices. Therefore, in Figure 12 or Figure 13 The array structure shown is one in which the word lines are shorter than the bit lines. Figure 22 The transients shown across the MRAM device can be discharged most rapidly by pulling the selected word line toward ground using an N-channel device, and pulling the bit line used to select the lower or upper layer to near the positive supply, such as 3.3V, for P2AP reading. Therefore, to allow the two layers to be Figure 11A Select word lines as in the upper layer of Figure 23 The shown reverse orientation of the underlying MRAM device. Such an arrangement can significantly reduce the bit error rate when reading data, as read disturb is reduced, and also allows for improved performance in terms of read latency.

[0181] Figure 23A two-tier implementation of a cross-point memory architecture is shown, where the MRAM devices in the lower tier are inverted relative to the upper tier in order to minimize capacitance in read operations. Figure 23 repeat Figure 11A The elements of the layer 1 cell are similarly numbered (eg, word line 1 1100 is now 2300), but the layer MRAM components of the layer 1 cell are reversed.

[0182] More specifically, in Figure 23 In FIG. 2 , the layer 1 memory cell is formed between the lower conductive line of word line 1 2300 and the middle conductive line of bit line 2310. The MRAM device 2302 now has its reference layer 2301 formed over a tunnel barrier 2303, which in turn is formed over a free layer 2305. This is relative to Figure 11A The Tier 1 MRAM device 1101 is inverted so that the Tier 1 memory cell is sensed by forcing current from the bit line 2310 through the MRAM device 2302. This is represented by the bold arrow flowing from the bit line 2310 to the word line 1 2300. Figure 23 In one embodiment, the threshold switch selector 2309 remains below the MRAM device 2302, allowing the processing sequence associated with forming this element to be the same in both layers, but an alternative embodiment reverses the order of the MRAM device 2302 and the threshold switch selector 2309.

[0183] In layer 2, the memory cells between word line 2 2320 and bit line 2310 are as follows: Figure 11A oriented as in FIG, where a free layer 2311 is formed over a tunnel barrier 2313, which in turn is formed over a reference layer 2315, with a threshold switch selector 2319 below. As with the tier 1 memory cells, the tier 2 memory cells are sensed by forcing current from the bit line 2310 through the MRAM device 2312. This is represented by the bold arrow flowing from the bit line 2310 to the word line 2 2320.

[0184] Figure 23 Also schematically shown are the selection and drive circuits for word line 1 2300, bit line 2310, and word line 1 2320. Figure 12 and Figure 13 , these elements can be considered as part of one of the word line drivers 1210a to 1210h or the bit line drivers 1212a to 1212d. As shown by the bold arrows, in a read operation along the P2AP direction, a read current is driven from the bit line 2310 to one or both of the word line 1 2300 and the word line 2 2320. The current I 读取(P2AP) can be provided by a current source 2345, which can be based on a current mirror connected to a power supply level, for example. The current source 2345 provides a read current I to the bit line 2310 through the PMOS device 2343. 读取 (P2AP), the PMOS device receives a decoding control signal BL Sel to select the bit line 2310. The read current is discharged from word line 1 2300 and word line 2 2320 by corresponding NMOS devices 2341 and 2347, which receive corresponding decoding control signals WL1 Sel to select word line 1 2300 and WL2 Sel to select word line 2 2320.

[0185] By increasing the threshold voltage (V 阈值 ) to reduce leakage in threshold switching devices and obtain the widest allowed V when using a P-channel pull-up device on one of the word lines or the bit line for a memory cell and an N-channel pull-down on the other of the word lines and the bit line. 阈值 range to avoid V 阈值 In the two-layer embodiment described primarily herein, since the bit lines are arranged between two separate word lines, and also since in the embodiment described above, ... since in the embodiment described above, the bit lines are arranged between two separate word lines, and since in the embodiment described above, the bit lines are arranged between two separate word lines, and Figure 12 and Figure 13 In the illustrated embodiment, bit lines tend to have longer lengths and, therefore, tend to have greater capacitance. Therefore, the rate at which transient voltage spikes can be dissipated during threshold selection switching is primarily determined by the RC characteristics of the word lines. One way to reduce drain time and read latency is to reduce capacitance by shortening conductor lengths and increasing the array's conductor-to-conductor spacing, but both techniques reduce memory density. Another way to reduce drain time and read latency without adversely affecting memory density is to reduce the size of the transistors driving the conductive lines. By using smaller NMOS devices 2341 and 2347 for word lines 2300 and 2320, and a larger PMOS device 2343 on bit line 2310, the capacitance of the primary path for dissipating transient voltages can be reduced without reducing array density.

[0186] Re-reference Figure 16A and Figure 16B In the self-referenced reading process shown in FIG, in the two sensing operations between t1 to t3 and t5 to t6, the current flows as follows Figure 23 As shown, both use I 读取 For the write from t3 to t5, where all memory cells are placed in the high resistance AP state, the current is also in the P2AP direction, as shown in Figure 23 shown, but for forced current use with I 写入 Therefore, in Figure 23In an embodiment, the array can operate with the bit line 2310 being uniformly pulled high by the PMOS device 2343, wherein the current source 2345 is switched to I during the interval t3 to t5. 写入 , and operates with word line 2300 and word line 2320 pulled low in unison by NMOS devices 2341 and 2347. Figure 19A and Figure 19B When writing the selected memory cell back to the low resistance parallel state (AP2P) as shown, these biases are reversed, with the selected bit line 2310 taken low and the selected word line of one or both word lines 2300 and 2320 taken high to drive I 写入 Passing through the selected memory cells in the AP2P direction. Note that since for each of the sub-operations of the SRR process, both the layer 1 memory cells and the layer 2 memory cells are biased in the same direction, this allows for implementations where these operations are performed in parallel for both layers.

[0187] Figure 24 is used Figure 23 A flow chart of an embodiment of performing a self-referenced read using a structure of a memory cell structure. The flow chart describes the SRR process for both layer 1 and layer 2 memory cells, with steps alternating between the two layers. The two layers can be operated independently, such that only layer 1 operations or layer 2 operations are performed, or they can be operated simultaneously, such that a given layer 2 operation is performed simultaneously with the corresponding layer 1 operation to simultaneously read the data contents of both layers, as described above for simultaneous reads along multiple word lines.

[0188] At step 2401, I 读取 The data content of the MRAM device 2302 of layer 1 is sensed by driving from bit line 2310 to word line 1 2300: the BL Sel signal to PMOS 2343 is asserted and the WL1 Sel signal to NMOS 2341 is asserted. The resistance state of the MRAM device 2302 can then be determined by the corresponding sense amplifier (i.e., one of SA 1228a to 1228h). Similarly, step 2403 determines the data content of the MRAM device 2312 of layer 2 by: asserting the BL Sel signal to PMOS 2343 and the WL2 Sel signal to NMOS 2347. 读取 Drive from bit line 2310 to word line 2 2320, where the resistance state of the MRAM device 2312 is determined by the corresponding sense amplifier (i.e., one of SAs 1228a to 1228h). Since both the tier 1 memory cells and the tier 2 memory cells can be biased simultaneously as in steps 2401 and 2403, these sensing operations can be performed simultaneously in some embodiments.

[0189] At step 2405, the BL Sel signal to the PMOS 2343 is asserted and the WL1 Sel signal to the NMOS 2341 is asserted, thereby 写入 Driving from bit line 2310 to word line 1 2300 writes the MRAM device 2302 of layer 1 to the AP state, but the current source 2345 is currently providing I 写入 At step 2407, the BL Sel signal to the PMOS 2343 is asserted and the WL1 Sel signal to the NMOS 2347 is asserted, thereby 写入 Driving from bit line 2310 to word line 22320 writes the MRAM device 2312 of layer 2 to the AP state, where the current source 2345 is currently providing I 写入 Since both the layer 1 memory cells and the layer 2 memory cells can be biased simultaneously as in steps 2405 and 2407, these sensing operations can be performed simultaneously in some embodiments. A second read of the SRR process can then be performed at steps 2409 and 2411, which can be performed as described above for steps 2401 and 2403, respectively.

[0190] If the MRAM element 2302 of the layer 1 memory cell is selected to be written into the low resistance parallel state, then at step 2413 the write current I 写入 The AP2P operation is performed by driving the bit line 2310 from word line 1 2300 (i.e., in the opposite direction from the previous step). Similarly, if the MRAM element 2312 of the layer 2 memory cell is selected to be written to the low resistance parallel state, then at step 2415 the write current I 写入 The AP2P operation is performed by driving current from word line 2 2320 to bit line 2310. When both steps 2413 and 2415 drive current from corresponding word lines into the same bit, these operations can be performed simultaneously.

[0191] like Figure 24 As discussed above, since each pair of steps biases the bit line and the corresponding word line in the same way, these steps can be performed in parallel. Conversely, if only one layer is read, only the steps associated with that layer can be performed.

[0192] Figure 25 is used to form Figure 23 In each step, the process can be similar to forming Figure 11A The structure of the processing, but Figure 25 The change in the order of processing steps between Layer 1 and Layer 2 is highlighted. As mentioned above, Figure 23is simplified, where only the free layer, tunnel barrier and reference layer MRAM are shown, and a more detailed description would include, for example, the above description of Figure 9 The additional structure.

[0193] At step 2501, a first set of conductive lines extending along a first direction is formed above a substrate. Figure 23 The first set of conductive lines is not shown in FIG. Figure 23 In the view of FIG. 1 , the first conductive line includes word line 12300 and corresponds to Figure 7D In the lower word line. Figure 23 In one embodiment, the threshold switch device is formed below the MRAM device in each layer, and the threshold switch selector 2309 is formed at step 2503. In other embodiments, the threshold switch device may be formed above the MRAM device in one or both of the layers. At step 2504, the layer 1 MRAM device 2302 is formed. Figure 23 In an embodiment in which the layer 1 MRAM device is inverted, step 2504 includes a sequence of sub-steps of forming a free layer 2305 above the threshold switch selector 2309 at step 2505, forming a tunnel barrier 2303 above the free layer 2305 at step 2507, and then forming a reference layer 2301 above the tunnel barrier 2303 at step 2509.

[0194] At step 2511, a second set of conductive lines is formed over the layer 1 MRAM device 2302. The second layer of conductive lines includes bit lines 2310 and corresponds to Figure 7D With the completion of step 2511, the memory structure of layer 1 is complete. In the cross-point architecture, this second set of conductive lines extends in a second direction above the substrate perpendicular to the first layer of conductive lines (bottom set of word lines). Although for the purpose of discussion, Figure 23 (and the above Figure 11A and Figure 11B ) shows the word lines and bits as running from left to right, but when viewed in a larger structure, one of these (the bit lines or the two layers of word lines) would more accurately run into the page, as Figures 7B to 7D shown.

[0195] The second layer is formed at the beginning of step 2513, which forms the layer 2 threshold switch selector 2319 above the second set of conductive lines (bit lines 2310). Figure 23In the processing sequence of embodiments of the present invention, the layer 2 threshold switch selector is again formed below the MRAM device of the memory cell of the layer, but other embodiments may reverse this as in layer 1. The layer 2 MRAM device 2312 is then formed in step 2514. The substeps of step 2514 reverse the order relative to layer 1: step 2515 forms a reference layer 2315 above the threshold switch selector 2319, step 2517 forms a tunnel barrier 2313 above the reference layer 2315, and step 2519 forms a free layer 2311 above the tunnel barrier 2313. In step 2521, a top layer of conductive lines (including word line 2 2320) is formed, which extends above the underlying structure in the same direction as the bottom layer of conductive lines (including word line 1 2300). For 2521, Figure 23 If additional layers are to be formed, the process can continue in the same manner, alternating processing modules for layer 1 with such modules for layer 2.

[0196] According to a first set of aspects, a device includes a nonvolatile memory having a substrate and one or more memory arrays formed on the substrate. Each of the arrays includes: a first set of conductive lines extending in a first direction parallel to a surface of the substrate; a second set of conductive lines formed above the first set of conductive lines and extending in a second direction parallel to the surface of the substrate; a third set of conductive lines formed above the second set of conductive lines and extending in the first direction; and a first set of memory cells and a second set of memory cells. Each of the first plurality of memory cells is connected between a corresponding one of the first group of conductive lines and a corresponding one of the second group of conductive lines, each of the first plurality of memory cells includes a threshold switch selector connected in series with a magnetoresistive random access memory (MRAM) device, the MRAM device of each of the first plurality of memory cells including: a reference layer having a fixed magnetic field polarity; and a free layer connected in series with the reference layer and having a programmable magnetic field polarity, wherein the free layer is formed below the reference layer; each of the second plurality of memory cells is connected between a corresponding one of the second group of conductive lines and a corresponding one of the third group of conductive lines, each of the second plurality of memory cells includes a threshold switch selector connected in series with the MRAM device, the MRAM device of each of the plurality of memory cells including: a reference layer having a fixed magnetic field polarity; and a free layer connected in series with the reference layer and having a programmable magnetic field polarity, wherein the free layer is formed above the reference layer;

[0197] In another aspect, a method includes sensing a data state of a selected one of a first plurality of memory cells by forcing a read current to flow from a second conductive line to a corresponding first conductive line, the selected one of the first plurality of memory cells being part of an array including a first plurality of memory cells and a second plurality of memory cells, each of the first plurality of memory cells and the second plurality of memory cells including a threshold switch selector connected in series with a magnetoresistive random access memory (MRAM) device. The method also includes sensing the data state of the selected one of the second plurality of memory cells by forcing a read current to flow from the corresponding second conductive line to a corresponding third conductive line. In addition, the method may include: writing a selected one of the first plurality of memory cells from the first state to the second state by forcing a write current to flow from the corresponding second conductive line to the corresponding first conductive line, and writing a selected one of the first plurality of memory cells from the first state to the second state by forcing a write current to flow from the corresponding first conductive line to the corresponding second conductive line; and also includes: writing a selected one of the second plurality of memory cells from the first state to the second state by forcing a write current to flow from the corresponding second conductive line to the corresponding third conductive line, and writing a selected one of the second plurality of memory cells from the second state to the first state by forcing a write current to flow from the corresponding third conductive line to the corresponding second conductive line.

[0198] In another set of aspects, an apparatus includes a controller circuit configured to be connected to an array of memory cells, each of which has a threshold switch selector connected in series with a magnetoresistive random access memory (MRAM) device, the array including a first plurality of memory cells and a second plurality of memory cells, wherein each of the first plurality of memory cells is connected between a corresponding one of a first set of conductive lines and a corresponding one of a second set of conductive lines, and each of the second plurality of memory cells is connected between a corresponding one of a third set of conductive lines and a corresponding one of a second set of conductive lines, the control circuit configured to: read a selected memory cell of the first plurality of memory cells by biasing a corresponding one of the first set of conductive lines to a lower voltage than a corresponding one of the second set of conductive lines; and read a selected memory cell of the first plurality of memory cells by biasing a corresponding one of the third set of conductive lines to a lower voltage than a corresponding one of the second set of conductive lines. reading a selected memory cell of the second plurality of memory cells by biasing a corresponding one of the first group of conductive lines to a voltage lower than that of the corresponding one of the second group of conductive lines; writing a selected memory cell of the first plurality of memory cells from the first state to the second state by biasing a corresponding one of the first group of conductive lines to a voltage higher than that of the corresponding one of the second group of conductive lines; writing a selected memory cell of the first plurality of memory cells from the second state to the first state by biasing a corresponding one of the first group of conductive lines to a voltage higher than that of the corresponding one of the second group of conductive lines; writing a selected memory cell of the second plurality of memory cells from the first state to the second state by biasing a corresponding one of the third group of conductive lines to a voltage lower than that of the corresponding one of the second group of conductive lines; and writing a selected memory cell of the second plurality of memory cells from the second state to the first state by biasing a corresponding one of the third group of conductive lines to a voltage higher than that of the corresponding one of the second group of conductive lines.

[0199] For the purposes of this document, references in the specification to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" may be used to describe different embodiments or the same embodiment.

[0200] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other components). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via an intervening element. When an element is referred to as being directly connected to another element, there are no intervening elements between the element and the other element. Two devices are "in communication" if they are directly connected or indirectly connected such that they are capable of communicating electronic signals between them.

[0201] For the purposes of this document, the term "based on" may be understood to mean "based, at least in part, on."

[0202] For the purposes of this document, the use of numerical terms such as a "first" object, a "second" object, and a "third" object without additional context may not imply an ordering of the objects, but may be used for identification purposes to identify different objects.

[0203] For the purposes of this document, the term "group" of objects may refer to a "group" of one or more objects.

[0204] The above detailed description has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The described embodiments were chosen to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize it in various embodiments and with various modifications as suited to the specific use contemplated. The scope of the invention is intended to be defined by the claims appended hereto.

Claims

1. A memory device comprising: Non-volatile memory, including: substrate; One or more memory arrays, the one or more memory arrays being formed on the substrate, each of the arrays comprising: a first set of conductive lines extending in a first direction parallel to a surface of the substrate; a second set of conductive lines formed above the first set of conductive lines and extending in a second direction parallel to the surface of the substrate; a third group of conductive lines formed above the second group of conductive lines and extending along the first direction; A first plurality of memory cells, each of the first plurality of memory cells being connected between a corresponding one of the first group of conductive lines and a corresponding one of the second group of conductive lines, each of the first plurality of memory cells comprising a threshold switch selector connected in series with a magnetoresistive random access memory (MRAM) device, the MRAM device of each of the first plurality of memory cells comprising: a reference layer having a fixed magnetic field polarity; and a free layer connected in series with the reference layer and having a programmable magnetic field polarity, wherein the free layer is formed below the reference layer; and a second plurality of memory cells, each of the second plurality of memory cells being connected between a corresponding one of the second group of conductive lines and a corresponding one of the third group of conductive lines, each of the second plurality of memory cells comprising a threshold switch selector connected in series with an MRAM device, the MRAM device of each of the second plurality of memory cells comprising: a reference layer having a fixed magnetic field polarity; and A free layer is connected in series with the reference layer and has a programmable magnetic field polarity, wherein the free layer is formed above the reference layer.

2. The apparatus of claim 1 , wherein the nonvolatile memory is formed on a memory die, the apparatus further comprising: A control die is connected to the memory die and configured to write data to and read data from the one or more memory arrays, the control die being formed separately from and bonded to the memory die.

3. The apparatus according to claim 1, further comprising: one or more control circuits connected to the first, second, and third groups of conductive lines, the one or more control circuits configured to: reading a selected memory cell of the first plurality of memory cells by biasing a corresponding one of the first set of conductive lines to a lower voltage than a corresponding one of the second set of conductive lines; reading a selected memory cell of the second plurality of memory cells by biasing a corresponding one of the third set of conductive lines to a lower voltage than a corresponding one of the second set of conductive lines; writing a selected one of the first plurality of memory cells from a first state to a second state by biasing a corresponding one of the first set of conductive lines to a lower voltage than a corresponding one of the second set of conductive lines; writing a selected one of the first plurality of memory cells from the second state to the first state by biasing a corresponding one of the first set of conductive lines to a higher voltage than a corresponding one of the second set of conductive lines; writing a selected memory cell of the second plurality of memory cells from the first state to the second state by biasing a corresponding one of the third set of conductive lines to a lower voltage than a corresponding one of the second set of conductive lines; as well as A selected memory cell of the second plurality of memory cells is written from the second state to the first state by biasing a corresponding one of the third set of conductive lines to a higher voltage than a corresponding one of the second set of conductive lines. The apparatus of claim 3 , wherein the first state is a high resistance state and the second state is a low resistance state.

5. The apparatus of claim 3 , wherein the one or more control circuits comprise: a first set of drivers, each of the first set of drivers being connected to a corresponding one of the first set of conductive lines; a second set of drivers, each of the second set of drivers being connected to a corresponding one of the second set of conductive lines; and a third group of drivers, each of the third group of drivers being connected to a corresponding one of the third group of conductive lines; wherein, when reading a selected one of the first plurality of memory cells, a corresponding one of the first group of drivers connects a corresponding one of the first group of conductive lines to a low voltage level via an N-channel device, and a corresponding one of the second group of drivers connects a corresponding one of the second group of conductive lines to a high voltage level via a P-channel device, and Wherein, when reading a selected memory cell from the second plurality of memory cells, a corresponding one of the third group of drivers connects a corresponding one of the third group of conductive lines to the low voltage level through an N-channel device, and a corresponding one of the second group of drivers connects a corresponding one of the second group of conductive lines to the high voltage level through a P-channel device.

6. The device according to claim 5, wherein: When reading a selected one of the first plurality of memory cells, a corresponding one of the second set of drivers is configured to drive a read current through the selected one of the first plurality of memory cells, and When reading a selected one of the second plurality of memory cells, a corresponding one of the second set of drivers is configured to drive the read current through the selected one of the second plurality of memory cells.

7. The apparatus of claim 3 , wherein the one or more control circuits are further configured to simultaneously read a selected memory cell from among the first plurality of memory cells connected to a first conductive line in the second set of conductive lines and a selected memory cell from among the second plurality of memory cells connected to the first conductive line in the second set of conductive lines.

8. The device of claim 3, wherein the second set of conductive lines is longer than both the first set of conductive lines and the third set of conductive lines.

9. The apparatus of claim 1 , wherein in each of the first plurality of memory cells, the threshold switch selector is formed below the series-connected MRAM device, and in each of the second plurality of memory cells, the threshold switch selector is formed below the series-connected MRAM device.

10. A method for a memory cell, comprising: sensing a data state of a selected one of a first plurality of memory cells by forcing a read current to flow from a corresponding second conductive line to a corresponding first conductive line, the selected one of the first plurality of memory cells being part of an array including a first plurality of memory cells and a second plurality of memory cells, each of the first plurality of memory cells and the second plurality of memory cells including a threshold switch selector connected in series with a magnetoresistive random access memory (MRAM) device; sensing a data state of a selected one of the second plurality of memory cells by forcing the read current to flow from the corresponding second conductive line to a corresponding third conductive line; writing a selected one of the first plurality of memory cells from a first state to a second state by forcing a write current from the corresponding second conductive line to the corresponding first conductive line; writing a selected one of the first plurality of memory cells from the second state to the first state by forcing the write current from the corresponding first conductive line to the corresponding second conductive line; writing a selected one of the second plurality of memory cells from the first state to the second state by forcing the write current from the corresponding second conductive line to the corresponding third conductive line; as well as A selected one of the second plurality of memory cells is written from the second state to the first state by forcing the write current from the corresponding third conductive line to the corresponding second conductive line.

11. The method of claim 10, wherein said sensing the data state of a selected one of a first plurality of memory cells and said sensing the data state of a selected one of a second plurality of memory cells are performed simultaneously.

12. The method according to claim 10, wherein: sensing the data state of a selected one of the first plurality of memory cells by forcing the read current from the second conductive line to the corresponding first conductive line includes connecting the corresponding first conductive line to a low voltage level through an N-channel device; as well as Sensing the data state of the selected one of the second plurality of memory cells by forcing the read current to flow from the corresponding second conductive line to the corresponding third conductive line includes connecting the corresponding third conductive line to the low voltage level through an N-channel device.

13. A memory device comprising: A controller circuit configured to be connected to an array of memory cells, each of which has a threshold switch selector connected in series with a magnetoresistive random access memory (MRAM) device, the array comprising a first plurality of memory cells and a second plurality of memory cells, wherein each of the first plurality of memory cells is connected between a corresponding one of a first group of conductive lines and a corresponding one of a second group of conductive lines, and each of the second plurality of memory cells is connected between a corresponding one of a third group of conductive lines and a corresponding one of a second group of conductive lines, the controller circuit configured to: reading a selected memory cell of the first plurality of memory cells by biasing a corresponding one of the first set of conductive lines to a lower voltage than a corresponding one of the second set of conductive lines; reading a selected memory cell of the second plurality of memory cells by biasing a corresponding one of the third set of conductive lines to a lower voltage than a corresponding one of the second set of conductive lines; writing a selected one of the first plurality of memory cells from a first state to a second state by biasing a corresponding one of the first set of conductive lines to a lower voltage than a corresponding one of the second set of conductive lines; writing a selected one of the first plurality of memory cells from the second state to the first state by biasing a corresponding one of the first set of conductive lines to a higher voltage than a corresponding one of the second set of conductive lines; writing a selected memory cell of the second plurality of memory cells from the first state to the second state by biasing a corresponding one of the third set of conductive lines to a lower voltage than a corresponding one of the second set of conductive lines; as well as A selected memory cell of the second plurality of memory cells is written from the second state to the first state by biasing a corresponding one of the third set of conductive lines to a higher voltage than a corresponding one of the second set of conductive lines.

14. The apparatus of claim 13 , wherein the controller circuit comprises: a first set of drivers, each of the first set of drivers being configured to connect to a corresponding one of the first set of conductive lines; a second set of drivers, each of the second set of drivers being configured to connect to a corresponding one of the second set of conductive lines; and a third set of drivers, each of the third set of drivers being configured to be connected to a corresponding one of the third set of conductive lines, wherein, when reading a selected one of the first plurality of memory cells, a corresponding one of the first group of drivers connects a corresponding one of the first group of conductive lines to a low voltage level via an N-channel device, and a corresponding one of the second group of drivers connects a corresponding one of the second group of conductive lines to a high voltage level via a P-channel device, and Wherein, when reading a selected memory cell from the second plurality of memory cells, a corresponding one of the third group of drivers connects a corresponding one of the third group of conductive lines to the low voltage level through an N-channel device, and a corresponding one of the second group of drivers connects a corresponding one of the second group of conductive lines to the high voltage level through a P-channel device.

15. The apparatus according to claim 14, wherein: When reading a selected one of the first plurality of memory cells, a corresponding one of the second set of drivers is configured to drive a read current through the selected one of the first plurality of memory cells, and When reading a selected one of the second plurality of memory cells, a corresponding one of the second set of drivers is configured to drive the read current through the selected one of the second plurality of memory cells.

16. The apparatus of claim 14 , wherein the controller circuit is further configured to simultaneously read a selected memory cell of the first plurality of memory cells connected to a first conductive line in the second set of conductive lines and a selected memory cell of the second plurality of memory cells connected to the first conductive line in the second set of conductive lines.

17. The apparatus of claim 13, wherein the controller circuit is formed on a control die, the apparatus further comprising: A memory die includes the memory cell array, the memory die being formed separately from and bonded to the control die.

18. The apparatus of claim 13, further comprising the memory cell array, the memory cell array comprising: substrate; the first set of conductive lines extending in a first direction parallel to a surface of the substrate; the second set of conductive lines formed above the first set of conductive lines and extending in a second direction parallel to the surface of the substrate; the third group of conductive lines, the third group of conductive lines being formed above the second group of conductive lines and extending along the first direction; The first plurality of memory cells are each connected between a corresponding one of the first group of conductive lines and a corresponding one of the second group of conductive lines, the MRAM device of each of the first plurality of memory cells comprising: a reference layer having a fixed magnetic field polarity; and a free layer connected in series with the reference layer and having a programmable magnetic field polarity, wherein the free layer is formed below the reference layer; and The second plurality of memory cells are each connected between a corresponding one of the second group of conductive lines and a corresponding one of the third group of conductive lines, the MRAM device of each memory cell in the second plurality of memory cells comprising: a reference layer having a fixed magnetic field polarity; and A free layer is connected in series with the reference layer and has a programmable magnetic field polarity, wherein the free layer is formed above the reference layer.

19. The device of claim 18, wherein the second set of conductive lines is longer than both the first set of conductive lines and the third set of conductive lines.

20. The apparatus of claim 13, wherein the first state is a high resistance state and the second state is a low resistance state.

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