Semiconductor structure and method for forming the same

Abstract

The present application provides a semiconductor structure and a method for forming the same, the method comprising: providing a substrate, a stacked layer formed on the surface of the substrate, the surface of the stacked layer including a mask layer, the stacked layer including a channel layer and a sacrificial layer alternately distributed in sequence; etching the mask layer and the stacked layer to form a discrete first fin and a second fin; filling a first dielectric layer between the first fin and the second fin, and forming a second dielectric layer on the sidewalls of the first fin and the second fin; etching back the first dielectric layer until the surface of the first dielectric layer is lower than the top of the stacked layer, forming a first opening; etching the stacked layer and the mask layer on the sidewalls of the first opening to form a second opening; filling the second opening with a third dielectric layer, the first dielectric layer and the third dielectric layer forming a dielectric wall between the first fin and the second fin. The technical solution of the present application can increase the process window of the forksheet device when patterning N-type devices and P-type devices.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the advancement of miniaturization and integration, semiconductor devices have shifted from traditional planar structures to FinFET structures, and then to GAA (Gate-All-Around) structures, which use silicon nanosheets. Nanosheets, however, are manufactured using manufacturing processes that limit the spacing between n-type and p-type devices, resulting in the nanosheet structure consuming a significant amount of device space.

[0003] As a result, a new semiconductor device structure (forksheet) was proposed. The forksheet structure is considered to be a natural extension of the nanosheet structure and can be used for semiconductor device structures below 3nm. Compared with the nanosheet, the channel of the forksheet device is controlled by a fork-shaped gate structure. This is achieved by introducing a dielectric wall between the P-type device and the N-type device before gate patterning.

[0004] The dielectric walls proposed so far all have equal width structures at the top and bottom, and the size of the dielectric walls is very small. Therefore, when performing the subsequent patterning process of N-type devices and P-type devices, the process window is small and the error is large. Summary of the Invention

[0005] The technical problem solved by the present application is to provide a semiconductor structure and a method for forming the same, which can increase the process window of the Forksheet device when patterning N-type devices and P-type devices.

[0006] To solve the above technical problems, the present application provides a method for forming a semiconductor structure, comprising: providing a substrate, a stacked layer formed on the surface of the substrate, the surface of the stacked layer including a mask layer, the stacked layer including a channel layer and a sacrificial layer alternately distributed in sequence; etching the mask layer and the stacked layer to form a discrete first fin and a second fin; filling a first dielectric layer between the first fin and the second fin, and forming a second dielectric layer on the sidewalls of the first fin and the second fin; etching back the first dielectric layer until the surface of the first dielectric layer is lower than the top of the stacked layer to form a first opening; etching the stacked layer and the mask layer on the sidewalls of the first opening to form a second opening; filling the second opening with a third dielectric layer, the first dielectric layer and the third dielectric layer constituting a dielectric wall between the first fin and the second fin.

[0007] In the embodiment of the present application, the channel layer is made of the same material as the substrate, but different from the material of the sacrificial layer.

[0008] In an embodiment of the present application, the materials of the substrate, the channel layer and the sacrificial layer include at least one of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum arsenide, indium gallium arsenide, gallium antimony phosphide or indium phosphide.

[0009] In an embodiment of the present application, the process of forming discrete first fins and second fins includes: etching the mask layer and the stack layer to form a plurality of discrete fin units; etching the mask layer and the stack layer of the fin unit to form discrete first fins and second fins.

[0010] In an embodiment of the present application, the process of filling the first dielectric layer between the first fin and the second fin includes: depositing a first dielectric material on the surface, sidewalls, and between the first fin and the second fin; removing the first dielectric material and retaining only the first dielectric material between the first fin and the second fin to form a first dielectric layer.

[0011] In an embodiment of the present application, the process of forming the second dielectric layer includes: depositing a second dielectric material on the surface, sidewalls and surface of the first fin and the second fin and the first dielectric layer; removing the second dielectric material and retaining only the second dielectric material on the sidewalls of the first fin and the second fin to form a second dielectric layer.

[0012] In the embodiment of the present application, the first dielectric layer is made of a different material from the second dielectric layer, but is made of the same material as the third dielectric layer.

[0013] In an embodiment of the present application, materials of the first dielectric layer and the third dielectric layer include silicon nitride, and material of the second dielectric layer includes silicon dioxide.

[0014] In the embodiment of the present application, the cross-section of the dielectric wall is T-shaped.

[0015] In an embodiment of the present application, after filling the second opening with the third dielectric layer, the process further includes: etching the second dielectric layer so that the surface of the second dielectric layer is no higher than the top of the bottommost channel layer; removing the mask layer; and removing the sacrificial layer of the first fin and the second fin to form channel layers spaced apart from each other.

[0016] In an embodiment of the present application, after removing the sacrificial layer, it also includes: forming a dummy gate structure, the dummy gate structure covering the channel layer of the first fin and the second fin, part of the sidewall and surface of the dielectric wall and part of the surface of the second dielectric layer, and filling part of the gap between the channel layers; using an epitaxial process to form a source and a drain covering the channel layer on both sides of the dummy gate structure; forming a fourth dielectric layer on both sides of the dummy gate structure, the fourth dielectric layer covering the source and the drain, the remaining sidewalls and surfaces of the dielectric wall and the remaining surface of the second dielectric layer.

[0017] In an embodiment of the present application, after forming the fourth dielectric layer, it also includes: removing the dummy gate structure and forming a first metal gate at a corresponding position; etching the first metal gate until the surface of the first metal gate is lower than the top of the dielectric wall; forming a photoresist layer on the surface of the first metal gate and a portion of the dielectric wall on the side where the first fin is located; using the photoresist layer as a mask, etching the first metal gate on the side where the second fin is located, forming a second metal gate at a corresponding position, and removing the photoresist layer.

[0018] In an embodiment of the present application, the first fin is used to manufacture NMOS, and the second fin is used to manufacture PMOS.

[0019] The present application also provides a semiconductor structure, comprising: a substrate; a dielectric wall, comprising a first dielectric layer and a third dielectric layer, wherein the first dielectric layer is located on a surface of the substrate, the third dielectric layer is located on a surface of the first dielectric layer, and the width of the third dielectric layer is greater than the width of the first dielectric layer; a first channel layer group and a second channel layer group, respectively located on two side walls of the first dielectric layer, wherein the first channel group and the second channel group each include a plurality of channel layers spaced apart from each other, and the bottommost channel layer is located on a surface of the substrate;

[0020] a first metal gate, wherein a surface of the first metal gate is lower than a top of the dielectric wall, covers the channel layer of the first channel layer group and a portion of the sidewall of the dielectric wall and a portion of the surface of the second dielectric layer, and fills a portion of the gap between the channel layers of the first channel layer group;

[0021] a second metal gate, wherein a surface of the second metal gate is lower than a top of the dielectric wall, covers the channel layer of the second channel layer group and a portion of the sidewall of the dielectric wall and a portion of the surface of the second dielectric layer, and fills a portion of the gap between the channel layers of the second channel layer group;

[0022] a source electrode, covering the channel layer on one side of the first metal gate and the second metal gate;

[0023] a drain electrode, covering the channel layer on the other side of the first metal gate and the second metal gate;

[0024] The fourth dielectric layer covers the source and drain, the remaining sidewalls and surfaces of the dielectric wall, and the remaining surface of the second dielectric layer.

[0025] The present application also provides another semiconductor structure, comprising: a substrate; a dielectric wall, comprising a first dielectric layer and a third dielectric layer, wherein the first dielectric layer is located on the surface of the substrate, the third dielectric layer is located on the surface of the first dielectric layer, and the cross-section of the dielectric wall is T-shaped; a first channel layer group and a second channel layer group, respectively located on the two side walls of the first dielectric layer, wherein the first channel layer group and the second channel layer group each include a plurality of channel layers spaced apart from each other, and the bottom channel layer is located on the surface of the substrate; a first metal gate, wherein the surface of the first metal gate is lower than the top of the dielectric wall, covering the first metal gate; The channel layer of the first channel layer group and part of the sidewalls of the dielectric wall and part of the surface of the second dielectric layer, and fill part of the gap between the channel layers of the first channel layer group; a second metal gate, the surface of the second metal gate is lower than the top of the dielectric wall, covers the channel layer of the second channel layer group and part of the sidewalls of the dielectric wall and part of the surface of the second dielectric layer, and fills part of the gap between the channel layers of the second channel layer group; a source electrode covers the channel layer on one side of the first metal gate and the second metal gate; and a drain electrode covers the channel layer on the other side of the first metal gate and the second metal gate;

[0026] The fourth dielectric layer covers the source and drain, the remaining sidewalls and surfaces of the dielectric wall, and the remaining surface of the second dielectric layer.

[0027] In an embodiment of the present application, the first channel layer group is used to manufacture an N-type device, and the second channel layer group is used to manufacture a P-type device.

[0028] Compared with the prior art, the method for forming a semiconductor structure of the technical solution of the present application has the following beneficial effects:

[0029] A forksheet device can be efficiently manufactured; a dielectric wall that is wide at the top and narrow at the bottom is formed between an N-type device and a P-type device, and the dielectric wall is composed of a first dielectric layer and a third dielectric layer. The wider third dielectric layer can increase the process window of the forksheet device when patterning the N-type device and the P-type device, and the narrower first dielectric layer can ensure that the miniaturization and integration of the device are not affected. Therefore, when the forksheet device is manufactured using the technical solution of the present application, the process error can be greatly reduced, and the performance and yield of the forksheet device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The following figures describe in detail exemplary embodiments disclosed in this application. Identical reference numerals denote similar structures in several views of the drawings. Those skilled in the art will appreciate that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description purposes only and are not intended to limit the scope of this application. Other embodiments may also achieve the same inventive intent as described in this application. It should be understood that the drawings are not drawn to scale. Among them:

[0031] Figure 1 It is a structural diagram of a Forksheet device;

[0032] Figure 2 A schematic flow chart of a method for forming a semiconductor structure according to an embodiment of the present application;

[0033] Figures 3 to 21 Schematic diagram of the structure corresponding to each step of the method for forming a semiconductor structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0034] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content of this application. Various local modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but is intended to be of the widest scope consistent with the claims.

[0035] refer to Figure 1 In existing forksheet devices, a dielectric wall 30 of equal width is introduced between the N-type device 10 and the P-type device 20 for isolation. When forming the forksheet device, the same type of devices are first formed on both sides of the dielectric wall 30, for example, the N-type device 10 is formed. Then, the N-type device on one side of the dielectric wall 30 is etched, for example, the N-type device on the right side of the dielectric wall 30 is etched. When etching the N-type device on the right side of the dielectric wall 30, it is necessary to cover the surface of the N-type device on the left side of the dielectric wall 30 and part of the dielectric wall surface with a photoresist layer to prevent damage to the N-type device on the left side of the dielectric wall 30 when etching the N-type device on the right side. However, due to the miniaturization requirements of the device, the width of the dielectric wall 30 is very narrow, resulting in a small process window when forming the photoresist layer, which is prone to offset. The formed photoresist layer may partially cover the surface of the N-type device on the right side of the dielectric wall 30, resulting in incomplete etching of the N-type device on the right side of the dielectric wall 30. After the P-type device is formed on the right side of the dielectric wall 30, some incompletely etched N-type devices still remain on the right side of the dielectric wall 30, resulting in device failure.

[0036] In view of this, the technical solution of the present application improves the structure of the dielectric wall to meet the process window requirements of the Forksheet when patterning P-type devices and N-type devices.

[0037] The technical solution of this application is described in detail below with reference to the embodiments and drawings.

[0038] refer to Figure 2 , an embodiment of the present application provides a method for forming a semiconductor structure, which mainly includes the following steps:

[0039] Step S1: providing a substrate, wherein a stacked layer is formed on the surface of the substrate, the surface of the stacked layer includes a mask layer, and the stacked layer includes a channel layer and a sacrificial layer that are alternately distributed in sequence;

[0040] Step S2: etching the mask layer and the stacked layer to form a separate first fin and a second fin;

[0041] Step S3: filling a first dielectric layer between the first fin and the second fin, and forming a second dielectric layer on the sidewalls of the first fin and the second fin;

[0042] Step S4: etching back the first dielectric layer until the surface of the first dielectric layer is lower than the top of the stacked layer, thereby forming a first opening;

[0043] Step S5: etching the stacked layer and the mask layer on the sidewall of the first opening to form a second opening;

[0044] Step S6: filling the second opening with a third dielectric layer, wherein the first dielectric layer and the third dielectric layer form a dielectric wall between the first fin and the second fin.

[0045] Combine Figure 2 and Figure 3 , providing a substrate 100. The substrate 100 may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon-on-insulator (SiO2) substrate, or a germanium-on-insulator (GeO2) substrate. It may also be a substrate comprising other elemental semiconductors or compound semiconductors, such as silicon carbide, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum indium arsenide, indium gallium arsenide, antimony gallium phosphide, or indium phosphide.

[0046] A stacked layer 110 is formed on the surface of the substrate 100, and the stacked layer 110 includes a channel layer 111 and a sacrificial layer 112 that are alternately distributed in sequence. It should be noted that the channel layer 111 at the bottom layer can be a part of the substrate 100, or can be formed by deposition alone. In the embodiment of the present application, the channel layer 111 is a part of the substrate 100, thus eliminating the need for an additional deposition process. Figure 3 In order to facilitate understanding of the structure of the bottom channel layer 111 , the substrate 100 and the bottom channel layer 111 are distinguished.

[0047] The sacrificial layer 112 is made of a different material from the channel layer 111 and the substrate 100 to improve the etching selectivity when the sacrificial layer 112 is subsequently removed. The channel layer 111 and the substrate 100 may be made of the same material. For example, the channel layer 111 and the sacrificial layer 112 may be made of at least one of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum indium arsenide, indium gallium arsenide, antimony gallium phosphide, or indium phosphide.

[0048] Since the thickness and number of the channel layer 111 serving as the channel determine the electrical characteristics, integration, and performance of the device, the thickness requirements for the channel layer 111 are relatively strict. It is necessary to avoid excessive surface scattering in the channel region while also enabling the device to operate normally. The effective number of the channel layer 111 serving as the channel can determine the width of the gate structure. The more effective the number, the greater the driving current capacity of the formed device by increasing the gate width. Therefore, the stacked layer 110 can be formed by an atomic layer deposition (ALD) process (if the bottommost channel layer 111 is part of the substrate 100, the stacked layer 110 other than the bottommost channel layer 111 is formed by an ALD process). When the stacked layer 110 is formed by the ALD process, the thickness and surface uniformity of each layer can be precisely controlled, thereby achieving the integration of the stacked layer 110 with the maximum height, avoiding the collapse of the stacked layer 110, and thus ensuring device performance.

[0049] There are no specific requirements for the number and thickness of the channel layer 111 and the sacrificial layer 112, and they are determined based on actual conditions. This embodiment of the present application uses three channel layers 111 and three sacrificial layers 112 as an example. Because the wider portion of the dielectric wall is located in the topmost sacrificial layer 112, the topmost sacrificial layer 112 is thicker than the other sacrificial layers 112.

[0050] The stacked layer 110 further includes a mask layer 120 on its surface. The mask layer 120 further includes a patterned photoresist layer (not shown). The material of the mask layer 120 may include silicon nitride, silicon oxynitride, or the like. The patterned photoresist layer may be a single-layer structure or a multi-layer structure comprising an advanced patterning film (APF, not shown), a dielectric anti-reflective layer (DARC, not shown), a bottom anti-reflective layer (BARC, not shown), and a photoresist layer (not shown) sequentially located on the surface of the mask layer 120. The patterned photoresist layer can define the size, shape, and distribution of the fins and the grooves between the fins.

[0051] In step S2 , the mask layer 120 and the stacked layer 110 are etched to form separate first fins 131 and second fins 132 .

[0052] refer to Figure 4 In the embodiment of the present application, the self-aligned double patterning process (SADP) technique can be used to etch the mask layer 120 and the stacked layer 110 to the surface of the substrate 100 (if the bottom channel layer 111 is part of the substrate 100, the mask layer 120 and the stacked layer 110 are etched into the substrate 100) to form a plurality of fin units 130 and a plurality of grooves 130a on the substrate 100. The figure shows three fin units 130 as an example. The fin units 130 protrude above the substrate 100 and can be shaped into strips, ribbons, or rectangular blocks, while the grooves 130a are located between adjacent fin units 130.

[0053] The following processes are described by taking one of the fin units 130 as an example.

[0054] refer to Figure 5 , the mask layer 120 and the stacked layer 110 of the fin unit 130 are etched to form a discrete first fin 131 and a second fin 132, as well as a trench 130b located between the first fin 131 and the second fin 132. Then, the patterned photoresist layer is removed. The formed first fin 131 and second fin 132 are used to fabricate different types of devices. For example, the first fin 131 is used to fabricate an N-type device (e.g., NMOS), and the second fin 132 is used to fabricate a P-type device (e.g., PMOS).

[0055] In some embodiments, a plasma dry etching process can be used to etch the mask layer 120 and the stacked layer 110, with hydrogen chloride gas used as the main etching gas, and chlorine, argon or helium can be added as a carrier gas. The etching process requires precise control of the etching time and the etching stop point so that the etching stops on the surface of the substrate 100 or in the substrate 100.

[0056] Next, step S3 is performed to fill the first dielectric layer 141 between the first fin 131 and the second fin 132 , and to form the second dielectric layer 142 on the sidewalls of the first fin 131 and the second fin 132 .

[0057] refer to Figure 6A first dielectric material is deposited on the surfaces, sidewalls, and between the first fin 131 and the second fin 132 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or a similar process. The first dielectric material is then removed, leaving only the first dielectric material between the first fin 131 and the second fin 132 to form a first dielectric layer 141. The process for removing the first dielectric material can employ an anisotropic dry etching process (e.g., plasma etching, atomic layer etching). The top surface of the formed first dielectric layer 141 is coplanar with the top surface of the mask layer 120.

[0058] refer to Figure 7 , forming a second dielectric layer 142 on the sidewalls of the first fin 131 and the second fin 132. First, a second dielectric material can be deposited on the surfaces and sidewalls of the first fin 131 and the second fin 132, and on the surface of the first dielectric layer 141, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, or a similar process. Then, excess second dielectric material is removed by a grinding process, leaving only the second dielectric material on the sidewalls of the first fin 131 and the second fin 132, to form the second dielectric layer 142. The grinding process can be chemical mechanical grinding, physical mechanical grinding, or the like.

[0059] To improve the etching selectivity when etching the second dielectric layer 142 , the first dielectric layer 141 and the second dielectric layer 142 may be made of different materials. For example, the first dielectric layer 141 may include silicon nitride, and the second dielectric layer 142 may include silicon dioxide.

[0060] exist Figure 6 and Figure 7 The structure of the first dielectric layer 141 formed in the prior art is the dielectric wall structure between the N-type device and the P-type device. Due to the narrow width of the first dielectric layer 141, the subsequent process window is small when patterning the N-type device or the P-type device, resulting in large process errors. Therefore, the following improvements are made in the embodiments of the present application.

[0061] refer to Figure 8 , etch back the first dielectric layer 141 until the surface of the first dielectric layer 141 is lower than the top of the stacked layer 110 (i.e., the top of the topmost sacrificial layer 112), forming a first opening 151. The back etching can be done by dry etching or wet etching. The height of the first opening 151 depends on the third dielectric layer 143 to be formed later (refer to Figure 10 ) thickness.

[0062] refer to Figure 9, the stacked layer 110 (i.e., the topmost sacrificial layer 112) and the mask layer 120 on the sidewalls of the first opening 151 are etched to form a second opening 152. In other words, the width of the second opening 152 formed by lateral expansion of the first opening 151 is greater than the width of the first opening 151. There is no specific requirement for the width of the second opening 152, which is determined based on the process window required for patterning N-type and P-type devices. The process for etching the stacked layer 110 and the mask layer 120 can be a dry etching process.

[0063] refer to Figure 10 , filling the second opening 152 with a third dielectric layer 143. First, a chemical vapor deposition process or a physical vapor deposition process can be used to deposit a third dielectric material on the surfaces of the second dielectric layer 142, the mask layer 120, and the second opening 152. Then, a chemical mechanical polishing process or a physical mechanical polishing process is used to polish the third dielectric material until the surfaces of the second dielectric layer 142 and the mask layer 120 are exposed. The surface of the formed third dielectric layer 143 is coplanar with the surfaces of the second dielectric layer 142 and the mask layer 120. The material of the third dielectric layer 143 can be the same as that of the first dielectric layer 141. For example, the material of the third dielectric layer 143 can include silicon nitride.

[0064] Since the width of the second opening 152 is greater than the width of the first opening 151, the width of the third dielectric layer 143 formed in the second opening 152 is greater than the width of the first dielectric layer 141. The third dielectric layer 143 and the first dielectric layer 141 constitute a dielectric wall 140 with a wide top and narrow bottom structure. In the embodiment of the present application, the cross-section of the dielectric wall 140 is T-shaped.

[0065] The dielectric wall fabricated using the formation method of the embodiment of the present application has a wider upper portion, while the lower portion maintains its original size, or can even be reduced in size. This allows for increasing the process window for patterning N-type and P-type devices in the forksheet device without affecting the miniaturization and integration of the device. Therefore, when fabricating a forksheet device using the formation method of the embodiment of the present application, process errors can be significantly reduced, improving product performance and yield.

[0066] After forming the dielectric wall 140, the following processes may be performed:

[0067] refer to Figure 11The second dielectric layer 142 is etched so that the surface of the second dielectric layer 142 is no higher than the top of the bottommost channel layer 111, thereby exposing the sidewalls of all channel layers 111 and sacrificial layers 112. This facilitates the subsequent removal of the sacrificial layer 112 and also facilitates the subsequent formation of a dummy gate structure that wraps around the channel layer 111. The second dielectric layer 142 can be etched using either a dry or wet etching process. The mask layer 120 is removed to expose the sacrificial layer 112, facilitating its removal.

[0068] refer to Figure 12 , the sacrificial layer 112 of the first fin 131 and the second fin 132 is removed to form channel layers 111 spaced apart from each other. The channel layer 111 on the side of the first fin 131 constitutes a first channel layer group 111a, and the channel layer 111 on the side of the second fin 132 constitutes a second channel layer group 111b. The first channel layer group 111a and the second channel layer group 111b are symmetrically distributed on both side walls of the first dielectric layer 141.

[0069] refer to Figure 13 and Figure 14 , Figure 14 for Figure 13 Cross-sectional view at AA. After removing the sacrificial layer 112, a dummy gate structure 160 is formed. The dummy gate structure 160 covers the channel layer 111 of the first fin 131 and the second fin 132, part of the sidewalls and surface of the dielectric wall 140, and part of the surface of the second dielectric layer 142, and fills part of the gap between the channel layers 111.

[0070] refer to Figure 15 A source 210 and a drain 220 covering the channel layer are respectively formed on both sides of the dummy gate structure 160 using an epitaxial process.

[0071] refer to Figure 16 A fourth dielectric layer 170 is formed on both sides of the dummy gate structure 160 , and the fourth dielectric layer 170 covers the source 210 and the drain 220 , the remaining sidewalls and surfaces of the dielectric wall 140 , and the remaining surfaces of the second dielectric layer 142 .

[0072] refer to Figure 17 and Figure 18 , Figure 18 for Figure 17 Cross-sectional view at position BB: The dummy gate structure 160 is removed, and a first metal gate 180 is formed at the corresponding position.

[0073] refer to Figure 19 and Figure 20The first metal gate 180 is etched until the surface of the first metal gate 180 is lower than the top of the dielectric wall 140. A photoresist layer 190 is formed on the surface of the first metal gate 180 and a portion of the dielectric wall 140 on the side where the first fin 131 is located. Using the photoresist layer 190 as a mask, the first metal gate 180 on the side where the second fin 132 is located is etched to form a second metal gate 200 at the corresponding position, and the photoresist layer 190 is removed.

[0074] Continue to refer Figure 20 and Figure 21 , Figure 20 Bit Figure 21 Cross-sectional view at BB. The embodiment of the present application also provides a semiconductor structure, which includes: a substrate 100; a dielectric wall 140, including a first dielectric layer 141 and a third dielectric layer 143, wherein the first dielectric layer 141 is located on the surface of the substrate 100, and the third dielectric layer 143 is located on the surface of the first dielectric layer 141, and the width of the third dielectric layer 143 is greater than the width of the first dielectric layer 141; a first channel layer group 111a and a second channel layer group 111b are respectively located on the two side walls of the first dielectric layer 141, and the first channel layer group 111a and the second channel group 111b each include a plurality of channel layers 111 spaced apart from each other, and the bottom channel layer 111 is located on the surface of the substrate 100; a first metal gate 180, the The surface of the first metal gate 180 is lower than the top of the dielectric wall 140, covering the channel layer of the first channel layer group 111a and part of the sidewall of the dielectric wall 140 and part of the surface of the second dielectric layer 142, and filling part of the gap between the channel layers of the first channel layer group 111a; the surface of the second metal gate 200 is lower than the top of the dielectric wall 140, covering the channel layer of the second channel layer group 111b and part of the sidewall of the dielectric wall 140 and part of the surface of the second dielectric layer 142, and filling part of the gap between the channel layers of the second channel layer group 111b; the source 210 covers the channel layer on one side of the first metal gate 180 and the second metal gate 200; the drain (refer to Figure 15 ), covering the channel layer on the other side of the first metal gate 180 and the second metal gate 200; a fourth dielectric layer 170, the fourth dielectric layer 170 covering the source 210 and the drain 220, the remaining sidewalls and surfaces of the dielectric wall 140 and the remaining surface of the second dielectric layer 142.

[0075] In some embodiments of the present application, the cross-sectional shape of the dielectric wall 140 is T-shaped, and the device types of the first channel layer group 111a and the second channel group 111b are different. For example, the first channel layer group 111a is used to make N-type devices (such as NMOS), and the second channel group 111b is used to make P-type devices (such as PMOS).

[0076] The semiconductor structures of various embodiments of the present application include a dielectric wall 140 formed of a first dielectric layer 141 and a third dielectric layer 143, wherein the width of the third dielectric layer 143 is greater than that of the first dielectric layer 141, and the width of the first dielectric layer 141 is less than or equal to the width of a dielectric wall in the prior art. Therefore, the semiconductor structures of various embodiments of the present application can increase the process window of the forksheet device when patterning N-type and P-type devices, reduce process errors, and significantly improve product performance and yield, while meeting device miniaturization and integration requirements.

[0077] In summary, after reading the contents of this application, those skilled in the art will understand that the foregoing contents are presented by way of example only and are not intended to be limiting. Although not expressly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. Such changes, improvements, and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0078] It should be understood that the term "and / or" used in this embodiment includes any and all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present.

[0079] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" indicates the absence of intervening elements. It should also be understood that the terms "comprising," "including," "include," or "comprising," when used in this specification, indicate the presence of recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0080] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the present application, the first element in some embodiments may be referred to as the second element in other embodiments. The same reference numerals or the same reference designators represent the same elements throughout the specification.

[0081] In addition, this specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein a stacked layer is formed on a surface of the substrate, the surface of the stacked layer includes a mask layer, and the stacked layer includes a channel layer and a sacrificial layer that are alternately distributed in sequence; Etching the mask layer and the stacked layer to form a discrete first fin and a second fin; Filling a first dielectric layer between the first fin and the second fin, and forming a second dielectric layer on the sidewalls of the first fin and the second fin; Etching back the first dielectric layer until the surface of the first dielectric layer is lower than the top of the stacked layer to form a first opening; Etching the stacked layer and the mask layer on the sidewall of the first opening to form a second opening; A third dielectric layer is filled in the second opening, and the first dielectric layer and the third dielectric layer form a dielectric wall between the first fin and the second fin.

2. The method for forming a semiconductor structure according to claim 1, wherein: The channel layer is made of the same material as the substrate but different from the material of the sacrificial layer.

3. The method for forming a semiconductor structure according to claim 2, wherein: The materials of the substrate, the channel layer and the sacrificial layer include at least one of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum indium arsenide, indium gallium arsenide, gallium antimony phosphide or indium phosphide.

4. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the separate first fin and second fin includes: Etching the mask layer and the stack layer to form a plurality of discrete fin units; The mask layer and the stacked layer of the fin unit are etched to form a separate first fin and a second fin.

5. The method for forming a semiconductor structure according to claim 1, wherein: The process of filling the first dielectric layer between the first fin and the second fin includes: Depositing a first dielectric material on the surface, sidewall, and between the first fin and the second fin; The first dielectric material is removed, and only the first dielectric material between the first fin and the second fin is retained to form a first dielectric layer.

6. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the second dielectric layer includes: Depositing a second dielectric material on the surface and sidewall of the first fin and the second fin and the surface of the first dielectric layer; The second dielectric material is removed, and only the second dielectric material on the sidewalls of the first fin and the second fin is retained to form a second dielectric layer.

7. The method for forming a semiconductor structure according to claim 1, wherein: The first dielectric layer is made of a different material from the second dielectric layer, but is made of the same material as the third dielectric layer.

8. The method for forming a semiconductor structure according to claim 7, wherein: The materials of the first dielectric layer and the third dielectric layer include silicon nitride, and the material of the second dielectric layer includes silicon dioxide.

9. The method for forming a semiconductor structure according to claim 1, wherein: The cross-section of the dielectric wall is T-shaped.

10. The method for forming a semiconductor structure according to claim 1, wherein: After the second opening is filled with the third dielectric layer, the method further includes: Etching the second dielectric layer so that the surface of the second dielectric layer is no higher than the top of the bottommost channel layer; removing the mask layer; and, The sacrificial layers of the first fins and the second fins are removed to form channel layers that are spaced apart from each other.

11. The method for forming a semiconductor structure according to claim 10, wherein: After removing the sacrificial layer, the method further includes: forming a dummy gate structure, wherein the dummy gate structure covers the channel layers of the first and second fins, part of the sidewalls and the surface of the dielectric wall, and part of the surface of the second dielectric layer, and fills part of the gap between the channel layers; forming a source electrode and a drain electrode covering the channel layer on both sides of the dummy gate structure by using an epitaxial process; A fourth dielectric layer is formed on both sides of the dummy gate structure, and the fourth dielectric layer covers the source and drain, the remaining sidewalls and surfaces of the dielectric wall, and the remaining surface of the second dielectric layer.

12. The method for forming a semiconductor structure according to claim 11, wherein: After forming the fourth dielectric layer, the method further includes: removing the dummy gate structure and forming a first metal gate at a corresponding position; Etching the first metal gate until the surface of the first metal gate is lower than the top of the dielectric wall; forming a photoresist layer on the surface of the first metal gate and a portion of the dielectric wall on the side where the first fin is located; Using the photoresist layer as a mask, the first metal gate on the side where the second fin is located is etched to form a second metal gate at a corresponding position, and then the photoresist layer is removed.

13. The method for forming a semiconductor structure according to claim 1, wherein: The first fin is used to make an N-type device, and the second fin is used to make a P-type device.

14. A semiconductor structure, characterized in that include: substrate; a dielectric wall comprising a first dielectric layer and a third dielectric layer, wherein the first dielectric layer is located on the surface of the substrate, the third dielectric layer is located on the surface of the first dielectric layer, and the width of the third dielectric layer is greater than that of the first dielectric layer; A first channel layer group and a second channel layer group are respectively located on both side walls of the first dielectric layer, and each of the first channel layer group and the second channel layer group includes a plurality of channel layers spaced apart from each other, and the bottom channel layer is located on the surface of the substrate; a second dielectric layer, located on a sidewall of the bottommost channel layer and having a surface no higher than a top of the bottommost channel layer; a first metal gate, wherein a surface of the first metal gate is lower than a top of the dielectric wall, covers the channel layer of the first channel layer group and a portion of the sidewall of the dielectric wall and a portion of the surface of the second dielectric layer, and fills a portion of the gap between the channel layers of the first channel layer group; a second metal gate, wherein a surface of the second metal gate is lower than a top of the dielectric wall, covers the channel layer of the second channel layer group and a portion of the sidewall of the dielectric wall and a portion of the surface of the second dielectric layer, and fills a portion of the gap between the channel layers of the second channel layer group; a source electrode, covering the channel layer on one side of the first metal gate and the second metal gate; a drain electrode, covering the channel layer on the other side of the first metal gate and the second metal gate; The fourth dielectric layer covers the source and drain, the remaining sidewalls and surfaces of the dielectric wall, and the remaining surface of the second dielectric layer.

15. The semiconductor structure according to claim 14, wherein: The first channel layer group is used to manufacture N-type devices, and the second channel layer group is used to manufacture P-type devices.

16. A semiconductor structure, characterized in that include: substrate; a dielectric wall comprising a first dielectric layer and a third dielectric layer, wherein the first dielectric layer is located on the surface of the substrate, the third dielectric layer is located on the surface of the first dielectric layer, and the cross-section of the dielectric wall is T-shaped; A first channel layer group and a second channel layer group are respectively located on both side walls of the first dielectric layer, and each of the first channel layer group and the second channel layer group includes a plurality of channel layers spaced apart from each other, and the bottom channel layer is located on the surface of the substrate; a second dielectric layer, located on a sidewall of the bottommost channel layer and having a surface no higher than a top of the bottommost channel layer; a first metal gate, wherein a surface of the first metal gate is lower than a top of the dielectric wall, covers the channel layer of the first channel layer group and a portion of the sidewall of the dielectric wall and a portion of the surface of the second dielectric layer, and fills a portion of the gap between the channel layers of the first channel layer group; a second metal gate, wherein a surface of the second metal gate is lower than a top of the dielectric wall, covers the channel layer of the second channel layer group and a portion of the sidewall of the dielectric wall and a portion of the surface of the second dielectric layer, and fills a portion of the gap between the channel layers of the second channel layer group; a source electrode, covering the channel layer on one side of the first metal gate and the second metal gate; a drain electrode, covering the channel layer on the other side of the first metal gate and the second metal gate; The fourth dielectric layer covers the source and drain, the remaining sidewalls and surfaces of the dielectric wall, and the remaining surface of the second dielectric layer.

17. The semiconductor structure according to claim 16, wherein: The first channel layer group is used to manufacture N-type devices, and the second channel layer group is used to manufacture P-type devices.

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