An integrated clamping diode structure and formation method

Abstract

The present invention discloses an integrated clamping diode structure and a forming method thereof. The structure includes: a chip body, a deep N-well layer, an N-type heavily doped buried layer, and a P-type heavily doped layer; the deep N-well layer, the N-type heavily doped buried layer, and the P-type heavily doped layer are all sequentially disposed inside the chip body; by setting the breakdown voltage and the clamping voltage of the clamping protection device, the present invention enables the surface functional circuit to operate normally during normal chip operation, and only triggers and clamps when the overvoltage exceeds a certain threshold of the maximum operating voltage, forming ESD and EOS protection, thereby solving the technical problem in the prior art that the single-chip integration of ESD and EOS protection will greatly increase the extra area of the chip.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and more specifically to an integrated clamped diode structure and a forming method thereof. Background Art

[0002] Currently, electrostatic discharge (ESD) and electrical overstress (EOS) are the main causes of integrated circuit chip failures. Both ESD and EOS phenomena belong to short-term overloads. When the chip pins are impacted by a spike voltage or spike current within a short period of time, if the energy exceeds the maximum rated value, it will cause damage or even failure to the function or reliability of the chip.

[0003] However, the current main method for ESD and EOS protection of chips is to add discrete ESD / surge protection devices, such as transient voltage suppression diodes (TVS), externally to the chips on the system circuit board, and then combine with the chip-level ESD path of the chip itself for protection. The external discrete protection device is the core clamping protection device for realizing ESD / EOS protection, and it is required to have a strong clamping voltage and current discharging ability. In the prior art, one type of idea is to additionally add ESD and EOS detection circuits and silicon surface power devices such as high-voltage MOS transistors in the chip circuit, and use the detection circuit module to control the turning on of the clamping protection MOS power transistor to achieve voltage clamping and discharge the large pulsed current of system ESD and EOS, thereby protecting the integrated circuit pins. The level of the maximum current for voltage clamping is proportional to the area of the clamping protection MOS power transistor. To achieve a large current discharging ability required for a higher ESD and EOS protection level, the clamping protection MOS power transistor can only increase its size to achieve this. Coupled with the ESD and EOS detection circuits, it occupies a large amount of chip area, reducing the area efficiency of the effective functional modules of the chip and greatly increasing the chip cost.

[0004] Therefore, how to provide a clamped protection diode structure that can solve the above problems is an urgent problem for those skilled in the art. Summary of the Invention

[0005] In view of this, the present invention provides an integrated clamped diode structure and a forming method thereof. By setting the breakdown voltage and clamping voltage of the clamping protection device, it does not affect the normal operation of the surface functional circuit when the chip is working normally, and only triggers and clamps when the overvoltage exceeds a certain threshold of the maximum operating voltage, forming ESD and EOS protection, thereby solving the technical problem that single-chip integration of ESD and EOS protection in the prior art will greatly increase the extra area of the chip.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] An integrated clamping diode structure, comprising: a chip body, a deep N-well layer, an N-type heavily doped buried layer, and a P-type heavily doped silicon substrate layer;

[0008] The deep N-well layer, the N-type heavily doped buried layer, and the P-type heavily doped silicon substrate layer are all sequentially disposed inside the chip body.

[0009] Preferably, inside the chip body, there are sequentially disposed: a lightly doped silicon epitaxial layer, a P-type heavily doped layer, and a buffer epitaxial layer. The deep N-well layer is located within the lightly doped silicon epitaxial layer, the N-type heavily doped buried layer is located between the lightly doped silicon epitaxial layer and the buffer epitaxial layer, and the P-type heavily doped layer is located within the buffer epitaxial layer.

[0010] Preferably, it further includes: a back gold terminal, and the back gold terminal is disposed on one side outside the chip body.

[0011] Preferably, it further includes: a first device, a second device, a third device, and a fourth device. The first device, the second device, the third device, and the fourth device are all disposed on one side outside the chip body.

[0012] Preferably, it further includes: a CMOS device, and the CMOS device is disposed inside the fourth device.

[0013] Preferably, it further includes: polysilicon resistors, and a plurality of the polysilicon resistors are disposed inside the third device and the fourth device.

[0014] Furthermore, the present invention also provides a method for forming an integrated clamping diode structure, comprising:

[0015] S1: Form the deep N-well layer inside the chip body, and sequentially add the N-type heavily doped buried layer and the P-type heavily doped silicon substrate layer below the deep N-well layer. The N-type heavily doped buried layer and the P-type heavily doped layer form a PN junction;

[0016] S2: Form the back gold terminal on one side outside the chip body to lead out the anode, and the cathode is led out from the deep N-well layer to complete the preparation of the integrated clamping diode structure.

[0017] Through the above technical solutions, it can be seen that compared with the prior art, the present invention discloses an integrated clamping diode structure and formation method. It does not need to be achieved by adding additional silicon surface devices and thus increasing the chip area as in the prior art. This patent forms a parasitic clamping protection diode in the silicon body between the isolation of the chip functional module itself and the substrate by adding a P-type heavy doping process level. It is particularly suitable for chips with large areas of chip circuit isolation modules. This parasitic surge clamping diode can provide very considerable system ESD and EOS surge protection functions without occupying surface area. The technical solution proposed by the present invention only forms an internal surge protection diode under the isolation of the chip's own circuit module by adding one process level. It not only saves transient voltage suppression diodes outside the chip and saves system board area, but also does not increase the chip area itself. It is a very efficient and low-cost innovative solution to solve ESD and EOS integrated protection, which is very suitable for application in current mobile terminal products. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0019] Figure 1 A cross-sectional view of an integrated clamping diode structure provided by the present invention;

[0020] Figure 2 A schematic top view of an integrated clamping diode structure provided by the present invention;

[0021] Figure 3 A schematic top view of an existing structure provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0023] See attached Figure 1-2 As shown, an embodiment of the present invention discloses an integrated clamping diode structure, comprising: a chip body 1, a deep N-well layer 9, an N-type heavily doped buried layer 10, and a P-type heavily doped silicon substrate layer 15;

[0024] The deep N-well layer 9, the N-type heavily doped buried layer 10, and the P-type heavily doped silicon substrate layer 15 are sequentially disposed inside the chip body 1.

[0025] In a specific embodiment, inside the chip body 1, there are sequentially disposed: a lightly doped silicon epitaxial layer 11, a P-type heavily doped layer 16, and a buffer epitaxial layer 14. The deep N-well layer 9 is located within the lightly doped silicon epitaxial layer 11, the N-type heavily doped buried layer 10 is located between the lightly doped silicon epitaxial layer 11 and the buffer epitaxial layer 14, and the P-type heavily doped layer 16 is located within the buffer epitaxial layer 14.

[0026] In a specific embodiment, it further includes: a back gold terminal 17, and the back gold terminal 17 is disposed on one side outside the chip body 1.

[0027] Specifically, the PN junction formed by the N-type heavily doped buried layer 10 and the P-type heavy doping 16 below it is a clamping discharge ESD and EOS protection diode. The anode is led out by the back gold terminal 17 of the P-type heavily doped silicon substrate layer 15, and the cathode is directly led out to the surface from the deep N-well layer 9 above the N-type heavily doped buried layer 10.

[0028] In a specific embodiment, it further includes: a first device 3, a second device 4, a third device 5, and a fourth device 6. The first device 3, the second device 4, the third device 5, and the fourth device 6 are all disposed on one side outside the chip body 1.

[0029] Specifically, the first device 3, the second device 4, the third device 5, and the fourth device 6 represent some conventional circuit modules that do not need to be made in isolation.

[0030] In the first device 3, the third device 5, and the fourth device 6, there are all dashed parts 8, which represent the schematic structure of the added P-type heavily doped layer 16 inside the first device 3, the third device 5, and the fourth device 6 with N-type buried layer isolation. A P-type heavily doped region pattern as shown by the dashed line 8 can be formed in the N-type buried layer pattern. The boundary of the PN junction between the P-type heavy doping and the N-type buried layer is inside the PN junction boundary between the N-type buried layer and the P-type substrate, so as to eliminate the influence of the breakdown voltage reduction caused by the PN junction boundary curvature between the P-type heavy doping and the N-type buried layer, and obtain a clamping diode stable breakdown voltage close to the planar junction. At the same time, multiple functional modules such as Figure 2 The 3 clamping diodes formed and marked as 3, 5, and 6 inside can be connected to the same protected pin to form parallel clamping diodes to increase the discharge current capacity.

[0031] In a specific embodiment, it further includes: a CMOS device 12, and the CMOS device 12 is disposed inside the fourth device 6.

[0032] In a specific embodiment, the device further includes: a polysilicon resistor 13 , and a plurality of polysilicon resistors 13 are disposed inside the third device 5 and the fourth device 6 .

[0033] Furthermore, an embodiment of the present invention also provides a method for forming an integrated clamping diode structure, comprising:

[0034] S1: forming a deep N-well layer 9 inside the chip body 1, and sequentially adding an N-type heavily doped buried layer 10 and a P-type heavily doped silicon substrate layer 15 below the deep N-well layer 9, so that the N-type heavily doped buried layer 10 and the P-type heavily doped layer 16 form a PN junction;

[0035] S2: A back-gold terminal 17 is formed on the outer side of the chip body 1 to lead out the anode, and the cathode is led out from the deep N-well layer 9, thereby completing the preparation of the integrated clamping diode structure.

[0036] See attached Figure 3 As shown in the figure, it is a top view of the chip layout of the integrated system-level ESD protection solution in the prior art. It can be seen that the following Figure 3 The chip area marked 2 is used to realize the surge discharge circuit module represented by the silicon surface surge discharge tube included between a-a' shown in the cross section. The present invention can place the ESD clamping protection in the body below the silicon surface of the chip, below the functional circuit and isolated from the surface device by the N-type buried layer. When the chip is working normally, it does not affect the normal operation of the surface functional circuit. It is triggered and clamped only when the overvoltage exceeds a certain threshold voltage of the maximum operating voltage, discharging the transient large current generated by ESD and EOS to protect the chip pins, and can reduce the size of the chip.

[0037] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method description.

[0038] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An integrated clamping diode structure, characterized in that, Including: A chip body (1), a deep N-well layer (9), an N-type heavily doped buried layer (10), and a P-type heavily doped silicon substrate layer (15); The deep N-well layer (9), the N-type heavily doped buried layer (10), and the P-type heavily doped silicon substrate layer (15) are sequentially arranged inside the chip body (1); Inside the chip body (1), a lightly doped silicon epitaxial layer (11), a P-type heavily doped layer (16), and a buffer epitaxial layer (14) are sequentially arranged. The deep N-well layer (9) is located in the lightly doped silicon epitaxial layer (11), the N-type heavily doped buried layer (10) is located between the lightly doped silicon epitaxial layer (11) and the buffer epitaxial layer (14), and the P-type heavily doped layer (16) is located in the buffer epitaxial layer (14); It further includes: a first device (3), a second device (4), a third device (5), and a fourth device (6). The first device (3), the second device (4), the third device (5), and the fourth device (6) are all arranged on one side outside the chip body (1); There are dotted parts (8) in the first device (3), the third device (5), and the fourth device (6), which represent the schematic structure of the added P-type heavily doped layer (16) inside the first device (3), the third device (5), and the fourth device (6) isolated by the N-type heavily doped buried layer (10). A P-type heavily doped region pattern as shown by the dotted part (8) is formed in the N-type heavily doped buried layer (10). The boundary of the PN junction between the P-type heavily doped region pattern and the N-type heavily doped buried layer (10) is inside the PN junction boundary between the N-type heavily doped buried layer (10) and the P-type heavily doped layer (16), so as to eliminate the influence of the reduction of the breakdown voltage caused by the curvature of the PN junction boundary between the P-type heavily doped region pattern and the N-type heavily doped buried layer (10), and obtain a clamping diode stable breakdown voltage close to a planar junction. At the same time, the three clamping diodes formed in the first device (3), the third device (5), and the fourth device (6) are connected to the same protected pin to form parallel clamping diodes to increase the discharge current capacity.

2. An integrated clamping diode structure according to claim 1, characterized in that, It further includes: A back gold terminal (17), and the back gold terminal (17) is arranged on one side outside the chip body (1).

3. An integrated clamp diode structure according to claim 1, characterized in that, It further includes: A CMOS device (12), and the CMOS device (12) is arranged inside the fourth device (6).

4. An integrated clamping diode structure according to claim 1, wherein It further includes: Polycrystalline silicon resistors (13), and a plurality of the polycrystalline silicon resistors (13) are arranged inside the third device (5) and the fourth device (6).

5. A forming method of an integrated clamping diode structure according to any one of claims 1-4, characterized in that, Including: S1: Form the deep N-well layer (9) inside the chip body (1), and sequentially add a lightly doped silicon epitaxial layer (11), the N-type heavily doped buried layer (10), the P-type heavily doped layer (16), the buffer epitaxial layer (14), and the P-type heavily doped silicon substrate layer (15) below the deep N-well layer (9). The N-type heavily doped buried layer (10) and the P-type heavily doped layer (16) form a PN junction; S2: Form a back gold terminal (17) on the outer side of the chip body (1) to lead out the anode, and the cathode is led out from the deep N-well layer (9) to complete the preparation of the integrated clamping diode structure.

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