Three-dimensional memory devices and methods of manufacturing the same

Abstract

The present application relates to three-dimensional memory devices and methods of manufacturing the same. A three-dimensional memory device includes a lower stack and an upper stack that are stacked with each other and each include a plurality of word lines alternately stacked with a plurality of interlayer dielectric layers, wherein each of the lower stack and the upper stack includes a first cell portion, a second cell portion, a link portion linking the first cell portion and the second cell portion, and a staircase portion extending from the first cell portion in parallel to the link portion, in which a pad region of the word line is disposed in a staircase manner, and wherein the link portion of the upper stack is disposed to overlap the staircase portion of the lower stack, and the staircase portion of the upper stack is disposed to overlap the link portion of the lower stack.

Description

TECHNICAL FIELD

[0001] Various embodiments relate generally to semiconductor technology, and more specifically to three-dimensional memory devices and methods of manufacturing the same. BACKGROUND

[0002] Three-dimensional memory devices have advantages in that, by increasing the number of layers by stacking memory cells in a vertical direction, a greater capacity can be achieved in the same area, thereby providing higher performance and excellent power efficiency.

[0003] In three-dimensional memory devices, integration can be increased by increasing the number of word lines to be stacked. However, if the number of word lines is increased, the number of wirings required to couple the word lines and the row decoder increases, and thus, the integration can be reduced. Accordingly, an efficient wiring layout method is required. SUMMARY

[0004] Various embodiments relate to three-dimensional memory devices having improved integration and methods of manufacturing the same.

[0005] In an embodiment, a three-dimensional memory device can include a lower layer stack and an upper layer stack stacked in a vertical direction and each including a plurality of word lines alternately stacked with a plurality of interlayer dielectric layers in the vertical direction, wherein each of the lower layer stack and the upper layer stack includes a first cell portion, a second cell portion, a coupling portion coupling the first cell portion and the second cell portion, and a staircase portion extending parallel to the coupling portion between the first cell portion and the second cell portion, the staircase portion including a plurality of pad regions arranged in a staircase manner and corresponding to the plurality of word lines, and wherein the coupling portion of the upper layer stack is disposed to overlap the staircase portion of the lower layer stack in the vertical direction, and the staircase portion of the upper layer stack is disposed to overlap the coupling portion of the lower layer stack in the vertical direction.

[0006] In an embodiment, a method for manufacturing a three-dimensional memory device can include forming a first pre-stack by alternately stacking a plurality of first interlayer dielectric layers and a plurality of first sacrificial layers in a vertical direction; forming a first staircase portion that exposes the plurality of first sacrificial layers in a staircase manner in the first pre-stack; forming a plurality of first vertical vias through the first staircase portion and a plurality of second vertical vias through a first link portion of the first pre-stack, the first link portion being disposed in parallel with the first staircase portion of the first pre-stack; forming a second pre-stack by alternately stacking a plurality of second interlayer dielectric layers and a plurality of second sacrificial layers on the first pre-stack; forming a second staircase portion in the second pre-stack, the second staircase portion overlapping the first link portion in the vertical direction and exposing the plurality of second sacrificial layers in a staircase manner; forming a plurality of third vertical vias and a plurality of fourth vertical vias, the plurality of third vertical vias being linked to the plurality of first vertical vias by a second link portion of the second pre-stack overlapping the first staircase portion in the vertical direction, the plurality of fourth vertical vias being linked to the plurality of second vertical vias by passing through the second staircase portion; and replacing the first sacrificial layers and the second sacrificial layers with an electrode material. BRIEF DESCRIPTION OF DRAWINGS

[0007] FIG. 1 is a block diagram schematically illustrating a three-dimensional memory device according to an embodiment of the present disclosure.

[0008] FIG. 2 is a perspective view illustrating a portion of a three-dimensional memory device according to an embodiment of the present disclosure.

[0009] FIG. 3A is a cross-sectional view taken along line A-A' of FIG. 2 .

[0010] FIG. 3B is a cross-sectional view taken along line B-B' of FIG. 2 .

[0011] FIG. 4 is a perspective view illustrating an upper stack and a lower stack of FIG. 2 .

[0012] FIG. 5 is a perspective view illustrating a memory device related to the present disclosure.

[0013] FIG. 6A to FIG. 13A is a perspective view illustrating a step of a method for manufacturing a three-dimensional memory device according to an embodiment of the present disclosure.

[0014] FIG. 6B to FIG. 13B are cross-sectional views taken along line A-A' of FIG. 6A to FIG. 13A , respectively.

[0015] FIG. 6C to FIG. 13Care cross-sectional views taken along lines B-B' of FIG. 6A to FIG. 13A

[0016] FIG. 14 is a cross-sectional view illustrating a first vertical via according to another embodiment of the present disclosure.

[0017] FIG. 15A to FIG. 16B is a diagram illustrating a method for forming FIG. 14 a first vertical via.

[0018] FIG. 17A and FIG. 17B is a cross-sectional view illustrating a first vertical via and a fourth vertical via according to yet another embodiment of the present disclosure.

[0019] FIG. 18A to FIG. 21B is a cross-sectional view illustrating a method for forming FIG. 17A a first vertical via and a fourth vertical via shown in FIG. 17B .

[0020] FIG. 22A to FIG. 22C is a diagram illustrating a first vertical via and a fourth vertical via according to still another embodiment of the present disclosure.

[0021] FIG. 23 is a diagram illustrating a three-dimensional memory device according to yet another embodiment of the present disclosure.

[0022] FIG. 24 is a block diagram schematically illustrating a memory system including a three-dimensional memory device according to an embodiment of the present disclosure.

[0023] FIG. 25 is a block diagram schematically illustrating a computing system including a three-dimensional memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] The advantages and features of the present disclosure and a method for achieving them will become apparent from the description of the exemplary embodiments given below and the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but can be implemented in various different ways. The exemplary embodiments of the present disclosure convey the scope of the present disclosure to those skilled in the art.

[0025] ​Because the graphics, sizes, ratios, angles, numbers of elements given in the drawings that describe the embodiments of the present disclosure are only exemplary, the present disclosure is not limited to the illustrated matters. Like reference numerals refer to like elements throughout the specification. In describing the present disclosure, detailed descriptions of related technologies will be omitted when it is determined that the detailed descriptions can obscure the gist of the present disclosure or clarity. It should be understood that the terms "include", "have", "comprise" and the like used in the specification and claims should not be interpreted as being limited to the listed items. When indefinite articles or definite articles are used in reference to singular nouns, unless explicitly stated otherwise, the articles can include plural forms of the nouns.

[0026] When elements in the embodiments of the present disclosure are explained, they should be interpreted to include error margins even if not explicitly mentioned.

[0027] In addition, when components of the present disclosure are described, terms such as first, second, A, B, (a), and (b) can be used. These terms are only to distinguish one component from another component, and do not limit the substance, order, sequence, or number of the components. In addition, the components in the embodiments of the present disclosure are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, as used herein, a first component can be a second component within the technical spirit of the present disclosure.

[0028] If a component is described as being "connected", "coupled", or "linked" to another component, it can mean that the component is not only directly "connected", "coupled", or "linked", but also indirectly "connected", "coupled", or "linked" via a third component. When a positional relationship such as "element A on element B", "element A above element B", "element A below element B", and "element A next to element B" is described, unless the term "directly" or "immediately" is explicitly used, one or more elements can be disposed between elements A and B.

[0029] The features of various exemplary embodiments of the present disclosure can be partially or wholly coupled, combined, or separated. Various interactions and operations are also technically feasible. The various exemplary embodiments can be practiced individually or in combination.

[0030] Hereinafter, various examples of the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0031] FIG. 1 is a block diagram schematically illustrating a three-dimensional memory device according to an embodiment of the present disclosure.

[0032] Referring to FIG. 1The three-dimensional memory device 100 according to embodiments of the present disclosure can include a memory cell array 110 and a logic circuit 120. The logic circuit 120 can include a row decoder (X-DEC) 121, a page buffer circuit 122, and a peripheral circuit (PERI circuit) 123.

[0033] The memory cell array 110 can include a plurality of memory blocks BLK. Although not shown, each memory block BLK can include a plurality of cell strings. Each cell string can include at least one drain select transistor, a plurality of memory cells, and at least one source select transistor, which are serially coupled. Although the following description represents some embodiments of the present disclosure using a vertical NAND flash memory as an example, it is noted that the present disclosure is not limited thereto, and other embodiments can include different types of memories.

[0034] The memory cell array 110 can be coupled to the row decoder 121 through a plurality of word lines WL. The memory cell array 110 can be coupled to the page buffer circuit 122 through a plurality of bit lines BL.

[0035] The row decoder 121 can select an arbitrary one of the memory blocks BLK included in the memory cell array 110 in response to a row address X_A provided from the peripheral circuit 123. The row decoder 121 can transfer an operation voltage X_V provided from the peripheral circuit 123 to a word line WL coupled to the memory block BLK selected from among the memory blocks BLK included in the memory cell array 110.

[0036] The page buffer circuit 122 can include a plurality of page buffers PB coupled to the bit lines BL, respectively. The page buffer circuit 122 can receive a page buffer control signal PB_C from the peripheral circuit 123, and can transmit and receive a data signal DATA to and from the peripheral circuit 123. The page buffer circuit 122 can control the bit lines BL disposed in the memory cell array 110 in response to the page buffer control signal PB_C. For example, the page buffer circuit 122 can detect data stored in the memory cells of the memory cell array 110 by sensing a signal of the bit lines BL of the memory cell array 110 in response to the page buffer control signal PB_C, and can transmit the data signal DATA to the peripheral circuit 123 depending on the detected data. The page buffer circuit 122 can apply a signal to the bit lines BL based on the data signal DATA received from the peripheral circuit 123 in response to the page buffer control signal PB_C, so that data can be written to the memory cells of the memory cell array 110. The page buffer circuit 122 can write data to or read data from the memory cells coupled to the activated word line.

[0037] The peripheral circuit 123 can receive a command signal CMD, an address signal ADD, and a control signal CTRL from outside the memory device 100, and can transmit and receive data DATA to and from a device (e.g., a memory controller) outside the memory device 100. The peripheral circuit 123 can output a signal, e.g., a row address X_A, a page buffer control signal PB_C, etc., for writing or reading data from or to the memory cell array 110, based on the command signal CMD, the address signal ADD, and the control signal CTRL. The peripheral circuit 123 can generate various voltages including an operating voltage X_V required in the memory device 100.

[0038] As the size of electronic products, particularly mobile products, in which the memory device 100 is mounted, is reduced, there is a demand for continued reduction in the size of the memory device 100. As the number of layers of the word lines WL is increased due to a demand for high capacity, the number of wirings coupling the word lines WL and the row decoder 121 is also constantly increasing. In order to suppress an increase in the size of the memory device 100 due to an increase in the number of wirings, and to improve integration, an efficient wiring layout method is required.

[0039] FIG. 2 is a perspective view illustrating a portion of a three-dimensional memory device according to an embodiment of the disclosure. FIG. 3A is a cross-sectional view taken along FIG. 2 line A-A' of FIG. 3B is a cross-sectional view taken along FIG. 2 line B-B' of FIG. 4 is a perspective view illustrating an upper stack and a lower stack of FIG. 2 .

[0040] Referring to FIG. 2 , FIG. 3A and FIG. 3B , a three-dimensional memory device according to an embodiment of the disclosure can include a substrate 10, a lower stack LS disposed on the substrate 10, and an upper stack US disposed on or above the lower stack LS.

[0041] The lower stack LS can include a plurality of first word lines WL1 alternately stacked with a plurality of interlayer dielectric layers 22A, and the upper stack US can include a plurality of second word lines WL2 alternately stacked with a plurality of interlayer dielectric layers 22B.

[0042] The first word line WL1 and the second word line WL2 can include an electrically conductive material. For example, the first word line WL1 and the second word line WL2 can include at least one selected from a doped semiconductor (e.g., doped silicon), a metal (e.g., tungsten, copper, or aluminum), an electrically conductive metal nitride (e.g., titanium nitride or tantalum nitride), and a transition metal (e.g., titanium or tantalum). The interlayer dielectric layers 22A and 22B can include silicon oxide.

[0043] The lower stack LS can further include a source select line SSL disposed below the plurality of first word lines WL1, and the upper stack US can further include a drain select line DSL disposed on or above the plurality of second word lines WL2.

[0044] The lower stack LS can include a first cell portion CELL1 disposed in a first cell region CR1, a second cell portion CELL2 disposed in a second cell region CR2, and a first staircase portion SP1 and a first connection portion CP1 both disposed in a thinning region SR between the first cell region CR1 and the second cell region CR2.

[0045] The first connection portion CP1 can connect the first cell portion CELL1 and the second cell portion CELL2. The first staircase portion SP1 can extend in parallel to the first connection portion CP1 and can have a staircase shape connected to the first cell portion CELL1 and lowered in a direction toward the second cell portion CELL2.

[0046] The upper stack US can include a third cell portion CELL3 disposed in the first cell region CR1 and overlapping the first cell portion CELL1 in a vertical direction, and the upper stack US can include a fourth cell portion CELL4 disposed in the second cell region CR2 and overlapping the second cell portion CELL2 in the vertical direction. The upper stack US can include a second staircase portion SP2 and a second connection portion CP2 both disposed in the thinning region SR.

[0047] The second connection portion CP2 can connect the third cell portion CELL3 and the fourth cell portion CELL4. The second staircase portion SP2 can extend in parallel to the second connection portion CP2 and can have a staircase shape connected to the third cell portion CELL3 and lowered in a direction toward the fourth cell portion CELL4.

[0048] Referring to FIG. 4Each of the first word lines WL1 included in the lower stack LS can have a first pad region PAD1. The first pad region PAD1 of the first word line WL1 can be disposed in a stepped shape in the first stepped portion SP1.

[0049] Similarly to the lower stack LS, each of the second word lines WL2 included in the upper stack US can have a second pad region PAD2. The second pad region PAD2 of the second word line WL2 can be disposed in a stepped shape in the second stepped portion SP2.

[0050] The second stepped portion SP2 of the upper stack US can overlap the first coupling portion CP1 of the lower stack LS in the vertical direction, and the second coupling portion CP2 of the upper stack US can overlap the first stepped portion SP1 of the lower stack LS in the vertical direction. The first stepped portion SP1 of the lower stack LS and the second stepped portion SP2 of the upper stack US can not overlap each other perpendicularly. Thus, the first pad region PAD1 and the second pad region PAD2 can be disposed in relatively different positions horizontally and vertically.

[0051] Referring again to FIG. 2 A plurality of vertical channels CH passing through the lower stack LS and the upper stack US can be defined in the first cell region CR1 and the second cell region CR2.

[0052] Although not shown in detail, each of the plurality of vertical channels CH can include a channel layer and a gate dielectric layer. The channel layer can include polysilicon or single-crystal silicon, and can include a p-type impurity such as boron (B) in some regions thereof. The gate dielectric layer can have a shape surrounding an outer wall of the channel layer. The gate dielectric layer can include a tunnel dielectric layer, a charge storage layer, and a blocking layer, which are sequentially stacked from the outer wall of the channel layer. In some embodiments, the gate dielectric layer can have an ONO (Oxide-Nitride-Oxide) layer stack structure in which an oxide layer, a nitride layer, and an oxide layer are sequentially stacked.

[0053] A source select transistor can be configured in a region or area around the vertical channel CH by the source select line SSL. A memory cell can be configured in a region or area around the vertical channel CH by the plurality of first word lines WL1 and the plurality of second word lines WL2. A drain select transistor can be configured in a region or area around the vertical channel CH by the drain select line DSL. The source select transistor, the plurality of memory cells, and the drain select transistor arranged in a row along one vertical channel CH can configure one cell string.

[0054] The present embodiment illustrates a case where the lower stack LS and the upper stack US are constructed on a single substrate 10. Thus, the first word lines WL1 of the lower stack LS and the second word lines WL2 of the upper stack US can be commonly coupled to a single cell string.

[0055] Referring again to FIG. 3A and FIG. 3B , a first dielectric layer ILD1 can be formed on the lower stack LS to cover the lower stack LS. An upper stack US can be disposed on the first dielectric layer ILD1. A second dielectric layer ILD2 can be formed on the upper stack US to cover the upper stack US.

[0056] A plurality of first vertical vias VIA1 and a plurality of second vertical vias VIA2 can be defined to pass through the lower stack LS and the first dielectric layer ILD1. The plurality of first vertical vias VIA1 can respectively correspond to the first pad regions PAD1 of the first stepped portions SP1 and can pass through the first stepped portions SP1 at the respective first pad regions PAD1. The plurality of second vertical vias VIA2 can pass through the first coupling portions CP1.

[0057] A plurality of third vertical vias VIA3 and a plurality of fourth vertical vias VIA4 can be defined to pass through the upper stack US and the second dielectric layer ILD2. The plurality of third vertical vias VIA3 can pass through the second coupling portions CP2 and can respectively be coupled to the plurality of first vertical vias VIA1. The plurality of fourth vertical vias VIA4 can respectively correspond to the second pad regions PAD2 of the second stepped portions SP2 and can be coupled to the second vertical vias VIA2 by passing through the second stepped portions SP2 at the respective second pad regions PAD2.

[0058] The first vertical vias VIA1 and the second vertical vias VIA2 can be isolated from the first word lines WL1 by a dielectric pattern 24A that can be defined between outer walls of the plurality of first vertical vias VIA1 and the plurality of second vertical vias VIA2 and the plurality of first word lines WL1. The dielectric pattern 24A can be alternately disposed along the outer walls of the plurality of first vertical vias VIA1 in the first stepped portions SP1 and along the outer walls of the plurality of second vertical vias VIA2 in the first coupling portions CP1 with the plurality of interlayer dielectric layers 22A. The dielectric pattern 24A can be formed of, for example, silicon oxide.

[0059] The third vertical vias VIA3 and the fourth vertical vias VIA4 can be isolated from the second word lines WL2 by a dielectric pattern 24B that can be defined between outer walls of the plurality of third vertical vias VIA3 and the plurality of fourth vertical vias VIA4 and the plurality of second word lines WL2. The dielectric pattern 24B can be alternately disposed along the outer walls of the plurality of third vertical vias VIA3 in the second coupling portions CP2 and along the outer walls of the plurality of fourth vertical vias VIA4 in the second stepped portions SP2 with the plurality of interlayer dielectric layers 22B. The dielectric pattern 24B can be formed of, for example, silicon oxide.

[0060] The first hard mask pattern HM1 can be defined on the first pad region PAD1 of the first word line WL1, respectively. The first hard mask pattern HM1 can be made of an electrically conductive material, so that the first word line WL1 and the first vertical via VIA1 corresponding to each other can be electrically coupled, respectively.

[0061] The second hard mask pattern HM2 can be defined on the second pad region PAD2 of the second word line WL2, respectively. The second hard mask pattern HM2 can be made of an electrically conductive material, so that the second word line WL2 and the fourth vertical via VIA4 corresponding to each other can be electrically coupled, respectively.

[0062] The plurality of first vertical vias VIA1 and the plurality of third vertical vias VIA3 can be used to configure an electrical path for coupling the first word line WL1 to a row decoder (not shown). The plurality of second vertical vias VIA2 and the plurality of fourth vertical vias VIA4 can be used to configure an electrical path for coupling the second word line WL2 to the row decoder.

[0063] Although not shown, a logic structure including the row decoder can be disposed under the substrate 10 or on the second dielectric layer ILD2, so as to overlap the lower stack LS and the upper stack US in a vertical direction.

[0064] The logic structure, the lower stack LS, and the upper stack US can be fabricated on a single wafer. However, the logic structure can also be fabricated on a wafer separate from the lower stack LS and the upper stack US, and then can be bonded by a bonding technique such as hybrid bonding. Because the logic structure overlaps the lower stack LS and the upper stack US in which the array of memory cells (110) of the three-dimensional memory device is configured in a vertical direction, a planar area occupied by the three-dimensional memory device can be reduced, and the integration of the three-dimensional memory device can be increased. FIG. 1

[0065] FIG. 5 is a perspective view illustrating a memory device related to the present disclosure.

[0066] Referring to FIG. 5 In order to provide a space in which the vertical via VIA12 for coupling the first word line WL1 of the lower stack LS and the second word line WL2 of the upper stack US to a row decoder (not shown) is disposed, an opening OFC can be formed in the lower stack LS and the upper stack US in the thinning region SR.

[0067] If the number of word lines is increased to increase the integration, the number of vertical vias VIA12 will need to be increased according to the number of increased word lines. However, since the number of vertical vias VIA12 that can be disposed in the opening OFC is limited, any increase in integration will be constrained or limited.

[0068] ​Furthermore, in order to couple the vertical via VIA11 to the pad area, the width W1 of the second step portion SP2 of the upper stack US can be smaller than the width W2 of the first step portion SP1 of the lower stack LS so as to expose the first pad area PAD1 of the lower stack LS. Due to this fact, the width W1 of the first and second pad areas PAD1 and PAD2 can be smaller than the width W2 of the first step portion SP1 of the lower stack LS. For example, the width W1 can be half of the width W2.

[0069] If the width of the first and second pad areas PAD1 and PAD2 is narrow, when the vertical via VIA11 is formed, an open failure that the vertical via VIA11 is not coupled to the pad area or a short failure that the vertical via VIA11 is coupled to at least two pad areas can occur due to lack of an alignment margin.

[0070] In FIG. 2 to FIG. 4 the embodiments of the disclosure shown in FIG. 5 , the above-mentioned disadvantages of the memory device having the structure of FIG. 2 to FIG. 4 , according to the embodiments of the disclosure, the second coupling portion CP2 of the upper stack US overlaps the first step portion SP1 of the lower stack LS in the vertical direction, and the second step portion SP2 of the upper stack US overlaps the first coupling portion CP1 of the lower stack LS in the vertical direction. The vertical vias VIA1 and VIA3 coupling the first word line WL1 to the row decoder pass through the first step portion SP1 of the lower stack LS and the second coupling portion CP2 of the upper stack US. The vertical vias VIA2 and VIA4 coupling the second word line WL2 to the row decoder pass through the first coupling portion CP1 of the lower stack LS and the second step portion SP2 of the upper stack US. Thus, it is not necessary to form a separate space or opening for disposing the vertical via in the lower stack LS and the upper stack US, and it is not necessary to dispose the vertical via in only a separately defined limited space as seen in FIG. 5 . Thus, it is possible to increase the number of vertical vias, which is advantageous for improving the integration.

[0071] In addition, the first pad area PAD1 can be configured to have a wider width, such as a width corresponding to the width W3 of the first step portion SP1 of the lower stack LS of FIG. 4 , and the second pad area PAD2 can be configured to have a wider width, such as a width corresponding to the width W3 of the second step portion SP2 of the upper stack US of FIG. 4 . Thus, by increasing the alignment margin in coupling the vertical via to the first and second pad areas PAD1 and PAD2, it is possible to help prevent the open failure or the short failure that can occur when the vertical via is formed.

[0072] FIG. 6A to FIG. 13A is a perspective view illustrating steps of a method for manufacturing a three-dimensional memory device according to an embodiment of the present disclosure. FIG. 6B to FIG. 13B are cross-sectional views taken along lines A-A' and B-B' of FIG. 6A to FIG. 13A respectively, and FIG. 6C to FIG. 13C are cross-sectional views taken along lines A-A' and B-B' of FIG. 6A to FIG. 13A respectively.

[0073] Referring to FIG. 6A to FIG. 6C , when a plurality of sacrificial layers 20A and a plurality of interlayer dielectric layers 22A are alternately stacked on the substrate 10, a first pre-stack P1 can be formed.

[0074] The plurality of sacrificial layers 20A and the plurality of interlayer dielectric layers 22A can be formed of different materials. The plurality of sacrificial layers 20A can be formed of a material having etch selectivity with respect to the plurality of interlayer dielectric layers 22A. For example, the plurality of interlayer dielectric layers 22A can be formed of an oxide, and the plurality of sacrificial layers 20A can be formed of a nitride.

[0075] As a portion of the first pre-stack P1 is etched into a staircase shape, a staircase portion S1 exposing the plurality of sacrificial layers 20A in the staircase shape and a coupling portion C1 disposed in parallel to the staircase portion S1 can be formed.

[0076] First hard mask patterns HM1 each having a via H1 can be formed on exposed regions of the sacrificial layers 20A in the staircase portion S1, respectively. The first hard mask patterns HM1 can be formed of a material having etch selectivity with respect to the plurality of sacrificial layers 20A and the plurality of interlayer dielectric layers 22A. The first hard mask patterns HM1 can be formed of a conductive material having etch selectivity with respect to the plurality of sacrificial layers 20A and the plurality of interlayer dielectric layers 22A.

[0077] Referring to FIG. 7A to FIG. 7C , a dielectric layer ILD1 can be formed on the first pre-stack P1 and the first hard mask patterns HM1. The dielectric layer ILD1 can be formed of a dielectric material having etch selectivity with respect to the sacrificial layers 20A. For example, if the sacrificial layers 20A are formed of a nitride, the dielectric layer ILD1 can be formed of an oxide.

[0078] After a mask pattern (not shown) having a plurality of openings is formed on the dielectric layer ILD1, the dielectric layer ILD1 and the first pre-stack P1 are etched using the mask pattern as an etch mask. A plurality of first vertical holes VH1 are formed through the staircase portion S1 of the first pre-stack P1, and a plurality of second vertical holes VH2 are formed through the landing portion C1 of the first pre-stack P1. Each of the plurality of first vertical holes VH1 can pass through a respective sacrificial layer 20A and expose a region common to the respective sacrificial layer 20A, and can be in communication with a via hole H1 defined on the exposed region of the respective sacrificial layer 20A in the first hard mask pattern HM1.

[0079] Referring to FIG. 8A to FIG. 8C An etchant E capable of removing the sacrificial layer 20A can be injected into the plurality of first vertical holes VH1 and the plurality of second vertical holes VH2. As portions of the sacrificial layer 20A around or common to the plurality of first vertical holes VH1 and portions of the sacrificial layer 20A around or common to the plurality of second vertical holes VH2 are removed by the etchant E, a plurality of horizontal trenches HH1 can be formed.

[0080] Referring to FIG. 9A to FIG. 9C A dielectric pattern 24A can be formed to fill the plurality of horizontal trenches HH1. For example, the dielectric pattern 24A can be formed by depositing a thin dielectric material on the sidewalls of the plurality of first vertical holes VH1 and the plurality of second vertical holes VH2 such that the plurality of horizontal trenches HH1 are filled. In another example, the dielectric pattern 24A can be formed by filling the plurality of horizontal trenches HH1, the plurality of first vertical holes VH1, and the plurality of second vertical holes VH2 with a dielectric material, and then removing the dielectric material filled in the plurality of first vertical holes VH1 and the plurality of second vertical holes VH2 and leaving the dielectric material in the plurality of horizontal trenches HH1. The dielectric pattern 24A can be formed of an oxide.

[0081] Referring to FIG. 10A to FIG. 10C As the plurality of first vertical holes VH1 and the plurality of second vertical holes VH2 are filled with a conductive material, a plurality of first vertical vias VIA1 and a plurality of second vertical vias VIA2 can be formed. Each of the plurality of first vertical vias VIA1 can be coupled to a respective first hard mask pattern HM1.

[0082] Referring to FIG. 11A to FIG. 11CA second pre-laminated layer P2 can be formed by alternately stacking multiple sacrificial layers 20B and multiple interlayer dielectric layers 22B on dielectric layer ILD1. The multiple sacrificial layers 20B and multiple interlayer dielectric layers 22B can be formed from different materials. The multiple sacrificial layers 20B can be formed from a material that has etch selectivity relative to the multiple interlayer dielectric layers 22B. For example, the multiple interlayer dielectric layers 22B can be formed from oxides, and the multiple sacrificial layers 20B can be formed from nitrides.

[0083] As a portion of the width of the second pre-laminated material P2 is etched into a stepped shape, a stepped portion S2 exposing multiple sacrificial layers 20B in a stepped shape and a connecting portion C2 extending parallel to the stepped portion S2 can be formed. The stepped portion S2 of the second pre-laminated material P2 can overlap with the connecting portion C1 of the first pre-laminated material P1 in the vertical direction, and the connecting portion C2 of the second pre-laminated material P2 can overlap with the stepped portion S1 of the first pre-laminated material P1 in the vertical direction.

[0084] Each second hard mask pattern HM2 having a via H2 can be formed on the exposed area of ​​the stepped portion S2 of the sacrificial layer 20B. The second hard mask pattern HM2 can be formed of a material that has etch selectivity relative to the plurality of sacrificial layers 20B and the plurality of interlayer dielectric layers 22B. For example, the second hard mask pattern HM2 can be formed of a conductive material that has etch selectivity relative to the plurality of sacrificial layers 20B and the plurality of interlayer dielectric layers 22B.

[0085] The dielectric layer ILD2 can be formed on the second pre-laminated layer P2 and the second hard mask pattern HM2. The dielectric layer ILD2 can be formed of a dielectric material that has etch selectivity relative to the sacrificial layer 20B. For example, if the sacrificial layer 20B is formed of a nitride, the dielectric layer ILD2 can be formed of an oxide.

[0086] After a mask pattern (not shown) with multiple openings is formed on the dielectric layer ILD2, the mask pattern is used as an etching mask to etch the dielectric layer ILD2 and the second pre-stack P2. Multiple third vertical vias VH3 are formed to pass through the connection portion C2 of the second pre-stack P2 and expose multiple first vertical vias VIA1, respectively. Multiple fourth vertical vias VH4 are formed to pass through the stepped portion S2 of the second pre-stack P2 and expose multiple second vertical vias VIA2, respectively. Each of the multiple fourth vertical vias VH4 can pass through and expose a region common to the sacrificial layers 20B, and can communicate with a via H2 in the second hard mask pattern HM2 defined on the exposed region of the corresponding sacrificial layer 20B.

[0087] Reference FIG. 12A to FIG. 12CAn etchant capable of removing the sacrificial layer 20B can be injected into multiple third vertical holes VH3 and multiple fourth vertical holes VH4. As the portion of the sacrificial layer 20B around or shared by the multiple third vertical holes VH3 and the portion of the sacrificial layer 20B around or shared by the multiple fourth vertical holes VH4 are removed by the etchant, multiple horizontal trenches HH2 can be formed.

[0088] Reference FIG. 13A to FIG. 13C A dielectric pattern 24B can be formed to fill multiple horizontal trenches HH2. For example, the dielectric pattern 24B can be formed by depositing a thin dielectric material on the sidewalls of multiple third vertical vias VH3 and multiple fourth vertical vias VH4, thereby filling the multiple horizontal trenches HH2. In another example, the dielectric pattern 24B can be formed by filling the multiple horizontal trenches HH2, multiple third vertical vias VH3, and multiple fourth vertical vias VH4 with a dielectric material, then removing the dielectric material filling the multiple third vertical vias VH3 and multiple fourth vertical vias VH4, and retaining the dielectric material in the multiple horizontal trenches HH2. The dielectric pattern 24B can be formed of oxide.

[0089] By filling multiple third vertical vias VH3 and multiple fourth vertical vias VH4 with conductive material, multiple third vertical vias VIA3 and multiple fourth vertical vias VIA4 can be formed. Multiple third vertical vias VIA3 are formed in the multiple third vertical vias VH3 and can be respectively connected to multiple first vertical vias VIA1. Multiple fourth vertical vias VIA4 are formed in the multiple fourth vertical vias VH4 and can each be connected to a corresponding second vertical via VIA2 and a corresponding second hard mask pattern HM2.

[0090] The remaining portions of sacrificial layers 20A and 20B can be replaced with electrode material to form the first word line and the second word line. FIG. 3A WL1 and WL2).

[0091] FIG. 14 This illustrates a cross-sectional view of a first vertical through-hole according to another embodiment of the present disclosure, and FIG. 15A to FIG. 16B This illustrates the method used to form FIG. 14 A cross-sectional view of the first vertical through-hole method.

[0092] Reference FIG. 14 In the first step portion SP1, the upper part VIA1_U of the first vertical via VIA1 passing through the dielectric layer ILD1 can have a larger width than the lower part VIA1_L of the first vertical via VIA1 passing through the stack in the first step portion SP1.

[0093] As mentioned above, by reference FIG. 8A to FIG. 8CThe process described forms a plurality of horizontal trenches FIG. 8B and FIG. 8C After the HH1 of FIG. 15A and FIG. 15B The horizontal trenches (HH1 of FIG. 8B and FIG. 8C ), the first vertical holes (VH1 of FIG. 8A ), and the second vertical holes (VH2 of FIG. 8A ) can be filled with a dielectric material 30 as shown in

[0094] A mask pattern PR1 can be formed on the dielectric layer ILD1. In FIG. 15A , the mask pattern PR1 can have a plurality of first openings OP1 that expose the dielectric material 30 and portions of the dielectric layer ILD1 around the first vertical holes (VH1 of FIG. 8A ). In FIG. 15B , the mask pattern PR1 can also have a plurality of second openings OP2 that expose the dielectric material 30 filled in the second vertical holes (VH2 of FIG. 8A ).

[0095] As the dielectric layer ILD1 and the dielectric material 30 are etched using the mask pattern PR1 and the first hard mask pattern HM1 as etch masks, the dielectric material 30 shared by the first vertical holes VH1 and the second vertical holes VH2 can be removed while a dielectric pattern 24A can be formed from the dielectric material 30 remaining in the horizontal trenches (HH1 of FIG. 8B and FIG. 8C ) as shown in FIG. 16A and FIG. 16B .

[0096] Because the first openings OP1 of the mask pattern PR1 not only expose the dielectric material 30 filled in the first vertical holes (VH1 of FIG. 8A ), but also expose the dielectric layer ILD1 around the first vertical holes (VH1 of FIG. 8A ), the upper portion of the first vertical holes VH1 can have a width that is wider than the width of the lower portion.

[0097] The mask pattern PR1 can be formed using a photoresist. The mask pattern PR1 left after etching the dielectric material 30 and the dielectric layer ILD1 can be removed by a lift-off process.

[0098] After that, as the plurality of first vertical holes VH1 and the plurality of second vertical holes VH2 are filled with a conductive material, a plurality of first vertical vias VIA1 (see FIG. 14 ) and a plurality of second vertical vias can be formed.

[0099] FIG. 17A and FIG. 17Bis a cross-sectional view illustrating a first vertical via and a fourth vertical via according to yet another embodiment of the present disclosure. FIG. 18A to FIG. 21B is a cross-sectional view illustrating a method of forming FIG. 17A and FIG. 17B a first vertical via and a fourth vertical via shown in

[0100] Referring to FIG. 17A , a lower portion VIA1_L of the first vertical via VIA1 can be located in the first staircase portion SP1 and can be isolated from the first word line WL1 by the dielectric pattern 24A.

[0101] An upper portion VIA1_U of the first vertical via VIA1 can pass through portions common to the dielectric layer ILD1 and the pad regions in the first hard mask pattern HM1, so as to be directly coupled to the first pad regions PAD1 of the corresponding first word line WL1. In this embodiment, the first hard mask pattern HM1 can be a conductive material or can be an insulating material.

[0102] Referring to FIG. 17B , a lower portion VIA4_L of the fourth vertical via VIA4 can be located in the second staircase portion SP2 and can be isolated from the second word line WL2 by the dielectric pattern 24B. An upper portion VIA4_U of the fourth vertical via VIA4 can pass through portions common to the dielectric layer ILD2 and the pad regions in the second hard mask pattern HM2, so as to be directly coupled to the second pad regions PAD2 of the corresponding second word line WL2. In this embodiment, the second hard mask pattern HM2 can be a conductive material or can be an insulating material.

[0103] As described above, after the plurality of horizontal trenches (HH1 of FIG. 8A to FIG. 8C are formed by the process described with reference to FIG. 8B and FIG. 8C , the horizontal trenches (HH1 of FIG. 18A and FIG. 18B , the first vertical hole (VH1 of FIG. 8B and FIG. 8C , and the second vertical hole (VH2 of FIG. 8A may be filled with the dielectric material 30 as shown in FIG. 8A .

[0104] A mask pattern PR2 can be formed on the dielectric layer ILD1. The mask pattern PR2 can have a plurality of first openings OP1' exposing portions of the dielectric material 30 and the dielectric layer ILD1 around the first vertical hole (VH1 of FIG. 8A . The mask pattern PR2 can also have a plurality of second openings OP2' exposing the dielectric material 30 filled in the second vertical hole (VH2 of FIG. 8A .

[0105] Using mask pattern PR2 and the first hard mask pattern HM1 as etching masks, the dielectric layer ILD1 and the dielectric material 30 can be etched. Therefore, as FIG. 19A and FIG. 19B As shown, the dielectric material 30 shared by the first vertical hole VH1 and the second vertical hole VH2 can be removed, while the dielectric material 30 retained in the horizontal trench can be removed. FIG. 8B and FIG. 8C The dielectric material 30 in HH1) forms a dielectric pattern 24A.

[0106] As the first hard mask pattern HM1 in the first vertical aperture VH1 is etched, the portion of the sacrificial layer 20A immediately below the first hard mask pattern HM1 is exposed. A mask pattern PR2 can be formed using photoresist. The remaining mask pattern PR2 can be removed using a stripping process.

[0107] Subsequently, by filling multiple first vertical holes VH1 and multiple second vertical holes VH2 with conductive material, multiple first vertical vias VIA1 can be formed (see...). FIG. 17A ) and multiple second vertical vias VIA2 (see FIG. 17B ).

[0108] As mentioned above, based on the above references FIG. 12A to FIG. 12C The described process forms multiple horizontal trenches ( FIG. 12B and FIG. 12C After HH2), such as FIG. 20A and FIG. 20B As shown, dielectric material 32 can fill horizontal trenches ( FIG. 12B and FIG. 12C HH2), the third vertical hole ( FIG. 12A VH3) and the fourth vertical hole ( FIG. 12A (VH4).

[0109] A mask pattern PR3 can be formed on the dielectric layer ILD2. The mask pattern PR3 can have a third vertical hole that exposes the dielectric material 32 and the dielectric layer ILD2. FIG. 12A The mask pattern PR3 may also have multiple first openings OP1″ around the portion of VH3. The mask pattern PR3 may also have a fourth vertical hole ( ) exposing the dielectric material 32 and the dielectric layer ILD2. FIG. 12A The portion surrounding VH4 has multiple second openings OP2″.

[0110] Using mask pattern PR3 and second hard mask pattern HM2 as etching masks, the dielectric layer ILD2 and dielectric material 32 can be etched. Therefore, as FIG. 21A and FIG. 21BAs shown, the dielectric material 32 common to the third vertical holes VH3 and the fourth vertical holes VH4 can be removed, while the dielectric pattern 24B can be formed from the dielectric material 32 remaining in the horizontal trench (HH2). FIG. 12B and FIG. 12C .

[0111] As the second hard mask pattern HM2 in the fourth vertical hole VH4 is etched, a portion of the sacrificial layer 20B immediately below the second hard mask pattern HM2 can be exposed. A photoresist can be used to form a mask pattern PR3. The remaining mask pattern PR3 can be removed by a lift-off process.

[0112] After that, as the plurality of third vertical holes VH3 and the plurality of fourth vertical holes VH4 are filled with a conductive material, a plurality of third vertical vias VIA3 (see FIG. 17A ) and a plurality of fourth vertical vias VIA4 (see FIG. 17B ) can be formed.

[0113] FIG. 22A to FIG. 22C is a diagram illustrating a first vertical via and a fourth vertical via according to still another embodiment of the present disclosure. In detail, FIG. 22A is a perspective view, FIG. 22B is a cross-sectional view taken along line A-A’ of FIG. 22A , and FIG. 22C is a cross-sectional view taken along line B-B’ of FIG. 22A .

[0114] Referring to FIG. 22A to FIG. 22C , each of the first vertical vias VIA1 can include a conductive pad portion 40 disposed on and directly coupled to a first pad region PAD1 of a corresponding first word line WL1. The conductive pad portion 40 can have a flat plate shape covering an upper surface of the first pad region PAD1 of the corresponding first word line WL1.

[0115] Each of the fourth vertical vias VIA4 can include a conductive pad portion 42 disposed on and directly coupled to a second pad region PAD2 of a corresponding second word line WL2. The conductive pad portion 42 can have a flat plate shape covering an upper surface of the second pad region PAD2 of the corresponding second word line WL2.

[0116] As previously described, after the step of forming the dielectric pattern 24A described above with reference to FIG. 9A to FIG. 9C , a process of removing the first hard mask pattern (HM1 of FIG. 9A ) can be additionally performed. In the case of the present embodiment, the first hard mask pattern can be made of a conductive material or a dielectric material.

[0117] Subsequently, based on the above references FIG. 10A to FIG. 10C The description describes filling the first vertical hole with a conductive material ( FIG. 9A VH1) and the second vertical hole ( FIG. 9A In the VH2 process, the space from which the first hard mask pattern has been removed can be filled with a conductive material. The conductive material filling the space from which the first hard mask pattern has been removed can form the conductive pad portion 40 of the first vertical via VIA1 (see...). FIG. 22B ).

[0118] As previously described, in the above reference FIG. 13A to FIG. 13C Following the steps of forming the dielectric pattern 24B as described, the removal of the second hard mask pattern can be additionally performed. FIG. 13A The process of HM2). In the process of filling the third vertical via (VH3) and the fourth vertical via (VH4) with conductive material, the space from which the second hard mask pattern has been removed can be filled with conductive material. The conductive material filling the space from which the second hard mask pattern has been removed can form the conductive pad portion 42 of the fourth vertical via VIA4 (see HM2). FIG. 22A and FIG. 22C ).

[0119] FIG. 23 This is a diagram illustrating a three-dimensional memory device according to yet another embodiment of the present disclosure.

[0120] Reference FIG. 23 The lower stack LS can be disposed in the first unit wafer CW1, and the upper stack US can be disposed in the second unit wafer CW2, which is disposed on the first unit wafer CW1.

[0121] The lower stack LS may include multiple first word lines WL1 stacked on the substrate 10A of the first unit wafer CW1, and the upper stack US may include multiple second word lines WL2 stacked on the substrate 10B of the second unit wafer CW2.

[0122] The lower stack LS may further include: a first source select line SSL1 disposed below a plurality of first word lines WL1; and a first drain select line DSL1 disposed on the plurality of first word lines WL1. The upper stack US may further include: a second source select line SSL2 disposed below a plurality of second word lines WL2; and a second drain select line DSL2 disposed on the plurality of second word lines WL2.

[0123] A plurality of first vertical channels CH1 can be defined through the lower stack LS and coupled to the substrate 10A in the first cell region CR1 and the second cell region CR2. A plurality of second vertical channels CH2 can be defined through the upper stack US and coupled to the substrate 10B in the first cell region CR1 and the second cell region CR2. The first cell wafer CW1 and the second cell wafer CW2 can be bonded to each other by a bonding technique, for example, by hybrid bonding.

[0124] Although not shown, the substrate 10B of the second cell wafer CW2 can include a plurality of vias for electrically coupling the plurality of first vertical vias VIA1 to the plurality of third vertical vias VIA3, and a plurality of vias for electrically coupling the plurality of second vertical vias VIA2 to the plurality of fourth vertical vias VIA4. A logic wafer including a row decoder can be bonded to the bottom of the first cell wafer CW1 or the top of the second cell wafer CW2.

[0125] FIG. 24 is a block diagram schematically illustrating a memory system including a three-dimensional memory device according to an embodiment of the disclosure.

[0126] Referring to FIG. 24 The memory system 600 according to an embodiment can include a non-volatile memory device (NVM device) 610 and a memory controller 620.

[0127] The non-volatile memory device (NVM device) 610 can be composed of the three-dimensional memory device described above and can be operated in the manner described above. The memory controller 620 can be configured to control the non-volatile memory device (NVM device) 610. By combining the non-volatile memory device (NVM device) 610 and the memory controller 620, a memory card or a solid state disk (SSD) can be provided. The SRAM 621 serves as a working memory of a processing unit (CPU) 622. The host interface (host I / F) 623 includes a data exchange protocol of a host coupled to the memory system 600.

[0128] The error correction code block (ECC) 624 detects and corrects errors included in data read from the non-volatile memory device (NVM device) 610.

[0129] The memory interface (memory I / F) 625 interfaces with the non-volatile memory device (NVM device) 610 of the present embodiment. The processing unit (CPU) 622 performs a general control operation for data exchange of the memory controller 620.

[0130] Although not shown in the drawings, it would be obvious to those skilled in the art to which the embodiments pertain that the memory system 600 according to the embodiments can be additionally provided with a ROM storing code data for interfacing with a host. The non-volatile memory device (NVM device) 610 can be provided as a multi-chip package composed of a plurality of flash memory chips.

[0131] As described above, the memory system 600 according to the embodiments can be provided as a high-reliability storage medium having a low possibility of error occurrence. Specifically, the non-volatile memory device of the embodiments can be included in a memory system such as a solid state disk (SSD) that is currently being actively researched. In this case, the memory controller 620 can be configured to communicate with an external (e.g., a host) through one of various interface protocols such as a USB (Universal Serial Bus) protocol, an MMC (Multi Media Card) protocol, a PCI-E (Peripheral Component Interconnect Express) protocol, a SATA (Serial Advanced Technology Attachment) protocol, a PATA (Parallel Advanced Technology Attachment) protocol, a SCSI (Small Computer System Interface) protocol, an ESDI (Enhanced Small Disk Interface) protocol, and an IDE (Integrated Drive Electronics) protocol.

[0132] FIG. 25 is a block diagram schematically illustrating a computing system including a three-dimensional memory device according to an embodiment of the disclosure.

[0133] Referring to FIG. 25 , the computing system 700 according to the embodiments can include a memory system 710, a microprocessor (CPU) 720, a RAM 730, a user interface 740, and a modem 750 (such as a baseband chipset) electrically coupled to a system bus 760. In the case where the computing system 700 according to the embodiments is a mobile device, a battery (not shown) for supplying an operating voltage of the computing system 700 can be additionally provided. Although not shown in the drawings, it would be obvious to those skilled in the art to which the embodiments pertain that the computing system 700 according to the embodiments can be additionally provided with an application chipset, a camera image processor (CIS), a mobile DRAM, etc. For example, the memory system 710 can be configured as an SSD (Solid State Drive / Disk) using a non-volatile memory to store data. Further, the memory system 710 can be provided as a fusion flash (e.g., OneNAND flash).

[0134] While example embodiments of the disclosure have been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure. Therefore, the embodiments disclosed in the above and drawings should be considered in a descriptive sense only and not for purposes of limiting the technical scope. The technical scope of the disclosure is not limited by the embodiments and drawings. The spirit and scope of the disclosure should be construed by the appended claims and encompass all equivalents within the scope of the appended claims.

[0135] Cross Reference to Related Applications

[0136] This application claims priority to Korean Patent Application No. 10-2020-0128435, filed on October 6, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A three-dimensional memory device, the three-dimensional memory device comprising: A lower stack and an upper stack, which are stacked vertically and each include multiple word lines that are alternately stacked with multiple interlayer dielectric layers in the vertical direction. Each of the lower and upper stacks includes a first unit portion, a second unit portion, a connecting portion connecting the first and second unit portions, and a stepped portion extending parallel to the connecting portion between the first and second unit portions. The stepped portion includes multiple pad areas arranged in a stepped manner and corresponding to the multiple letter lines. Wherein, the connecting portion of the upper stack is configured to overlap with the stepped portion of the lower stack in the vertical direction, and the stepped portion of the upper stack is configured to overlap with the connecting portion of the lower stack in the vertical direction.

2. The three-dimensional memory device according to claim 1, further comprising: A plurality of first vertical through holes, the plurality of first vertical through holes passing vertically through the stepped portion of the lower stack; A plurality of second vertical through holes, the plurality of second vertical through holes passing vertically through the connecting portion of the lower stack; A plurality of third vertical vias, the plurality of third vertical vias passing vertically through the connecting portion of the upper stack and respectively connecting to the plurality of first vertical vias; as well as A plurality of fourth vertical vias, which pass vertically through the stepped portion of the upper stack and are respectively connected to the plurality of second vertical vias. The plurality of first vertical vias respectively correspond to the plurality of word lines of the lower stack, pass through the plurality of pad areas of the plurality of word lines, and are electrically connected to the corresponding plurality of word lines. The plurality of fourth vertical vias correspond to the plurality of word lines of the upper stack, pass through the plurality of pad areas of the plurality of word lines, and are electrically connected to the corresponding plurality of word lines.

3. The three-dimensional memory device according to claim 2, further comprising: A plurality of first dielectric patterns are defined between the outer walls of the plurality of first vertical vias and the outer walls of the plurality of second vertical vias and the plurality of letter lines of the lower stack, thereby isolating the plurality of first vertical vias and the plurality of second vertical vias from the plurality of letter lines of the lower stack; as well as Multiple second dielectric patterns are defined between the outer walls of the multiple third vertical vias and the outer walls of the multiple fourth vertical vias and the multiple letter lines of the upper stack, thereby isolating the multiple third vertical vias and the multiple fourth vertical vias from the multiple letter lines of the upper stack.

4. The three-dimensional memory device according to claim 3, further comprising: Multiple conductive hard mask patterns are respectively disposed on the multiple pad areas of the multiple word lines of the lower stack, and the multiple word lines of the lower stack are electrically connected to the corresponding multiple first vertical vias.

5. The three-dimensional memory device according to claim 4, further comprising: A dielectric layer covering the underlying stack and the plurality of conductive hard mask patterns. Each of the plurality of first vertical vias has an upper portion passing through the dielectric layer and a lower portion passing through the stepped portion of the lower stack, wherein the width of the upper portion is greater than the width of the lower portion.

6. The three-dimensional memory device according to claim 3, further comprising: Multiple conductive hard mask patterns are respectively disposed on the multiple pad areas of the multiple word lines of the upper stack, and the multiple word lines of the upper stack are electrically connected to the corresponding multiple fourth vertical vias.

7. The three-dimensional memory device according to claim 3, further comprising: Multiple hard mask patterns are respectively disposed on the multiple pad areas of the multiple word lines of the lower stack; as well as A dielectric layer covering the underlying stack and the plurality of hard mask patterns. Each of the plurality of first vertical vias is directly connected to the corresponding word line by passing through the dielectric layer and the hard mask pattern disposed on the pad area of ​​the corresponding word line.

8. The three-dimensional memory device according to claim 3, further comprising: Multiple hard mask patterns are respectively disposed on the multiple pad areas of the multiple word lines of the upper stack; as well as A dielectric layer covering the upper stack and the plurality of hard mask patterns. Each of the plurality of fourth vertical vias is directly connected to the corresponding word line by passing through the dielectric layer and the hard mask pattern disposed on the pad area of ​​the corresponding word line.

9. The three-dimensional memory device according to claim 3, wherein, Each of the plurality of first vertical vias includes a conductive pad portion disposed on the pad area of ​​the corresponding word line and connected to the corresponding word line.

10. The three-dimensional memory device according to claim 3, wherein, Each of the plurality of fourth vertical vias includes a conductive pad portion disposed on the pad area of ​​the corresponding word line and connected to the corresponding word line.

11. A method for manufacturing a three-dimensional memory device, the method comprising the steps of: A first pre-laminated material is formed by alternately stacking multiple first interlayer dielectric layers and multiple first sacrificial layers in the vertical direction; A first stepped portion is formed in the first pre-laminated material to expose the plurality of first sacrificial layers in a stepped manner; A plurality of first vertical through holes are formed through the first stepped portion and a plurality of second vertical through holes are formed through the first connecting portion of the first pre-laminated material, wherein the first connecting portion is arranged parallel to the first stepped portion of the first pre-laminated material; A second pre-laminated material is formed by alternately stacking multiple second interlayer dielectric layers and multiple second sacrificial layers on the first pre-laminated material; A second step portion is formed in the second pre-laminated material, which overlaps with the first connecting portion in the vertical direction and exposes the plurality of second sacrificial layers in a stepped manner; Multiple third vertical vias and multiple fourth vertical vias are formed. The multiple third vertical vias are connected to the multiple first vertical vias by passing through a second connecting portion that overlaps with the first step portion in the vertical direction of the second pre-laminated material. The multiple fourth vertical vias are connected to the multiple second vertical vias by passing through the second step portion. as well as The first and second sacrificial layers are replaced with electrode materials.

12. The method of claim 11, further comprising the step of: After the first step portion is formed, a plurality of hard mask patterns are formed on the exposed areas of the corresponding plurality of first sacrificial layers in the first step portion, each of the plurality of hard mask patterns having a through hole; A dielectric layer is formed covering the first pre-stack and the plurality of hard mask patterns; A plurality of first vertical holes are formed through the dielectric layer and the first pre-stack, the plurality of first vertical holes being disposed in the first stepped portion to communicate with through holes in the plurality of hard mask patterns respectively, and a plurality of second vertical holes are formed in the first connecting portion; Multiple horizontal trenches are formed by removing portions of the first sacrificial layer around the plurality of first vertical holes and portions of the first sacrificial layer around the plurality of second vertical holes; as well as A dielectric pattern is formed in the plurality of horizontal trenches. Specifically, as the plurality of first vertical holes and the plurality of second vertical holes are filled with conductive material, the plurality of first vertical vias and the plurality of second vertical vias are formed.

13. The method according to claim 12, wherein, The steps for forming the dielectric pattern include the following: Dielectric material is formed in the plurality of horizontal trenches, the plurality of first vertical holes, and the plurality of second vertical holes; A mask pattern is formed on the dielectric layer, the mask pattern having a plurality of first openings and a plurality of second openings, the plurality of first openings exposing dielectric material in the plurality of first vertical holes and the dielectric layer surrounding the plurality of first vertical holes, and the plurality of second openings exposing dielectric material in the plurality of second vertical holes; and The first vertical hole and the second vertical hole are exposed by etching the dielectric material and the dielectric layer using the mask pattern and the hard mask pattern as etching masks.

14. The method of claim 13, further comprising the step of: After exposing the plurality of first vertical holes and the plurality of second vertical holes, the plurality of first sacrificial layers immediately below the plurality of hard mask patterns are exposed by removing the plurality of hard mask patterns in the plurality of first vertical holes.

15. The method of claim 12, further comprising the step of: After the dielectric pattern is formed, and before the plurality of first vertical holes and the plurality of second vertical holes are filled with the conductive material, the plurality of hard mask patterns are removed. Specifically, in filling the plurality of first vertical holes and the plurality of second vertical holes with the conductive material, the space from which the plurality of hard mask patterns have been removed is filled with the conductive material.

16. The method of claim 11, further comprising the step of: After the second step portion is formed, a plurality of hard mask patterns are formed on the exposed areas of the corresponding plurality of second sacrificial layers in the second step portion, each of the plurality of hard mask patterns having a through hole; A dielectric layer is formed covering the second pre-stack and the plurality of hard mask patterns; A plurality of first vertical holes are formed through the dielectric layer and the second pre-laminated material. The plurality of first vertical holes are disposed in the second stepped portion to communicate with the through holes of the plurality of hard mask patterns respectively. A plurality of second vertical holes are formed in the second connecting portion. Multiple horizontal trenches are formed by removing portions of the second sacrificial layer around the plurality of first vertical holes and portions of the second sacrificial layer around the plurality of second vertical holes; as well as A dielectric pattern is formed in the plurality of horizontal trenches. Among them, as the plurality of first vertical holes and the plurality of second vertical holes are filled with conductive material, the plurality of third vertical vias and the plurality of fourth vertical vias are formed.

17. The method according to claim 16, wherein, The steps for forming the dielectric pattern include the following: Dielectric material is formed in the plurality of horizontal trenches, the plurality of first vertical holes, and the plurality of second vertical holes; A mask pattern is formed on the dielectric layer, the mask pattern having a plurality of first openings and a plurality of second openings, the plurality of first openings exposing dielectric material in the plurality of first vertical holes and the dielectric layer surrounding the plurality of first vertical holes, and the plurality of second openings exposing dielectric material in the plurality of second vertical holes; and The first vertical hole and the second vertical hole are exposed by etching the dielectric material and the dielectric layer using the mask pattern and the hard mask pattern as etching masks.

18. The method of claim 17, further comprising the step of: After exposing the plurality of first vertical holes and the plurality of second vertical holes, the plurality of second sacrificial layers immediately below the plurality of hard mask patterns are exposed by removing the plurality of hard mask patterns in the plurality of first vertical holes.

19. The method of claim 16, further comprising the step of: After the dielectric pattern is formed, and before the plurality of first vertical holes and the plurality of second vertical holes are filled with the conductive material, the plurality of hard mask patterns are removed. Specifically, in filling the plurality of first vertical holes and the plurality of second vertical holes with the conductive material, the space from which the plurality of hard mask patterns have been removed is filled with the conductive material.

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