Channel structure including tunneling layer and method for forming the same

Abstract

Embodiments of memory devices and methods for manufacturing the same are disclosed. In one example, a memory device includes: a substrate; a memory stack; and a channel structure. The memory stack includes alternating conductor and dielectric layers above the substrate. The channel structure extends through the memory stack into the substrate and includes a functional layer, the functional layer including a tunneling layer having a nitrogen weight percentage of no greater than approximately 28%.

Description

[0001] This application is a divisional application of the invention patent application with the application date of January 14, 2020, entitled “Channel structure including a tunneling layer with an adjusted nitrogen weight percentage and its formation method”, and application number 202080000132.8. Technical Field

[0002] Embodiments of the present disclosure relate to three-dimensional (3D) memory devices, weight fractions thereof, and methods of manufacturing the same. Background Art

[0003] Planar memory cells have been scaled to smaller sizes through improvements in process technology, circuit design, programming algorithms, and manufacturing techniques. However, as the feature size of memory cells approaches a lower limit, planar processing and manufacturing techniques become challenging and costly. As a result, the storage density of planar memory cells approaches an upper limit.

[0004] Three-dimensional (3D) memory architectures can address density limitations in planar memory cells. 3D memory architectures include a memory array and peripheral devices for controlling signals to and from the memory array. Summary of the Invention

[0005] Disclosed herein are embodiments of a channel structure including a tunneling layer having a tuned nitrogen weight percentage and methods of fabricating the same.

[0006] In one example, a memory device includes: a substrate; a memory stack; and a channel structure. The memory stack includes alternating conductor layers and dielectric layers above the substrate. The channel structure extends through the memory stack into the substrate and includes a functional layer having a tunneling layer, wherein the tunneling layer has a nitrogen weight percentage of no greater than approximately 28%.

[0007] In another example, a method for forming a memory device includes the following operations. First, a channel hole is formed in a stacked structure above a substrate. A barrier layer, a memory layer, and a tunnel layer are sequentially deposited radially from the sidewalls of the channel hole toward the center of the channel hole. A heat treatment is performed to adjust the nitrogen weight content in the tunnel layer to no more than approximately 28%. A semiconductor layer is deposited above the tunnel layer in the channel hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure.

[0009] Figure 1 A schematic diagram illustrating a cross-section of a portion of a channel structure in a 3D memory device according to some embodiments.

[0010] Figure 2 An annealing apparatus used in various embodiments of the present disclosure is shown.

[0011] Figures 3A to 3D An exemplary fabrication process for forming a channel structure having a tunneling layer with a reduced nitrogen weight percentage is shown, in accordance with some embodiments.

[0012] Figure 4 The weight percentage of nitrogen formed under different annealing conditions according to some embodiments is shown.

[0013] Figure 5 The weight percentages of nitrogen and oxygen formed under different annealing conditions are shown according to some embodiments.

[0014] Figure 6 A flow chart illustrating an exemplary fabrication process for forming a channel structure having an exemplary tunneling layer with a reduced nitrogen weight percentage is shown, in accordance with some embodiments.

[0015] Figures 7A-7C Exemplary parameter adjustments during an annealing process are shown in accordance with some embodiments.

[0016] Embodiments of the present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0017] Although specific configurations and arrangements have been discussed, it will be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure may also be used in a variety of other applications.

[0018] It should be noted that references to "one embodiment," "an embodiment," "example embodiment," "some embodiments," etc., in the application documents indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes that particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, whether or not explicitly described, it is within the knowledge of those skilled in the art to modify that feature, structure, or characteristic in connection with other embodiments.

[0019] Generally, terminology is understood at least in part based on usage in context. For example, the term "one or more," as used herein, may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" may again be understood to convey either singular usage or plural usage, depending at least in part on the context. Additionally, the term "based on" may be understood to not necessarily be intended to convey an exclusive set of factors, and may alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0020] It will be readily understood that the meaning of “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, such that “on” means not only “directly on” (something), but also includes “on” (something) with intervening features or layers therebetween, and “over” or “over” means not only “over” or “on” (something), but also can include “over” or “over” (something) with no intervening features or layers therebetween (i.e., directly on something).

[0021] Furthermore, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," etc., may be used for ease of description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0022] As used herein, the term "substrate" refers to a material onto which subsequent layers of material are added. The substrate itself can be patterned. The material added atop the substrate can be patterned, or the material added atop the substrate can remain unpatterned. Furthermore, the substrate can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be composed of a non-conductive material such as glass, plastic, or a sapphire wafer.

[0023] As used herein, the term "layer" refers to a portion of a material comprising an area having a thickness. A layer can extend over the entirety of an underlying or overlying structure, or can have a width smaller than the width of an underlying or overlying structure. In addition, a layer can be a region of a continuous structure having a thickness less than that of a homogeneous or heterogeneous continuous structure. For example, a layer can be located between any pair of horizontal planes between the top surface and the bottom surface of a continuous structure, or between any pair of horizontal planes at the top surface and the bottom surface of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above it, and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductors and a contact layer (wherein interconnect lines and / or via contacts are formed) and one or more dielectric layers.

[0024] As used herein, the term "nominal / nominally" refers to a desired or target value for a characteristic or parameter of a component or process operation that is set during the design phase of a product or process, together with a range of values ​​above and / or below the desired value. The range of values ​​can be due to slight variations in manufacturing processes or tolerances. As used herein, the term "approximately" indicates a value of a given quantity that can vary based on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term "approximately" can indicate that the value of a given quantity can vary, for example, within 10-30% of that value (e.g., ±10%, ±20%, or ±30% of that value).

[0025] As used herein, the term "3D NAND memory string" refers to a vertically-oriented string of memory cell transistors connected in series on a laterally-oriented substrate such that the string of memory cell transistors extends in a vertical direction relative to the substrate. As used herein, the term "vertical" means nominally perpendicular to a lateral surface of the substrate.

[0026] As used herein, the terms "stairs," "steps," and "levels" are used interchangeably. As used herein, a staircase structure refers to a set of surfaces comprising at least two horizontal surfaces and at least two vertical surfaces, such that each horizontal surface is adjacent to a first vertical surface extending upward from a first edge of the horizontal surface and adjacent to a second vertical surface extending downward from a second edge of the horizontal surface. "Stairs" refers to the vertical offset in height of a set of adjacent surfaces.

[0027] In a 3D memory device, a memory cell is formed at the intersection of a gate electrode and a 3D NAND memory string. A 3D NAND memory string typically includes a channel structure having a barrier layer, a storage layer, a tunnel layer, and a semiconductor layer arranged radially from the sidewalls of the channel structure to the center of the channel structure.

[0028] The tunneling layer usually comprises silicon oxynitride (SiO x N y , also referred to herein as "SiON"), a dielectric material that provides / determines the nitrogen weight percentage (wt%, referred to as "mass percentage") in the tunneling layer. The nitrogen weight percentage is critical to the electrical properties and film quality of the tunneling layer. It is therefore important to form a tunneling layer with high film quality and the desired nitrogen weight percentage. In conventional device manufacturing, the tunneling layer is formed by deposition without any post-deposition processing, and the adjustment of the nitrogen weight percentage in the tunneling layer may be limited, for example, typically in the range of about 28% to about 40%. Defects in the tunneling layer may not be repairable. In other words, it may be difficult to adjust the nitrogen weight percentage in the tunneling layer and simultaneously obtain the desired film quality. That is, the process window for controlling the nitrogen weight percentage in the tunneling layer is relatively small.

[0029] According to various embodiments of the present disclosure, a 3D memory device having a channel structure is provided, the channel structure having a tunnel layer with a reduced nitrogen weight percentage. The range of the nitrogen weight percentage in the disclosed tunnel layer can be lower than the range of the nitrogen weight percentage in a conventionally formed tunnel layer, so that the disclosed method can be used to increase the range of the nitrogen weight percentage in the tunnel layer, thereby making it easier to adjust the nitrogen weight percentage in the tunnel layer. That is, the process window for controlling the nitrogen weight percentage in the tunnel layer can be expanded, especially at the lower end. According to an embodiment, in order to form the tunnel layer, an annealing process is performed before depositing the semiconductor layer to reduce the nitrogen weight percentage in the tunnel layer and improve the film quality of the tunnel layer. Various parameters of the annealing process can be controlled and adjusted to produce a tunnel layer with a desired nitrogen weight percentage.

[0030] In order to form the desired atmosphere for the annealing process, in some embodiments, oxygen is introduced into the reactor chamber; and in some embodiments, a mixture of oxygen and hydrogen chloride gas is introduced into the reactor chamber. The flow rate of oxygen can be higher than the flow rate of hydrogen chloride gas. The annealing time period can be controlled in the range of about 30 minutes to about 120 minutes. The annealing temperature can be controlled in the range of about 800 degrees Celsius to about 950 degrees Celsius. The resulting tunneling layer can have a nitrogen weight percentage of about 10% to about 28%, which is lower than the nitrogen weight percentage in conventionally formed tunneling layers. At the same time, the annealing process can reduce the number of defects in the tunneling layer and / or allow the distribution of nitrogen atoms to be more uniform, thereby improving the film quality of the tunneling layer.

[0031] Figure 1 1 shows a cross-sectional view of a portion of a channel structure 100 according to some embodiments. The channel structure 100 may be part of a 3D NAND memory string extending in a memory stack comprising a plurality of interleaved conductor layers and dielectric layers. The conductor layer serves as a gate electrode (e.g., 101) of the memory string. Figure 1 As shown, gate electrode 101 forms contact with the channel structure. For simplicity, a portion of the channel structure is depicted, shown as element 106, which includes a barrier layer 102, a reservoir layer 103, a tunneling layer 104, and a semiconductor layer 105 (e.g., forming a semiconductor channel therein). The barrier layer 102, the reservoir layer 103, the tunneling layer 104, and the semiconductor layer 105 (e.g., forming a semiconductor channel therein) are arranged sequentially along the x-axis (e.g., horizontally) or in a direction substantially orthogonal to the direction in which the semiconductor layer 105 extends. In some embodiments, element 106 further includes a dielectric core (not shown), wherein the semiconductor layer 105 is positioned between the tunneling layer 104 and the dielectric core. The barrier layer 102, the reservoir layer 103, the tunneling layer 104, and the semiconductor layer 105 can extend along the z-axis (e.g., vertically). The gate electrode 101 can include any suitable conductive material, such as tungsten (W), cobalt (Co), aluminum (Al), copper (Cu), silicide, and / or doped polysilicon.

[0032] Each of the blocking layer 102, the storage layer 103, and the tunneling layer 104 may comprise a single layer structure or a multilayer structure. The blocking layer 102 reduces or prevents charge from escaping into the gate electrode 101, while the storage layer 103 traps the charge. The tunneling layer 104 facilitates charge tunneling under an appropriate bias voltage. The semiconductor layer 105, in which a semiconductor channel is formed, facilitates vertical charge transfer within the channel structure. The tunneling layer 104 may affect the electrical characteristics of the memory cell, such as programming / erase speed, leakage current, endurance, and data retention.

[0033] In some embodiments, barrier layer 102 includes a dielectric material, such as a dielectric metal oxide. For example, the first barrier layer may include a dielectric metal oxide having a sufficiently high dielectric constant (e.g., greater than 7.9). Examples of the first barrier layer include aluminum oxide, hafnium oxide, lanthanum oxide, yttrium oxide, tantalum oxide, silicates thereof, nitrogen-doped compounds thereof, and / or alloys thereof. Barrier layer 102 may include a dielectric material different from the aforementioned dielectric materials. For example, barrier layer 102 may include silicon oxide, silicon oxynitride, and / or silicon nitride.

[0034] Storage layer 103 may be a charge trapping layer formed on blocking layer 102. In some embodiments, storage layer 103 includes one or more insulating materials, such as silicon nitride and / or silicon oxynitride (SiON).

[0035] The tunneling layer 104 may include a dielectric material above the storage layer 103. The tunneling layer 104 may include a silicon oxide layer, one or more silicon oxynitride layers, a dielectric metal oxide, a dielectric metal oxynitride, a dielectric metal silicate, and / or alloys thereof. In some embodiments, the tunneling layer 104 includes a silicon oxide layer and multiple silicon oxynitride layers, wherein the silicon oxide layer is located between the multiple silicon oxynitride layers and the storage layer 103. In some embodiments, the thickness of the tunneling layer 104 is in a range from about 5 nm to about 20 nm, such as between 5 nm and 20 nm (e.g., 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, any range bounded by the lower end of any of these values, or any range bounded by any two of these values).

[0036] The tunneling layer 104 may have a nitrogen weight percentage (e.g., N wt %) of not greater than about 28%. In some embodiments, the nitrogen weight percentage is in a range from about 10% to about 28%, such as between 10% and 28% (e.g., 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19%, 20%, 21%, 22%, 23%, 24%, 25%, 26%, 27%, 28%, any range bounded by the lower end of any of these values, or any range bounded by any two of these values). For example, the nitrogen weight percentage can be between 10% and 28%, for example, between about 10% and about 20%, between about 12% and about 28%, between about 12% and about 20%, between about 14% and 20%, between about 12% and about 18%, between about 14% and about 18%, and between about 16% and about 18%. In some embodiments, the nitrogen weight percentage can be about 10%, 12%, 15%, 16.5%, 18%, 20%, 21.5%, 23%, 25%, 26.5%, and 28%. In some embodiments, the nitrogen weight percentage can be no greater than about 20%, such as between 10% and 20% (e.g., 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19%, 20%, any range bounded by the lower end of any of these values, or any range bounded by any two of these values). For example, the nitrogen weight percentage can be between 10% and 20%, such as between about 10% and about 18%, between about 12% and about 18%, between about 12% and about 16%, and between about 14% and about 16%. In some embodiments, the nitrogen weight percentage can be about 10%, 12%, 15%, 16.5%, 18%, and 20%. The nitrogen weight percentage of tunnel layer 104 can be reduced / adjusted compared to tunnel layers made by conventional processes that do not involve the annealing process disclosed herein.

[0037] In some embodiments, the oxygen weight percentage of the tunneling layer 104 can be adjusted to, for example, not less than about 32%. In some embodiments, the oxygen weight percentage is in a range of about 32% to about 46%, such as between 32% and 46% (e.g., 32%, 33%, 34%, 35%, 36%, 37%, 38%, 39%, 40%, 41%, 42%, 43%, 44%, 45%, 46%, any range bounded by the lower end of any of these values, or any range bounded by any two of these values). For example, the oxygen weight percentage can be between about 32% and 46%, for example, between about 32% and about 44%, between about 34% and about 46%, between about 34% and about 44%, between about 36% and about 44%, between about 36% and about 42%, between about 38% and about 42%, and between about 36% and about 40%. In some embodiments, the oxygen weight percentage may be approximately 32%, 34%, 35.5%, 37%, 39.5%, 41%, 42.5%, and 43%.

[0038] Semiconductor layer 105 may include one or more semiconductor materials, such as single element semiconductor materials, III-V compound semiconductor materials, II-VI compound semiconductor materials, and / or organic semiconductor materials. In some embodiments, semiconductor layer 105 includes a polysilicon layer. In some embodiments, element 106 further includes a dielectric core located above semiconductor layer 105. The dielectric core may include a suitable dielectric material and may completely or partially fill (without or with air gaps) the remaining space (in channel structure 100) surrounded by semiconductor layer 105. In some embodiments, the dielectric core includes SiO, for example, SiO of sufficiently high purity.

[0039] Figure 2 FIG. 2 shows an annealing apparatus 200 used in an annealing process for forming the channel structure 100 according to some embodiments. Specifically, the annealing apparatus 200 can be used to form the tunneling layer 104 in a 3D memory device before depositing the semiconductor layer 105. Figures 3A-3D An exemplary fabrication method 300 for forming a channel structure, eg, similar to channel structure 100 , is shown in accordance with some embodiments. Figure 6 A flow chart 600 of method 300 is shown, according to some embodiments. Figure 4 and Figure 5 The trend of the weight percentage of nitrogen and oxygen under various annealing conditions is shown. Figures 1 to 6 It should be understood that the operations shown in method 300 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some operations may be performed simultaneously or in conjunction with FIG. 3 and FIG. Figure 6 In some embodiments, method 300 is used to form Figure 1 The channel structure 100 in FIG.

[0040] Reference Figure 6 , the method 300 begins at operation 602 , where a channel hole is formed in a stack structure above a substrate. Figure 3A The corresponding structure is shown.

[0041] like Figure 3A As shown, one or more channel holes 310 are formed and extend in a stack structure 304 above a substrate 302. The stack structure 304 may be a dielectric stack including a plurality of alternating sacrificial layers 306 and a plurality of dielectric layers 308. The substrate 302 may include silicon (e.g., single crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable material.

[0042] The stacked structure 304 may include a plurality of dielectric layers 308 and a plurality of sacrificial layers 306 alternately stacked in a vertical direction. Each sacrificial layer 306 and the underlying dielectric layer 308 may form a sacrificial / dielectric pair. In some embodiments, the stacked structure 304 is a staircase structure (not shown) including a plurality of stairs, each of which includes one or more sacrificial / dielectric pairs. In some embodiments, the sacrificial layers 306 and the dielectric layer 308 may include different materials and thus may be selectively etched, for example, in a gate replacement process.

[0043] The stacked structure 304 can be formed by forming a material stack of multiple staggered initial dielectric layers and initial sacrificial layers on the substrate 302 and repeatedly etching the material stack using an etching mask (e.g., a patterned PR layer on the material stack). Each initial sacrificial layer and the initial dielectric layer below can be referred to as an initial dielectric pair. In some embodiments, one or more initial dielectric pairs can form a level / staircase. The initial sacrificial and dielectric layers can be formed by alternately depositing sacrificial material layers and dielectric material layers on the substrate 302. In some embodiments, the initial sacrificial layer includes silicon nitride, and the initial dielectric layer includes silicon oxide. The deposition of the initial sacrificial layer and the dielectric layer can include atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or any combination thereof.

[0044] The patterned PR layer is trimmed (e.g., etched incrementally and inwardly from the boundary of the material stack (typically from all directions)) and the patterned PR layer is used as an etch mask to etch the exposed portion of the material stack. The amount of trimmed PR can be directly related to (e.g., a determining factor for) the size of the staircase. The trimming of the PR layer can be achieved using appropriate etching, for example, an isotropic etching process, such as wet etching. One or more PR layers can be formed and trimmed continuously to form a stacked structure 304. After trimming the PR layer, each dielectric pair can be etched using a suitable etchant to remove a portion of both the initial sacrificial layer and the underlying initial dielectric layer. The etched initial sacrificial layer and initial dielectric layer can form a sacrificial layer 306 and a dielectric layer 308, respectively, which form stairs in the stacked structure 304. The PR layer (single layer or multiple layers) can then be removed. The etching of the material stack and the etch mask can include an anisotropic etching process such as dry etching and / or an isotropic etching process such as wet etching.

[0045] The channel holes 310 may be formed by an anisotropic etching process such as dry etching and / or an isotropic etching process such as wet etching. In some embodiments, deep reactive ion etching (DRIE) is used to form the channel holes 310. In some embodiments, the channel holes 310 each extend in the stacked structure 304 and expose the substrate 302. In some embodiments, the channel holes 310 extend into the substrate 302. Optionally, a semiconductor plug 322 may be formed at the lower portion of the channel hole 310 by epitaxial growth and / or deposition. The semiconductor plug 322 may contact the substrate 302 in the lower portion of the channel hole 310.

[0046] Return Reference Figure 6 After forming the channel holes, the method 300 proceeds to operation 604 , where a functional layer is formed, the functional layer including a barrier layer, a memory layer, and a tunneling layer sequentially deposited on a sidewall of each channel hole. Figure 3B The corresponding structure is shown.

[0047] like Figure 3B As shown, a barrier layer 312, functional layers including a storage layer 314, and a tunneling layer 316 may be sequentially deposited on the sidewalls of the channel hole 310. In some embodiments, the deposition of the barrier layer 312, the storage layer 314, and the tunneling layer 316 includes a thin film deposition process such as ALD, CVD, PVD, or any combination thereof. In some embodiments, the deposition of the barrier layer 312, the storage layer 314, and / or the tunneling layer 316 includes ALD. In some embodiments, the barrier layer 312, the storage layer 314, and the tunneling layer 316 are radially arranged from the sidewalls of the channel hole 310 toward the center of the channel hole 310. The tunneling layer 316 may be above the storage layer 314 and may be exposed in the channel hole 310.

[0048] Return Reference Figure 6 After depositing the barrier layer, the memory layer, and the tunneling layer, the method 300 proceeds to operation 606 where a thermal treatment is performed. Figure 3C The corresponding structure is shown.

[0049] like Figure 3C As shown, a thermal treatment may be performed. In some embodiments, the thermal treatment includes an annealing process. In some embodiments, the thermal treatment reduces the nitrogen weight percentage in tunneling layer 316, thereby forming an annealed tunneling layer 326 having a reduced nitrogen weight percentage. In some embodiments, the thermal treatment also causes the oxygen weight percentage in the annealed tunneling layer 326 to increase. In some embodiments, the thermal treatment repairs defects in tunneling layer 316 and improves the film quality of tunneling layer 316. For example, the annealed tunneling layer 326 may have a denser film. In some embodiments, a reactive gas, such as oxygen and / or hydrogen chloride gas, repairs dangling bonds and defects in tunneling layer 316. In some embodiments, the thermal treatment improves the electrical performance of the 3D memory device. For example, the annealed tunneling layer 326 may improve data retention in the 3D memory device. In some embodiments, the nitrogen weight percentage in the annealed tunneling layer 326 is reduced, such as to a range of approximately 10% to approximately 28%. In some embodiments, the nitrogen weight percentage is in a range of approximately 10% to approximately 20%. In some embodiments, the thermal treatment has little effect on the material composition of the storage layer 314 and the barrier layer 312 .

[0050] The heat treatment can be performed in the annealing device 200. Return to reference Figure 2The annealing apparatus 200 may include a furnace 202, a plurality of gas sources 204, a sample holder 208 for accommodating a plurality of samples 206, and a controller 214 for controlling various operations and parameters of the thermal process. The furnace 202 may include a resistively heated furnace that provides a reactor chamber 220 in which the samples are annealed. The annealing conditions in the reactor chamber 220 may be controlled by controlling various parameters, such as the annealing time period, annealing temperature, annealing pressure, gas flow rate, or any other parameters associated with the thermal process. These parameters and operations may be controlled by the controller 214, such as a computer and / or an operator. The gas source 204 provides a gas that creates the annealing atmosphere. In some embodiments, the gas source 204 provides at least oxygen. In some embodiments, the gas source 204 provides at least nitrogen. In some embodiments, the gas source 204 provides at least hydrogen. In some embodiments, the gas source 204 provides a mixture of oxygen, hydrogen chloride gas, and / or nitrogen. In some embodiments, the gases, such as oxygen, hydrogen chloride gas, and nitrogen, include any suitable gas containing the corresponding element and are not limited to a single element. Gases from gas source 204 can be introduced into furnace 202 through inlet 210 to mix and fill reactor chamber 220. Controller 214 can control the flow rates of oxygen and hydrogen chloride gases to achieve a desired annealing pressure and a desired flow rate ratio. In some embodiments, sample holder 208 comprises quartz. Gases are exhausted through exhaust port 212.

[0051] Sample 206, which may include, for example, a 3D memory device having stacked structure 304 and tunneling layer 316 formed within stacked structure 304, may be placed on sample holder 208 within reactor chamber 220 for thermal processing. In various embodiments, sample 206 may be placed horizontally and / or vertically within reactor chamber 220. Various parameters may be adjusted to achieve optimized results that can reduce the nitrogen weight percentage in tunneling layer 104 and maximize the range of nitrogen weight percentages within tunneling layer 104. The annealing temperature, controlled by, for example, controller 214, may be within a range of approximately 700 degrees Celsius to approximately 1000 degrees Celsius. In some embodiments, the annealing temperature is within a range of approximately 800 degrees Celsius to approximately 950 degrees Celsius. The annealing time period, controlled by, for example, controller 214, may be within a range of approximately 20 minutes to approximately 150 minutes. In some embodiments, the annealing time period is within a range of approximately 30 minutes to approximately 120 minutes. In some embodiments, the annealing pressure, controlled by controller 214, is approximately atmospheric pressure. In various embodiments, annealing parameters such as annealing temperature, annealing time period, and annealing pressure are flexibly adjusted based on the desired nitrogen weight percentage, and such values ​​should not be limited by the embodiments of the present disclosure.

[0052] In some embodiments, oxygen is introduced into the reactor chamber 220 via the inlet 210 by the controller 214 for thermal treatment. In some embodiments, a mixture of oxygen and hydrogen chloride gas is introduced into the reactor chamber 220 via the inlet 210 by the controller 214. In some embodiments, thermal treatment using a mixture of hydrogen chloride gas and oxygen in an atmosphere can reduce the nitrogen weight percentage in the tunneling layer 104 to a greater extent than using only oxygen. In some embodiments, when the mixture is introduced, the flow rate of the oxygen is higher than the flow rate of the hydrogen chloride gas. In some embodiments, the flow rate of the oxygen is in a range of about 5 liters to about 10 liters per minute, and the flow rate of the hydrogen chloride gas is in a range of about 50 cubic centimeters (ccm) to about 150 ccm per minute. In some embodiments, when other annealing parameters (e.g., annealing pressure, annealing time period, and gases and their corresponding flow rates) remain the same, a higher annealing temperature results in a lower nitrogen weight percentage in the tunneling layer.

[0053] As an example, in Figure 4 and Figure 5 The weight percentage of nitrogen and / or oxygen formed under different annealing conditions is shown in FIG. Figure 4 A comparison of the weight percentage of nitrogen in the tunneling layer when using different gases in the atmosphere during an annealing process according to some embodiments is shown. The horizontal axis represents the depth of the tunneling layer, and the vertical axis represents the number of nitrogen (N) atoms per cubic centimeter. Figure 4 The trend of the nitrogen weight percentage as a function of the depth of the tunneling layer is thus shown and can be determined based on the characterization results of secondary ion mass spectroscopy (SIMS). Figure 4 (increasing from left to right in the figure) represents the distance along the x-axis from the tunneling layer / semiconductor layer interface (or the exposed surface of the tunneling layer if the nitrogen weight percentage measurement is performed before the semiconductor layer is deposited) toward the reservoir layer. Figure 3B and Figure 3C As shown in FIG, depth represents, for example, the distance along the x-axis from the exposed surface of the tunneling layer 316 / 326 to a measurement point in the tunneling layer 316 / 326. The measurement point can be anywhere in the tunneling layer 316 / 326 up to the tunneling layer / storage layer interface. After the semiconductor layer 318 is deposited, as shown in FIG. Figure 3D As shown, the depth starts from the tunneling layer / semiconductor layer interface rather than the exposed surface of the tunneling layer 316 / 326. The depth is less than or equal to the thickness of the tunneling layer, which is in the range of about 5 nm to about 20 nm. Figure 4In the tunneling layer, (i) "As Dep" indicates the nitrogen weight percentage without any annealing process; (ii) "Post N2 ANN" indicates the nitrogen weight percentage using N2; (iii) "Post N2O ANN" indicates the nitrogen weight percentage using N2O; (iv) "Post O2 ANN" indicates the nitrogen weight percentage using only O2; and (v) "Post HCL+O2 ANN" indicates the nitrogen weight percentage using a mixture of O2 and hydrogen chloride gas. In the annealing processes (i)-(v), other annealing parameters, such as annealing temperature, annealing pressure and annealing time period, may be the same. Figure 4 As shown in FIG, , annealing process (ii), which is an annealing process using only N2 (e.g., without any oxygen), has the highest nitrogen weight percentage compared to other annealing processes using O2 or an oxygen-containing gas. Using N2O for the annealing process results in a lower nitrogen weight percentage compared to using only O2 in the annealing process. The lowest nitrogen weight percentage can be achieved by using a mixture of O2 and hydrogen chloride gas in the annealing process.

[0054] Figure 5 The weight percentages of oxygen and nitrogen at different annealing time periods according to some embodiments are shown. The horizontal axis represents the depth of the tunneling layer, and the vertical axis represents the percentages of nitrogen (N) and oxygen (O). The depth of the tunneling layer can be explained in the same way as Figure 4 The explanations of are similar or identical and will not be repeated here. Figure 5 The trends of nitrogen weight percentage and oxygen weight percentage as a function of tunneling layer depth are shown and can be determined based on the characterization results of x-ray photoelectron spectroscopy (XPS). Figure 5 , in the tunneling layer, (i) "80min ANL N" represents the weight percentage of nitrogen under an annealing time period of 80 minutes; (ii) "50min ANL N" represents the weight percentage of nitrogen under an annealing time of 50 minutes; (iii) "Skip ANL N" represents the weight percentage of nitrogen without any annealing process; (iv) "80min ANL O" represents the weight percentage of oxygen under an annealing time period of 80 minutes; (ii) "50min ANL O" represents the weight percentage of oxygen under an annealing time period of 50 minutes; (iii) "Skip ANL O" represents the weight percentage of oxygen without any annealing process. In the annealing processes (i)-(vi), the annealing parameters such as annealing temperature, annealing pressure and gas may be the same. In some embodiments, a mixture of oxygen and hydrogen chloride gas is used to fill the reactor chamber 220 for annealing processes (i)-(vi). As Figure 5As shown, a longer annealing period can result in a lower nitrogen weight percentage and a higher oxygen weight percentage. The tunnel layer without any annealing process can have the highest nitrogen weight percentage and the lowest oxygen weight percentage. In some embodiments, the change in nitrogen weight percentage can gradually decrease as the annealing process proceeds.

[0055] In one example, the annealing temperature is about 800 degrees Celsius to about 900 degrees Celsius, the annealing time period is about 30 minutes, the annealing pressure is about standard atmospheric pressure, and oxygen and a mixture of oxygen and hydrogen chloride gas are introduced into the reactor chamber 220 for the annealing process. The nitrogen weight percentage obtained from the annealing process using only oxygen is about 22%, and the nitrogen weight percentage obtained from the annealing process using oxygen and hydrogen chloride gas is about 15%. In another example, as the annealing time period increases to about 80 minutes, the nitrogen weight percentage decreases to about 15% (using only oxygen) and 10% (using the mixture), respectively.

[0056] In some embodiments, a recess etching process is performed before or after the annealing process to remove corresponding portions of the tunneling layer 316 (or the annealed tunneling layer 326), the storage layer 314, and the barrier layer 312 below the channel hole 310 to expose the semiconductor plug 322 (or the substrate 302 if the semiconductor plug 322 is not formed). The recess etching process may include a suitable etching process, such as dry etching and / or wet etching.

[0057] Return Reference Figure 6 After the annealing process, the method 300 proceeds to operation 608 where a semiconductor layer and a dielectric core are subsequently deposited in the channel hole to completely or partially fill the channel hole. Figure 3D The corresponding structure is shown.

[0058] like Figure 3D As shown, a semiconductor layer 318 may be deposited over the annealed tunneling layer 325. The semiconductor layer 318 may be in contact with the substrate 302 (if the semiconductor plug 322 is not formed) or in contact with the semiconductor plug 322. A semiconductor channel may be formed in the semiconductor layer 318 and may be conductively connected to the substrate 302. In some embodiments, a dielectric core 320 is deposited over the semiconductor layer 318 to completely or partially fill the remaining space in the channel hole 310. The deposition of the semiconductor layer 318 and the dielectric core 320 may include a thin film deposition process such as ALD, CVD, PVD, or any combination thereof. A channel structure having the barrier layer 312, the storage layer 314, the annealed tunneling layer 326, the semiconductor layer 318, and the dielectric core 320 may be formed.

[0059] In some embodiments, a recess etch, such as a dry etch and / or a wet etch, is performed to remove the top of the channel structure and form another plug in the recessed area. The other plug can be formed by depositing a semiconductor material using one or more of ALD, CVD, PVD, or any combination thereof. The other plug can serve as an etch stop layer for the layers in the channel structure in subsequent manufacturing operations and can also serve as the drain of the corresponding 3D NAND memory string. In some embodiments, a gate replacement process is performed to replace the sacrificial layer 306 with multiple conductor layers, which serve as gate electrodes for the 3D NAND memory string. The sacrificial layer 306 can be removed by an isotropic etching process (e.g., wet etching) to form multiple lateral recesses in the stacked structure 304. Conductor material, such as W, Co, Al, Cu, silicide, and / or doped polysilicon, can be deposited to fill the lateral grooves to form a conductor layer. The deposition of the conductor material can include ALD, CVD, PVD, electroplating, or any combination thereof. A plurality of memory cells may be formed of gate electrodes and 3D NAND memory strings, and the stack structure 304 may therefore be referred to as a memory stack.

[0060] 7A to 7C Each shows an example of a parameter value adjusted as a function of time during a thermal treatment (e.g., an annealing process) according to some embodiments. The parameter can be adjusted in different, for example, continuous, time periods. In some embodiments, in each time period, the parameter changes as a linear function of time or maintains a constant value. The parameter can represent any suitable condition / variable that can be controlled / adjusted during the annealing process. For example, the parameter can include a processing pressure (e.g., an annealing pressure), a processing temperature (e.g., an annealing temperature), and / or a gas flow rate. These different conditions / variables can be adjusted to their respective desired values ​​independently or simultaneously. It should be understood that for ease of explanation, the symbols "t1", "t2", "t3", ..., can represent the same time or different times in each figure, and "P1", "P2", ..., can represent the same value or different values ​​in each figure. In some embodiments, the times such as t1, t2, t3, ..., are all less than the maximum processing time of the thermal treatment, and the parameter values ​​such as P1, P2, ..., are all less than the maximum parameter value of the thermal treatment. It should also be understood that, 7A to 7C The various exemplary trends in parameter adjustment are presented only and should not be construed as limiting the actual parameter values ​​and times associated with each parameter in the thermal process. For example, the process pressure and process temperature may be adjusted independently or simultaneously and may follow the same trend or different trends. The change from one parameter value to another and / or a single parameter value may be linear, exponential, and / or parabolic.

[0061] As an example, in Figure 7AIn the example, the parameter value may be P1 in the time period (t1, t2), increase from P1 to P2 in the time period (t2, t3), maintain P2 in the time period (t3, t4), increase from P2 to P3 in the time period (t4, t5), maintain P3 in the time period (P5, P6), decrease from P3 to P1 in the time period (t6, t7), and maintain P1 starting from t7. In another example, Figure 7B In some embodiments, the parameter value may be P1 during the time period (t1, t2), increase from P1 to P2 during the time period (t2, t3), and remain at P2 during the time period (t3, t4). Figure 7B In , P represents the annealing temperature. In some embodiments, P1 represents about 800 degrees Celsius to about 850 degrees Celsius, P2 represents about 850 degrees Celsius to about 900 degrees Celsius, the time period (t1, t2) represents about 30 minutes, the time period (t2, t3) represents about 5 minutes, and the time period (t3, t4) represents about 30 minutes. As a further example, in Figure 7C In the embodiment, the parameter value may be maintained at P4 during the time period (t1, t2), decreased from P4 to P3 during the time period (t2, t3), decreased from P3 to P2 during the time period (t3, t4), decreased from P2 to P1 during the time period (t4, t5), and maintained at P1 from t5 onwards. In various embodiments, the actual value of the parameter value and the change of the parameter value over time will be affected by the annealing conditions and flexibly controlled according to the desired material properties (e.g., the nitrogen weight percentage of the tunneling layer), and should not be limited by the embodiments of the present disclosure.

[0062] According to an embodiment of the present disclosure, a memory device includes: a substrate; a memory stack; and a channel structure. The memory stack includes alternating conductor layers and dielectric layers above the substrate. The channel structure extends through the memory stack into the substrate and includes a functional layer having a tunneling layer, wherein the tunneling layer has a nitrogen weight percentage of no greater than approximately 28%.

[0063] In some embodiments, the functional layer further includes a barrier layer and a storage layer. The barrier layer, the storage layer, and the tunneling layer are radially arranged from the sidewall to the center of the channel structure.

[0064] In some embodiments, the nitrogen weight percentage is in a range from about 10% to about 28%.

[0065] In some embodiments, the weight percentage of oxygen in the tunneling layer is in a range from about 32% to about 46%.

[0066] In some embodiments, the channel structure further includes: a semiconductor layer above the tunneling layer; and a dielectric core above the semiconductor layer and filling the channel structure.

[0067] In some embodiments, the tunneling layer includes silicon oxynitride.

[0068] In some embodiments, the tunneling layer includes a composite structure including a plurality of silicon oxynitride layers.

[0069] In some embodiments, the memory device further includes a semiconductor plug in contact with the substrate and the channel structure.

[0070] In some embodiments, the nitrogen weight percentage is no greater than about 20%.

[0071] According to an embodiment of the present disclosure, a method for forming a memory device includes the following operations. First, a channel hole is formed in a stacked structure above a substrate. A barrier layer, a memory layer, and a tunneling layer are sequentially deposited radially from the sidewalls of the channel hole toward the center of the channel hole. A heat treatment is performed to adjust the nitrogen weight content in the tunneling layer to no more than approximately 28%. A semiconductor layer is deposited above the tunneling layer in the channel hole.

[0072] In some embodiments, the thermal treatment reduces the nitrogen content by weight in the tunneling layer.

[0073] In some embodiments, performing the thermal treatment includes performing an annealing process.

[0074] In some embodiments, performing the annealing process includes providing an annealing atmosphere filled with oxygen.

[0075] In some embodiments, performing the annealing process includes providing the annealing atmosphere filled with a mixture of oxygen gas and hydrogen chloride gas.

[0076] In some embodiments, the flow rate of oxygen gas is higher than the flow rate of hydrogen chloride gas.

[0077] In some embodiments, providing the annealing process further comprises providing at least one of an annealing time period, an annealing temperature, or an annealing pressure. In some embodiments, the annealing time period is in a range of about 20 minutes to about 150 minutes. In some embodiments, the annealing temperature is in a range of about 700 degrees Celsius to about 1000 degrees Celsius. In some embodiments, the annealing pressure is about standard atmospheric pressure.

[0078] In some embodiments, the thermal treatment reduces the number of defects in the tunneling layer.

[0079] In some embodiments, performing the thermal treatment includes adjusting a parameter value of the thermal treatment over a continuous period of time. The parameter value includes at least one of a process pressure, a process temperature, or a flow rate of a gas.

[0080] In some embodiments, depositing the barrier layer, the storage layer, and the tunneling layer each includes atomic layer deposition (ALD).

[0081] In some embodiments, the annealing process is performed before deposition of the semiconductor layer.

[0082] In some embodiments, the method further includes depositing a dielectric core over the semiconductor layer to at least partially fill the channel hole.

[0083] The foregoing description of specific embodiments will reveal the general nature of the present disclosure, and by applying knowledge in the art, others can readily modify and / or adapt various applications of the specific embodiments without undue experimentation and without departing from the general concepts of the present disclosure. Therefore, based on the teachings and guidance presented herein, it is intended that such adjustments and modifications are within the meaning and scope of the equivalents of the disclosed embodiments. It should be understood that the wording or terminology herein is used for descriptive purposes only and not for limitation, so that the terms or wording of this application document will be interpreted by those skilled in the art based on the teachings and guidance.

[0084] The embodiments of the present disclosure are described above with reference to functional building blocks that illustrate the implementation of specific functions and relationships thereof. The boundaries of these functional building blocks are arbitrarily defined for the purposes of this description. Alternative boundaries can be defined so long as the specified functions and relationships are appropriately performed.

[0085] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0086] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A storage device comprising: a memory stack comprising alternating conductor and dielectric layers; as well as a channel structure extending through the memory stack, wherein the channel structure includes a functional layer, and the functional layer includes a tunneling layer; The tunneling layer is obtained by heat treating a deposited tunneling layer; through the heat treatment, the nitrogen weight percentage of the tunneling layer is reduced relative to the nitrogen weight percentage of the deposited tunneling layer and is reduced to no more than 28%.

2. The memory device according to claim 1, wherein The functional layer further includes a barrier layer and a storage layer, and the barrier layer, the storage layer, and the tunnel layer are radially arranged from a sidewall to a center of the channel structure.

3. The memory device according to claim 1, wherein The nitrogen weight percentage is in the range of 10% to 28%.

4. The memory device according to any one of claims 1 to 3, wherein: The weight percentage of oxygen in the tunneling layer is in a range of 32% to 46%.

5. The memory device according to any one of claims 1 to 3, wherein: The channel structure further includes: a semiconductor layer above the tunneling layer; and A dielectric core is over the semiconductor layer and fills the trench structure.

6. The memory device according to any one of claims 1 to 3, wherein: The tunneling layer includes silicon oxynitride.

7. The memory device according to any one of claims 1 to 3, wherein: The tunneling layer includes a composite structure including a plurality of silicon oxynitride layers.

8. The memory device according to any one of claims 1 to 3, further comprising a substrate, the alternating conductor and dielectric layers being above the substrate. 9 . The memory device of claim 8 , the channel structure extending through the memory stack to the substrate. 10 . The memory device according to claim 8 , further comprising a semiconductor plug in contact with the substrate and the channel structure.

11. The memory device according to any one of claims 1 to 3, wherein: The nitrogen weight percentage is not greater than 20%.

12. A method for forming a memory device, comprising: forming a channel hole in the stack structure above the substrate; Depositing a barrier layer, a storage layer, and a tunneling layer in radial order from the sidewall of the channel hole toward the center of the channel hole; performing a heat treatment on the deposited tunnel layer to adjust the nitrogen weight content in the tunnel layer to be no more than 28%; as well as A semiconductor layer is deposited over the tunneling layer in the channel hole.

13. The method according to claim 12, wherein: Performing the heat treatment includes performing an annealing process.

14. The method according to claim 13, wherein Performing the annealing process includes providing an annealing atmosphere filled with oxygen.

15. The method according to claim 14, wherein Performing the annealing process includes providing the annealing atmosphere filled with a mixture of oxygen and hydrogen chloride gases.

16. The method according to claim 15, wherein The flow rate of oxygen gas is higher than the flow rate of hydrogen chloride gas.

17. The method according to claim 13, wherein: Providing the annealing process further comprises providing at least one of an annealing time period, an annealing temperature, or an annealing pressure, and wherein, The annealing time period is in the range of 20 minutes to 150 minutes; The annealing temperature is in the range of 700 degrees Celsius to 1000 degrees Celsius; and The annealing pressure is approximately standard atmospheric pressure.

18. The method according to claim 12, wherein: Performing the thermal treatment includes adjusting a parameter value of the thermal treatment over successive time periods, the parameter value including at least one of a process pressure, a process temperature, or a flow rate of a gas.

19. The method according to claim 12, wherein: Depositing the barrier layer, the storage layer, and the tunneling layer each includes atomic layer deposition (ALD).

20. The method according to claim 13, wherein The annealing process is performed before deposition of the semiconductor layer.

21. The method of claim 12, further comprising depositing a dielectric core over the semiconductor layer to at least partially fill the trench hole.

Images