Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor and Method of Manufacturing the Same

Abstract

The present invention relates to a silicon carbide metal oxide semiconductor field effect transistor and a manufacturing method thereof. The transistor includes first and second cells, which together include a drain electrode layer, an ohmic contact layer, a substrate layer, an epitaxial layer, an interlayer dielectric layer, and a source electrode layer. The first cell further includes a first deep well region, a second deep well region, a first shallow well region, a second shallow well region, a first source region, a second source region, a first gate oxide layer, and a first polysilicon gate. The second cell further includes a third deep well region, a fourth deep well region, a third shallow well region, a fourth shallow well region, a second gate oxide layer, a third gate oxide layer, a second polysilicon gate, and a third polysilicon gate. The transistor can not only ensure that it has advantages such as low short-circuit current density, high short-circuit withstand capacity, and long short-circuit time, but also can reduce the forward voltage drop of the body diode and the reverse leakage current of the Schottky diode at the same time.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor device manufacturing, and particularly relates to a silicon carbide metal oxide semiconductor field effect transistor and a manufacturing method thereof. Background Art

[0002] Power electronics technology has become one of the important supporting technologies in modern industrial society. Among them, silicon carbide metal oxide semiconductor field effect transistors (also known as SiC MOSFETs) are widely used in various fields such as electric vehicles, photovoltaic inverters, rail transit, wind power generation, and motor drives due to their high operating frequency, low switching losses, large power density, and the ability to miniaturize passive devices and heat dissipation components. Even so, existing silicon carbide metal oxide semiconductor field effect transistors still have defects, such as high short-circuit current density, low short-circuit withstand, short short-circuit time, and high forward voltage drop of the body diode. Therefore, it is necessary to improve them better. Summary of the Invention

[0003] In order to solve all or part of the above problems, the purpose of the present invention is to provide a silicon carbide metal oxide semiconductor field effect transistor and a manufacturing method thereof, so as to solve the problems of high short-circuit current density, low short-circuit withstand, short short-circuit time, and high forward voltage drop of the body diode in the prior art. This can not only ensure that the silicon carbide metal oxide semiconductor field effect transistor has advantages such as low short-circuit current density, high short-circuit withstand, and long short-circuit time, but also reduce the reverse leakage current of the Schottky diode while reducing the forward voltage drop of the body diode.

[0004] According to a first aspect of the present invention, there is provided a silicon carbide metal oxide semiconductor field effect transistor, which includes alternately arranged first and second cells. The first and second cells jointly include a drain electrode layer, an ohmic contact layer, a substrate layer, an epitaxial layer, an interlayer dielectric layer, and a source electrode layer arranged in a stacked manner. The first cell further includes: first and second deep well regions, both of which are formed in the epitaxial layer and are in contact with the interlayer dielectric layer; first and second shallow well regions, which are respectively formed in the first and second deep well regions; first and second source regions, which are respectively formed in the first and second deep well regions. The number of the first source regions is two, and the two first source regions are symmetric about the first shallow well region and are both in contact with the first shallow well region. The number of the second source regions is two, and the two second source regions are symmetric about the second shallow well region and are both in contact with the second shallow well region; a first gate oxide layer, which is formed in the interlayer dielectric layer and is in contact with the epitaxial layer, the first and second deep well regions; a first polysilicon gate, which is also formed in the interlayer dielectric layer and covers the gate oxide layer; the second cell includes: third and fourth deep well regions, both of which are formed in the epitaxial layer and are in contact with the interlayer dielectric layer; third and fourth shallow well regions, which are respectively formed in the third and fourth deep well regions; second and third gate oxide layers, which are both formed in the interlayer dielectric layer and respectively cover the third and fourth deep well regions; second and third polysilicon gates, which are respectively formed in the interlayer dielectric layer and respectively cover the second and third gate oxide layers; wherein, the source electrode layer includes a first settlement part that makes ohmic contact with both the first shallow well region and the first source region, a second settlement part that makes ohmic contact with both the second shallow well region and the second source region, a third settlement part that makes ohmic contact with the third shallow well region, a fourth settlement part that makes Schottky contact with the third deep well region, the fourth deep well region, and the epitaxial layer, and a fifth settlement part that makes ohmic contact with the fourth shallow well region. The interval between the third and fourth deep well regions is smaller than the interval between the first and second deep well regions.

[0005] Further, the interval between the third and fourth deep well regions is 1.0 - 3.0 μm.

[0006] Further, the ohmic contact is formed by aluminum, titanium, and / or nickel, and the thickness is 10 - 500 nm.

[0007] Further, the Schottky contact is formed by titanium, molybdenum, tungsten, nickel, and / or platinum, and the thickness is 10 - 500 nm.

[0008] Further, the substrate layer, the epitaxial layer, the first source region, and the second source region are all formed of an N-type silicon carbide semiconductor material, and the first, second, third, and fourth deep trench regions and the first, second, third, and fourth shallow trench regions are all formed of a P-type silicon carbide semiconductor material.

[0009] Further, the semiconductor doping concentration in the first, second, third, and fourth deep trench regions is 5e16 - 5e18 cm -3 , and the thickness is 0.5 - 3.0 μm; the semiconductor doping concentration in the first, second, third, and fourth shallow trench regions is 1e18 - 1e19 cm -3 , and the thickness is 0.5 - 1.5 μm; the semiconductor doping concentration in the first and second source regions is 5e18 - 2e19 cm -3 , and the thickness is 0.2 - 0.5 μm.

[0010] Further, the thickness of the substrate layer is 100 - 180 μm, and the resistivity is 0.01 - 0.03 Ω·cm; while the thickness of the epitaxial layer is 5 - 100 μm, and the doping concentration is 1e14 - 5e16 cm -3 .

[0011] Further, the material of the interlayer dielectric layer is one or any combination of silicon dioxide, silicon nitride, silicon oxynitride, borophosphosilicate glass, and borosilicate glass, and the thickness of the interlayer dielectric layer is 0.5 - 2 μm.

[0012] Further, the materials of the source electrode layer and the drain electrode layer are both aluminum, titanium, nickel, and / or silver. The thickness of the flat part of the source electrode layer for connecting the first, second, third, fourth, and fifth sedimentation parts is 2 - 5 μm, and the thickness of the drain electrode layer is 0.5 - 4 μm.

[0013] According to a second aspect of the present invention, there is provided a method for manufacturing a silicon carbide metal oxide semiconductor field effect transistor, which is the above-mentioned silicon carbide metal oxide semiconductor field effect transistor, and the steps thereof include: Step 1, preparing a substrate and fabricating an epitaxial layer on the substrate; Step 2, fabricating first, second, third, and fourth deep well regions on the epitaxial layer; Step 3, fabricating first and second source regions in the first and second deep well regions respectively; Step 4, fabricating first, second, third, and fourth shallow well regions in the first, second, third, and fourth deep well regions respectively; Step 5, fabricating first, second, and third gate oxide layers on the epitaxial layer and first, second, and third polysilicon gate electrodes covering the first, second, and third gate oxide layers in sequence; Step 6, fabricating an interlayer dielectric layer on the epitaxial layer capable of burying the first, second, and third gate oxide layers and the first, second, and third polysilicon gate electrodes; Step 7, fabricating a source electrode layer on the interlayer dielectric layer, making the source electrode layer have ohmic contact with the first shallow well region, the second shallow well region, the third shallow well region, the fourth shallow well region, the first source region, and the second source region, and also have Schottky contact with the third deep well region, the fourth deep well region, and the epitaxial layer; Step 8, thinning the substrate to form a substrate layer; Step 9, fabricating an ohmic contact layer on the substrate layer; Step 10, fabricating a drain electrode layer on the ohmic contact layer.

[0014] The silicon carbide metal oxide semiconductor field effect transistor (also referred to as this transistor) and the manufacturing method of this transistor provided by the present invention cancel the source regions included in the second cell, which is equivalent to improving the continuous source regions in the prior art into discontinuous source regions, so that the channel density can be reduced, the short-circuit current density can be decreased, the short-circuit tolerance can be enhanced, and the effect of increasing the short-circuit time can be achieved while the size of the silicon carbide metal oxide semiconductor field effect transistor remains unchanged. A Schottky contact is formed on the epitaxial layer between the third deep well region and the fourth deep well region in this transistor, and the interval between the third deep well region and the fourth deep well region with Schottky contact is smaller than the interval between the first deep well region and the second deep well region without Schottky contact, which is equivalent to integrating a Schottky diode on the basis of the prior art and enhancing the shielding effect of the electric field at the Schottky contact by the third deep well region and the fourth deep well region under reverse bias conditions. This can reduce the forward voltage drop of the body diode and the reverse leakage current of the Schottky diode at the same time. Therefore, the silicon carbide metal oxide semiconductor field effect transistor and its manufacturing method can solve the problems existing in the prior art, such as high short-circuit current density, low short-circuit tolerance, short short-circuit time, and high forward voltage drop of the body diode. At the same time, the structure of this transistor is simple, easy to assemble, safe and reliable in use, and convenient for implementation and popularization. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In the figures:

[0016] Figure 1 This is a partial structural schematic diagram of the silicon carbide metal oxide semiconductor field effect transistor according to an embodiment of the present invention;

[0017] Figure 2 shows Figure 1 the first cell at the position of line A-A in

[0018] Figure 3 shows Figure 1 the second cell at the position of line B-B in

[0019] In the drawings, like components are denoted by like reference numerals. The drawings are not drawn to actual scale. Detailed Embodiment

[0020] The present invention will be further described below with reference to the drawings.

[0021] As Figures 1 to 3 shown, a silicon carbide metal oxide semiconductor field effect transistor 100 of the present invention includes alternately arranged first cells 1 and second cells 2, wherein the first cells 1 and the second cells 2 together include a drain electrode layer 3, an ohmic contact layer 8, a substrate layer 4, an epitaxial layer 5, an interlayer dielectric layer 6, and a source electrode layer 7 which are stacked. As Figure 2 shown, the first cell 1 further includes a first deep well region 11 and a second deep well region 12 which are all formed in the epitaxial layer 5 and are connected to the interlayer dielectric layer 6, a first shallow well region 13 formed in the first deep well region 11, a second shallow well region 14 formed in the second deep well region 12, two first source regions 15 formed in the first deep well region 11, two second source regions 16 formed in the second deep well region 12, and a first gate oxide layer 17 formed in the interlayer dielectric layer 6 and connected to the epitaxial layer 5, the first deep well region 11, and the second deep well region 12, and a first polysilicon gate 18 formed in the interlayer dielectric layer 6 and covering the first gate oxide layer 17. Among them, the two first source regions 15 are symmetric with respect to the first shallow well region 13 and are both connected to the first shallow well region 13, and the two second source regions 16 are symmetric with respect to the second shallow well region 14 and are both connected to the second shallow well region 14. As Figure 3As shown in the figure, the second cell 2 includes a third deep well region 21 and a fourth deep well region 22 that are all formed in the epitaxial layer 5 and are in contact with the interlayer dielectric layer 6, a third shallow well region 23 formed in the third deep well region 21, a fourth shallow well region 24 formed in the fourth deep well region 22, a second gate oxide layer 25 formed in the interlayer dielectric layer 6 and covering the third deep well region 21, a third gate oxide layer 26 formed in the interlayer dielectric layer 6 and covering the fourth deep well region 22, a second polysilicon gate 27 formed in the interlayer dielectric layer 6 and covering the second gate oxide layer 25, and a third polysilicon gate 28 formed in the interlayer dielectric layer 6 and covering the third gate oxide layer 26. Among them, the source electrode layer 7 includes a first settling portion 71 that makes ohmic contact with both the first shallow well region 13 and the first source region 15, a second settling portion 72 that makes ohmic contact with both the second shallow well region 14 and the second source region 16, a third settling portion 73 that makes ohmic contact with the third shallow well region 23, a fourth settling portion 74 that makes Schottky contact with both the third deep well region 21, the fourth deep well region 22, and the epitaxial layer 5, and a fifth settling portion 75 that makes ohmic contact with the fourth shallow well region 24. At the same time, the interval between the third deep well region 21 and the fourth deep well region 22 is smaller than the interval between the first deep well region 11 and the second deep well region 12. In a preferred embodiment, the interval between the third deep well region 21 and the fourth deep well region 22 is 1.0 - 3.0 μm.

[0022] For the silicon carbide metal oxide semiconductor field effect transistor 100 of this embodiment (also referred to as this transistor 100), the source regions included in the second cell 2 are cancelled, which is equivalent to improving the continuous source region in the prior art to a discontinuous source region. This enables the channel density to be reduced, the short - circuit current density to be decreased, the short - circuit tolerance to be enhanced, and the short - circuit time to be increased, while the size of the silicon carbide metal oxide semiconductor field effect transistor 100 remains unchanged. A Schottky contact is formed on the epitaxial layer between the third deep well region 21 and the fourth deep well region 22 in this transistor 100, and the interval between the third deep well region 21 and the fourth deep well region 22 with the Schottky contact is smaller than the interval between the first deep well region 11 and the second deep well region 12 without the Schottky contact. This is equivalent to integrating a Schottky diode on the basis of the prior art and enhancing the shielding effect of the electric field at the Schottky contact by the third deep well region 21 and the fourth deep well region 22 under reverse - bias conditions. This can reduce the forward voltage drop of the body diode and the reverse leakage current of the Schottky diode at the same time. Therefore, the silicon carbide metal oxide semiconductor field effect transistor 100 can solve the problems existing in the prior art, such as high short - circuit current density, low short - circuit tolerance, short short - circuit time, and high forward voltage drop of the body diode. At the same time, the structure of this transistor 100 is simple, easy to assemble, safe and reliable in use, and convenient for implementation and popularization.

[0023] In this embodiment, both the source electrode layer 7 and the drain electrode layer 3 are prepared from materials such as aluminum, titanium, nickel, and / or silver through a magnetron sputtering or evaporation process. The ohmic contact is formed by aluminum, titanium, and / or nickel, and the Schottky contact is formed by titanium, molybdenum, tungsten, nickel, and / or platinum. The thickness of the flat portion of the source electrode layer 7 for connecting the first settling portion 71, the second settling portion 72, the third settling portion 73, the fourth settling portion 74, and the fifth settling portion 75 is 2 - 5 μm. The thicknesses of the ohmic contacts between the first settling portion 71 and the first shallow trench region 13 and the first source region 15, between the second settling portion 72 and the second shallow trench region 14 and the second source region 16, between the third settling portion 73 and the third shallow trench region 23, between the fifth settling portion 75 and the fourth shallow trench region 24, and between the drain electrode layer 3 and the substrate layer 4 are all 10 - 500 nm. The thickness of the Schottky contact between the fourth settling portion 74 and the third deep trench region 21, the fourth deep trench region 22, and the epitaxial layer 5 is 10 - 500 nm. In a preferred embodiment, the materials of both the source electrode layer 7 and the drain electrode layer 3 are aluminum-titanium-nickel-silver laminated metal with low cost and good performance.

[0024] In this embodiment, the substrate layer 4, the epitaxial layer 5, the first source region 15, and the second source region 16 are all formed from N-type silicon carbide semiconductor material. The first deep trench region 11, the second deep trench region 12, the third deep trench region 21, and the fourth deep trench region 22, as well as the first shallow trench region 13, the second shallow trench region 14, the third shallow trench region 23, and the fourth shallow trench region 24, are all formed from P-type silicon carbide semiconductor material. The silicon carbide metal oxide semiconductor field effect transistor 100 can have advantages such as high voltage resistance, high temperature resistance, low operating loss, and high-frequency switching due to the use of silicon carbide semiconductor material with a large bandgap, high breakdown field strength, high saturated electron drift velocity, and high thermal conductivity.

[0025] In this embodiment, the semiconductor doping concentrations in the first deep trench region 11, the second deep trench region 12, the third deep trench region 21, and the fourth deep trench region 22 are all 5e16 - 5e18 cm -3 , and the thicknesses are all 0.5 - 3.0 μm; the semiconductor doping concentrations in the first shallow trench region 13, the second shallow trench region 14, the third shallow trench region 23, and the fourth shallow trench region 24 are all 1e18 - 1e19 cm -3 , and the thicknesses are all 0.5 - 1.5 μm; the semiconductor doping concentrations in the first source region 15 and the second source region 16 are all 5e18 - 2e19 cm -3 , and the thicknesses are all 0.2 - 0.5 μm. When manufacturing the corresponding regional structures according to the above requirements, the silicon carbide metal oxide semiconductor field effect transistor 100 has a better comprehensive effect.

[0026] In this embodiment, the thickness of the substrate layer 4 is 100 - 180 μm, and the resistivity is 0.01 - 0.03 Ω·cm; while the thickness of the epitaxial layer 5 is 5 - 100 μm, and the doping concentration is 1e14 - 5e16 cm -3 .

[0027] In this embodiment, the material of the interlayer dielectric layer 6 is one or any combination of silicon dioxide, silicon nitride, silicon oxynitride, borophosphosilicate glass, and borosilicate glass, and the thickness of the interlayer dielectric layer 6 is 0.5 - 2 μm.

[0028] According to the manufacturing method of the silicon carbide metal oxide semiconductor field effect transistor 100 provided by the present invention, its steps include: Step 1, prepare a substrate and fabricate an epitaxial layer 5 on the substrate; Step 2, fabricate a first deep well region 11, a second deep well region 12, a third deep well region 21, and a fourth deep well region 22 on the epitaxial layer 5; Step 3, fabricate a first source region 15 and a second source region 16 in the first deep well region 11 and the second deep well region 12 respectively; Step 4, fabricate a first shallow well region 13, a second shallow well region 14, a third shallow well region 23, and a fourth shallow well region 24 in the first deep well region 11, the second deep well region 12, the third deep well region 21, and the fourth deep well region 22 respectively; Step 5, fabricate a first gate oxide layer 17, a second gate oxide layer 25, and a third gate oxide layer 26 on the epitaxial layer and a first polysilicon gate 18, a second polysilicon gate 27, and a third polysilicon gate 28 covering the first gate oxide layer 17, the second gate oxide layer 25, and the third gate oxide layer 26 in sequence; Step 6, fabricate an interlayer dielectric layer 6 on the epitaxial layer 5 that can bury the first gate oxide layer 17, the second gate oxide layer 25, the third gate oxide layer 26, the first polysilicon gate 18, the second polysilicon gate 27, and the third polysilicon gate 28; Step 7, fabricate a source electrode layer 7 on the interlayer dielectric layer 6, and ensure that the source electrode layer 7 has an ohmic contact with the first shallow well region 13, the second shallow well region 14, the third shallow well region 23, the fourth shallow well region 24, the first source region 15, and the second source region 16, and also has a Schottky contact with the third deep well region 21, the fourth deep well region 22, and the epitaxial layer 5; Step 8, thin the substrate and form it into a substrate layer 4; Step 9, fabricate an ohmic contact layer 8 on the substrate layer 4; Step 10, fabricate a drain electrode layer 3 on the ohmic contact layer 8.

[0029] In summary, the silicon carbide metal oxide semiconductor field effect transistor 100 and its manufacturing method according to the embodiments of the present invention can solve the problems existing in the prior art, such as high short - circuit current density, low short - circuit withstand capacity, short short - circuit time, and high forward voltage drop of the body diode. It can not only ensure that the silicon carbide metal oxide semiconductor field effect transistor has advantages such as low short - circuit current density, high short - circuit withstand capacity, and long short - circuit time, but also can reduce the reverse leakage current of the Schottky diode while reducing the forward voltage drop of the body diode.

[0030] In addition, terms such as "first", "second", etc. are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. In the description of the present invention, "a plurality of" means more than two unless otherwise specifically defined.

[0031] In this application, unless otherwise clearly specified and defined, terms such as "installed", "connected", "joined", "fixed", etc. shall be construed in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal connection of two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0032] The above are only the preferred embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily make changes or variations within the technical scope disclosed by the present invention, and such changes or variations should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims. As long as there is no structural conflict, the technical features mentioned in each embodiment can be combined in any way. The present invention is not limited to the specific embodiments disclosed in the text, but includes all technical solutions falling within the scope of the claims.

Claims

1. A silicon carbide metal oxide semiconductor field effect transistor includes first and second cells arranged alternately. The first and second cells together include a drain electrode layer, an ohmic contact layer, a substrate layer, an epitaxial layer, an interlayer dielectric layer, and a source electrode layer arranged in a stacked manner. It is characterized in that: The first cell further includes: first and second deep well regions, both of which are formed in the epitaxial layer and are in contact with the interlayer dielectric layer; first and second shallow well regions, which are respectively formed in the first and second deep well regions; first and second source regions, which are respectively formed in the first deep well region and the second deep well region. The number of the first source regions is two, and the two first source regions are symmetric about the first shallow well region and are both in contact with the first shallow well region. The number of the second source regions is two, and the two second source regions are symmetric about the second shallow well region and are both in contact with the second shallow well region; a first gate oxide layer, which is formed in the interlayer dielectric layer and is in contact with the epitaxial layer, the first and second deep well regions; a first polysilicon gate, which is also formed in the interlayer dielectric layer and covers the gate oxide layer; The second cell includes: third and fourth deep well regions, both of which are formed in the epitaxial layer and are in contact with the interlayer dielectric layer; third and fourth shallow well regions, which are respectively formed in the third and fourth deep well regions; second and third gate oxide layers, both of which are formed in the interlayer dielectric layer and respectively cover the third and fourth deep well regions; second and third polysilicon gates, which are respectively formed in the interlayer dielectric layer and respectively cover the second and third gate oxide layers; Wherein, the source electrode layer includes a first settling portion that makes ohmic contact with both the first shallow well region and the first source region, a second settling portion that makes ohmic contact with both the second shallow well region and the second source region, a third settling portion that makes ohmic contact with the third shallow well region, a fourth settling portion that makes Schottky contact with the third deep well region, the fourth deep well region, and the epitaxial layer, and a fifth settling portion that makes ohmic contact with the fourth shallow well region. The interval between the third and fourth deep well regions is less than the interval between the first and second deep well regions.

2. The silicon carbide metal oxide semiconductor field effect transistor according to claim 1, wherein The interval between the third and fourth deep well regions is 1.0 - 3.0 μm.

3. The silicon carbide metal oxide semiconductor field effect transistor according to claim 1, wherein The ohmic contact is formed by aluminum, titanium, and / or nickel, and the thickness is 10 - 500 nm.

4. The silicon carbide metal oxide semiconductor field effect transistor according to claim 1, wherein The Schottky contact is formed by titanium, molybdenum, tungsten, nickel, and / or platinum, and the thickness is 10 - 500 nm.

5. The silicon carbide metal oxide semiconductor field effect transistor according to any one of claims 1 to 4, characterized in that, The substrate layer, the epitaxial layer, the first source region, and the second source region are all formed of N-type silicon carbide semiconductor material, and the first, second, third, and fourth deep well regions and the first, second, third, and fourth shallow well regions are all formed of P-type silicon carbide semiconductor material.

6. The silicon carbide metal oxide semiconductor field effect transistor according to claim 5, characterized in that The semiconductor doping concentrations in the first, second, third, and fourth deep well regions are all 5e16 - 5e18 cm -3 , and the thicknesses are all 0.5 - 3.0 μm; the semiconductor doping concentrations in the first, second, third, and fourth shallow well regions are all 1e18 - 1e19 cm -3 , and the thicknesses are all 0.5 - 1.5 μm; the semiconductor doping concentrations in the first and second source regions are all 5e18 - 2e19 cm -3 , and the thicknesses are all 0.2 - 0.5 μm.

7. The silicon carbide metal oxide semiconductor field effect transistor according to claim 5, wherein The thickness of the substrate layer is 100 - 180 μm, and the resistivity is 0.01 - 0.03 Ω·cm; while the thickness of the epitaxial layer is 5 - 100 μm, and the doping concentration is 1e14 - 5e16 cm -3 .

8. The silicon carbide metal oxide semiconductor field effect transistor according to any one of claims 1 to 4, characterized in that, The material of the interlayer dielectric layer is one or any combination of silicon dioxide, silicon nitride, silicon oxynitride, borophosphosilicate glass, and borosilicate glass, and the thickness of the interlayer dielectric layer is 0.5 - 2 μm.

9. The silicon carbide metal oxide semiconductor field effect transistor according to claim 1, characterized in that, The materials of the source electrode layer and the drain electrode layer are both aluminum, titanium, nickel, and / or silver. The thickness of the flat part of the source electrode layer for connecting the first, second, third, fourth, and fifth sedimentation parts is 2 - 5 μm, and the thickness of the drain electrode layer is 0.5 - 4 μm.

10. A manufacturing method of a silicon carbide metal oxide semiconductor field effect transistor, the silicon carbide metal oxide semiconductor field effect transistor being the silicon carbide metal oxide semiconductor field effect transistor according to any one of claims 1 to 9, characterized in that, The steps include: Step 1: Prepare a substrate and fabricate an epitaxial layer on the substrate. Step 2: Fabricate first, second, third, and fourth deep well regions on the epitaxial layer. Step 3: Fabricate a first source region and a second source region in the first deep well region and the second deep well region respectively. Step 4: Fabricate first, second, third, and fourth shallow well regions in the first, second, third, and fourth deep well regions respectively. Step 5: Fabricate first, second, and third gate oxide layers on the epitaxial layer, and first, second, and third polysilicon gate electrodes covering the first, second, and third gate oxide layers in sequence. Step 6: Fabricate an interlayer dielectric layer on the epitaxial layer that can bury the first, second, and third gate oxide layers and the first, second, and third polysilicon gate electrodes. Step 7: Fabricate a source electrode layer on the interlayer dielectric layer, and make the source electrode layer have ohmic contact with the first shallow well region, the second shallow well region, the third shallow well region, the fourth shallow well region, the first source region, and the second source region, and also have Schottky contact with the third deep well region, the fourth deep well region, and the epitaxial layer. Step 8: Thinning the substrate to form a substrate layer. Step 9: Fabricate an ohmic contact layer on the substrate layer. Step 10: Fabricate a drain electrode layer on the ohmic contact layer.

Images