Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device suitable for suppressing latch-up is provided. In a mesa region sandwiched between adjacent active trenches, the third semiconductor layer has regions discretely arranged in a first direction in such a manner as to contact one of the adjacent active trenches and not contact the other active trench, and regions discretely arranged in the first direction in such a manner as to contact the other active trench and not contact one active trench. In the mesa region sandwiched between adjacent active trenches, the fourth semiconductor layer is arranged, in a plan view, between the third semiconductor layer on the side contacting one active trench and the third semiconductor layer on the side contacting the other active trench, and between the respective regions of the third semiconductor layer discretely arranged in the first direction.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. Background Art

[0002] From the viewpoint of energy saving, a switching device having a low turn-on voltage is sought. As a switching device having a low turn-on voltage, a trench gate type IGBT (Insulated Gate Bipolar Transistor) is cited. The structure of the trench gate type IGBT is disclosed in Patent Document 1.

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 2000-106434

[0004] In the structure of Patent Document 1, the width of the emitter layer is locally narrowed and the emitter layer is arranged in an H shape. However, at the intersection of the emitter layer arranged in an H shape, there are problems such as an increase in the spreading resistance and a decrease in the latch-up tolerance. Thus, the structure of Patent Document 1 is not necessarily suitable for suppressing latch-up. Summary of the Invention

[0005] An object of the present invention is to provide a semiconductor device suitable for suppressing latch-up and a method of manufacturing a semiconductor device suitable for suppressing latch-up for manufacturing the semiconductor device.

[0006] The semiconductor device of the present invention has a semiconductor substrate having a first main surface and a main surface opposite to the first main surface, i.e., a second main surface. A transistor is provided in a first element region of the semiconductor substrate. The semiconductor substrate in the first element region has: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type, which is disposed closer to the first main surface side than the first semiconductor layer; a third semiconductor layer of the first conductivity type, which is selectively disposed on the first main surface side of the second semiconductor layer; a first electrode electrically connected to the third semiconductor layer; and a fourth semiconductor layer having a higher impurity concentration of the second conductivity type than the second semiconductor layer, disposed between the second semiconductor layer and the first electrode. The semiconductor substrate in the first element region is provided with a plurality of first trenches penetrating the third semiconductor layer and the second semiconductor layer from the first main surface to reach the first semiconductor layer. When viewed from above, the plurality of first trenches each extend in a first direction, and the plurality of first trenches are arranged in a strip shape when viewed from above. At least a part of the plurality of first trenches are active trenches provided with gate electrodes in such a manner as to face the second semiconductor layer with a gate insulating film interposed therebetween in the first trench. The strip-shaped arrangement of the plurality of first trenches has a portion where the active trenches are adjacent to each other. In the mesa region sandwiched between the adjacent trenches, i.e., in the mesa region sandwiched between the adjacent active trenches, the third semiconductor layer has regions discretely arranged in the first direction in such a manner as to be in contact with one of the adjacent active trenches and not in contact with the other active trench, and regions discretely arranged in the first direction in such a manner as to be in contact with the other active trench and not in contact with one active trench. In the mesa region sandwiched between the adjacent active trenches, the fourth semiconductor layer is disposed, when viewed from above, between the third semiconductor layer on the contact side with one active trench and the third semiconductor layer on the contact side with the other active trench, and between the respective regions of the third semiconductor layer discretely arranged in the first direction.

[0007] Moreover, as one aspect of the manufacturing method of the semiconductor device of the present invention, it is a method for manufacturing the semiconductor device of the present invention. The second semiconductor layer is formed by a first ion implantation, the third semiconductor layer is formed by a second ion implantation, and the fourth semiconductor layer is formed by a third ion implantation. The masks used in the first ion implantation, the masks used in the second ion implantation, and the masks used in the third ion implantation are each different.

[0008] Effects of the Invention

[0009] The semiconductor device of the present invention is a semiconductor device in which a strip-shaped arrangement of a plurality of first trenches has portions where active trenches are adjacent to each other. In a mesa region that is sandwiched by adjacent trenches, i.e., a mesa region that is sandwiched by adjacent active trenches, the third semiconductor layer has regions that are discretely arranged in a first direction so as to be in contact with one of the adjacent active trenches and not in contact with the other active trench, and regions that are discretely arranged in the first direction so as to be in contact with the other active trench and not in contact with one active trench. In the mesa region that is sandwiched by adjacent active trenches, the fourth semiconductor layer is arranged, in a plan view, between the third semiconductor layer on the side in contact with one active trench and the third semiconductor layer on the side in contact with the other active trench, and between the respective regions of the third semiconductor layer that are discrete in the first direction. Thus, the semiconductor device of the present invention is a semiconductor device suitable for suppressing latch-up.

[0010] Further, regarding the manufacturing method of the semiconductor device of the present invention, as one aspect thereof, it is a method for manufacturing the semiconductor device of the present invention. The second semiconductor layer is formed by a first ion implantation, the third semiconductor layer is formed by a second ion implantation, and the fourth semiconductor layer is formed by a third ion implantation. The masks used in the first ion implantation, the masks used in the second ion implantation, and the masks used in the third ion implantation are all different. Thus, the manufacturing method of the semiconductor device of the present invention is a manufacturing method for manufacturing a semiconductor device suitable for suppressing latch-up. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a plan view of the semiconductor device of Embodiment 1.

[0012] Figure 2 It is a cross-sectional view of the semiconductor device of Embodiment 1.

[0013] Figure 3 It is a plan view of the semiconductor device of Embodiment 2.

[0014] Figure 4 It is a cross-sectional view of the semiconductor device of Embodiment 2.

[0015] Figure 5 It is a plan view of the semiconductor device of Embodiment 3.

[0016] Figure 6 It is a cross-sectional view of the semiconductor device of Embodiment 3.

[0017] Figure 7 It is a plan view of the semiconductor device of Embodiment 4.

[0018] Figure 8 It is a plan view of the semiconductor device of Embodiment 4.

[0019] Figure 9 It is a top view of the semiconductor device of Embodiment 5.

[0020] Figure 10 It is a top view of the semiconductor device of Embodiment 5.

[0021] Figure 11 It is a cross-sectional view of the semiconductor device of Embodiment 6.

[0022] Figure 12 It is a cross-sectional view of the semiconductor device of Embodiment 7.

[0023] Figure 13 It is a cross-sectional view of the semiconductor device of Embodiment 8.

[0024] Figure 14 It is a cross-sectional view of the semiconductor device of Embodiment 9.

[0025] Figure 15 It is a flowchart showing the manufacturing method of the semiconductor device of Embodiment 10.

[0026] Figure 16 It is a cross-sectional view showing the state of the manufacturing process of the semiconductor device of Embodiment 10.

[0027] Figure 17 It is a cross-sectional view showing the state of the manufacturing process of the semiconductor device of Embodiment 10.

[0028] Figure 18 It is a cross-sectional view showing the state of the manufacturing process of the semiconductor device of Embodiment 10.

[0029] Figure 19 It is a cross-sectional view showing the state of the manufacturing process of the semiconductor device of Embodiment 10.

[0030] Figure 20 It is a cross-sectional view showing the state of the manufacturing process of the semiconductor device of Embodiment 10.

[0031] Figure 21 It is a cross-sectional view showing the state of the manufacturing process of the semiconductor device of Embodiment 10.

[0032] Figure 22 It is a flowchart showing the manufacturing method of the semiconductor device of Embodiment 11.

[0033] Figure 23 It is a cross-sectional view showing the state of the manufacturing process of the semiconductor device of Embodiment 11.

[0034] Figure 24 It is a cross-sectional view showing the state of the manufacturing process of the semiconductor device of Embodiment 11. Detailed implementation mode

[0035] <Preface>

[0036] In the following description, n-type and p-type represent the conductivity types of semiconductors. In the present invention, the first conductivity type is n-type and the second conductivity type is p-type for description, but it is also possible to make the first conductivity type p-type and the second conductivity type n-type.

[0037] In addition, the drawings are schematically shown, and the mutual relationships of the sizes and positions of the images shown in different drawings are not necessarily accurately recorded and can be appropriately changed. In addition, in the following description, the same reference numerals are given to the same structural elements for illustration, and their names and functions are also the same. Therefore, their detailed descriptions may sometimes be omitted.

[0038] <A. Embodiment 1>

[0039] <A-1. Structure and operation>

[0040] In Figure 1 a top view of the semiconductor device 100 is shown, and in Figure 2 a cross-sectional view of the semiconductor device 100 taken along the line A-A of Figure 1 is shown.

[0041] The semiconductor device 100 has a semiconductor substrate 120, which has a first main surface 120a and a main surface on the side opposite to the first main surface 120a, that is, a second main surface 120b.

[0042] An IGBT is provided in the element region (the first element region) of the semiconductor substrate 120.

[0043] In the element region where the IGBT is provided, the semiconductor substrate 120 has: an n-type drift layer 1 (first semiconductor layer); a carrier accumulation layer 2 (eighth semiconductor layer) having an n-type impurity concentration higher than that of the drift layer 1 and provided on the first main surface 120a side of the drift layer 1; a p-type base layer 3 provided on the first main surface 120a side compared with the drift layer 1; an n-type emitter layer 4 (third semiconductor layer) selectively provided on the first main surface 120a side of the base layer 3; an emitter electrode 9 (first electrode) electrically connected to the emitter layer 4; a contact layer 5 (fourth semiconductor layer) having a higher p-type impurity concentration than the base layer 3 and disposed between the base layer 3 and the emitter electrode 9; a buffer layer 10 having a higher n-type impurity concentration than the drift layer 1 and disposed on the second main surface 120b side compared with the drift layer 1; a p-type collector layer 11 (fifth semiconductor layer) disposed on the second main surface 120b side compared with the buffer layer 10; and a collector electrode 12 (second electrode) disposed on the second main surface 120b side of the semiconductor substrate 120. The carrier accumulation layer 2 is provided between the drift layer 1 and the base layer 3. The contact layer 5 is selectively provided on the first main surface 120a side of the base layer 3.

[0044] The semiconductor substrate 120 is in Figure 2 the range from the emitter layer 4 and the contact layer 5 to the collector layer 11. The end portions on the third direction side of the emitter layer 4 and the contact layer 5 are the first main surface 120a, and the end portion on the side opposite to the third direction of the collector layer 11 is the second main surface 120b. The thickness of the semiconductor substrate 120 can be, for example, 80 μm to 200 μm.

[0045] In the element region where the IGBT is provided, a plurality of trenches (first trenches) penetrating the emitter layer 4 and the base layer 3 from the first main surface 120a to reach the drift layer 1 are provided in the semiconductor substrate 120. The plurality of trenches (first trenches) each extend in the first direction in a top view, and in addition, the plurality of active trenches 6 are arranged in a strip shape in a top view. The impurity concentration may continuously change at the boundary between the drift layer 1 and the carrier accumulation layer 2, but in this case, in the surface layer portion on the first main surface 120a side of the region combining the drift layer 1 and the carrier accumulation layer 2, a region where the impurity concentration is greater than or equal to 5 times the impurity concentration of the central portion of the drift layer 1 may be set as the carrier accumulation layer 2, and a region less than 5 times may be set as the drift layer 1.

[0046] In the present embodiment, a plurality of active trenches 6 are provided as the plurality of trenches (first trenches). In particular, the strip-shaped arrangement of the plurality of trenches (first trenches) has portions where the active trenches 6 are adjacent to each other.

[0047] An active gate electrode 8 is disposed in the active trench 6 so as to face the base layer 3 (second semiconductor layer) with a gate insulating film 7 therebetween.

[0048] An emitter electrode 9 is formed above the active gate electrode 8 with an interlayer insulating film 13 therebetween. The emitter layer 4 and the contact layer 5 are in contact with the emitter electrode 9 via a contact hole 14, which is a part of the opening in the interlayer insulating film 13, and the emitter layer 4 and the contact layer 5 are connected to the emitter electrode 9.

[0049] The collector layer 11 and the collector electrode 12 are electrically connected.

[0050] The drift layer 1 is an n-type semiconductor layer having, for example, arsenic (As) or phosphorus (P) as an n-type impurity, and the concentration of the n-type impurity is 1.0E+12 / cm 3 ~1.0E+15 / cm 3 。

[0051] The carrier accumulation layer 2 is an n-type semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+13 / cm 3 ~1.0E+17 / cm 3 。 In addition, the semiconductor device 100 may also be configured such that the carrier accumulation layer 2 is not provided, and the drift layer 1 is also provided in the region of the carrier accumulation layer 2 as shown in Figure 2 。

[0052] The base layer 3 is a p-type semiconductor layer having, for example, boron (B) or aluminum (Al) as a p-type impurity, and the concentration of the p-type impurity is 1.0E+12 / cm 3 ~1.0E+19 / cm 3 。

[0053] The emitter layer 4 is an n-type semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+17 / cm 3 ~1.0E+20 / cm 3 。

[0054] The contact layer 5 is a p-type semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+15 / cm 3 ~1.0E+20 / cm 3 。

[0055] The buffer layer 10 is an n-type semiconductor layer. For example, it may be formed by implanting phosphorus or protons (H+), or may be formed by implanting both phosphorus and protons (H+). The concentration of the n-type impurity in the buffer layer 10 is 1.0E+12 / cm 3 ~1.0E+18 / cm 3 。

[0056] The collector layer 11 is a p-type semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+16 / cm 3 ~1.0E+20 / cm 3 .

[0057] The active gate electrode 8 can be made of polysilicon doped with phosphorus or the like, or a metal.

[0058] The emitter electrode 9 can be made of, for example, aluminum (Al), aluminum silicon (AlSi), etc., and can also include a barrier metal made of titanium (Ti), titanium nitride (TiN), titanium silicon (TiSi), etc., and can also include a plug made of tungsten (W), etc.

[0059] In the mesa region sandwiched by adjacent active trenches 6, that is, in the mesa region sandwiched by adjacent active trenches 6, the emitter layer 4 has regions discretely arranged in the first direction in such a way as to be in contact with one of the adjacent active trenches 6 and not in contact with the other active trench 6, and regions discretely arranged in the first direction in such a way as to be in contact with the other active trench 6 and not in contact with one active trench 6.

[0060] In addition, in the mesa region sandwiched by adjacent active trenches 6, the contact layer 5 is arranged between the emitter layer 4 on the side in contact with one active trench 6 and the emitter layer 4 on the side in contact with the other active trench 6 when viewed from above, and between the respective regions of the emitter layer 4 discretely arranged in the first direction. In particular, the contact layer 5 has a continuous region in contact with both adjacent active trenches 6, and in terms of the position in the first direction, this continuous region includes a plurality of regions of the emitter layer 4 discretely arranged in the first direction.

[0061] In the case of the semiconductor device 100, the current of the holes flowing into the region directly below the emitter layer 4 flows not only in the first direction but also in the second direction and flows out to the contact layer 5. Therefore, compared with the case where the emitter layer 4 is connected from one active trench 6 to the other active trench 6, the latch-up tolerance can be improved. In this way, the semiconductor device 100 is a semiconductor device suitable for suppressing latch-up.

[0062] The width in the first direction of one of the discrete regions of the emitter layer 4 in contact with the side wall of the active trench 6 at the side wall of the active trench 6 is larger than the width in the first direction between the discrete regions of the emitter layer 4 adjacent in the first direction at the side wall of this active trench 6.

[0063] If the width in the first direction of one of the discrete regions of the emitter layer 4 is set as Ln, and the width in the first direction between the discrete regions of the emitter layer 4 at the sidewalls of the active trench 6 is set as Lp, then Ln > Lp. Ln and Lp can be about 0.1 to 50.0 μm. By setting Ln > Lp, the density of the emitter layer 4 can be increased to increase the saturation current. In addition, by adjusting Lp, the value of the saturation current can be adjusted. Ln and Lp can also be different according to each discrete region of the emitter layer 4. However, in this case, for example, for one of the discrete regions of the emitter layer 4, when the width in the first direction where this one discrete region contacts the sidewall of the active trench 6 is set as Ln, and the interval between this one discrete region and another discrete region adjacent to this one discrete region in the first direction at the sidewall of the active trench 6 is set as Lp, it is set as Ln > Lp.

[0064] If the width of the active trench 6 in the second direction orthogonal to the first direction is set as Wt, the width of the mesa region of the semiconductor substrate 120 exposed on the first main surface 120a is set as Wm, the width of the emitter layer 4 is set as Wn, the width of the contact layer 5 is set as Wp, and the width of the contact hole 14 is set as Wc (refer to Figure 1 ), then Wt and Wm can be about 0.3 to 10.0 μm, and Wn can be about 0.1 to 2.0 μm. Wp can be greater than or equal to 0.1 μm. The width Wc of the contact hole 14 is the width in the second direction of the region on the first main surface 120a of the semiconductor substrate 120 where the interlayer insulating film 13 is not provided.

[0065] To prevent short - circuit between the active gate electrode 8 and the emitter electrode 9, it is preferably Wc < Wm - 0.02 μm. To prevent insulation between the emitter layer 4 and the emitter electrode 9, it is preferably Wc > Wp + 0.02 μm.

[0066] For the semiconductor device 100, the current of the holes flowing directly below the emitter layer 4 flows not only in the first direction but also in the second direction and flows out to the contact layer 5. Therefore, compared with the case where the emitter layer 4 is connected from one active trench 6 to another active trench 6 in the mesa region sandwiched by adjacent active trenches 6, the latch - up tolerance can be improved. In addition, by reducing Wn, the latch - up tolerance can be further improved.

[0067] In the case of a trench-gate IGBT, increasing the ratio of the emitter layer can increase the saturation current. However, if the ratio of the emitter layer is simply increased, there is a problem of reduced latch-up tolerance. The reason is that if the emitter layer is enlarged to increase the ratio of the emitter layer, the spreading resistance directly under the emitter layer increases. If the interval between the emitter layers is reduced, the emitter layers are connected to each other by the lateral diffusion of impurities passing through the emitter layer during manufacturing. Thus, there is a trade-off relationship between the latch-up tolerance and the saturation current.

[0068] By configuring the emitter layer 4 as the configuration described in the present embodiment, the trade-off relationship between the latch-up tolerance and the saturation current can be improved. For example, a semiconductor device 100 with a high latch-up tolerance and a high saturation current can be provided.

[0069] <A-2. Effects>

[0070] In the case of the semiconductor device 100, in the mesa region sandwiched by adjacent active trenches 6, the emitter layer 4 has regions discretely arranged in the first direction in such a way that it contacts one of the adjacent active trenches 6 and does not contact the other active trench 6, and regions discretely arranged in the first direction in such a way that it contacts the other active trench 6 and does not contact one active trench 6. In addition, in the mesa region sandwiched by adjacent active trenches 6, the contact layer 5 is arranged between the emitter layer 4 on the side contacting one active trench 6 and the emitter layer 4 on the side contacting the other active trench 6, and between the respective regions of the emitter layer 4 discretely arranged in the first direction when viewed from above. Thus, the semiconductor device 100 is a semiconductor device suitable for suppressing latch-up.

[0071] In the case of the semiconductor device 100, the width in the first direction where one of the discrete regions of the emitter layer 4 contacts the side wall of the active trench 6 is larger than the width in the first direction between the discrete regions of the emitter layer 4 adjacent in the first direction at the side wall of the active trench 6. Thereby, the saturation current can be increased.

[0072] <B. Embodiment 2>

[0073] In Figure 3 a top view of the IGBT, i.e., the semiconductor device 101, is shown, and in Figure 4 a cross-sectional view taken along line B-B of the Figure 3 of the semiconductor device 101 is shown.

[0074] Regarding the semiconductor device 101, as a part of a plurality of trenches (first trenches) that penetrate the base layer 3 and the carrier accumulation layer 2 from the first main surface 120a of the semiconductor substrate 120 to reach the drift layer 1, dummy trenches 15 are provided. A dummy gate electrode 16 is formed in the dummy trenches 15 with a gate insulating film 7 interposed therebetween. The dummy gate electrode 16 is electrically connected to the emitter electrode 9. The arrangement of the plurality of trenches (first trenches) of the semiconductor device 101 has a portion where the active trenches 6 are adjacent to each other, and the arrangement of the emitter layer 4 and the contact layer 5 in the mesa region sandwiched by the adjacent active trenches 6 is the same as the arrangement described in the first embodiment.

[0075] Regarding the semiconductor device 101, the emitter layer 4 is formed so as not to contact the side wall of the dummy trench 15. The semiconductor device 101 has a mesa region sandwiched by the active trench 6 and the dummy trench 15. In this mesa region, the emitter layer 4 has a region discretely arranged in the first direction so as to contact the active trench 6 and not contact the dummy trench 15. In such a structure, similarly, in this mesa region sandwiched by the active trench 6 and the dummy trench 15, the current of the holes flowing into the region directly below the emitter layer 4 flows in both the first direction and the second direction and flows out to the contact layer 5, so it is suitable for suppressing latch-up.

[0076] Regarding an IGBT having a carrier accumulation layer, in order to deplete the carrier accumulation layer during breakdown voltage retention, it is necessary to reduce the trench pitch to a certain value or less, and it is difficult to reduce the parasitic capacitance of the chip. Regarding the semiconductor device 101, compared with the first embodiment, by adding the dummy trenches 15, the trench pitch can be reduced to a certain value or less to ensure the breakdown voltage, and the parasitic capacitance of the chip can be reduced.

[0077] In a structure having both the active trench 6 and the dummy trench 15, by arranging the active trenches 6 adjacent to each other, the coupling capacitance between the active trench 6 and the dummy trench 15 can be reduced, and the parasitic capacitance of the chip can be reduced.

[0078] <C. Third Embodiment>

[0079] In Figure 5 shows a top view of the IGBT, that is, the semiconductor device 102, and in Figure 6 shows a cross-sectional view of the semiconductor device 102 taken along the C-C line of Figure 5 .

[0080] In the semiconductor device 102, an interlayer insulating film 13 is provided between the contact layer 5 and the emitter electrode 9 across two or more continuously adjacent dummy trenches 15. In particular, the interlayer insulating film 13 is provided entirely between two or more continuously adjacent dummy trenches 15 without forming a contact hole 14, and the contact layer 5 and the emitter electrode 9 are insulated by the interlayer insulating film 13 between two or more continuously adjacent dummy trenches 15. The other aspects of the semiconductor device 102 are the same as those of the semiconductor device 101 of the second embodiment.

[0081] By reducing the density of the contact holes 14 , the holes injected by the collector electrode 12 can be accumulated near the first main surface 120 a , thereby reducing the on-voltage.

[0082] <D.实施方式4>

[0083] exist Figure 7 and Figure 8 2 shows a top view of a semiconductor device 103 which is an IGBT. The structure of the semiconductor device 103 is the same as that of the semiconductor device 100 of the first embodiment, except that the arrangement of the emitter layer 4 in the first direction is different depending on the position in the second direction.

[0084] In the semiconductor device 103, the emitter layer 4 is arranged in the first direction as follows, for example: Figure 7 , Figure 8 As shown, one active trench 6 side and the other active trench 6 side sandwiching the mesa region are different, and in particular, one active trench 6 side and the other active trench 6 side are arranged to be staggered by a width Sp in the first direction. Figure 7 In the example shown, the emitter layer 4 is arranged in the same manner in the first direction on both sides of the active trench 6, but Figure 8 In the example shown, the emitter layers 4 are also arranged in the first direction so as to be shifted by the width Sp on both sides of the active trench 6 .

[0085] The arrangement of the emitter layer 4 in the first direction may be the same on one active trench 6 side and the other active trench 6 side sandwiching the mesa region, and may be different on both sides of the active trench 6 .

[0086] By making the arrangement of the emitter layer 4 in the first direction different from that in the second direction, it is possible to disperse the current injected from the emitter layer 4 and improve the uniformity of heat generation in the chip.

[0087] <E.实施方式5>

[0088] exist Figure 9 and Figure 10 1 is a top view of an IGBT, ie, a semiconductor device 104 .

[0089] The structure of the semiconductor device 104 is different in the shape of each discrete region of the emitter layer 4 compared to the semiconductor device 100 of Embodiment 1. Other than this, the semiconductor device 104 is the same as the semiconductor device 100.

[0090] As Figure 9 and Figure 10 shown, for the semiconductor device 104, at a part in the first direction, a part of the width wn in the second direction becomes wider, and there is a convex portion 4a protruding in the second direction. That is, the discrete regions of the emitter layer 4 in the first direction include regions where the width in the second direction perpendicular to the first direction becomes wider locally in the first direction.

[0091] The convex portion 4a may be formed in a number greater than or equal to 1 with respect to one of the discretely formed regions of the emitter layer 4, may be formed at different positions for each of the discretely formed regions of the emitter layer 4, or may be formed only in a part of the discretely formed regions of the emitter layer 4.

[0092] If the width of the convex portion 4a in the second direction is set as Wn', and the width in the first direction is set as Ln', then Wn' < Wp, Ln' ≤ Wn.

[0093] With the structure of this embodiment, it is possible to ensure the latch-up tolerance and reduce the contact resistance between the emitter layer 4 and the emitter electrode 9.

[0094] <F. Embodiment 6>

[0095] In Figure 11 is shown a cross-sectional view of an IGBT, that is, the semiconductor device 105.

[0096] For the semiconductor device 105, the contact hole 14 is formed deeper toward the second main surface 120b side compared to the first main surface 120a. That is, in the element region (the first element region) of the semiconductor substrate 120 where the IGBT is provided, a trench 40 (the second trench) is provided from the first main surface 120a of the semiconductor substrate 120 toward the second main surface 120b side, and the contact hole 14 includes the trench 40.

[0097] On the side surface of the trench 40, the emitter layer 4 and the emitter electrode 9 are in contact, and on the bottom surface of the contact hole 14, the contact layer 5 and the emitter electrode 9 are in contact. The base layer 3 is provided on the second main surface 120b side of the contact layer 5, and the contact layer 5 is disposed between the base layer 3 and the emitter electrode 9.

[0098] With the structure of this embodiment, it is easy for the holes injected from the collector layer 11 to flow out from the contact layer 5, and the latch-up tolerance can be improved.

[0099] <G. Embodiment 7>

[0100] In Figure 12 shows a cross-sectional view of the IGBT, i.e., the semiconductor device 106.

[0101] In the semiconductor device 106, an active gate electrode 8 and a shielding electrode 17 are formed in the active trench 6 with a gate insulating film 7 interposed therebetween. The gate insulating film 7 is also provided between the active gate electrode 8 and the shielding electrode 17.

[0102] The shielding electrode 17 is electrically connected to the emitter electrode 9.

[0103] The center of the shielding electrode 17 in the depth direction (the third direction) is located on the side of the second main surface 120b compared to the center of the active gate electrode 8 in the depth direction, and the end portion of the active gate electrode 8 on the side of the second main surface 120b is included in the range where the carrier accumulation layer 2 is provided in the depth direction. As described in Embodiment 1, the impurity concentration may continuously change at the boundary between the drift layer 1 and the carrier accumulation layer 2. However, in this case, in the surface layer portion on the side of the first main surface 120a of the region combining the drift layer 1 and the carrier accumulation layer 2, a region where the impurity concentration is greater than or equal to 5 times the impurity concentration of the central portion of the drift layer 1 may be set as the carrier accumulation layer 2, and a region less than 5 times may be set as the drift layer 1.

[0104] By forming the shielding electrode 17 on the side of the second main surface 120b of the active gate electrode 8, the parasitic capacitance can be reduced. In order to form a channel for inverting a part of the base layer 3 and connecting the emitter layer 4 and the carrier accumulation layer 2 through this channel, it is necessary for the depth of the active gate electrode 8 to be deeper than that of the base layer 3. Therefore, the end portion of the active gate electrode 8 on the side of the second main surface 120b is included in the range where the carrier accumulation layer 2 is provided in the depth direction (the third direction).

[0105] <H. Embodiment 8>

[0106] In Figure 13 shows a cross-sectional view of the semiconductor device 107.

[0107] In the semiconductor device 107, the semiconductor substrate 120 has a diode region 201 (the second element region) where a diode is provided in addition to the IGBT region 200 (the first element region).

[0108] In the semiconductor device 107, the IGBT region 200 and the diode region 201 are adjacent in the second direction.

[0109] In Figure 13Among them, the structure of the IGBT region 200 is shown in the same way as the structure described in Embodiment 1. However, the planar structure and cross-sectional structure of the IGBT region 200 of the semiconductor device 107 can be the structures described in any one of Embodiments 1 to 7. Correspondingly, in any one of Embodiments 1 to 7, the operation of the IGBT region 200 can achieve the effects described in any one of Embodiments 1 to 7.

[0110] The diode region 201 has: a drift layer 1; a p-type anode layer 20 (the sixth semiconductor layer), which is disposed closer to the first main surface 120a side than the drift layer 1; a plurality of diode trenches 18 (the third trenches), which penetrate the anode layer 20 from the first main surface 120a of the semiconductor substrate 120 to reach the drift layer 1; a diode trench electrode 19, which is disposed on the inner wall of the diode trench 18 with a gate insulating film 7 interposed therebetween; an n-type cathode layer 21 (the seventh semiconductor layer), which has a higher concentration of n-type impurities than the drift layer 1 and is disposed closer to the second main surface 120b side than the drift layer 1; and a collector electrode 12, which is electrically connected to the cathode layer 21.

[0111] The diode trench electrode 19 is electrically connected to the emitter electrode 9.

[0112] The anode layer 20 is a p-type semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+12 / cm 3 ~1.0E+19 / cm 3 .

[0113] The cathode layer 21 is an n-type semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+16 / cm 3 ~1.0E+21 / cm 3 .

[0114] The anode layer 20 can be formed by the same process as the base layer 3 or by a different process. In addition, in order to reduce the contact resistance with the emitter electrode 9, a contact layer 5 can be formed on a part of the anode layer 20 as shown in Figure 13 .

[0115] The contact layer 5 is a p-type semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+15 / cm 3 ~1.0E+20 / cm 3 .

[0116] With the structure of this embodiment, the semiconductor device 107 can operate as an RC-IGBT (Reverse-Conducting IGBT, reverse-conducting IGBT).

[0117] <I. Embodiment 9>

[0118] Shown is a cross-sectional view of semiconductor device 108. Figure 14 in

[0119] In Embodiment 9, when the end of emitter layer 4 in the second direction is set as the end of IGBT region 200, and the end of cathode layer 21 is set as the end of diode region 201, there is a boundary region 202 between IGBT region 200 and diode region 201. IGBT region 200 and boundary region 202, diode region 201 and boundary region 202 are adjacent to each other in the second direction. The structures of IGBT region 200 and diode region 201 are the same as those in Embodiment 8.

[0120] The structure on the first major surface 120a side of boundary region 202 can be the same as that of the diode region, and the structure on the second major surface 120b side of boundary region 202 can be the same as that of IGBT region 200.

[0121] By adding boundary region 202, it is possible to suppress the inflow of holes from IGBT region 200 into diode region 201 and reduce the recovery loss.

[0122] <J. Embodiment 10>

[0123] Figure 15 Shown is a flowchart of a method for manufacturing a semiconductor device according to Embodiment 10. In this embodiment, it is mainly assumed that the semiconductor device 100 according to Embodiment 1 is manufactured, but it can also be similarly applied to the manufacturing method for manufacturing any one of semiconductor devices 101 to 108 according to other embodiments.

[0124] First, prepare a semiconductor substrate constituting drift layer 1 (step S1).

[0125] Next, as Figure 16 shown, perform a masking process on the first major surface 120a side of the semiconductor substrate to form mask 30 (step S2). Mask 30 is used in the ion implantation for forming base layer 3 and the ion implantation for forming carrier accumulation layer 2. Mask 30 is formed, for example, as Figure 16 shown, to cover the outer peripheral region 203 of semiconductor device 100. The outer peripheral region 203 is omitted in the figures other than Figure 16 this.

[0126] Next, perform ion implantation for forming base layer 3 (first ion implantation) (step S3), perform ion implantation for forming carrier accumulation layer 2 (fourth ion implantation) (step S4), and perform activation annealing. Thus, it becomes Figure 17The state shown. In addition, either the ion implantation for the base layer 3 or the ion implantation for the carrier accumulation layer 2 can be performed first.

[0127] Next, an active trench 6 is formed (step S5).

[0128] Next, a mask process for the emitter layer 4 is performed to form a mask 31 (step S6). Thus, it becomes Figure 18 The state shown.

[0129] Next, using the mask 31, ion implantation (second ion implantation) for forming the emitter layer 4 is performed, and activation annealing is carried out. Thus, it becomes Figure 19 The state shown.

[0130] Next, a mask process for the contact layer 5 is performed to form a mask 32 (step S8). Thus, it becomes Figure 20 The state shown.

[0131] Next, ion implantation (third ion implantation) for forming the contact layer 5 is performed, and activation annealing is carried out. Thus, it becomes Figure 21 The state shown.

[0132] Next, an interlayer insulating film 13 is formed in such a way as to form a contact hole 14 (step S10), an emitter electrode 9 is formed (step S11), and a structure on the second main surface 120b side is formed (step S12), obtaining Figure 2 The structure of the semiconductor device 100 shown.

[0133] The process of forming the active trench 6 described in step S5 can be at any position during the period from before the mask process for the base layer 3 and the carrier accumulation layer 2 implemented in step S2 to before the interlayer insulating film 13 is formed in step S10.

[0134] In order to reduce the manufacturing cost, it is preferable that the ion implantation for forming the carrier accumulation layer 2, the base layer 3, the emitter layer 4, and the contact layer 5 is once each. Thus, the distribution of the impurity concentration in the thickness direction of each of the contact layer 5 and the emitter layer 4 has, for example, only one peak.

[0135] In addition, the activation annealing of the carrier accumulation layer 2, the base layer 3, the emitter layer 4, and the contact layer 5 can be carried out individually or multiple ones can be carried out collectively.

[0136] When the carrier accumulation layer 2 is not provided in the semiconductor device 100, step S4 is not required.

[0137] As described above, in the method of manufacturing a semiconductor device according to the present embodiment, the base layer 3 is formed by the first ion implantation, the emitter layer 4 is formed by the second ion implantation, the contact layer 5 is formed by the third ion implantation, and the carrier accumulation layer 2 is formed by the fourth ion implantation. The same mask 30 is used for the first ion implantation and the fourth ion implantation, and the masks 30, 31, and 32 used for the first ion implantation and the fourth ion implantation, the second ion implantation, and the third ion implantation are different from each other. Accordingly, the patterns of the emitter layer 4 and the contact layer 5 can be adjusted independently.

[0138] <K. Embodiment 11>

[0139] Figure 22 The flowchart showing the method of manufacturing a semiconductor device according to Embodiment 11 is shown. In the present embodiment, the case of manufacturing the semiconductor device 100 according to Embodiment 1 is mainly assumed for description, but the method can be similarly applied to the manufacturing method of any of the semiconductor devices 101 to 108 according to other embodiments.

[0140] First, a semiconductor substrate constituting the drift layer 1 is prepared (step S21).

[0141] Next, a mask treatment is performed on the first main surface 120a side of the semiconductor substrate to form a mask 30 (step S22). The mask 30 is used in the ion implantation for forming the base layer 3, the ion implantation for forming the carrier accumulation layer 2, and the ion implantation for forming the emitter layer 4. The mask 30 is formed, for example, Figure 16 so as to cover the outer peripheral region 203 of the semiconductor device 100.

[0142] Next, the ion implantation for forming the base layer 3 (the fifth ion implantation) is performed (step S23), the ion implantation for forming the carrier accumulation layer 2 (the eighth ion implantation) is performed (step S24), the ion implantation for forming the emitter layer 4 (the sixth ion implantation) is performed (step S25), and activation annealing is performed. Thus, the state shown in Figure 23 is obtained. In addition, the order of performing the ion implantation for the base layer 3, the ion implantation for the carrier accumulation layer 2, and the ion implantation for the emitter layer 4 can be changed.

[0143] Next, an active trench 6 is formed (step S26).

[0144] Next, a mask treatment for the contact layer 5 is performed to form a mask 33 (step S27). Thus, the state shown in Figure 24 is obtained.

[0145] Next, ion implantation (seventh ion implantation) for forming the contact layer 5 is performed (step S28), and activation annealing is performed. Thus, it becomes Figure 21 the state shown. Since the ion implantation amount when forming the contact layer 5 in step S28 is higher than the ion implantation amount when forming the emitter layer 4 in step S25, the emitter layer 4 pre-implanted with impurity ions can be locally counter-doped to form the contact layer 5.

[0146] Next, an interlayer insulating film 13 is formed so as to form contact holes 14 (step S29), an emitter electrode 9 is formed (step S30), and a structure on the second main surface 120b side is formed (step S31), obtaining Figure 2 the structure of the semiconductor device 100 shown.

[0147] The process of forming the active trench 6 described in step S26 can be at any position during the period from before the mask process for the base layer 3, the carrier accumulation layer 2, and the emitter layer 4 implemented in step S22 to before the interlayer insulating film 13 is formed in step S29.

[0148] In order to reduce the manufacturing cost, it is preferable that the ion implantation for forming the carrier accumulation layer 2, the base layer 3, the emitter layer 4, and the contact layer 5 is each performed once. Thus, the distribution of the impurity concentration of each of the contact layer 5 and the emitter layer 4 in the thickness direction has, for example, only one peak.

[0149] In addition, the activation annealing of the carrier accumulation layer 2, the base layer 3, the emitter layer 4, and the contact layer 5 can be performed individually or multiple ones can be performed collectively.

[0150] When the carrier accumulation layer 2 is not provided in the semiconductor device 100, step S24 is not required.

[0151] As described above, in the method for manufacturing a semiconductor device according to the present embodiment, the base layer 3 is formed by the fifth ion implantation, the emitter layer 4 is formed by the sixth ion implantation, the contact layer 5 is formed by the seventh ion implantation, the carrier accumulation layer 2 is formed by the eighth ion implantation, the fifth ion implantation, the sixth ion implantation, and the eighth ion implantation use the same mask 30, and after the fifth ion implantation, the sixth ion implantation, and the eighth ion implantation are performed, the seventh ion implantation is performed using a mask 33 different from the mask 30 used in the fifth ion implantation, the sixth ion implantation, and the eighth ion implantation. Thus, compared with the method for manufacturing a semiconductor device of Embodiment 10, the mask process for the emitter layer 4 can be reduced, and the manufacturing cost can be lowered.

[0152] As described above, several embodiments are suggested, but are not limited to the above embodiments, and various expansions can be made. As the element structure, it can be applied to power devices such as IGBTs, MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors), and RC-IGBTs, and there are no restrictions on the breakdown voltage level, FZ (Floating Zone) substrates / MCZ (Magnetic field applied Czochralski) substrates / epitaxial substrates, etc. when applying.

[0153] In addition, the embodiments can be freely combined, and the embodiments can be appropriately deformed and omitted.

[0154] Explanation of reference numerals

[0155] 1 Drift layer, 2 Carrier accumulation layer, 3 Base layer, 4 Emitter layer, 4a Protrusion, 5 Contact layer, 6 Active trench, 7 Gate insulating film, 8 Active gate electrode, 9, Emitter electrode, 10 Buffer layer, 11 Collector layer, 12 Collector electrode, 13 Interlayer insulating film, 14 Contact hole, 15 Dummy trench, 16 Dummy gate electrode, 17 Shielding electrode, 18 Diode trench, 19 Diode trench electrode, 20 Anode layer, 21 Cathode layer, 30, 31, 32, 33 Masks, 40 Trench, 100, 101, 102, 103, 104, 105, 106, 107, 108 Semiconductor device, 120 Semiconductor substrate, 120a First main surface, 120b Second main surface, 200 IGBT region, 201 Diode region, 202 Boundary region, 203 Peripheral region.

Claims

1. A semiconductor device having a semiconductor substrate with a first main surface and a main surface opposite to the first main surface, i.e., a second main surface, wherein a transistor is provided in a first element region of the semiconductor substrate, and the semiconductor substrate has in the first element region: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type, which is disposed closer to the first main surface than the first semiconductor layer; a third semiconductor layer of the first conductivity type, which is selectively disposed on the first main surface side of the second semiconductor layer; a first electrode electrically connected to the third semiconductor layer; and a fourth semiconductor layer having a higher impurity concentration of the second conductivity type than the second semiconductor layer, and disposed between the second semiconductor layer and the first electrode, wherein the semiconductor substrate is provided in the first element region with a plurality of first trenches that penetrate the third semiconductor layer and the second semiconductor layer from the first main surface to reach the first semiconductor layer, each of the plurality of first trenches extends in a first direction when viewed from above, the plurality of first trenches are arranged in a strip shape when viewed from above, at least a part of the plurality of first trenches are active trenches provided with gate electrodes so as to face the second semiconductor layer with a gate insulating film interposed therebetween in the first trenches, the strip-shaped arrangement of the plurality of first trenches has portions where the active trenches are adjacent to each other, in a mesa region sandwiched by adjacent trenches, i.e., a mesa region sandwiched by the adjacent active trenches, the third semiconductor layer has regions discretely arranged in the first direction so as to contact one of the adjacent active trenches and not contact the other active trench, and regions discretely arranged in the first direction so as to contact the other active trench and not contact the one active trench, in the mesa region sandwiched by the adjacent active trenches, the fourth semiconductor layer is disposed, when viewed from above, between the third semiconductor layer on the side in contact with one of the active trenches and the third semiconductor layer on the side in contact with the other active trench, and between the respective regions of the third semiconductor layer discretely arranged in the first direction, a part of the plurality of first trenches are dummy trenches having dummy gate electrodes formed with a gate insulating film interposed therebetween in the trenches, the dummy gate electrodes are electrically connected to the first electrode, and the third semiconductor layer is formed so as not to contact the side walls of the dummy trenches.

2. The semiconductor device according to claim 1, wherein in the mesa region sandwiched by the adjacent active trenches, the width in the first direction of one of the discrete regions of the third semiconductor layer in contact with the side wall of the active trench is larger than the width in the first direction between the discrete regions of the third semiconductor layer adjacent in the first direction at the side wall of the active trench.

3. The semiconductor device according to claim 1 or 2, wherein In the mesa region sandwiched by the adjacent active trenches, the fourth semiconductor layer has a continuous region in contact with both of the adjacent active trenches, and, with respect to the position in the first direction, the continuous region includes a plurality of discrete regions of the third semiconductor layer in the first direction.

4. The semiconductor device according to claim 1, wherein In the mesa region sandwiched between the active trench and the dummy trench, the third semiconductor layer has regions discretely arranged in the first direction so as to be in contact with the active trench and not in contact with the dummy trench.

5. The semiconductor device according to claim 1 or 4, wherein: The stripe-shaped arrangement of the plurality of first grooves has a portion where the dummy grooves are adjacent to each other, An interlayer insulating film is formed between the semiconductor substrate and the first electrode so as to extend across adjacent dummy trenches in the stripe-shaped arrangement of the plurality of first trenches in a plan view.

6. The semiconductor device according to claim 5, wherein: Between the semiconductor substrate and the first electrode, the interlayer insulating film is formed entirely between the adjacent dummy trenches in the stripe-shaped arrangement of the plurality of first trenches in a plan view.

7. The semiconductor device according to claim 1 or 2, wherein: The fourth semiconductor layer is selectively provided on the first main surface side of the second semiconductor layer.

8. The semiconductor device according to claim 1 or 2, wherein: The semiconductor base includes an eighth semiconductor layer having a higher first conductivity type impurity concentration than the first semiconductor layer, provided between the first semiconductor layer and the second semiconductor layer in the first element region.

9. The semiconductor device according to claim 8, wherein: The gate electrode and the shield electrode are arranged in the active trench via a gate insulating film. The shielding electrode is electrically connected to the first electrode. The center of the shield electrode in the depth direction is located closer to the second main surface than the center of the gate electrode in the depth direction. An end portion of the gate electrode on the second main surface side is included in a range where the eighth semiconductor layer is provided in a depth direction.

10. A method for manufacturing a semiconductor device, which is a method for manufacturing the semiconductor device according to any one of claims 1 to 7, In the method for manufacturing a semiconductor device, The second semiconductor layer is formed by first ion implantation, The third semiconductor layer is formed by a second ion implantation, The fourth semiconductor layer is formed by a third ion implantation, The mask used in the first ion implantation, the mask used in the second ion implantation, and the mask used in the third ion implantation are different from each other.

11. A method for manufacturing a semiconductor device, which is a method for manufacturing the semiconductor device according to claim 8 or 9, In the method for manufacturing a semiconductor device, The second semiconductor layer is formed by first ion implantation, The third semiconductor layer is formed by a second ion implantation, The fourth semiconductor layer is formed by a third ion implantation, The eighth semiconductor layer is formed by a fourth ion implantation. The same mask is used in the first ion implantation and the fourth ion implantation. The mask used in the first ion implantation and the fourth ion implantation, the mask used in the second ion implantation, and the mask used in the third ion implantation are different from each other.

12. A method of manufacturing a semiconductor device, which is a method of manufacturing the semiconductor device according to any one of claims 1 to 7. In this method of manufacturing the semiconductor device, The second semiconductor layer is formed by a fifth ion implantation. The third semiconductor layer is formed by a sixth ion implantation. The fourth semiconductor layer is formed by a seventh ion implantation. The same mask is used in the fifth ion implantation and the sixth ion implantation. After the fifth ion implantation and the sixth ion implantation are performed, the seventh ion implantation is performed using a mask different from the mask used in the fifth ion implantation and the sixth ion implantation.

13. A method of manufacturing a semiconductor device, which is a method of manufacturing the semiconductor device according to claim 8 or 9. In this method of manufacturing the semiconductor device, The second semiconductor layer is formed by a fifth ion implantation. The third semiconductor layer is formed by a sixth ion implantation. The fourth semiconductor layer is formed by a seventh ion implantation. The eighth semiconductor layer is formed by an eighth ion implantation. The same mask is used in the fifth ion implantation, the sixth ion implantation, and the eighth ion implantation. After the fifth ion implantation, the sixth ion implantation, and the eighth ion implantation are performed, the seventh ion implantation is performed using a mask different from the mask used in the fifth ion implantation, the sixth ion implantation, and the eighth ion implantation.

14. A semiconductor device having a semiconductor substrate with a first main surface and a main surface opposite to the first main surface, i.e., a second main surface. A transistor is provided in a first element region of the semiconductor substrate. The semiconductor substrate has in the first element region: A first semiconductor layer of a first conductivity type; A second semiconductor layer of a second conductivity type, which is disposed closer to the first main surface side than the first semiconductor layer; A third semiconductor layer of a first conductivity type, which is selectively disposed on the first main surface side of the second semiconductor layer; A first electrode electrically connected to the third semiconductor layer; and A fourth semiconductor layer having a higher impurity concentration of the second conductivity type than the second semiconductor layer, disposed between the second semiconductor layer and the first electrode. The semiconductor substrate is provided with a plurality of first trenches in the first element region that penetrate the third semiconductor layer and the second semiconductor layer from the first main surface to reach the first semiconductor layer. The plurality of first trenches each extend in a first direction when viewed from above. The plurality of first trenches are arranged in a strip shape when viewed from above. At least a part of the plurality of first trenches is an active trench in which a gate electrode is provided so as to face the second semiconductor layer with a gate insulating film interposed therebetween within the first trench. The strip-shaped configuration of the plurality of first trenches has portions where the active trenches are adjacent to each other. In a mesa region in a region sandwiched by adjacent trenches, i.e., a mesa region sandwiched by the adjacent active trenches, the third semiconductor layer has regions discretely arranged in the first direction in such a manner as to be in contact with one of the adjacent active trenches and not in contact with the other active trench, and regions discretely arranged in the first direction in such a manner as to be in contact with the other active trench and not in contact with the one active trench. In the mesa region sandwiched by the adjacent active trenches, the fourth semiconductor layer is arranged, in a plan view, between the third semiconductor layer on the side in contact with one of the active trenches and the third semiconductor layer on the side in contact with the other active trench, and between the respective regions of the third semiconductor layer discretely arranged in the first direction. The arrangement of the third semiconductor layer in the first direction varies depending on the position in the second direction.

15. The semiconductor device according to claim 14, wherein the arrangement of the third semiconductor layer in the first direction is different between one active trench side and the other active trench side in the mesa region sandwiched by the adjacent active trenches.

16. The semiconductor device according to claim 14, wherein the arrangement of the third semiconductor layer in the first direction is different on both sides of the active trench.

17. A semiconductor device having a semiconductor substrate having a first main surface and a main surface opposite to the first main surface, i.e., a second main surface. A transistor is provided in a first element region of the semiconductor substrate. The semiconductor substrate has, in the first element region: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type, which is provided closer to the first main surface side than the first semiconductor layer; a third semiconductor layer of a first conductivity type, which is selectively provided on the first main surface side of the second semiconductor layer; a first electrode electrically connected to the third semiconductor layer; and a fourth semiconductor layer having a higher impurity concentration of the second conductivity type than the second semiconductor layer, and arranged between the second semiconductor layer and the first electrode. The semiconductor substrate is provided, in the first element region, with a plurality of first trenches that penetrate the third semiconductor layer and the second semiconductor layer from the first main surface to reach the first semiconductor layer. The plurality of first trenches each extend in a first direction in a plan view. The plurality of first trenches are arranged in a strip shape in a plan view. At least a part of the plurality of first trenches is an active trench in which a gate electrode is provided so as to face the second semiconductor layer with a gate insulating film interposed therebetween within the first trench. The strip-shaped configuration of the plurality of first trenches has portions where the active trenches are adjacent to each other. In a mesa region sandwiched by adjacent trenches, i.e., a mesa region sandwiched by adjacent active trenches among the mesa regions, the third semiconductor layer has regions discretely arranged in the first direction in such a manner as to be in contact with one of the adjacent active trenches and not in contact with the other active trench, and regions discretely arranged in the first direction in such a manner as to be in contact with the other active trench and not in contact with the one active trench. In the mesa region sandwiched by the adjacent active trenches, the fourth semiconductor layer is arranged, in a plan view, between the third semiconductor layer on the side in contact with one of the active trenches and the third semiconductor layer on the side in contact with the other active trench, and between the regions of the third semiconductor layer discretely arranged in the first direction. The regions of the third semiconductor layer discretely arranged in the first direction include regions where the width in the second direction perpendicular to the first direction locally widens in the first direction.

18. A semiconductor device having a semiconductor substrate, the semiconductor substrate having a first main surface and a main surface opposite to the first main surface, i.e., a second main surface. Transistors are provided in a first element region of the semiconductor substrate. The semiconductor substrate has, in the first element region: A first semiconductor layer of a first conductivity type; A second semiconductor layer of a second conductivity type, which is provided closer to the first main surface side than the first semiconductor layer; A third semiconductor layer of a first conductivity type, which is selectively provided on the first main surface side of the second semiconductor layer; A first electrode electrically connected to the third semiconductor layer; and A fourth semiconductor layer, which has a higher impurity concentration of the second conductivity type than the second semiconductor layer and is arranged between the second semiconductor layer and the first electrode. In the first element region of the semiconductor substrate, a plurality of first trenches are provided that penetrate the third semiconductor layer and the second semiconductor layer from the first main surface to reach the first semiconductor layer. In a plan view, each of the plurality of first trenches extends in a first direction. In a plan view, the plurality of first trenches are arranged in a strip shape. At least a part of the plurality of first trenches are active trenches provided with gate electrodes in such a manner as to face the second semiconductor layer with a gate insulating film interposed therebetween in the first trench. The strip-shaped arrangement of the plurality of first trenches has portions where the active trenches are adjacent to each other. In a mesa region sandwiched by adjacent trenches, i.e., a mesa region sandwiched by adjacent active trenches among the mesa regions, the third semiconductor layer has regions discretely arranged in the first direction in such a manner as to be in contact with one of the adjacent active trenches and not in contact with the other active trench, and regions discretely arranged in the first direction in such a manner as to be in contact with the other active trench and not in contact with the one active trench. In the mesa region sandwiched by the adjacent active trenches, the fourth semiconductor layer is disposed, in a plan view, between the third semiconductor layer on the contact side with one of the active trenches and the third semiconductor layer on the contact side with the other active trench, and between the regions of the third semiconductor layer discrete in the first direction. In the first element region, a second trench is provided extending from the first main surface of the semiconductor substrate toward the second main surface side. The third semiconductor layer is exposed on the side wall of the second trench. The fourth semiconductor layer includes a portion provided at the bottom of the second trench. The first electrode includes a portion provided in the second trench. On the side surface of the second trench, the third semiconductor layer is in contact with the first electrode. On the bottom surface of the second trench, the fourth semiconductor layer is in contact with the first electrode.

19. A semiconductor device having a semiconductor substrate with a first main surface and a main surface opposite to the first main surface, i.e., a second main surface. A transistor is provided in the first element region of the semiconductor substrate. The semiconductor substrate in the first element region has: A first semiconductor layer of a first conductivity type; A second semiconductor layer of a second conductivity type, which is disposed closer to the first main surface side than the first semiconductor layer; A third semiconductor layer of a first conductivity type, which is selectively disposed on the first main surface side of the second semiconductor layer; A first electrode electrically connected to the third semiconductor layer; and A fourth semiconductor layer having a higher impurity concentration of the second conductivity type than the second semiconductor layer, and disposed between the second semiconductor layer and the first electrode. In the first element region of the semiconductor substrate, a plurality of first trenches are provided penetrating the third semiconductor layer and the second semiconductor layer from the first main surface to reach the first semiconductor layer. In a plan view, the plurality of first trenches each extend in a first direction. In a plan view, the plurality of first trenches are arranged in a strip shape. At least a part of the plurality of first trenches are active trenches provided with gate electrodes in such a manner as to face the second semiconductor layer with a gate insulating film interposed therebetween in the first trench. The strip-shaped arrangement of the plurality of first trenches has portions where the active trenches are adjacent to each other. In the mesa region sandwiched by the adjacent active trenches in the region sandwiched by the adjacent trenches, i.e., the mesa region, the third semiconductor layer has regions discretely arranged in the first direction in such a manner as to be in contact with one of the adjacent active trenches and not in contact with the other active trench, and regions discretely arranged in the first direction in such a manner as to be in contact with the other active trench and not in contact with the one active trench. In the mesa region sandwiched by the adjacent active trenches, the fourth semiconductor layer is disposed, in a plan view, between the third semiconductor layer on the contact side with one of the active trenches and the third semiconductor layer on the contact side with the other active trench, and between the regions of the third semiconductor layer discrete in the first direction. The first element region has: a fifth semiconductor layer of a second conductivity type, which is located on the second main surface side compared with the first semiconductor layer; and a second electrode, which is electrically connected to the fifth semiconductor layer. In a plan view of the semiconductor substrate, a diode is provided in a second element region different from the first element region. The second element region has: the first semiconductor layer; a sixth semiconductor layer of a second conductivity type, which is disposed on the first main surface side compared with the first semiconductor layer; a plurality of third trenches, which penetrate the sixth semiconductor layer from the first main surface to reach the first semiconductor layer; a diode trench electrode, which is disposed in the third trench with a gate insulating film therebetween; a seventh semiconductor layer of a first conductivity type, which is disposed on the second main surface side compared with the first semiconductor layer; and the second electrode, which is electrically connected to the seventh semiconductor layer. The diode trench electrode is electrically connected to the first electrode.

20. The semiconductor device according to claim 19, wherein a boundary region is provided between the first element region and the second element region, the boundary region has: the first semiconductor layer; the fifth semiconductor layer, which is disposed on the second main surface side compared with the first semiconductor layer; and the sixth semiconductor layer, which is disposed on the first main surface side compared with the first semiconductor layer.

21. A semiconductor device having a semiconductor substrate having a first main surface and a main surface opposite to the first main surface, i.e., a second main surface. A transistor is provided in a first element region of the semiconductor substrate. The semiconductor substrate has, in the first element region: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type, which is disposed on the first main surface side compared with the first semiconductor layer; a third semiconductor layer of a first conductivity type, which is selectively disposed on the first main surface side of the second semiconductor layer; a first electrode, which is electrically connected to the third semiconductor layer; and a fourth semiconductor layer, which has a higher impurity concentration of the second conductivity type compared with the second semiconductor layer and is disposed between the second semiconductor layer and the first electrode. A plurality of first trenches are provided in the first element region of the semiconductor substrate, which penetrate the third semiconductor layer and the second semiconductor layer from the first main surface to reach the first semiconductor layer. The plurality of first trenches each extend in a first direction in a plan view. The plurality of first trenches are arranged in a strip shape in a plan view. At least a part of the plurality of first trenches are active trenches provided with a gate electrode in a manner of facing the second semiconductor layer with a gate insulating film therebetween in the first trench. The strip-shaped configuration of the plurality of first trenches has portions where the active trenches are adjacent to each other. In the mesa region sandwiched by adjacent trenches, i.e., the mesa region sandwiched by the adjacent active trenches, the third semiconductor layer has regions discretely arranged in the first direction in such a manner as to be in contact with one of the adjacent active trenches and not in contact with the other active trench, and regions discretely arranged in the first direction in such a manner as to be in contact with the other active trench and not in contact with the one active trench. In the mesa region sandwiched by the adjacent active trenches, the fourth semiconductor layer is arranged, in a plan view, between the third semiconductor layer on the side in contact with one of the active trenches and the third semiconductor layer on the side in contact with the other active trench, and between the respective regions of the third semiconductor layer that are discrete in the first direction. The distributions in the thickness direction of the impurity concentrations of the fourth semiconductor layer and the third semiconductor layer each have only one peak.

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