Nitride semiconductor light-emitting device

Abstract

Provided is a nitride semiconductor light-emitting element capable of increasing the light-emitting output and suppressing a temporal decrease in the light-emitting output. A light-emitting element (1) that outputs ultraviolet light includes: an active layer (40) including a quantum well structure that generates ultraviolet light; a dislocation-inhibiting structure layer (52) formed on the active layer (40) and including a dislocation-inhibiting structure (520) that stops or bends dislocations (D) from the active layer (40); and a p-type contact layer (54) formed on the dislocation-inhibiting structure layer (52) and having a thickness of 10 nm or more and 30 nm or less.

Description

Technical Field

[0001] The present invention relates to a nitride semiconductor light-emitting element. Background Art

[0002] In recent years, nitride semiconductor light-emitting elements such as light-emitting diodes and laser diodes that output ultraviolet light have been provided, and the development of nitride semiconductor light-emitting elements with improved light-emitting output has been promoted (see Patent Document 1).

[0003] The nitride semiconductor light-emitting element described in Patent Document 1 includes: a substrate; a buffer layer formed on the substrate; an n-type cladding layer formed on the buffer layer; an active layer formed on the n-type cladding layer and including a multiple quantum well layer; a multiple semiconductor layer formed on the active layer; a p-side electrode formed on the multiple semiconductor layer; and an n-side electrode formed on a part of the region of the n-type cladding layer. The multiple semiconductor layer includes: an electron blocking layer; a p-type cladding layer formed on the electron blocking layer; and a p-type contact layer formed on the p-type cladding layer.

[0004] In this nitride semiconductor light-emitting element, the thickness of the p-type contact layer is, for example, as thin as 10 nm, whereby the light-emitting output can be increased.

[0005] Prior Art Documents

[0006] Patent Documents

[0007] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2019-121654 Summary of the Invention

[0008] Problems to be Solved by the Invention

[0009] However, in the above-described conventional nitride semiconductor light-emitting element, there is a problem that dislocations (dislocation lines) from the active layer reach the p-type contact layer (especially the surface of the p-type contact layer). When such dislocations from the p-type contact layer to the active layer occur, current concentration occurs at the dislocation portion, and the metal element of the p-side electrode enters the active layer through the dislocation portion. As a result, the light-emitting output of the nitride semiconductor light-emitting element tends to decrease over time with the passage of energization time.

[0010] Therefore, an object of the present invention is to provide a nitride semiconductor light-emitting element that can increase the light-emitting output and can suppress the temporal decrease in the light-emitting output.

[0011] Solutions for Solving the Problems

[0012] In order to achieve the above object, the present invention provides a nitride semiconductor light-emitting element, which is a nitride semiconductor light-emitting element that outputs ultraviolet light, and is characterized by comprising: an active layer including a quantum well structure that generates the above-mentioned ultraviolet light; a dislocation suppression structure layer formed on the above-mentioned active layer and including a dislocation suppression structure that stops or bends dislocations from the above-mentioned active layer; and a p-type contact layer formed on the above-mentioned dislocation suppression structure layer and having a thickness of 10 nm or more and 30 nm or less. In addition, the "above" mentioned here is a concept representing the relative positional relationship between one object and another object, and includes not only the state in which the one object is directly disposed above the other object without a third object in between, but also the state in which the one object is disposed above the other object with a third object in between.

[0013] Effects of the Invention

[0014] According to the present invention, it is possible to provide a nitride semiconductor light-emitting element that can improve the light emission output and can suppress the temporal decrease in the light emission output. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a cross-sectional view schematically showing an example of the configuration of a light-emitting element according to an embodiment of the present invention.

[0016] Figure 2 It is a cross-sectional view showing the periphery of the dislocation suppression structure layer.

[0017] Figure 3 It is an AFM image of the surface of the dislocation suppression structure layer.

[0018] Figure 4 It is a view showing the periphery of the dislocation suppression portion, (a) is a cross-sectional view, and (b) is a plan view.

[0019] Figure 5 It is a TEM image of the periphery of the dislocation suppression portion viewed from a direction orthogonal to the stacking direction in a state where dislocations occur.

[0020] Figure 6 (a) of is a coordinate diagram showing the concentration distribution of Si concentration in the stacking direction, and (b) is a coordinate diagram showing the concentration distribution of Mg concentration in the stacking direction.

[0021] Figure 7 It is a flowchart showing the manufacturing process of the light-emitting element.

[0022] Figure 8 It is a table showing the initial light emission output and the remaining light emission output after energization in the examples and each comparative example.

[0023] Explanation of Reference Signs

[0024] 1: Light-emitting element, 40: Active layer, 52: Layer containing dislocation suppression structure, 54: p-type contact layer, 520: Dislocation suppression structure, 521: Dislocation suppression portion, D: Dislocation, L1: Height in the stacking direction, L2: Width in the direction orthogonal to the stacking direction, L3: Separation distance between the dislocation suppression portion and the active layer. Detailed implementation mode

[0025] (Implementation mode)

[0026] The implementation modes of the present invention will be described with reference to the accompanying drawings. In addition, the implementation modes described below are shown as preferred specific examples for implementing the present invention. Although some various technically preferred technical matters are specifically illustrated, the technical scope of the present invention is not limited to this specific solution. In addition, the dimensional ratios of the respective constituent elements in each of the drawings do not necessarily match the dimensional ratios of the actual nitride semiconductor light-emitting element. In addition, when the present invention is described below, the stacking direction of each layer of the nitride semiconductor light-emitting element is simply referred to as the "stacking direction", and the nitride semiconductor light-emitting element is simply referred to as the "light-emitting element". In addition, in the following description, "above" represents the relative positional relationship between one object and another object, and includes not only the state in which the one object is directly disposed above the other object without a third object in between, but also the state in which the one object is disposed above the other object with a third object in between.

[0027] Figure 1 It is a cross-sectional view schematically showing an example of the structure of a light-emitting element 1 according to an embodiment of the present invention. The light-emitting element 1 includes, for example, a laser diode and a light-emitting diode (LED). In the present embodiment, as the light-emitting element 1, a light-emitting diode (LED) that outputs ultraviolet light (so-called deep ultraviolet light) having a center wavelength of 200 nm or more and 365 nm or less is taken as an example for description.

[0028] As Figure 1 shown, the light-emitting element 1 is configured to have: a substrate 10; a buffer layer 20 formed on the substrate 10; an n-type cladding layer 30 formed on the buffer layer 20; an active layer 40 formed on the n-type cladding layer 30 and including a multi-quantum well structure that generates ultraviolet light; a multiple semiconductor layer 50 formed on the active layer 40; a p-side electrode 60 formed on the multiple semiconductor layer 50; and an n-side electrode 70 formed on a part of the region of the n-type cladding layer 30.

[0029] The semiconductor constituting the light-emitting element 1 can, for example, be made of Al x Ga 1-xGroup-III nitride semiconductors of a binary or ternary system represented by N (0 ≤ x ≤ 1). In addition, part of N can be replaced by phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), etc.

[0030] The substrate 10 is a sapphire substrate including a sapphire (Al2O3) single crystal. In addition to the sapphire substrate, for example, an aluminum nitride (AlN) substrate or an aluminum gallium nitride (AlGaN) substrate can also be used as the substrate 10.

[0031] The buffer layer 20 is formed of aluminum nitride. Additionally, when the substrate 10 is an AlN substrate or an AlGaN substrate, the buffer layer 20 may not necessarily be provided.

[0032] The n-type cladding layer 30 is a layer formed of n-type AlGaN (hereinafter, also simply referred to as "n-type AlGaN"), and an AlGaN doped with silicon (Si) as an n-type impurity can be used. p Ga 1-p N (0 < p ≤ 1) layer. In the present embodiment, the dopant concentration (Si concentration) of the n-type cladding layer 30 is 0.5 × 10 19 [atoms / cm 3 or more and 2.5 × 10 19 [atoms / cm 3 or less. In addition, the Al composition ratio of the AlGaN forming the n-type cladding layer 30 is 50% or more and 60% or less (0.5 ≤ p ≤ 0.6) and is larger than the Al composition ratio (r) of the well layer 42 (p > r). Further, the Al composition ratio of the AlGaN forming the n-type cladding layer 30 is preferably as small as possible within the range larger than the Al composition ratio of the well layer 42. In addition, as the n-type impurity doped into the n-type cladding layer 30, germanium (Ge), selenium (Se), tellurium (Te), etc. can also be used instead of silicon. Additionally, the structure of the n-type cladding layer 30 can be a single-layer structure or a multi-layer structure.

[0033] The active layer 40 is a layer including a multi-quantum well structure (quantum well structure) in which three barrier layers 41 and three well layers 42 are alternately stacked in such a manner that the barrier layer 41 is on the n-type cladding layer 30 side and the well layer 42 is on the multiple semiconductor layer 50 side. The active layer 40 combines electrons and holes within the multi-quantum well structure to generate light of a specified wavelength. In the present embodiment, the active layer 40 is configured to have a bandgap of 3.4 eV or more in order to output deep ultraviolet light with a wavelength of 365 nm or less, and due to this multi-quantum well structure, ultraviolet light with a center wavelength of 200 nm or more and 365 nm or less is generated. In addition, the number of the barrier layers 41 and the well layers 42 is not limited to three each, and two can be provided respectively, or four or more can be provided respectively. Additionally, it can also be a configuration of a single quantum well structure having one barrier layer 41 and one well layer 42 provided respectively.

[0034] Each barrier layer 41 can use undoped Al q Ga 1-q N (0 < q ≤ 1) layer. In the present embodiment, the Al composition ratio of the AlGaN forming each barrier layer 41 is 50% or more (q ≥ 0.5), and preferably 60% or more and 90% or less (0.6 ≤ q ≤ 0.9). In addition, each barrier layer 41 has a thickness of 2 nm or more and 50 nm or less, and preferably has a thickness of 5 nm or more and 20 nm or less. Further, each barrier layer 41 may also be a layer containing an n-type impurity or a p-type impurity.

[0035] Each well layer 42 can use undoped Al r Ga 1-r N (0 ≤ r < 1) layer. In the present embodiment, the Al composition ratio of the AlGaN forming each well layer 42 is 30% or more and 40% or less (0.3 ≤ r ≤ 0.4). In addition, each well layer 42 has a thickness of 2 nm or more and 3.5 nm or less. Further, in the case of a quantum well structure such as the present embodiment that uses a multi-quantum well structure as the active layer 40, each well layer 42 and each barrier layer 41 other than the well layer 42 in contact with the multiple semiconductor layer 50 may also contain an n-type impurity.

[0036] The multiple semiconductor layer 50 includes: an electron blocking layer 51 formed on the active layer 40; a dislocation suppression structure-containing layer 52 formed on the electron blocking layer 51, including a dislocation suppression structure 520 that bends the dislocation D (dislocation line) from the active layer 40 (refer to Figure 5 ); a p-type cladding layer 53 formed on the dislocation suppression structure-containing layer 52; and a p-type contact layer 54 formed on the p-type cladding layer 53. That is, in the light-emitting element 1 of the present embodiment, the dislocation suppression structure-containing layer 52 is formed on the active layer 40 with the electron blocking layer 51 interposed therebetween, and the p-type contact layer 54 is formed on the dislocation suppression structure-containing layer 52 with the p-type cladding layer 53 interposed therebetween. In addition, the dislocation D mentioned here is a through dislocation that penetrates through the multiple layers formed in the light-emitting element 1. In addition, the dislocation suppression structure-containing layer 52 will be described later.

[0037] The electron blocking layer 51 includes: a first electron blocking layer 51a on the active layer 40 side; and a second electron blocking layer 51b on the dislocation suppression structure-containing layer 52 side. The electron blocking layer 51 serves to suppress the overflow of electrons and their intrusion toward the p-type cladding layer 53 side.

[0038] The first electron blocking layer 51a is a layer formed of p-type AlGaN (hereinafter, also simply referred to as "p-type AlGaN"), and Al doped with magnesium (Mg) as a p-type impurity can be used s Ga 1-sN (0 < s ≤ 1) layer. In this embodiment, the dopant concentration (Mg concentration) of the first electron blocking layer 51a is 5 × 10 19 [atoms / cm 3 or less. In addition, the first electron blocking layer 51a has a thickness of 30 nm or less, preferably a thickness of 0.5 nm or more and 5 nm or less, more preferably a thickness of 1.5 nm or more and 2.5 nm or less. Further, the Al composition ratio of the AlGaN forming the first electron blocking layer 51a is preferably 80% or more (s ≥ 0.8).

[0039] The second electron blocking layer 51b is a layer formed of p-type AlGaN and can use Al t Ga 1-t N (0 < t < 1) layer doped with magnesium as a p-type impurity. In this embodiment, the dopant concentration (Mg concentration) of the second electron blocking layer 51b is 1 × 10 18 [atoms / cm 3 or more and 1 × 10 20 [atoms / cm 3 or less. In addition, the Al composition ratio of the AlGaN forming the second electron blocking layer 51b is 45% or more and 90% or less (0.45 ≤ t ≤ 0.9), smaller than the Al composition ratio of the first electron blocking layer 51a and larger than the Al composition ratio of the p-type cladding layer 53 (v < t < s, u < t < s). In addition, the second electron blocking layer 51b has a thickness of 5 nm or more and 100 nm or less. Further, it is preferable that the thickness of the second electron blocking layer 51b is thinner than that of the p-type contact layer 54. In addition, the first electron blocking layer 51a and the second electron blocking layer 51b are not necessarily limited to p-type semiconductor layers and may also be undoped semiconductor layers.

[0040] The p-type cladding layer 53 includes: a first p-type cladding layer 53a on the side of the dislocation suppression structure layer 52; and a second p-type cladding layer 53b on the side of the p-type contact layer 54.

[0041] The first p-type cladding layer 53a is a layer formed of p-type AlGaN or p-type GaN and can use Al u Ga 1-u N (0 ≤ u ≤ 1) layer doped with magnesium as a p-type impurity. In this embodiment, the dopant concentration (Mg concentration) of the first p-type cladding layer 53a is 1 × 10 18 [atoms / cm 3 or more and 1 × 10 20 [atoms / cm 3As described below. In addition, the Al component ratio of the AlGaN forming the first p-type cladding layer 53a is 55% or more and 65% or less (0.55 ≤ u ≤ 0.65). In addition, the first p-type cladding layer 53a has a thickness of 10 nm or more and 100 nm or less, and preferably has a thickness of 55 nm or more and 85 nm or less.

[0042] The second p-type cladding layer 53b is a layer formed of p-type AlGaN or p-type GaN, and an AlGaN doped with magnesium as a p-type impurity can be used. v Ga 1-v N (0 ≤ v ≤ 1) layer. In the present embodiment, the dopant concentration (Mg concentration) of the second p-type cladding layer 53b is 1×10 18 [atoms / cm 3 or more and 1×10 20 [atoms / cm 3 or less. In addition, the Al component ratio of the AlGaN forming the second p-type cladding layer 53b gradually decreases from 60% to 0% from the first p-type cladding layer 53a side toward the p-type contact layer 54 side in the thickness direction. In addition, the second p-type cladding layer 53b has a thickness of 2 nm or more and 8 nm or less. By setting the component gradient in this way, the occurrence of dislocations D caused by the difference in the Al component ratio between the p-type cladding layer 53 and the p-type contact layer 54 can be suppressed.

[0043] The p-type contact layer 54 is a layer formed of p-type AlGaN or p-type GaN, and an AlGaN doped with magnesium as a p-type impurity can be used. w Ga 1-w N (0 ≤ w ≤ 1) layer. In the present embodiment, the dopant concentration (Mg concentration) of the p-type contact layer 54 is 5×10 18 [atoms / cm 3 or more and 5×10 20 [atoms / cm 3 or less. In addition, the Al component ratio of the AlGaN forming the p-type contact layer 54 is 10% or less (0 ≤ w ≤ 0.1), and preferably 0% (w = 0). In addition, the p-type contact layer 54 has a thickness of 10 nm or more and 30 nm or less, and preferably has a thickness of 15 nm or more and 25 nm or less.

[0044] In addition, as the p-type impurity doped into the electron blocking layer 51, the p-type cladding layer 53, and the p-type contact layer 54, zinc (Zn), beryllium (Be), calcium (Ca), strontium (Sr), barium (Ba), carbon (C), etc. can also be used instead of magnesium.

[0045] In addition, preferably, the dopant concentration (Si concentration) of silicon in the electron blocking layer 51, the p-type cladding layer 53, and the p-type contact layer 54 is 5×1017 [atoms / cm 3 The following is the background level of the measuring device.

[0046] The p-side electrode 60 is formed of rhodium (Rh). In addition, it is preferable that the p-side electrode 60 is made of a material having a high reflectance to ultraviolet rays.

[0047] The n-side electrode 70 is formed of a multilayer film formed by sequentially laminating titanium (Ti) / aluminum (Al) / titanium / gold (Au) on the n-type cladding layer 30.

[0048] Next, a description will be given with reference to Figures 2 to 4 the dislocation suppression structure layer 52. The dislocation suppression structure layer 52 is mainly formed of AlGaN having an Al composition ratio of 75% or more and 85% or less (that is, the portion other than the dislocation suppression portion 521 described later is formed of AlGaN having an Al composition ratio of 75% or more and 85% or less). And, as y Ga 1-y shown in N (0.75 ≤ y ≤ 0.85), the dislocation suppression structure layer 52 includes a dislocation suppression structure 520 in which a plurality of dislocation suppression portions 521 are scattered vertically and horizontally in a direction orthogonal to the stacking direction. In addition, Figure 2 and Figure 3 shown, Figure is a cross-sectional view around the dislocation suppression structure layer 52, Figure 2 Figure is a cross-sectional view around the dislocation suppression structure layer 52, Figure 3 Figure is an AFM image of the surface of the dislocation suppression structure layer 52 (an image of the observation result of the surface by an atomic force microscope).

[0049] Each dislocation suppression portion 521 is formed of a V-shaped pit. In the present embodiment, the V-shaped pit is a portion where the growth mode of the matrix phase is changed (the growth of a plane other than the C-plane is promoted, etc.) due to silicon being doped into the matrix phase or a compound containing silicon (such as SiN) precipitating into the matrix phase. Specifically, as Figure 4 shown in (a) of Figure, each dislocation suppression portion 521 has a trapezoidal cross-sectional shape that tapers at the top with the active layer 40 side as the top side when viewed from a direction orthogonal to the stacking direction. In addition, as Figure 4As shown in FIG. (b), each dislocation suppression portion 521 has a hexagonal planar shape when viewed from the stacking direction. That is, each dislocation suppression portion 521 is formed in a shape of a hexagonal truncated pyramid with the active layer 40 side as the top side. In addition, the height L1 of each dislocation suppression portion 521 in the stacking direction is 5 nm or more and 50 nm or less, and preferably 10 nm or more and 30 nm or less. Further, the width L2 of each dislocation suppression portion 521 in the direction orthogonal to the stacking direction is 5 nm or more and 200 nm or less. Moreover, the separation distance L3 between each dislocation suppression portion 521 and the active layer 40 in the stacking direction (the distance in the stacking direction between the end face position of the active layer 40 side of each dislocation suppression portion 521 and the interface position between the multiple semiconductor layer 50 and the active layer 40) is 0 nm or more and 100 nm or less, and preferably 50 nm or less, more preferably 30 nm or less. In addition, the thickness of the dislocation suppression structure-containing layer 52 is determined by the height L1 of each dislocation suppression portion 521 in the stacking direction. Therefore, the thickness of the dislocation suppression structure-containing layer 52 is 5 nm or more and 50 nm or less, and preferably 10 nm or more and 30 nm or less.

[0050] By providing such a dislocation suppression portion 521, as Figure 5 shown, it is possible to bend (kink) the dislocations D (dislocation lines) from the active layer 40 laterally in the stacking direction at each dislocation suppression portion 521. Thereby, it is possible to suppress the dislocations D from the active layer 40 from reaching the p-type contact layer 54 (especially the surface of the p-type contact layer 54). That is, it is possible to avoid the situation where dislocations occur from the active layer 40 to the p-type contact layer 54. In addition, the reason why the dislocations D (dislocation lines) from the active layer 40 are bent laterally in the stacking direction due to each dislocation suppression portion 521 is presumed as follows: In each dislocation suppression portion 521, the growth mode of the matrix phase is changed, so that the propagation direction of the dislocations D is changed. In addition, the dislocations D are generated due to the difference in lattice constants between the substrate 10 and the layers stacked on the substrate 10. In addition, Figure 5 is a TEM image (a captured image by a transmission electron microscope) of the periphery of the dislocation suppression structure-containing layer 52 when viewed from the direction orthogonal to the stacking direction in the state where dislocations occur.

[0051] In addition, in the dislocation suppression structure-containing layer 52, as Figure 6 shown in FIG. (a), regarding the concentration distribution of the Si concentration in the stacking direction, there is a concentration peak (maximum value) higher than other parts in the dislocation suppression structure-containing layer 52. The Si concentration at this concentration peak is 1×10 18 [atoms / cm 3 or more and 1×10 20 [atoms / cm 3 or less, and preferably 3×10 18 [atoms / cm 3 or more and 5×1019 [atoms / cm 3 or less. In addition, in the example of (a) of Figure 6 , the Si concentration at the concentration peak is 3.41×10 19 [atoms / cm 3 . Thus, by having a concentration peak of silicon, magnesium is attracted to the position of the concentration peak.

[0052] Moreover, in the dislocation suppression structure layer 52, as shown in Figure 6 (b), regarding the concentration distribution of the Mg concentration in the stacking direction, there is a concentration peak (maximum value) higher than other parts within the dislocation suppression structure layer 52. The Mg concentration at this concentration peak is 5×10 18 [atoms / cm 3 or more and 5×10 20 [atoms / cm 3 or less. And it is preferably 7×10 18 [atoms / cm 3 or more and 5×10 19 [atoms / cm 3 or less. In addition, in the example of (b) of Figure 6 , the Mg concentration at the concentration peak is 2.67×10 19 [atoms / cm 3 .

[0053] In addition, the position of the concentration peak of the Mg concentration and the position of the concentration peak of the Si concentration are the same position in the stacking direction. Strictly speaking, there may sometimes be a deviation of ±5 nm or less between the position of the concentration peak of the Mg concentration and the position of the concentration peak of the Si concentration in the stacking direction, but as long as the deviation is ±5 nm or less, they can be regarded as being in the same position. At least it can be said that the position of the concentration peak of the Mg concentration and the position of the concentration peak of the Si concentration in the stacking direction are in approximately the same position with a deviation of ±5 nm or less. In addition, Figure 6 the concentration distributions shown in (a) and (b) of

[0054] (Manufacturing process of the light-emitting element)

[0055] Next, with reference to Figure 7 the manufacturing process (manufacturing method) of the light-emitting element 1 will be described. The manufacturing process of this light-emitting element 1 starts from the state where the wafer that becomes the substrate 10 is placed in the chamber.

[0056] As shown in Figure 7As shown, in the manufacturing process of the light-emitting element 1, the buffer layer growth process S1, the n-type cladding layer growth process S2, the active layer growth process S3, the electron blocking layer growth process S4, the dislocation suppression structure-containing layer formation process S5, the p-type cladding layer growth process S6, the p-type contact layer growth process S7, the region removal process S8, the n-side electrode formation process S9, the p-side electrode formation process S10, and the dicing process S11 are sequentially performed. In addition, the growth of each layer in each growth process can use well-known epitaxial growth methods such as Metal Organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), and Hydride Vapor Phase Epitaxy (HVPE). Further, trimethylaluminum (TMA) as an Al source, trimethylgallium (TMG) as a Ga source, and ammonia (NH3) as an N source are appropriately supplied into the chamber to grow the AlGaN layer or AlN layer and GaN layer. In addition, by adjusting the supply amounts of these source gases, it is controlled so that the Al composition ratio of each layer becomes the target value.

[0057] In the buffer layer growth process S1, the buffer layer 20 is epitaxially grown on the wafer (the surface of the wafer) by high-temperature growth at 1000°C or higher and 1400°C or lower. In addition, in the buffer layer growth process S1, the buffer layer 20 is grown such that the Al composition ratio of the buffer layer 20 is 100% and the thickness of the buffer layer 20 is 1800 nm or more and 2200 nm or less.

[0058] In the n-type cladding layer growth process S2, the n-type cladding layer 30 is epitaxially grown on the buffer layer 20 grown by the buffer layer growth process S1 (the surface of the buffer layer 20) under the temperature condition of 1020°C or higher and 1180°C or lower. In addition, in the n-type cladding layer growth process S2, the n-type cladding layer 30 is grown such that the Al composition ratio of the n-type cladding layer 30 is 50% or more and 60% or less and the thickness of the n-type cladding layer 30 is 1800 nm or more and 2200 nm or less.

[0059] In the active layer growth step S3, on the n-type cladding layer 30 grown by the n-type cladding layer growth step S2 (on the surface of the n-type cladding layer 30), the active layer 40 is epitaxially grown under the temperature condition of 1000 °C or higher and 1100 °C or lower. That is, the three barrier layers 41 and the three well layers 42 constituting the active layer 40 are epitaxially grown layer by layer alternately. Further, in the active layer growth step S3, each barrier layer 41 is grown such that the Al composition ratio of each barrier layer 41 is 50% or more (preferably 60% or more and 90% or less) and the thickness of each barrier layer 41 is 2 nm or more and 50 nm or less (preferably 5 nm or more and 20 nm or less), and each well layer 42 is grown such that the Al composition ratio of each well layer 42 is 30% or more and 40% or less and the thickness of each well layer 42 is 2 nm or more and 3.5 nm or less.

[0060] In the electron blocking layer growth step S4, on the active layer 40 grown by the active layer growth step S3 (on the surface of the active layer 40), the first electron blocking layer 51a and the second electron blocking layer 51b are epitaxially grown under the temperature condition of 1000 °C or higher and 1100 °C or lower. Thus, the electron blocking layer 51 is grown on the active layer 40. Further, in the electron blocking layer growth step S4, the first electron blocking layer 51a is grown such that the Al composition ratio of the first electron blocking layer 51a is 80% (preferably 100%) and the thickness of the first electron blocking layer 51a is 30 nm or less (preferably 0.5 nm or more and 5 nm or less, more preferably 1.5 nm or more and 2.5 nm or less), and the second electron blocking layer 51b is grown such that the Al composition ratio of the second electron blocking layer 51b is 45% or more and 90% or less and the thickness of the second electron blocking layer 51b is 10 nm or more and 115 nm or less. In addition, in the present embodiment, since a part of the second electron blocking layer 51b constitutes the dislocation-containing suppression structure layer 52, the second electron blocking layer 51b is grown such that it is thicker than the target thickness (5 nm or more and 100 nm or less) of the final second electron blocking layer 51b by the thickness (5 nm or more and 15 nm or less) of the dislocation-containing suppression structure layer 52.

[0061] In the step S5 of forming the dislocation suppression structure layer, tetramethylsilane (TMSi) and ammonia are supplied into the chamber under the temperature condition of 1000 °C or higher and 1100 °C or lower, and a plurality of dislocation suppression portions 521 are formed on the surface side of the second electron blocking layer 51b. That is, when tetramethylsilane and ammonia are supplied into the chamber under the temperature condition of 1000 °C or higher and 1100 °C or lower, silicon is doped into the matrix phase or a compound containing silicon (such as SiN) precipitates into the matrix phase on the surface side of the second electron blocking layer 51b. As a result, the growth mode of the matrix phase is changed, and a plurality of dislocation suppression portions 521 are formed. Thus, a dislocation suppression structure 520 is formed on the surface side of the second electron blocking layer 51b, and the dislocation suppression structure layer 52 is formed in such a manner that a part of the surface side of the second electron blocking layer 51b becomes the dislocation suppression structure layer 52. In addition, in the step S5 of forming the dislocation suppression structure layer, the height L1 of each dislocation suppression portion 521 in the stacking direction is made 5 nm or more and 50 nm or less (preferably 10 nm or more and 30 nm or less), the width L2 of each dislocation suppression portion 521 in the direction orthogonal to the stacking direction is made 5 nm or more and 200 nm or less, and the separation distance L3 between each dislocation suppression portion 521 and the active layer 40 in the stacking direction is made 0 nm or more and 100 nm or less (preferably 50 nm or less, more preferably 30 nm or less), thereby forming the dislocation suppression structure layer 52. As described above, the thickness of the dislocation suppression structure layer 52 is determined by the height L1 of each dislocation suppression portion 521 in the stacking direction. Therefore, in the step S5 of forming the dislocation suppression structure layer, it can also be said that the dislocation suppression structure layer 52 is formed in such a manner that the thickness of the dislocation suppression structure layer 52 is 5 nm or more and 50 nm or less (preferably 10 nm or more and 30 nm or less).

[0062] In the p-type cladding layer growth step S6, the first p-type cladding layer 53a and the second p-type cladding layer 53b are epitaxially grown on the dislocation-containing suppression structure layer 52 (on the surface of the dislocation-containing suppression structure layer 52) formed by the dislocation-containing suppression structure layer formation step S5 under the temperature condition of 1000 °C or higher and 1100 °C or lower. Thereby, the p-type cladding layer 53 is grown on the dislocation-containing suppression structure layer 52. In addition, in the p-type cladding layer growth step S6, the first p-type cladding layer 53a is grown such that the Al composition ratio of the first p-type cladding layer 53a is 55% or more and 65% or less and the thickness of the first p-type cladding layer 53a is 10 nm or more and 100 nm or less (preferably 55 nm or more and 85 nm or less), and the second p-type cladding layer 53b is grown such that the Al composition ratio of the second p-type cladding layer 53b has a compositional gradient from 60% to 0% and the thickness of the second p-type cladding layer 53b is 2 nm or more and 8 nm or less. In addition, the first p-type cladding layer 53a has a thickness of 10 nm or more and 100 nm or less, and preferably has a thickness of 55 nm or more and 85 nm or less.

[0063] In the p-type contact layer growth step S7, the p-type contact layer 54 is epitaxially grown on the p-type cladding layer 53 (on the surface of the p-type cladding layer 53) grown by the p-type cladding layer growth step S6 under the temperature condition of 900 °C or higher and 1100 °C or lower. In the p-type contact layer growth step S7, the p-type contact layer 54 is grown such that the Al composition ratio of the p-type contact layer 54 is 10% or less (preferably 0%) and the thickness of the p-type contact layer 54 is 10 nm or more and 30 nm or less (preferably 15 nm or more and 25 nm or less).

[0064] In the region removal step S8, a mask is formed on the p-type contact layer 54 grown by the p-type contact layer growth step S7, and the regions in the active layer 40, the electron blocking layer 51, the dislocation-containing suppression structure layer 52, the p-type cladding layer 53, and the p-type contact layer 54 where the mask is not formed are removed.

[0065] In the n-side electrode formation step S9, the n-side electrode 70 is formed on the exposed surface 30a of the n-type cladding layer 30 (refer to Figure 1 ). In the p-side electrode formation step S10, the p-side electrode 60 is formed on the p-type contact layer 54 from which the mask has been removed. The n-side electrode 70 and the p-side electrode 60 can be formed by well-known methods such as electron beam evaporation and sputtering.

[0066] In the dicing step S11, the wafer (the laminated structure body in which each layer and each electrode are formed on the wafer) is diced into a specified size. Thereby, the light-emitting element 1 shown in Figure 1 is formed.

[0067] (Examples and Comparative Examples)

[0068] Next, an embodiment of the light-emitting element 1 as a specific example of the above-described embodiment, and a first comparative example and a second comparative example of the light-emitting element 1 as comparative examples not having the dislocation suppression structure layer 52 will be described. In the configurations of the embodiment and each comparative example, parts not particularly specified are based on the above-described embodiment.

[0069] In the embodiment, the thicknesses of the buffer layer 20, n-type cladding layer 30, barrier layer 41, well layer 42, first electron blocking layer 51a, second electron blocking layer 51b, dislocation suppression structure layer 52, first p-type cladding layer 53a, second p-type cladding layer 53b, and p-type contact layer 54 are made 2000 nm, 2000 nm, 7 nm, 3 nm, 1.8 nm, 13.8 nm, 10 nm, 70 nm, 5 nm, and 20 nm, respectively. Further, for each dislocation suppression portion 521, the height L1 in the stacking direction is made 13.3 nm, the width L2 in the direction orthogonal to the stacking direction is made 42.2 nm, and the separation distance L3 between the active layer 40 and each dislocation suppression portion 521 is made 15.6 nm.

[0070] The first comparative example is a configuration in which the dislocation suppression structure layer 52 and the p-type cladding layer 53 are omitted and the thickness of the p-type contact layer 54 is increased. In the first comparative example, the thicknesses of the buffer layer 20, n-type cladding layer 30, barrier layer 41, well layer 42, first electron blocking layer 51a, second electron blocking layer 51b, and p-type contact layer 54 are made 2000 nm, 2000 nm, 7 nm, 3 nm, 1.8 nm, 23.8 nm, and 700 nm, respectively.

[0071] The second comparative example is a configuration in which the dislocation suppression structure layer 52 and the second p-type cladding layer 53b are omitted. In the second comparative example, the thicknesses of the buffer layer 20, n-type cladding layer 30, barrier layer 41, well layer 42, first electron blocking layer 51a, second electron blocking layer 51b, first p-type cladding layer 53a, and p-type contact layer 54 are made 2000 nm, 2000 nm, 7 nm, 3 nm, 1.8 nm, 23.8 nm, 75 nm, and 20 nm, respectively.

[0072] (Measurement Results)

[0073] In the above-described embodiment, first comparative example, and second comparative example, the initial light emission output and the remaining light emission output after energization were measured, and Figure 8The results shown in the table. In addition, the initial luminous output in this measurement result is the luminous output when a current of 350 mA is applied in the unused state, and the unit is mW (milliwatt). In addition, the remaining luminous output after energization in this measurement result is the percentage of the luminous output when a current of 350 mA is applied after long-term energization, with the initial luminous output being 100%, and the unit is %(percentage). In addition, in the measurement of the remaining luminous output after energization, as the long-term energization, the energization was performed for 208 hours for the examples, 160 hours for the first comparative example, and 96 hours for the second comparative example.

[0074] As Figure 8 shown, regarding the initial luminous output, the value of the example is much higher than that of the first comparative example and also higher than that of the second comparative example. In addition, as shown in this figure, regarding the remaining luminous output after energization, the value of the example is much higher than that of the second comparative example and also higher than that of the first comparative example. Thus, it can be seen that by thinning the p-type contact layer 54 and providing a dislocation suppression structure layer 52 between the p-type contact layer 54 and the active layer 40, a luminous output equal to or higher than that when only the p-type contact layer 54 is thinned can be obtained, and the temporal decrease in the luminous output with the passage of energization time can be suppressed to the same extent as when only the p-type contact layer 54 is thickened.

[0075] (Functions and effects of the embodiment)

[0076] As described above, according to the configuration of the above embodiment, by thinning the p-type contact layer 54 and providing a dislocation suppression structure layer 52 between the p-type contact layer 54 and the active layer 40, it is possible to suppress the dislocations D (through dislocations, dislocation lines) in the active layer 40 from reaching the p-type contact layer 54 (mainly the surface of the p-type contact layer 54), prevent current concentration accompanied by dislocations D or the intrusion of metal elements into the active layer 40, suppress the temporal decrease in the luminous output with the passage of energization time (the reliability is improved), and the luminous output can be increased. That is, if the thickness of the p-type contact layer 54 is increased to suppress the dislocations D from reaching the p-type contact layer 54, the ultraviolet light will be absorbed due to the light absorption caused by the thickness of the p-type contact layer 54, resulting in a decrease in the luminous output. However, according to the configuration of the above embodiment, even when the p-type contact layer 54 is thinned, it is possible to suppress the dislocations D from the active layer 40 from reaching the p-type contact layer 54 and suppress the temporal decrease in the luminous output with the passage of energization time. Therefore, it is possible to balance the suppression of the temporal decrease in the luminous output and the increase in the luminous output.

[0077] In addition, through the dislocation suppression structure 520, a light scattering effect will occur. Therefore, the luminous output can be further increased. That is, since the light is scattered by the dislocation suppression structure 520, the light does not enter the p-type contact layer 54 but returns to the n-type cladding layer 30 side. Therefore, the luminous output can be further increased.

[0078] (Modified Example)

[0079] In addition, in the above-described embodiment, the dislocation suppression structure 520 (dislocation suppression portion 521) is configured to bend the dislocation D (dislocation line) from the active layer 40, but it may also be configured that the dislocation suppression structure 520 (dislocation suppression portion 521) stops the dislocation D (dislocation line) from the active layer 40.

[0080] In addition, in the above-described embodiment, the dislocation suppression portion 521 has a trapezoidal cross-sectional shape with the active layer 40 side as the top side when viewed in a direction orthogonal to the stacking direction, but it may also be configured that the dislocation suppression portion 521 has a triangular cross-sectional shape with the active layer 40 side as the top side when viewed in a direction orthogonal to the stacking direction. Further, it may also be configured that the dislocation suppression portion 521 has a square cross-sectional shape, a circular cross-sectional shape, a semi-circular cross-sectional shape, an elliptical cross-sectional shape, a semi-elliptical cross-sectional shape, a trapezoidal cross-sectional shape with the p-type contact layer 54 side as the top side, a triangular cross-sectional shape with the p-type contact layer 54 side as the top side, etc. when viewed in a direction orthogonal to the stacking direction.

[0081] In addition, in the above-described embodiment, Si is introduced into the matrix phase to change the growth mode, or a compound containing Si (such as SiN) is precipitated to form the dislocation suppression portion 521, but the dislocation suppression portion 521 may also be formed of polycrystalline semiconductors such as SiN, SiN2, polysilicon, polycrystalline nitride semiconductors, etc. The dislocation suppression portion 521 may also be formed of oxides such as silicon oxide (SiO x ), titanium oxide (TiO x ), zirconium oxide (ZrO x ), etc. In addition, the dislocation suppression portion 521 may also be formed of well-known nitrides that are usually used as so-called ELO (Selective Lateral Growth) masks, and the dislocation suppression portion 521 may also be formed of high melting point metals such as titanium (Ti) and tungsten (W). Further, the dislocation suppression portion 521 may also be formed of a multilayer film of the materials listed here.

[0082] Moreover, in the above-described embodiment, tetramethylsilane and ammonia are supplied into the chamber under the temperature condition of 1000 °C or higher and 1100 °C or lower to form a plurality of dislocation suppression portions 521 on the AlGaN layer, but it may also be configured that well-known vapor growth methods such as evaporation, sputtering, VPE (Vapor Phase Epitaxy) are used as the formation method of the plurality of dislocation suppression portions 521.

[0083] In addition, in the above-described embodiment, the dislocation-inhibiting structure layer 52 is configured to be disposed between the electron blocking layer 51 and the p-type cladding layer 53. However, it may also be configured such that as long as the dislocation-inhibiting structure layer 52 is located between the active layer 40 and the p-type contact layer 54, the dislocation-inhibiting structure layer 52 can be disposed at any position in the multiple semiconductor layer 50. For example, it may be configured such that the dislocation-inhibiting structure layer 52 is disposed between the active layer 40 and the electron blocking layer 51, or it may be configured such that the dislocation-inhibiting structure layer 52 is disposed between the p-type cladding layer 53 and the p-type contact layer 54. Further, it may also be configured such that the dislocation-inhibiting structure layer 52 is disposed between the first electron blocking layer 51a and the second electron blocking layer 51b, or between the first p-type cladding layer 53a and the second p-type cladding layer 53b.

[0084] Moreover, in the above-described embodiment, the multiple semiconductor layer 50 is configured to have only one dislocation-inhibiting structure layer 52. However, it may also be configured such that the multiple semiconductor layer 50 has multiple dislocation-inhibiting structure layers 52. In this case, each position of the multiple dislocation-inhibiting structure layers 52 can also be disposed at any position in the multiple semiconductor layer 50. For example, it may be configured such that the multiple semiconductor layer 50 has two dislocation-inhibiting structure layers 52, with the first layer disposed between the electron blocking layer 51 and the p-type cladding layer 53, and the second layer disposed between the p-type cladding layer 53 and the p-type contact layer 54. Additionally, for example, it may also be configured such that the multiple semiconductor layer 50 has two dislocation-inhibiting structure layers 52, with the first layer disposed between the active layer 40 and the electron blocking layer 51, and the second layer disposed between the electron blocking layer 51 and the p-type cladding layer 53.

[0085] Furthermore, in the above-described embodiment, the multiple semiconductor layer 50 is configured to have an electron blocking layer 51, a dislocation-inhibiting structure layer 52, a p-type cladding layer 53, and a p-type contact layer 54. However, it may also be configured such that the electron blocking layer 51 is omitted in the multiple semiconductor layer 50, or it may be configured such that the p-type cladding layer 53 is omitted in the multiple semiconductor layer 50. Further, it may also be configured such that both the electron blocking layer 51 and the p-type cladding layer 53 are omitted in the multiple semiconductor layer 50.

[0086] In addition, in the above-described embodiment, the electron blocking layer 51 is a two-layer structure including a first electron blocking layer 51a with a high Al composition ratio and a second electron blocking layer 51b with a low Al composition ratio. However, the electron blocking layer 51 may also be a single-layer structure including only one layer.

[0087] Moreover, in the above-described embodiment, the p-type cladding layer 53 is a two-layer structure of a first p-type cladding layer 53a with a fixed Al composition ratio and a second p-type cladding layer 53b with a composition gradient of the Al composition ratio. However, the p-type cladding layer 53 may also be a single-layer structure including only one layer.

[0088] In addition, in the above-described embodiment, it may also be configured such that the active layer 40 has a dislocation suppression structure in which a plurality of dislocation suppression portions (e.g., V-shaped pits) are scattered vertically and horizontally in a direction orthogonal to the stacking direction. In this case, preferably, in a plan view, the positions of the respective dislocation suppression portions in the dislocation suppression structure of the active layer 40 coincide with the positions of the respective dislocation suppression portions 521 in the dislocation suppression structure 520 of the dislocation suppression structure-containing layer 52.

[0089] (Summary of the embodiment)

[0090] Next, regarding the technical idea grasped from the above-described embodiment, reference numerals in the embodiment are cited for description. However, the respective reference numerals and the like in the following description do not limit the constituent elements in the claims to the components specifically shown in the embodiment.

[0091] [1] A nitride semiconductor light-emitting element (1) that outputs ultraviolet light, characterized by comprising: an active layer (40) that includes a quantum well structure that generates the above-mentioned ultraviolet light; a dislocation suppression structure-containing layer (52) that is formed on the above-mentioned active layer (40) and includes a dislocation suppression structure (520) that stops or bends dislocations (D) from the above-mentioned active layer (40); and a p-type contact layer (54) that is formed on the above-mentioned dislocation suppression structure-containing layer (52) and has a thickness of 10 nm or more and 30 nm or less.

[0092] [2] The nitride semiconductor light-emitting element (1) according to [1], characterized in that the above-mentioned dislocation suppression structure (520) is composed of a plurality of dislocation suppression portions (521) scattered vertically and horizontally in a direction orthogonal to the stacking direction.

[0093] [3] The nitride semiconductor light-emitting element (1) according to [2], characterized in that each of the above-mentioned plurality of dislocation suppression portions (521) is a V-shaped pit.

[0094] [4] The nitride semiconductor light-emitting element (1) according to [2] or [3], characterized in that each of the above-mentioned plurality of dislocation suppression portions (521) has a trapezoidal cross-sectional shape or a triangular cross-sectional shape with the above-mentioned active layer (40) side as the top side when viewed from a direction orthogonal to the above-mentioned stacking direction.

[0095] [5] The nitride semiconductor light-emitting element (1) according to any one of [2] to [4], characterized in that the height (L1) of each of the above-mentioned plurality of dislocation suppression portions (521) in the above-mentioned stacking direction is 5 nm or more and 50 nm or less.

[0096] [6] The nitride semiconductor light-emitting element (1) according to any one of [2] to [5], characterized in that the width (L2) in a direction orthogonal to the stacking direction of each of the plurality of dislocation suppression portions (521) is 5 nm or more and 200 nm or less.

[0097] [7] The nitride semiconductor light-emitting element (1) according to any one of [2] to [6], characterized in that the separation distance (L3) in the stacking direction between each of the dislocation suppression portions (521) in the stacking direction and the active layer (40) is 0 nm or more and 100 nm or less.

Claims

1. A nitride semiconductor light-emitting device, which is a nitride semiconductor light-emitting device that outputs ultraviolet light, is characterized in that, Comprising: An active layer including a quantum well structure that generates the above ultraviolet light; A dislocation suppression structure layer formed on the above active layer, including a dislocation suppression structure that stops or bends dislocations from the above active layer; and A p-type contact layer formed on the above dislocation suppression structure layer, having a thickness of 10 nm or more and 30 nm or less, The above dislocation suppression structure includes a silicon-containing compound, The above active layer emits ultraviolet light with a central wavelength of 200 nm or more and 365 nm or less, The Al component ratio of the above p-type contact layer is 10% or less, The above dislocation suppression structure is composed of a plurality of dislocation suppression portions scattered vertically and horizontally in a direction orthogonal to the stacking direction, In the above dislocation suppression structure layer, regarding the concentration distribution of the Si concentration in the above stacking direction, there is a concentration peak higher than other parts in the above dislocation suppression structure layer, The Si concentration at the concentration peak of the above Si concentration is 1×10 18 [atoms / cm 3 or more and 1×10 20 [atoms / cm 3 or less. In the above dislocation suppression structure layer, regarding the concentration distribution of the Mg concentration in the above stacking direction, there is a concentration peak higher than other parts in the above dislocation suppression structure layer, The position of the concentration peak of the above Mg concentration and the position of the concentration peak of the above Si concentration are the same position in the above stacking direction, or positions with a deviation of ±5 nm or less.

2. The nitride semiconductor light-emitting element according to claim 1, wherein Each of the above plurality of dislocation suppression portions is a V-shaped pit.

3. The nitride semiconductor light-emitting element according to claim 1 or 2, wherein When each of the above plurality of dislocation suppression portions is viewed from a direction orthogonal to the above stacking direction, it has a trapezoidal cross-sectional shape or a triangular cross-sectional shape with the above active layer side as the top side.

4. The nitride semiconductor light-emitting element according to claim 1, wherein The height of each of the above plurality of dislocation suppression portions in the above stacking direction is 5 nm or more and 50 nm or less.

5. The nitride semiconductor light-emitting element according to claim 1, wherein The width of each of the above plurality of dislocation suppression portions in a direction orthogonal to the above stacking direction is 5 nm or more and 200 nm or less.

6. The nitride semiconductor light-emitting element according to claim 1, wherein The separation distance between each of the above plurality of dislocation suppression portions and the above active layer in the above stacking direction is 0 nm or more and 100 nm or less.

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