A low power consumption, high slew rate and low distortion output stage circuit

Abstract

A low-power, high-slew-rate, and low-distortion output-stage circuit belongs to the field of integrated circuits. It comprises an emitter follower, a bias current source, a Class AB output-stage circuit, a driver tube bias current positive feedback circuit, a capacitive coupling circuit, and a collector voltage synchronous tracking circuit. The driver tube bias current positive feedback circuit samples the output-stage current and provides positive feedback. The capacitive coupling circuit is located between the bases of the output devices. The collector voltage synchronous tracking circuit connects the emitter follower's collector to the emitter of the Class AB output-stage circuit, causing the emitter follower's collector voltage to change synchronously with the Class AB output-stage circuit's emitter voltage. This circuit addresses the low power consumption, low slew rate, and high distortion issues of existing Class AB output-stage circuits. By utilizing technical solutions such as driver tube bias current positive feedback, capacitive coupling, and collector voltage synchronous tracking, it achieves low quiescent current, high slew rate, and low distortion. The circuit is widely applicable to low-power, high-slew-rate, and low-distortion output-stage circuits.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits, and further relates to a low-power consumption, high-slew rate, and low-distortion output stage circuit. Background Art

[0002] In transistor amplifiers, Class AB output stages are widely used due to their low quiescent current and minimal crossover distortion. Quiescent current, slew rate, and distortion are key performance indicators for Class AB output stages.

[0003] like Figure 1 The figure shows a traditional Class AB output stage circuit structure. PNP device P1 and NPN device N1 form emitter followers. Current source I1 provides bias current for P1, while current source I2 provides bias current for N1. NPN device N2 and PNP device P2 are output devices, capable of supplying high current to the load. R1 and R2 are emitter degeneration resistors, which ensure a more even current flow between N2 and P2 and prevent current concentration. The output circuit structure formed by N2 and R1, and the output circuit structure formed by P2 and R2 are shown.

[0004] like Figure 1 As shown in the figure, to avoid extra power consumption and maximize the output swing, R1 and R2 are kept as small as possible. When unloaded, the emitter currents of N2 and P2 are equal and very small, so the voltage across R1 and R2 can be ignored.

[0005] like Figure 1 As shown, the emitter currents of P1 and N1 are I1 and I2, respectively. Let the ratio of the emitter area of P2 to P1 be kp, and the ratio of the emitter area of N2 to N1 be kn. The emitter currents of N2 and P2 are equal, let this current be I0. Ignoring the voltage across R1 and R2, for matching considerations, the design is generally:

[0006] I0=I1k p =I2k n .

[0007] Due to the consideration of high output current, the general output stage design will have kp and kn both much greater than 1. It can be seen that I0 is the main source of static current in Class AB output stage circuits.

[0008] Assuming that under the limiting current condition, the current gains of N2 and P2 are βn2 and βp2 respectively, the maximum pull-up current is:

[0009] I H =I1β N2 .

[0010] The maximum pull-down current is:

[0011] I L=I2β P2 .

[0012] From the above three equations, we can see that there is a contradiction between the maximum output current and the static power consumption. In order to reduce the static current, it is necessary to reduce I0, so it is necessary to either reduce I1 and I2, or reduce k p and k n Reducing I1 and I2 will directly reduce the maximum output current. Reducing kp and kn will reduce the driving capability of N2 and P2. n2 and β p2 attenuation, resulting in a decrease in the maximum output current.

[0013] like Figure 1 As shown in Figure 1, when the input signal suddenly changes, the fixed current charges the base capacitance of the output device, causing the slew rate to decrease. Taking the input signal as an example, when the emitter current of P1 suddenly drops to 0, I1 charges the base capacitance of N2. Assuming that the system slew rate is SR when the output stage delay is not considered, the sum of all the capacitances from the base of N2 to ground is C BN2 , since I2 is a fixed current, when The output stage delay will limit the slew rate of the system. The same problem will occur when the input signal suddenly drops.

[0014] like Figure 1 As shown in FIG, since N1 and P1 are emitter followers, their linearity will be affected by the Early voltage.

[0015] After normalization, the second harmonic of BJT is The third harmonic is The third-order intermodulation distortion is Where U is the relative current swing. For an emitter follower with a fixed collector voltage, Where V in is the amplitude of the input sinusoidal voltage signal, V A is the Early voltage. It can be seen that the nonlinearity is caused by the change of the collector-emitter voltage with the change of the input voltage.

[0016] In summary, the traditional Class AB output stage circuit structure faces three problems: 1. The contradiction between quiescent current and output current; 2. The slew rate is limited by the fixed bias current; 3. The nonlinearity or distortion problem caused by the emitter follower.

[0017] In view of this, the present invention is proposed. Summary of the Invention

[0018] The purpose of the present invention is to solve the following three major problems in existing Class AB output stage circuits:

[0019] 1. Reducing static power consumption will lead to the contradiction of reducing the maximum output current.

[0020] 2. When the input signal changes suddenly, the base capacitance of the output device is charged by a fixed current, which causes the slew rate to decrease.

[0021] 3. Since the input end is an emitter follower, it is affected by the Early voltage. The collector-emitter voltage changes with the input voltage, causing the linearity to become nonlinear and the output signal to be highly distorted.

[0022] To this end, the present invention provides a low-power, high-slew-rate, low-distortion output stage circuit, such as Figure 3-Figure 5 As shown in the figure, the contradiction between quiescent current and output current is resolved by using positive feedback technology of driver tube bias current; capacitor coupling technology is used to solve the problem of slew rate being limited by fixed bias current; and collector voltage synchronous tracking technology is used to solve the distortion problem caused by emitter follower.

[0023] Explanation of symbols involved in all formulas of the present invention:

[0024] IX represents a DC current source, and the number X following it represents the serial number of the DC current source.

[0025] IPXX represents the current at a certain port of a PNP device, where I represents the current symbol, P in the subscript PXX represents the PNP bipolar transistor symbol, the first X represents the device number, which is an Arabic numeral such as 1, 2, 3, etc., and the second X represents the device port, which is C (collector), B (base), and E (emitter).

[0026] INXX represents the current at a certain port of an NPN device, where I represents the current symbol, N in the subscript NXX represents the symbol of the NPN bipolar transistor, the first X represents the device number, which is an Arabic numeral such as 1, 2, 3, etc., and the second X represents the device port, which is C (collector), B (base), and E (emitter).

[0027] VPXX represents the voltage at a certain port of a PNP device, where I represents the current symbol, the P in the subscript PXX represents the PNP bipolar transistor symbol, the first X represents the device number, which is an Arabic numeral such as 1, 2, 3, etc., and the second X represents the device port, which is C (collector), B (base), and E (emitter).

[0028] VNXX represents the voltage at a certain port of an NPN device, where I represents the current symbol, N in the subscript NXX represents the symbol of the NPN bipolar transistor, the first X represents the device number, which is an Arabic numeral such as 1, 2, 3, etc., and the second X represents the device port, which is C (collector), B (base), and E (emitter).

[0029] KXXXX represents the ratio of the emitter areas of two bipolar transistor devices, where the first and third Xs represent the device type, which is P or N respectively; the second and fourth Xs represent the device number, which is Arabic numerals such as 1, 2, 3, etc.

[0030] like Figure 3-Figure 5 As shown, the driver tube bias current positive feedback scheme, capacitor coupling scheme, and collector voltage synchronous tracking scheme are described in detail as follows:

[0031] 1. Driver tube bias current positive feedback scheme

[0032] The positive feedback scheme of the driver tube bias current refers to increasing the pre-stage bias current of the output device while the output current increases, so as to achieve the purpose of improving the output current capability.

[0033] like Figure 2 As shown in the figure, P1, P2, P3, P4, P5, P6, and P7 are PNP transistors of the same type, and N1, N2, N3, N4, N5, N6, and N7 are NPN transistors of the same type. VBP and VBN are fixed voltage bias signals, and P6, P7, N6, and N7 respectively form DC current sources, of which P7 and N7 respectively form Figure 1 I1 and I2 in.

[0034] If the base current is neglected, then:

[0035] I N5C =I P6C .

[0036] I N6C =I P5C .

[0037]

[0038] N3 and P3 are used to sample the collector current of N2 and P2 respectively, so K N3N2 and K P3P2 Much less than 1.

[0039] When the output is unloaded, the current across R3 and R4 is very small, so the voltage across R3 and R4 can be ignored. At this time:

[0040]

[0041] After the matching design of P1, P2, N1, and N2, we have:

[0042] I N2C =I P2C =I N1C K N2N1 =I P1C K P2P1 .

[0043] Ignoring the base current and the collector currents of N3 and N3, we have:

[0044] I N1C =I N7C +I N4C .

[0045] I P1C =I P7C +I P4C .

[0046] You can get:

[0047] I N2C =I P2C =(I N7C +K N4N5 I N5C )K N2N1 =(I P7C +K P4P5 I P5C )K P2P1 .

[0048] Right now:

[0049] I N2C =I P2C =(I N7C +K N4N5 K P6P7 I P7C )K N2N1 =(I P7C +K P4P5 K N6N7 I N7C )K P2P1 .

[0050] Because I P7C , I N7C is a fixed current, K N4N5 , K N6N7 , K N2N1 , K P4P5 , K P6P7 , K P2P1 The device ratio is fixed, so the current of the output device is fixed.

[0051] When the output pull-up current is applied, the feedback mechanism will increase the collector current of P4. Assume that the output pull-up current increases ΔI relative to the quiescent current of the output device. OUT , then the collector current increment of P4 is:

[0052]

[0053] Where k is the Boltzmann constant, T is the thermodynamic temperature, and q is the elementary charge. Similarly, when the output pull-down current increases ΔI relative to the quiescent current of the output device, OUT , then the collector current increment of N4 is:

[0054]

[0055] Obviously, as the output current increases, the bias current of P4 and N4 also rises rapidly. When designing the circuit parameters, it is necessary to make the local loop gain less than 1 under high current conditions to avoid excessive current caused by positive feedback and burn out the device.

[0056] 2. Capacitive coupling solution

[0057] The capacitive coupling scheme refers to adding capacitors to make the base voltage of the output device change synchronously to achieve the purpose of increasing the slew rate.

[0058] like Figure 2 As shown, let the total capacitance from the base of N2 to ground be CBN2. When the input signal suddenly increases, the rising slope of the output signal, that is, the rising slope of the voltage at the base of N2 is:

[0059]

[0060] Similarly, assuming that the total capacitance from the base of P2 to ground is CBP2, when the input signal suddenly drops, the falling slope of the output signal, that is, the falling slope of the base voltage of P2 is:

[0061]

[0062] It can be seen that both the rising and falling slopes are limited by the fixed bias current.

[0063] like Figure 3 As shown, in Figure 2 Add capacitor C1 to the circuit. When the input signal suddenly increases, due to the emitter-follower structure of N1, the emitter voltage of N1 also increases suddenly. Due to the coupling effect of C1, the base voltage of N2 also increases suddenly. Suppose the voltage value of the sudden increase of the input signal is ΔV in ,but:

[0064]

[0065] Similarly, when the input signal suddenly drops ΔV in ,have:

[0066]

[0067] It can be seen that increasing C1 helps improve the slew rate. NP2 and C1>>C BP2When the output signal almost follows the input signal, the Class AB output stage circuit no longer imposes a significant restriction on the system's slew rate.

[0068] 3. Collector voltage synchronous tracking solution

[0069] The collector voltage synchronous tracking scheme is to achieve the purpose of improving linearity by making the collector voltage and emitter voltage of the emitter follower change synchronously.

[0070] like Figure 3 As shown, the relative current swing of emitter follower N1 is:

[0071]

[0072] Among them, I n1c is the AC small signal amplitude of the collector current of N1, g mN1 is the small signal transconductance of N1, r oN1 is the collector small signal output resistance of N1, k is the Boltzmann constant, T is the thermodynamic temperature, q is the elementary charge, V in is the amplitude of the input sinusoidal voltage signal, V AN is the Early voltage of the NPN.

[0073] The relative current swing of emitter follower N1 is:

[0074]

[0075] Among them, I p1c is the AC small signal amplitude of the collector current of P1, g mP1 is the small signal transconductance of P1, r oP1 is the collector small signal output resistance of P1, k is the Boltzmann constant, T is the thermodynamic temperature, q is the elementary charge, V in is the amplitude of the input sinusoidal voltage signal, V AP is the Early voltage of the PNP.

[0076] The second harmonic of N1 is:

[0077]

[0078] The third harmonic of N1 is:

[0079]

[0080] The third-order intermodulation distortion of N1 is:

[0081]

[0082] The second harmonic of P1 is:

[0083]

[0084] The third harmonic of P1 is:

[0085]

[0086] The third-order intermodulation distortion of N1 is:

[0087]

[0088] It can be seen that since the collector current changes with the input voltage signal, N1 and P1 produce nonlinearity. Figure 4 As shown, in Figure 3 On the basis of, connect the collector of P1 to the emitter of P2, and connect the collector of N1 to the emitter of N2. Ignore the voltage of R1 and R2, and ignore V N2B -V N2E and V P2E -V P2B The change of V N1B -V N1E and V P1E -V P1B Almost no V in changes, so:

[0089] I n1c =I p1c =0.

[0090] Therefore, the distortion introduced by N1 and P1 is all zero, and the Class AB output stage circuit will not add new distortion to the system.

[0091] Compared with the prior art, the present invention has the following beneficial effects:

[0092] The class AB output stage circuit structure of the present invention achieves the goals of low quiescent current, high slew rate and low distortion through a positive feedback scheme of the driving tube bias current, a capacitor coupling scheme and a synchronous tracking scheme of the collector voltage.

[0093] The technical solution of the present invention is widely used in the technical field of output stage circuits with low power consumption, high slew rate and low distortion. BRIEF DESCRIPTION OF THE DRAWINGS

[0094] Figure 1 This is a schematic diagram of the traditional Class AB output stage circuit structure.

[0095] Figure 2 This is a schematic diagram of the Class AB output stage circuit structure with a driver tube bias current positive feedback circuit.

[0096] Figure 3 This is a schematic diagram of the Class AB output stage circuit structure with a driver tube bias current positive feedback circuit and coupling capacitor.

[0097] Figure 4 This is a schematic diagram of the Class AB output stage circuit structure with a driver tube bias current positive feedback circuit, coupling capacitor and collector voltage synchronous tracking circuit.

[0098] Figure 5 The diagram is a schematic diagram of the integrated layout structure of a Class AB output stage circuit with a driver tube bias current positive feedback circuit, a coupling capacitor, and a collector voltage synchronous tracking circuit. DETAILED DESCRIPTION

[0099] like Figure 5 As shown, the embodiments of the present invention are as follows:

[0100] In the integrated circuit layout, the input units P1, N1 and the output units P2, N2, R1, R2 are divided into several groups of equal quantity, and each group is connected accordingly.

[0101] N3 and P3 respectively sample the current of one of N2 and P2, and the sampled current is sent to R3 and R4 respectively to increase the current of P4 and N4 when outputting large current.

[0102] Taking the base of P4 as the AC loop disconnect point, its loop gain is

[0103] GH = g mP4 β N2 K N3N2 R3

[0104] Taking the base of N4 as the AC loop disconnect point, its loop gain is

[0105] GL=g mN4 β P2 K P3P2 R4

[0106] where g mP4 is the transconductance of P4, g mN4 is the transconductance of N4, β N2 is the current gain of N2 under large current conditions, β P2 is the current gain of P2 at high current. By adjusting the parameters, both GH and GL are less than 1.

[0107] The capacitance of C1 is designed to be 10 times the sum of all the capacitances from the base of N2 and P2 to ground to avoid the delay of the Class AB output stage circuit affecting the system slew rate.

[0108] The collector of the PNP device group P1 is connected to the emitter of the corresponding PNP device group P2, and the collector of the NPN device group N1 is connected to the emitter of the corresponding NPN device group N2, so that V N1B -V N1E and VP1E -V P1B Almost no V in Changes occur so that the Class AB output stage circuit does not increase system distortion.

[0109] In summary, the Class AB output stage circuit structure described in the present invention achieves the goals of low quiescent current, large slew rate, and low distortion through the positive feedback scheme of the driving tube bias current, the capacitor coupling scheme, and the collector voltage synchronous tracking scheme.

[0110] It should be noted that the embodiments described above are intended to be illustrative and not limiting of the scope of the present invention, which is subject to the claims. Those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, if such modifications and variations fall within the scope of the claims and their equivalents, the present invention is intended to encompass such modifications and variations.

Claims

1. A low-power, high-slew-rate, low-distortion output stage circuit, characterized in that: include: Same type of PNP transistors P1, P2, P3, P4, P5, P6, P7, same type of NPN transistors N1, N2, N3, N4, N5, N6, N7, resistors R1, R2, R3, R4; fixed voltage bias signals VBP and VBN; positive power supply VCC and negative power supply VEE; The P1 and N1 respectively constitute emitter followers, serving as input circuits of the output stage circuit; The P2, N2, R1 and R2 constitute a class AB push-pull amplifier, which serves as the output circuit of the output stage circuit; P6 and P7 constitute the DC current source at the emitter end of P1; Said N6 and N7 constitute the DC current source at the emitter end of N1; P4 and P5 form a positive feedback circuit for outputting a pull-up current, and the collector current of P4 generates an increment, so that the local loop gain is less than 1 under high current conditions; N4 and N5 form a positive feedback circuit for outputting a pull-down current, and the collector current of N4 generates an increment, so that the local loop gain is less than 1 under high current conditions; N3 samples the collector current of N2, and the sampled current is sent to R3; P3 samples the collector current of P2, and the sampled current is sent to R4; The base of P1 is connected to the base of N1 and the input signal terminal, the collector of P1 is connected to the VEE terminal, the emitter of N7, the emitter of N6, one end of R4, the emitter of N4, and the collector of P2, the emitter of P1 is connected to the collector of P7, the collector of P4, the base of N3, and the base of N2; the collector of N1 is connected to the power supply VCC terminal, the emitter of P7, the emitter of P6, one end of R3, the emitter of P4, and the collector of N2, the emitter of N1 is connected to the collector of N7, the collector of N4, the base of P3, and the base of P2; the base of P7 is connected to the base of P6 and VBP end is connected; the emitter of P5 is connected to the other end of R3 and the collector of N3, the collector of P5 is connected to the collector of N6, and the base of P5 is connected to the collector of P5 and the base of P4; the base of N7 is connected to the VBN end and the base of N6; the emitter of N5 is connected to the other end of R4 and the collector of P3, the collector of N5 is connected to the collector of P6, the base of N5 and the base of N4; the emitter of P3 is connected to the emitter of P2 and one end of R2; the emitter of N3 is connected to the emitter of N2 and one end of R1; the other end of R1 and the other end of R2 are connected to the output signal end.

2. The low-power, high-slew-rate, low-distortion output stage circuit according to claim 1, wherein: A capacitor C1 is connected between the bases of N2 and N3 and the bases of P2 and P3.

3. The low-power, high-slew-rate, low-distortion output stage circuit according to claim 2, wherein: The capacitance of C1 is 10 times the sum of all the capacitances from the base of N2 and P2 to the ground.

4. The low-power, high-slew-rate, low-distortion output stage circuit according to claim 2, wherein: Connect the collector of P1 to the emitter of P2, and connect the collector of N1 to the emitter of N2 to form a collector voltage synchronous tracking circuit.

5. The low-power, high-slew-rate, low-distortion output stage circuit according to claim 1, wherein: In the integrated circuit layout, the P1, N1, P2, N2, R1, and R2 are divided into several groups of equal quantity, and each group is connected in parallel.

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