Calibration method and device for analog-to-digital converter based on memristor array

Abstract

A calibration method and electronic device for an analog-to-digital converter based on a memristor array. The analog-to-digital converter includes an input terminal, a bias terminal, and a result output terminal. The calibration method includes: performing a multiplication-addition operation using at least one column of the memristor array, providing a first current to the input terminal, and providing a reference current to the bias terminal via a regulation circuit to obtain a first digital output value at the result output terminal; determining whether the first digital output value matches a target digital output value corresponding to the first current; and, in response to a mismatch between the first digital output value and the target digital output value, adjusting the reference current provided to the regulation circuit. This method and device can calibrate the analog-to-digital converter, and has low overhead and simple operation for existing memristor array architectures.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a method and apparatus for calibrating an analog-to-digital converter based on a memristor array. Background Art

[0002] With the advancement of science and technology and the rapid development of information technology, computing architectures based on memristor arrays are considered to be a highly promising next-generation data processing device due to their advantages such as integrated storage and computing, low energy consumption, large-scale integration, and parallel operation. Furthermore, with the continuous increase in data storage density, the necessity of multi-resistance devices is becoming increasingly prominent. This not only places higher demands on multi-resistance devices, but also requires supporting peripheral circuits to perform reliable and efficient write operations on the devices. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a calibration method for an analog-to-digital converter, wherein the analog-to-digital converter includes an input terminal, a bias terminal, and a result output terminal. The calibration method includes: performing a multiplication-addition operation using at least one column of a memristor array, providing a first current to the input terminal, and providing a reference current to the bias terminal through an adjustment circuit to obtain a first digital output value at the result output terminal; determining whether the first digital output value matches a target digital output value corresponding to the first current; and in response to the first digital output value not matching the target digital output value, adjusting the magnitude of the reference current provided to the adjustment circuit to reduce the degree of mismatch between the first digital output value and the target digital output value.

[0004] For example, in a calibration method for an analog-to-digital converter provided in at least one embodiment of the present disclosure, in response to a mismatch between a first digital output value and the target digital output value, the magnitude of a reference current provided by an adjustment circuit is adjusted, including: in response to the first digital output value being greater than the target digital output value, increasing the reference current to reduce the degree of mismatch between the first digital output value and the target digital output value; or in response to the first digital output value being less than the target digital output value, decreasing the reference current to reduce the degree of mismatch between the first digital output value and the target digital output value.

[0005] For example, in a calibration method for an analog-to-digital converter provided in at least one embodiment of the present disclosure, the magnitude of a reference current provided by an adjustment circuit is adjusted, including: in response to a mismatch between the first digital output value and the target digital output value, feeding back the first digital output value of the analog-to-digital converter to the adjustment circuit; changing the reference current by the adjustment circuit according to the first digital output value, and providing the changed first digital output value to the bias terminal.

[0006] For example, in a calibration method for an analog-to-digital converter provided in at least one embodiment of the present disclosure, before providing a first current to an input terminal through at least one column of a memristor array, the calibration method further includes: programming at least one column of the memristor array so that the conductance of each memristor in the at least one column is in a first conductance state, wherein a target digital output value is determined corresponding to the first conductance state.

[0007] For example, in a calibration method for an analog-to-digital converter provided in at least one embodiment of the present disclosure, the first conductance state of the conductance of each memristor is an intermediate resistance state of the conductance value of each memristor.

[0008] For example, in a calibration method for an analog-to-digital converter provided in at least one embodiment of the present disclosure, at least one column includes 1 column, and programming at least one column of the memristor array includes: programming the 1 column in the memristor array so that the conductance of each memristor in the 1 column is in a first conductance state.

[0009] For example, in a calibration method for an analog-to-digital converter provided in at least one embodiment of the present disclosure, performing a multiplication-addition operation using at least one column of a memristor array includes: inputting the same input voltage signal to the input ends of each row of the memristor array, and performing a multiplication-addition operation on the input voltage signal and the conductance value of the memristor in at least one column by using at least one column of the memristor array, and obtaining a first current as the operation result from the input end.

[0010] For example, in a calibration method for an analog-to-digital converter provided in at least one embodiment of the present disclosure, the method further includes: selecting a reference current when the first digital output value matches the target digital output value as the rated standard reference current of the analog-to-digital converter.

[0011] At least one embodiment of the present disclosure provides a calibration device for an analog-to-digital converter, wherein the analog-to-digital converter includes an input terminal, a bias terminal, and a result output terminal, and the calibration device includes: a signal acquisition module, configured to operate at least one column in a memristor array to perform multiplication and addition operations to obtain a first current and provide the first current to the input terminal of the analog-to-digital converter; an adjustment circuit, configured to provide a reference current to the bias terminal of the analog-to-digital converter, wherein the analog-to-digital converter performs analog-to-digital conversion on the first current based on the first current and the reference current, and outputs a first digital output value; a control drive module, configured to receive the first digital output value and determine whether the first digital output value matches a target digital output value corresponding to the first current, and when the first digital output value does not match the target digital output value, the adjustment circuit adjusts the magnitude of the reference current to reduce the degree of mismatch between the first digital output value and the target digital output value.

[0012] For example, in a calibration device for an analog-to-digital converter provided in at least one embodiment of the present disclosure, the control drive module is further configured to: when the first digital output value is greater than the target digital output value, increase the reference current to reduce the degree of mismatch between the first digital output value and the target digital output value; or when the first digital output value is less than the target digital output value, decrease the reference current to reduce the degree of mismatch between the first digital output value and the target digital output value. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0014] Figure 1 shows a schematic diagram of a memristor array;

[0015] Figure 2A shows a schematic diagram of a memristor unit having a 1T1R structure;

[0016] Figure 2B shows a schematic diagram of a memristor unit having a 2T2R structure;

[0017] Figure 2C The figure is a schematic diagram of a memristor device including a memristor array;

[0018] Figure 3 A schematic flowchart of a method for calibrating an analog-to-digital converter based on a memristor array according to at least one embodiment of the present disclosure;

[0019] Figure 4 A schematic diagram of an analog-to-digital converter for a memristor array provided by at least one embodiment of the present disclosure;

[0020] Figure 5 A schematic flowchart of an example of a method for calibrating an analog-to-digital converter based on a memristor array according to at least one embodiment of the present disclosure;

[0021] Figure 6 A schematic diagram illustrating a method for calibrating an analog-to-digital converter for a memristor array provided in accordance with at least one embodiment of the present disclosure; and

[0022] Figure 7 A schematic block diagram of a calibration device for an analog-to-digital converter provided in at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0024] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0025] The present disclosure is described below through several specific embodiments. To keep the following description of the embodiments of the present invention clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of an embodiment of the present invention appears in more than one figure, the component is represented by the same reference numeral in each figure.

[0026] Since the analog-to-digital converter quantizes the final result after multiplying and adding the conductance values ​​in the memristor array, a calibration method based on the memristor array that is low-cost, easy to operate, and can optimize the accuracy of the analog-to-digital converter is particularly critical.

[0027] Memristors, as a new type of electronic device, can adjust their conductance state by applying external stimuli. Before a memristor array operates, it is typically necessary to set the individual conductance values ​​within the array to within a desired range. For example, memristor array operations include reset and set operations to adjust the memristor resistance, as well as sampling operations to read the memristor resistance.

[0028] After setting the conductance of each memristor in the memristor array, the resistance (or conductance) of the memristor unit can be read by a read circuit. This read circuit can detect the current flowing through the memristor and convert the detected current value into a corresponding digital value (digital code). For example, the read circuit includes an SA (sensing amplifier) ​​to detect the current. In order to convert the detected current value into a corresponding digital value, the SA can further include an IDAC (bit current digital-to-analog converter) to provide the reference current required for the conversion. As the process feature size advances, the conductance of the devices in the memristor becomes smaller and smaller (i.e., the resistance value becomes larger and larger). In addition, in order to avoid read interference, the upper limit of the read voltage applied to the memristor when reading the resistance value of the memristor is usually limited. For example, the typical value of the read voltage is 0.2V, so the current flowing through the memristor becomes smaller and smaller.

[0029] Furthermore, given the requirements for multi-bit devices and redundancy in circuit design, the read currents used to characterize the different conductance states of memristor arrays are becoming increasingly smaller. For example, in a 28nm process, the unit current can be as low as a few hundred nanoamperes. However, actual simulations have shown that accurately replicating currents in the hundreds of nanoamperes range is not easy, and the SA often requires calibration during device programming.

[0030] For example, memristors in a memristor array are typically assigned a conductance range and are expected to be programmed to within this specified range. During the memristor conductance programming process, after the conductance value is set and then read and verified, the reference current values ​​provided by the IDACs in the readout circuit's SA (Automatic Detector) truly define the conductance of the memristor array. Therefore, accurate replication of the unit current by the IDACs in the readout circuit's SA is crucial. To ensure the device remains within the specified conductance range, increasing the unit reference current mirror (overall IDAC drift) will result in underutilization of the SA's range. Decreasing the unit reference current mirror (overall IDAC drift) will cause the SA to exceed its range. Both of these situations result in suboptimal SA accuracy in practical applications. Furthermore, using the inaccurate current detected by the SA as a reference for device programming can cause the programmed conductance range of the device to deviate from the pre-set range.

[0031] For example, for a fixed read voltage, such as a 0.2V read voltage used by the read circuit, when reading the conductance of the memristor, for a conductance of 2μS to 20μS, the resulting detection current ranges from 0.4μA to 4μA, which corresponds to a specific conductance and produces a specific and unique digital output value. To achieve accurate measurement, the SA in the read circuit needs to be verified. To verify the SA, for example, an externally adjustable and known current source can be used as the input of the SA, the output of the SA can be observed, and the actual digital output of the SA can be compared with the expected digital output. The current bias of the IDAC included in the SA can then be adjusted based on the comparison result so that the actual digital output code output by the SA corresponds to the expected digital output code, thereby verifying the SA.

[0032] Conventionally, verifying the accuracy of the SA in the reading circuit of the device requires setting a precise resistor on the chip and applying a predetermined detection voltage to the resistor to verify the SA, or generating a precise current and detecting the current through the SA to verify the SA. However, these methods will undoubtedly increase additional overhead, and the verification operation is cumbersome.

[0033] On the other hand, for a memristor array, after programming the conductance values ​​of each memristor in the memristor array, when using the memristor array to perform operations (such as performing inference operations or training operations on a neural network), the memristor array generates an output signal by performing multiplication and addition operations on an input signal, such as an input voltage signal, and outputs the output signal (current signal) through an output circuit. For example, the output circuit includes an analog-to-digital converter (ADC), which performs analog-to-digital conversion on the output signal to obtain a corresponding digital value, which is used, for example, for subsequent processing by software or hardware. Therefore, the accuracy of the ADC that outputs and reads the output signal of the memristor array is also a value that needs to be verified so that the range of the ADC can match the range of the output signal of the memristor array.

[0034] In this regard, the inventors of the present disclosure have discovered that, in actual operation, assuming that the deviation of the detection results of the SA in the read circuit of the memristor array is not particularly large, then the deviation of the conductivity state range of the memristor obtained by programming based on the SA from the predetermined range will not be large. Therefore, even if the reference current of the IDAC included in the SA is inaccurate, the relative ratio between the various conductivity states of the memristor obtained by programming using the SA will not change, and a certain number of bits of data can also be normally represented. Therefore, the overall linearity deviation caused by programming using the SA is not an essential problem. Moreover, in the actual circuit implementation process, when the surrounding environments of the IDAC units in each SA in the read circuit are ensured to be sufficiently similar, the ratio between the various conductivity states, that is, the linearity, can be fully guaranteed. However, for the ADC of the output circuit of the memristor array, since it is necessary to digitize the output current of a column of devices, if the range of the ADC is still designed according to the preset resistance range, it is easy for the output of the ADC to exceed the range or be underutilized. Therefore, it is urgent to realize a calibration method with low cost and simple operation to improve the accuracy of the ADC in the output circuit of the memristor array without causing loss of the range of the SA in the reading circuit.

[0035] At least one embodiment of the present disclosure provides a calibration method for an analog-to-digital converter based on a memristor array. The analog-to-digital converter includes an input terminal, a bias terminal, and a result output terminal. The calibration method includes: performing a multiplication-addition operation using at least one column of the memristor array, providing a first current to the input terminal, and providing a reference current to the bias terminal through a regulation circuit to obtain a first digital output value at the result output terminal; determining whether the first digital output value matches a target digital output value corresponding to the first current; and in response to the first digital output value not matching the target digital output value, adjusting the magnitude of the reference current provided to the regulation circuit to reduce the degree of mismatch between the first digital output value and the target digital output value.

[0036] At least one embodiment of the present disclosure provides a calibration device for an analog-to-digital converter, wherein the analog-to-digital converter includes an input terminal, a bias terminal, and a result output terminal, and the calibration device includes a signal acquisition module, an adjustment circuit, and a control drive module. The signal acquisition module is configured to operate at least one column of a memristor array to perform a multiplication-addition operation to obtain a first current and provide the first current to the first input terminal of the analog-to-digital converter; the adjustment circuit is configured to provide a reference current to the bias terminal of the analog-to-digital converter, wherein the analog-to-digital converter performs analog-to-digital conversion on the first current based on the first current and the reference current and outputs a first digital output value; the control drive module is configured to receive the first digital output value and determine whether the first digital output value matches a target digital output value corresponding to the first current. When the first digital output value does not match the target digital output value, the adjustment circuit adjusts the magnitude of the first reference current to reduce the degree of mismatch between the first digital output value and the target digital output value.

[0037] The above-mentioned embodiments of the present disclosure disclose a method and apparatus for calibrating an analog-to-digital converter based on a memristor array, such as an analog-to-digital converter (ADC) used in an output circuit of a memristor array, which can calibrate the ADC in the memristor array. Furthermore, the calibration has low overhead for the memristor array architecture and is simple to operate. The accuracy of the ADC in the output circuit can be improved based on the accuracy of the SA in the reading circuit, thereby improving the accuracy of inference operations or training operations performed after programming the memristor array.

[0038] The memristor array operates by performing multiplication and accumulation calculations in parallel based on Kirchhoff's current law and Ohm's law. Furthermore, both data storage and calculation can be performed by the various devices in the memristor array, avoiding the overhead of data movement in the von Neumann architecture.

[0039] For example, Figure 1 A schematic diagram of a memristor array is shown. Figure 1 As shown, the memristor array is composed of a plurality of memristor units, which form an array of M rows and N columns, where M and N are both positive integers. Each memristor unit includes a switch element and one or more memristors. <1> 、WL <2> ...WL <m>Represent the word lines of the first row, the second row, ... the Mth row, BL <1> BL <2> ...BL <n>Represents the bit lines of the first column, the second column...the Nth column, and SL <1> , SL <2> ...SL <m>Respectively represent the source lines of the first row, the second row, ... the Mth row. The control electrode (e.g., the gate of the transistor) of the switch element in each row of the memristor unit circuit is connected to the word line corresponding to the row, the memristor in each column of the memristor unit circuit is connected to the bit line corresponding to the column, and the source electrode of the transistor in each row of the memristor unit circuit is connected to the source line corresponding to the row. It should be noted that the direction of rows and columns in this disclosure is not limited to Figure 1 The scope of the present disclosure is not limited to the situation in the above description, but can be determined as needed, and will not be described in detail below.

[0040] For example, Figure 1 The memristor unit shown can be, for example, a 1T1R structure or a 2T2R structure, wherein the memristor unit of the 1T1R structure includes a switching transistor and a memristor, and the memristor unit of the 2T2R structure includes two switching transistors and two memristors. The present disclosure has no restrictions on the type, structure, etc. of the memristor device. It should be noted that the transistors used in the embodiments of the present disclosure can all be thin-film transistors or field-effect transistors (such as MOS field-effect transistors) or other switching devices with the same characteristics. The source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be structurally indistinguishable. The embodiments of the present disclosure do not limit the type of transistor used.

[0041] For example, Figure 2A A schematic diagram of a memristor unit with a 1T1R structure is shown, Figure 2A As shown, the 1T1R structured memristor unit includes a transistor M1 and a memristor R1.

[0042] For example, when the transistor M1 is an N-type transistor, its gate is connected to the word line terminal WL, for example, when a high level is input to the word line terminal WL, the transistor M1 is turned on; the first electrode of the transistor M1 can be a source electrode and is configured to be connected to the source line terminal SL, for example, the transistor M1 can receive a reset voltage through the source line terminal SL; the second electrode of the transistor M1 can be a drain electrode and is configured to be connected to the second electrode (for example, the negative electrode) of the memristor R1, and the first electrode (for example, the positive electrode) of the memristor R1 is connected to the bit line terminal BL, for example, the memristor R1 can receive a set voltage through the bit line terminal BL. For example, when transistor M1 is a P-type transistor, its gate is connected to the word line terminal WL. For example, when the word line terminal WL is input with a low level, transistor M1 is turned on. The first electrode of transistor M1 can be a drain and configured to be connected to the source line terminal SL. For example, transistor M1 can receive a reset voltage through the source line terminal SL. The second electrode of transistor M1 can be a source and configured to be connected to the second electrode (for example, the negative electrode) of memristor R1. The first electrode (for example, the positive electrode) of memristor R1 is connected to the bit line terminal BL. For example, memristor R1 can receive a set voltage through the bit line terminal BL. It should be noted that the resistive memory structure can also be implemented as other structures, such as a structure in which the second electrode of memristor R1 is connected to the source line terminal SL, and the embodiments of the present disclosure are not limited to this.

[0043] The following embodiments are described by taking the transistor M1 as an N-type transistor as an example.

[0044] The function of the word line terminal WL is to apply a corresponding voltage to the gate of the transistor M1, thereby controlling whether the transistor M1 is turned on or off. When operating the memristor R1, such as performing a set operation or a reset operation, it is necessary to first turn on the transistor M1, that is, it is necessary to apply a turn-on voltage to the gate of the transistor M1 through the word line terminal WL. After the transistor M1 is turned on, for example, a voltage can be applied to the memristor R1 through the source line terminal SL and the bit line terminal BL to change the resistance state of the memristor R1. For example, a set voltage can be applied through the bit line terminal BL to put the memristor R1 in a low-resistance state; for another example, a reset voltage can be applied through the source line terminal SL to put the memristor R1 in a high-resistance state. For example, the resistance value of the high-resistance state is more than 100 times the resistance value of the low-resistance state, for example, more than 1000 times.

[0045] It should be noted that in the embodiments of the present disclosure, for example, by simultaneously applying voltages to the word line terminal WL and the bit line terminal BL, the resistance of the memristor R1 can be made smaller, that is, the memristor R1 changes from a high-resistance state to a low-resistance state. The operation of changing the memristor R1 from a high-resistance state to a low-resistance state is referred to as a set operation. By simultaneously applying voltages to the word line terminal WL and the source line terminal SL, the resistance of the memristor R1 can be made larger, that is, the memristor R1 changes from a low-resistance state to a high-resistance state. The operation of changing the memristor R1 from a low-resistance state to a high-resistance state is referred to as a reset operation. For example, the memristor R1 has a threshold voltage. When the input voltage amplitude is less than the threshold voltage of the memristor R1, the resistance value (or conductance value) of the memristor R1 does not change. In this case, the resistance value (or conductance value) of the memristor R1 can be used for calculations by inputting a voltage less than the threshold voltage; the resistance value (or conductance value) of the memristor R1 can be changed by inputting a voltage greater than the threshold voltage.

[0046] For example, Figure 2B FIG shows a schematic diagram of a memristor unit with a 2T2R structure. Figure 2B As shown, the 2T2R structure memristor unit includes two transistors M1 and M2 and two memristors R1 and R2. The following description is based on an example in which both transistors M1 and M2 are N-type transistors.

[0047] The gate of the transistor M1 is connected to the word line terminal WL1. For example, when a high level is input to the word line terminal WL1 of M1, the transistor M1 is turned on. The gate of the transistor M2 is connected to the word line terminal WL2. For example, when a high level is input to the word line terminal WL2 of M2, the transistor M2 is turned on. The first electrode of the transistor M1 can be a source and is configured to be connected to the source line terminal SL. For example, the transistor M1 can receive a reset voltage through the source line terminal SL. The first electrode of the transistor M2 can be a source and is configured to be connected to the source line terminal SL. For example, the transistor M2 can receive a reset voltage through the source line terminal SL. The first electrode of the transistor M1 is connected to the first electrode of the transistor M2, and is connected together to the source line terminal SL. The second electrode of the transistor M1 may be a drain and configured to be connected to the second electrode (e.g., the negative electrode) of the memristor R1, and the first electrode (e.g., the positive electrode) of the memristor R1 is connected to the bit line terminal BL1, for example, the memristor R1 may receive a set voltage through the bit line terminal BL1; the second electrode of the transistor M2 may be a drain and configured to be connected to the second electrode (e.g., the negative electrode) of the memristor R2, and the first electrode (e.g., the positive electrode) of the memristor R2 is connected to the bit line terminal BL2, for example, the memristor R2 may receive a set voltage through the bit line terminal BL2.

[0048] It should be noted that the transistors M1 and M2 in the 2T2R structure memristor unit may also be P-type transistors, which will not be described in detail here.

[0049] For example, when performing a read operation on the memristor R1, Figure 2A As shown, transistor M1 needs to be turned on first. That is, a turn-on voltage can be applied to the gate of transistor M1 through the word line terminal WL. For example, the source line terminal SL can be grounded and a DC voltage can be provided to the resistor to be read. For example, a DC voltage can be applied to the bit line terminal BL, and the current flowing through the resistor can be read using the SA. The SA can output a digital output code corresponding to the detected current. Therefore, this digital output code can directly reflect the size of the resistance value in the memristor unit. For example, when the resistance value reflected by the SA deviates from the expected resistance value, a corresponding set operation or reset operation can be performed on the memristor unit to change the resistance value of the memristor unit, thereby changing the resistance value of the memristor unit and then reading it again through the SA.

[0050] Figure 2C Schematic diagram of a memristor device including a memristor array. The memristor device includes a memristor array and a peripheral driving circuit thereof, wherein the peripheral driving circuit is used to realize input and output functions. Figure 2C As shown, the memristor device includes a signal acquisition device, a word line driver circuit, a bit line driver circuit, a source line driver circuit, a memristor array, and a data output circuit. Furthermore, the memristor device may further include a read circuit (not shown) comprising a sense amplifier (SA) for reading the resistance value of the programmed memristor.

[0051] For example, the signal acquisition device is configured to convert the digital signal into a plurality of first analog signals through a digital to analog converter (DAC) so as to be input to a plurality of column signal input terminals of the memristor array when performing signal processing, for example.

[0052] For example, a memristor array includes M source lines, M word lines, and N bit lines, as well as a plurality of memristor cells arranged in an array of M rows and N columns. For example, each memristor cell has a 1T1R structure. For example, a parameter matrix for Fourier transform can be mapped to the plurality of memristor cells in the memristor array.

[0053] For example, the operation of the memristor array is achieved through a word line driver circuit, a bit line driver circuit, and a source line driver circuit.

[0054] For example, a word line driver circuit includes multiple multiplexers (Mux) for switching word line input voltages; a bit line driver circuit includes multiple multiplexers for switching bit line input voltages; and a source line driver circuit also includes multiple multiplexers (Mux) for switching source line input voltages. For example, the source line driver circuit also includes multiple ADCs for converting analog signals into digital signals.

[0055] For example, the memristor array includes a programming (same below) mode and a computing mode. When the memristor array is in the operating mode, the memristor unit is in the initialized state, and the values ​​of the parameter elements in the parameter matrix can be written into the memristor array, for example, the weight matrix of the neural network can be mapped to the memristor array. For example, the source line input voltage, bit line input voltage, and word line input voltage of the memristor are switched to the corresponding preset voltage range through a multiplexer. Then, by applying a read voltage to the input end of the memristor array, the resistance value of each memristor in the memristor array can be detected through the reading circuit; and if the resistance value of a memristor does not match the preset value, it can be reset.

[0056] For example, by Figure 2C The control signal WL_sw[1:M] of the multiplexer in the word line driving circuit switches the word line input voltage to the corresponding voltage range. For example, when the memristor is set, the word line input voltage is set to 2V (volts). For example, when the memristor is reset, the word line input voltage is set to 5V. For example, the word line input voltage can be Figure 2C The voltage signal V_WL[1:M] in is obtained.

[0057] For example, by Figure 2C The control signal SL_sw[1:M] of the multiplexer in the source line driving circuit switches the source line input voltage to the corresponding voltage range. For example, when the memristor is set, the source line input voltage is set to 0V, and when the memristor is reset, the source line input voltage is set to 2V. For example, the source line input voltage can be Figure 2C The voltage signal V_SL[1:M] in is obtained.

[0058] For example, by Figure 2C The control signal BL_sw[1:N] of the multiplexer in the bit line driving circuit switches the bit line input voltage to the corresponding voltage range. For example, when the memristor is set, the bit line input voltage is set to 2V, and when the memristor is reset, the bit line input voltage is set to 0V. For example, the bit line input voltage can be Figure 2C The DAC is obtained.

[0059] For example, when the memristor array is in computing mode, the memristors in the memristor array are in a conductive state that can be used for computing (inference or training), and the bit line input voltage input to the column signal input terminal does not change the conductance value of the memristor. For example, multiplication and addition operations can be performed through the memristor array to complete the calculation. Figure 2C The control signal WL_sw[1:M] of the multiplexer in the word line driving circuit switches the word line input voltage to the corresponding voltage range. For example, when the start signal is applied, the word line input voltage of the corresponding row is set to 5V. For example, when the start signal is not applied, the word line input voltage of the corresponding row is set to 0V, for example, the GND signal is connected. Figure 2C The control signal SL_sw[1:M] of the multiplexer in the source line driver circuit determines which columns the output current is quantized; and BL_sw[1:N] determines which BLs apply the input voltage.

[0060] For example, the data output circuit may include multiple ADCs, which may quantize current signals at multiple column signal output terminals and convert them into digital outputs.

[0061] Figure 3 A schematic flowchart of a method for calibrating an analog-to-digital converter based on a memristor array according to at least one embodiment of the present disclosure; Figure 4 A schematic diagram of an analog-to-digital converter for a memristor array provided in at least one embodiment of the present disclosure. Figure 3 and Figure 4 Provide explanation.

[0062] like Figure 4 As shown, the memristor device includes a memristor array 201 and an analog-to-digital converter in an output circuit coupled to the memristor array 201. The memristor array 201 includes multiple rows and columns of memristor units. Figure 4 Only one column is shown as an example, and all components except the analog-to-digital converter are omitted. The memristor array 201 can receive one or more voltage signals in the row direction and, after processing by the memristor array 201, output one or more output currents in the column direction. The output current corresponding to a column of memristors is the result of multiplying and adding the conductance of the memristors in that column with the input voltage signal or signals. The output current is converted to a digital value by an analog-to-digital converter (described below) in the output circuit. The embodiments of the present disclosure do not limit the structure and type of the memristor unit.

[0063] For example, analog signals are input to the multiple column signal input terminals of the memristor array after the conductance setting (programming) is completed. For example, the analog signals can be voltage signals, so that the memristor array can be controlled to perform multiplication and addition operations. According to Kirchhoff's law, the output current of the memristor array can be obtained according to the following formula (1):

[0064] Formula (1)

[0065] Where j=1, …, M and k=1, …, N.

[0066] In the above formula (1), V k represents the voltage input to the kth column signal input terminal among multiple column signal input terminals, I j Represents the current signal output by the jth row signal output terminal among multiple row signal output terminals. jk represents the overall conductance of the memristor unit located in the jth row and the kth column. According to Kirchhoff's law, the memristor array can perform multiplication and accumulation calculations (i.e., the multiplication and addition operations mentioned above) in parallel.

[0067] This analog-to-digital converter is used to convert the analog current signal output by the memristor array in the memristor device as a calculation result into a digital current signal. Typically, one analog-to-digital converter is connected to each column of memristors. The analog-to-digital converter includes an input terminal, a bias terminal, and a result output terminal. The input terminal is connected to the output terminal of at least one column of the memristor array, and the bias terminal is connected to a calibration adjustment circuit.

[0068] More specifically, if Figure 4 As shown, the analog-to-digital converter may include a signal amplifying circuit 401, a comparator 501, and a bit current digital-to-analog converter circuit (IDAC) 301. The input terminal of the signal amplifying circuit 401 serves as the input terminal A of the analog-to-digital converter, receiving the first current I from the memristor array. in The bias terminal of the bit current digital-to-analog converter circuit (IDAC) 301 is also the bias terminal of the ADC itself, and is used to replicate the off-chip reference current I0 by integer multiples to generate multiple comparison currents for comparison. Each comparison current value corresponds to a digital value. The current values ​​of the multiple comparison currents (i.e., the corresponding digital values) can be increased one by one according to the working mode, or increased according to, for example, a binary search method. The comparison current I DAC is input to the bias terminal of the signal amplifying circuit 401. Here, the reference current I0 is provided by the regulating circuit 302, which can adjust the magnitude of the reference current I0. For example, the larger the reference current I0 is, the larger the comparison current value generated by the IDAC 301 for the same digital value is.

[0069] For example, the signal amplifying circuit 401 can amplify the input signal. For example, the signal amplifying circuit 401 can be a transimpedance amplifier that converts the input current signal into a voltage signal. Here, the input first current I in and comparison current I DAC After being converted into a voltage signal, it is input into the comparator 501 .

[0070] The comparator 501 includes two input terminals, namely a third input terminal D and a fourth input terminal E, and a result output terminal C. The third input terminal D and the fourth input terminal E are respectively used to receive two signals for comparison, and the result output terminal C serves as the result output terminal of the analog-to-digital converter. The comparator 501 compares two voltage signals, which are the input current and the output current of the IDAC 301 converted by the TIA, and thus the first current I can be obtained by comparison. in and comparison current I DAC Which is larger (or smaller). The comparator 501 converts the first current I in The first current I is obtained by comparing the first current with the multiple comparison currents (i.e., the currents corresponding to the multiple digital output values) input in sequence. in The relationship between the first current I in The corresponding first digital output value N is output as the result output value of the analog-to-digital conversion. As described above, the larger the reference current I0 is, the larger the comparison current value generated by the IDAC 301 for the same digital value is. in , the smaller the digital value output by the output terminal C is.

[0071] like Figure 3 As shown, for a programmed memristor array, the analog-to-digital converter calibration method based on the memristor array includes the following steps S101-S104:

[0072] Step 101 : performing a multiplication-addition operation using at least one column of a memristor array, providing a first current to an input terminal, and providing a reference current to a bias terminal through a regulating circuit, so as to obtain a first digital output value at a result output terminal.

[0073] In this step, a voltage signal is applied to the signal input terminals of the memristor array in the row direction, and a multiplication-addition operation is performed using at least one column of the memristor array. This generates a first current corresponding to the at least one column of memristors. The first current is the result of the multiplication-addition operation of the applied voltage signal and the conductance value obtained by programming the at least one column of memristors. An analog-to-digital converter generates a first digital output value corresponding to the first current based on a received reference current (i.e., the reference current input to the IDAC 301 of the analog-to-digital converter). For example, the applied voltage signal can be selected as needed, such as an integer N times the read voltage (e.g., 0.2V) used by the read circuit, where N is greater than or equal to 1. For example, when the voltage signal is equal to the read voltage, the target digital output value in the following step 102 can be directly obtained by reading the output value of the SA in the circuit. This calibrates the SA of the read circuit involved in the programming process and the ADC of the output circuit involved in the calculation process, achieving adaptive calibration of the ADC with respect to the SA.

[0074] Step 102 : Determine whether the first digital output value matches the target digital output value corresponding to the first current.

[0075] Step 103 : In response to the mismatch between the first digital output value and the target digital output value, adjust the magnitude of the reference current provided to the regulating circuit to reduce the mismatch between the first digital output value and the target digital output value.

[0076] Step 104 : In response to the first digital output value matching the target digital output value, determining the first digital output value as a final output value.

[0077] Figure 3 The calibration method shown can calibrate the output digital value of the memristor array after the memristor array completes the forward calculation (the above-mentioned multiplication and addition operation). In this method, calibration is directly performed on the first digital output value ultimately output by the ADC in the output circuit, thereby avoiding the additional overhead of first calibrating the SA and then calibrating the final ADC output value, and avoiding the tedious operations required for such a secondary calibration. This method also helps to improve the accuracy of the ADC used in the forward calculation of the memristor array.

[0078] As described above, for example, before performing step 101, in order to provide a first current to the input terminal through at least one column of the memristor array, the calibration method further includes programming the at least one column of the memristor array so that the conductance of each memristor in the at least one column is in a first conductance state, and during the programming process, reading the set first conductance state using a read circuit (including the SA). A target digital output value is determined corresponding to the first conductance state. For example, the target digital output value is determined based on the first conductance state and a voltage signal selected for a forward operation, thereby ensuring that, after inputting the corresponding voltage signal, a first current obtained by performing a multiplication-addition operation using the at least one column of the memristor array is a desired current value. For example, assuming the conductance of the memristor is set to 2μS (corresponding to a resistance of 500K ohms), when a read voltage of 0.2V is used, the SA output of the reading circuit has a digital value of 0100 (binary). Then, when the voltage signal (input signal) applied during the forward operation is also 0.2V, the target digital output value during calibration should be 0100 (binary). Alternatively, when the voltage signal applied during the forward operation is also 0.4V, the target digital output value during calibration should be 1000 (binary).

[0079] For example, in at least one embodiment of the present disclosure, Figure 4 As shown, the memristor array 201 passes a first current I into the signal amplifying circuit 401. in Before, programming is first performed on at least one column of the memristor array 201 so that the conductance of each memristor in the at least one column is in a first conductance state, for example, a target digital output value N0 of an ADC for verification purposes is obtained from the first conductance state.

[0080] The multiplication and addition operation using at least one column of the memristor array can be performed using multiple columns (i.e., greater than or equal to two columns) or only one column. In the former case, the calibrated analog-to-digital converter is electrically connected to the output ends of the multiple columns of memristors; and in the latter case, the calibrated analog-to-digital converter is electrically connected to the output end of only the one column of memristors, for example.

[0081] For example, in at least one embodiment of the present disclosure, a column in a memristor array is programmed so that the conductance of each memristor in the column is in a first conductance state. Figure 4 As shown, one column of the selected memristor array 201 is electrically connected to the analog-to-digital converter, so that the first current I obtained by performing multiplication and addition operations on the memristor in the column is in It is input to the input terminal A of the analog-to-digital converter being verified.

[0082] For example, in the memristor array 201, a multiplexer (not shown) can be used to select the rows and columns for conductance programming; conductance programming can then be performed on each memristor cell in the selected column. For example, when setting the conductance value of the memristor cell in the selected column, the conductance value can be adjusted, for example, through a corresponding set operation or reset operation. During the conductance adjustment process, the conductance value of the memristor cell can be read, for example, by a readout circuit SA, thereby obtaining a digital output value corresponding to each memristor cell. For example, when the memristor cells in the selected column of the memristor are set to a first conductance state, the first conductance state can be an intermediate resistance state of the conductance values ​​of each memristor. This intermediate resistance state corresponds to half the range of the analog-to-digital converter (ADC) in the output circuit. For example, if the digital value output by the ADC is 0 to 127 (decimal), then this intermediate resistance state corresponds to 64 (corresponding to 1000000 in binary), but the embodiments of the present disclosure are not limited to this.

[0083] For example, in a memristor array-based analog-to-digital converter calibration method provided in at least one embodiment of the present disclosure, step 101 further includes: passing the same input voltage signal to the input terminals of each row of the memristor array, performing a multiplication and addition operation on the input voltage signal and the conductance value of the memristor in the at least one column by using at least one column of the memristor array, and obtaining a first current as the operation result from the input terminal. Figure 4 As shown, the input terminals of a selected column of memristors are electrically connected together and input with the same voltage signal V0.

[0084] Therefore, according to the above formula (1), if the conductance of the memristors in the column is set to the intermediate resistance state, when the same voltage signal V0 is input to the input terminals of the multiple memristor units in the column, the current output value after the multiplication and addition operation of the memristor units in each row of the column corresponds to the current i under the voltage signal V0. j , so for each row i j After adding the current I of the memristor unit in the middle resistance state, the current output I of the memristor unit in the middle resistance state can be obtained. i ; Accordingly, the current output I i The conversion result after ADC also corresponds to the middle range of ADC.

[0085] Specifically, for step 101, Figure 4 As shown, a first current I can be provided to the input terminal A of the analog-to-digital converter by using a column of the memristor array 201 to perform a multiplication and addition operation. in The reference current I0 is provided to the bias terminal B of the analog-to-digital converter through the regulating circuit 302; the IDAC 301 outputs a first current I0 based on the reference current I0. in There are multiple comparison currents for comparison, and each comparison current value corresponds to a digital value. The current values ​​of the multiple comparison currents (ie, the corresponding digital values) can be increased one by one according to the working mode, or increased according to a binary search method, for example.

[0086] The first current I in and comparison current I DAC The same signal amplifier circuit 401 can be used to amplify and convert the signals into voltage signals, and then enter the comparator 501 for comparison. After a plurality of cycles, the result output terminal C of the comparator 501 outputs the signal corresponding to the first current I in The first digital output value N.

[0087] In at least one example, the signal amplifying circuit 401 is a transimpedance amplifier that can convert a current signal into a voltage signal. For example, the signal amplifying circuit 401 can realize the first current I in The amplification and conversion can achieve the corresponding amplified signal V at the third input terminal D of the comparator 501. in For example, the signal amplifying circuit 401 can also realize the comparison current I DAC The amplification and conversion can achieve the corresponding amplified signal V at the third input terminal E of the comparator 501. DAC .

[0088] The comparator 501 converts the first current I in Amplified signal V in , and corresponding to the comparison current I DAC The amplified signal V DAC The comparator 501 compares the first current I in The first current I is obtained by comparing with a plurality of comparison currents (i.e., currents corresponding to a plurality of digital values) input in sequence. in and a string of numbers (for example, the string of numbers consists of numbers 0 or 1), thereby determining a digital value corresponding to the first current, wherein the digital value is output as a first digital output value N of the analog-to-digital conversion.

[0089] For example, in step 102, the first digital output value N and the first current I are determined. in The corresponding target digital output value N matches. For example, after the comparator 501 performs comparison and thus realizes analog-to-digital conversion, it can output a corresponding digital signal N; collect the digital signal N, and then determine whether the first digital output value N matches the first current I in The corresponding target digital output value N0 (the number may be provided by the system or input by the user) is matched, and the judgment result is provided to the regulating circuit 302 connected to the bit current digital-to-analog conversion circuit 301.

[0090] In step 103, for example, in response to the mismatch between the first digital output value N and the target digital output value N0, the conversion base of the bit current digital-to-analog conversion circuit 301 can be changed by changing the size of the reference current I0 applied to the bit current digital-to-analog conversion circuit 301, thereby reducing the degree of mismatch between the first digital output value N and the target digital output value N0; or in response to the match between the first digital output value N and the target digital output value N0, the first digital output value N can be determined as the final output value.

[0091] For example, in the case where the first digital output value N does not match the target digital output value N0, step 103 may further include: when the first digital output value N is greater than the target digital output value N0, the reference current I0 applied to the bit current digital-to-analog conversion circuit 301 may be increased; or when the first digital output value N is less than the target digital output value N0, the reference current I0 applied to the bit current digital-to-analog conversion circuit 301 may be decreased, thereby reducing the degree of mismatch between the first digital output value N and the target digital output value.

[0092] For example, in at least one embodiment of the present disclosure, Figure 4 As shown, the third input terminal D obtains the corresponding amplified signal V in and the third input terminal E to obtain the corresponding amplified signal V DAC The comparison is performed in the comparator 501 and a comparison result is obtained. For example, the comparator 501 may include an M-bit register and a control circuit. For example, the M-bit register is used to record the result of the successive approximation comparison; for example, the amplified signal V in and amplified signal V DAC The comparison result can be output to control the bit current digital-to-analog conversion circuit 301 to output the next bit (time) of comparison current I0 until the comparator 501 outputs the target digital output value N0.

[0093] For example, in at least one example, according to the search algorithm, the M-bit register is first set to the middle value of the range. For example, for a range of 63 (i.e., 2^6, expressed as 111111 in binary), a comparison current corresponding to 32 can be used for the first comparison, and the MSB of the register is set to 1, which corresponds to the binary result 100000; for example, with V REF The full scale of the analog-to-digital converter corresponds to V DAC First, the amplified signal V is compared in the comparator 501. in With V REF / 2, at V in Greater than V REF / 2, the comparator 501 outputs a logic high level or "1", and the MSB of the M-bit register remains 1, that is, the highest target digital value finally output is 1; on the contrary, in the case of V in Less than V REF In the case of / 2, the comparator outputs a logic low level or "2", and the MSB of the M-bit register is cleared to 0, that is, the highest target digital value finally output is 0; then, the control logic (SAR control logic) in the comparator 501 moves to the next bit and uses the binary method based on the comparison result to determine the bit lower than the MSB. The next comparison is performed in the same way until the M-bit comparison is completed and the M-bit digital code is converted into the M-bit register.

[0094] For example, in at least one embodiment of the present disclosure, when determining whether the first digital output value N is equal to the first current I in When the corresponding target digital output value N0 does not match, IDAC 301 changes the value of reference current I0, thereby adjusting the rated comparison voltage V of the analog-to-digital converter corresponding to the reference current I0. REF Adjust, for example, to V REF2 .

[0095] For example, when the first digital output value N is greater than the first current I in When the target digital output value N0 is reached, the reference current I0 applied to the IDAC 301 can be increased, that is, the rated comparison voltage V REF The reference range of the ADC is increased, so that the first current I in The ADC output digital value (output code) corresponding to the reference range after the adjustment will decrease; on the contrary, for example, when the first digital output value N is less than the first current I in When the target digital output value is reached, the reference current I0 can be reduced by IDAC 301, that is, the rated comparison voltage V REF The reference range of the ADC is reduced as a whole, so that the first current I in The ADC output digital value corresponding to the reduced reference range interval will increase.

[0096] After the reference current I0 applied to the IDAC 301 is changed, the comparator 501 of the ADC may output the first current I in The changed first digital output value N1 is then compared with the first current I in The analog-to-digital converter 301 is compared with the corresponding target digital output value N0, and the result determines whether the reference current I0 applied to the IDAC 301 needs to be adjusted and how to adjust it. The feedback-adjustment-output-feedback process is repeated until the analog-to-digital converter finally outputs the desired first digital output value N0.

[0097] Therefore, according to the comparison result between the first digital output value N and the target digital output value N0, the rated comparison voltage V of the analog-to-digital converter corresponding to the reference current I0 is adjusted. REF , the mismatch between the first digital output value N and the target digital output value N0 can be reduced.

[0098] In step 104, when the comparator 501 outputs the first current I in When the first digital output value N matches the target digital output value N0, the first digital output value N at this time can be determined as the final output value of the analog-to-digital converter.

[0099] For example, accordingly, for calibration, the reference current I0 when the first digital output value N matches the target digital output value N0 is selected as the rated standard reference current of the analog-to-digital converter, and the rated standard reference current is used as the rated reference current for the calibrated analog-to-digital converter.

[0100] For example, Figure 5 A schematic flowchart of a specific example of a method for calibrating an analog-to-digital converter based on a memristor array provided in at least one embodiment of the present disclosure.

[0101] For example, Figure 5 In the method shown, the resistance of the memristor cell is set to the desired value using the readout circuit's analog signal conditioning (SA). Here, the output of the output circuit's ADC is set to a binary value of 100..0 (omitting bits with 0s), representing the intermediate resistance state of the memristor cell. For example, if the ADC outputs a 6-bit binary value (corresponding to a full-scale range of 127), the resistance value can be set to 100,000. When the SA is used to read the resistance value in this intermediate resistance state, the corresponding digital output code should be the middle value of the SA's range. For another example, if the SA outputs an 8-bit binary value, the resistance value can be set to 10,000,000.

[0102] In this example, the ADC calibration method includes the following steps:

[0103] Step 601: Select a column from the memristor array and program the resistance of the memristor cells in this column to an intermediate resistance state where the SA output is 100..0 when the read voltage is V0. Accordingly, the full-scale SA in the read circuit is a resistance state where the SA output is 111..1.

[0104] Step 602: When the input voltage signal is also V0, the selected column of the memristor array completes the forward calculation (the multiplication and addition operation described above) in the intermediate resistance state, resulting in the binary output value of the ADC. If the ADC output value is greater than 100..0, execute step 603; if the ADC output value is less than 100..0, execute step 604; if the ADC output value is equal to 100..0, calibration is complete.

[0105] Step 603: Increase the reference current of the ADC;

[0106] Step 604: Reduce the reference current of the ADC.

[0107] For example, in Figure 5 In the analog-to-digital converter calibration method provided in the illustrated embodiment, when a voltage signal V0 is applied to a column of a memristor array, the resistance of the memristor cells in the column of the memristor array is programmed to an intermediate resistance state. The output value of the signal processing unit (SA) used to program the memristor cells is half the full scale. For example, for a 6-bit device, the output of the SA is 100,000. Therefore, after completing the forward calculation for the column of the memristor array, the corresponding ADC target output value ADC should be 100,000. The ADC can be calibrated accordingly by comparing the actual output digital value with the target ADC output value of 100,000 corresponding to the intermediate resistance state. For example, when the digital output value of the ADC is greater than the target digital output value of 100,000 determined based on the intermediate resistance state of the SA output value of 100,000, the reference range of the ADC is increased by increasing the reference current of the reference current ADC; conversely, for example, when the digital output value of the ADC is less than the target digital output value of 100,000 corresponding to the intermediate resistance state, for example, the reference current of the reference current ADC is reduced, that is, the rated comparison voltage is reduced, so that the reference range of the ADC is reduced, thereby achieving calibration of the ADC range.

[0108] Furthermore, by setting the conductance of a selected column item in the memristor array to an intermediate resistance state, the target output value 100..0 of the memristor after completing the forward calculation can be obtained. Furthermore, by comparing the ADC output value with the target output value 100..0 and adjusting the ADC reference current, the ADC accuracy can be calibrated. This ensures that the corresponding SA output value and ADC output value both fluctuate around the midpoint of their respective ranges, with a lower probability of exceeding full-scale or exceeding the range limit. Therefore, during this calibration process, by setting the memristor resistance to an intermediate resistance state, damage to the SA in the readout circuit or the ADC in the output circuit can be reduced during the adjustment process, thereby enhancing protection for the analog-to-digital converter.

[0109] Figure 6 A schematic diagram illustrating a method for calibrating an analog-to-digital converter for a memristor array according to at least one embodiment of the present disclosure.

[0110] exist Figure 6 In the embodiment, the meanings of the various parts are as follows and the device mentioned is, for example, a memristor:

[0111] (a) Expected conductance range of the device.

[0112] (b) the expected ADC range corresponding to the expected conductance range;

[0113] (c) Actual conductance range due to SA deviation;

[0114] (d) Actual ADC range corresponding to device deviation caused by SA deviation;

[0115] (e) Actual ADC range.

[0116] For example, in a typical method, calibration of the output results of a memristor array during computation involves two steps. The first step, from step (c) to step (a), involves calibrating the SA in the readout circuit to reduce the error in the SA's output value, ensuring that the actual (calibrated) conductance range caused by the SA's deviation matches the device's expected conductance range, thereby improving the SA's accuracy when programming the memristor's conductance value. The second step, from step (e) to step (b), involves calibrating the ADC in the output circuit to reduce the error in the ADC's output value, ensuring that the actual (calibrated) ADC range caused by the ADC's deviation matches the expected ADC range corresponding to the expected conductance range, thereby improving the ADC's accuracy when outputting the memristor's output current value. However, this typical method separates the calibration of the SA and the ADC. Furthermore, if the ADC range is designed based on a preset conductance range, it is easy for the ADC output to exceed the range or be underutilized.

[0117] However, the deviation of SA is usually not large, and the deviation of the measurement results obtained based on the SA from the expected conductivity range will not be large. Even if there is a certain inaccuracy in SA, the relative ratio between the various conductivity states of various devices obtained using the same SA does not change, and a certain number of bits of data can be normally represented.

[0118] Therefore, it is possible to directly calibrate the range of the ADC used for forward calculation of the memristor array. Figure 6 As shown, the embodiment of the present disclosure does not adopt the above-mentioned conventional method, but adopts the calibration process from (e) to (d), so that the actual (calibrated) ADC range matches the actual (calibrated) ADC range corresponding to the device deviation caused by the deviation of the SA, so that the calibration of the ADC is associated with the calibration of the SA, thereby realizing adaptive calibration of the ADC to the SA.

[0119] For example, when multiplication and addition calculations are performed on at least one column of the memristor array, the ADC supports analog-to-digital conversion of the multiplication and addition results for the currents of m rows of devices. For the expected conductance range of the device in (a), i.e., the target conductance range of the device, for example, assuming the expected conductance range of the device is (2μS, 20μS), then when the read voltage is 0.2V, the expected SA current range is the first interval, i.e., (0.4μA, 4μA). For the ADC range corresponding to the expected conductance range in (b), within the set forward calculation voltage range, the ADC range corresponding to the expected conductance range can be set to (0.4 * m) μA. For (c), due to the deviation of the SA itself, after programming the memristor, the actual conductance range of the memristor does not match that in (a). For example, when the SA indicates a detected current of 0.4 μA, the actual conductance of the memristor is not 20 μS, but rather 25 μS. Therefore, the output current of the programmed device during forward calculation is in the second range, for example, (0.5 μA, 5 μA). For (d), based on the actual ADC range corresponding to the device deviation caused by the deviation of the SA, the ADC range needs to be calibrated to (0.5 * m) μA. Therefore, by using the calibration process from (e) to (d), the ADC range can be calibrated while taking into account the SA, improving output accuracy.

[0120] At least one embodiment of the present disclosure further provides a calibration device for an analog-to-digital converter. Figure 7 A schematic block diagram of a calibration device for an analog-to-digital converter provided in at least one embodiment of the present disclosure.

[0121] For example, Figure 7 As shown, the calibration device 700 includes a signal acquisition module 701, an analog-to-digital conversion module 702, and a control and driving module 703. The signal acquisition module 701 is configured to operate at least one column of the memristor array to perform a multiplication and addition operation to obtain a first current, and provide the first current to the input terminal of the analog-to-digital converter; the adjustment circuit 702 is configured to provide a reference current to the bias terminal of the analog-to-digital converter, wherein the analog-to-digital converter performs an analog-to-digital conversion on the first current based on the first current and the reference current, and outputs a first digital output value.

[0122] The control driving module 703 is configured to receive a first digital output value and determine whether the first digital output value matches a target digital output value corresponding to the first current. When the first digital output value does not match the target digital output value, the adjustment circuit adjusts the magnitude of the reference current to reduce the degree of mismatch between the first digital output value and the target digital output value.

[0123] For example, in at least one embodiment of the present disclosure, when the first digital output value does not match the target digital output value corresponding to the first current, the adjustment circuit can adjust the magnitude of the reference current; for example, when the first digital output value is greater than the target digital output value, the adjustment circuit can increase the reference current; or when the first digital output value is less than the target digital output value, the adjustment circuit can decrease the reference current to reduce the degree of mismatch between the first digital output value and the target digital output value.

[0124] It should be noted that, for example, the operation process of the ADC calibration device can refer to steps 101 to 104 of the ADC calibration method based on a memristor array and the related descriptions in each embodiment.

[0125] There are a few points to note:

[0126] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0127] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0128] The foregoing description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the appended claims.< / m> < / n> < / m>

Claims

1. A method for calibrating an analog-to-digital converter, wherein: The analog-to-digital converter includes an input terminal, a bias terminal, and a result output terminal. The calibration method comprises: Performing a multiplication-addition operation using at least one column of the memristor array, providing a first current to the input terminal, and providing a reference current to the bias terminal through a regulating circuit, so as to obtain a first digital output value at the result output terminal; determining whether the first digital output value matches a target digital output value corresponding to the first current; and In response to the first digital output value not matching the target digital output value, adjusting the magnitude of the reference current provided to the regulating circuit to reduce the degree of mismatch between the first digital output value and the target digital output value, Wherein, in response to the first digital output value not matching the target digital output value, adjusting the magnitude of the reference current provided by the regulating circuit includes: In response to the first digital output value being greater than the target digital output value, increasing the reference current to reduce the mismatch between the first digital output value and the target digital output value; or In response to the first digital output value being smaller than the target digital output value, the reference current is adjusted down to reduce the mismatch between the first digital output value and the target digital output value.

2. The calibration method according to claim 1, wherein: The adjusting the magnitude of the reference current provided by the adjusting circuit includes: In response to the first digital output value not matching the target digital output value, feeding back the first digital output value of the analog-to-digital converter to the conditioning circuit; The reference current is changed by the regulating circuit according to the first digital output value, and the changed first digital output value is provided to the bias terminal.

3. The calibration method as claimed in claim 1, wherein: Before providing the first current to the input terminal through the at least one column of the memristor array, the calibration method further includes: The at least one column of the memristor array is programmed so that conductance of each memristor in the at least one column is in a first conductance state, wherein the target digital output value is determined corresponding to the first conductance state.

4. The calibration method according to claim 3, wherein: The first conductance state of the conductance of each of the memristors is an intermediate resistance state of the conductance value of each of the memristors.

5. The calibration method as claimed in claim 3, wherein: The at least one column includes one column, and programming the at least one column of the memristor array includes: The column in the memristor array is programmed so that the conductance of each memristor in the column is in the first conductance state.

6. The calibration method according to claim 1, wherein: The performing a multiplication-addition operation by using the at least one column of the memristor array comprises: A same input voltage signal is applied to the input terminals of each row of the memristor array, and after performing the multiplication and addition operation on the input voltage signal and the conductance values ​​of the memristors in the at least one column using the at least one column of the memristor array, the first current as the operation result is obtained from the input terminal.

7. The calibration method according to any one of claims 1 to 6, further comprising: A reference current when the first digital output value matches the target digital output value is selected as a rated standard reference current of the analog-to-digital converter.

8. A calibration device for an analog-to-digital converter, wherein: The analog-to-digital converter includes an input terminal, a bias terminal, and a result output terminal. The calibration device comprises: a signal acquisition module configured to operate at least one column of the memristor array to perform a multiplication-addition operation to obtain a first current and provide the first current to an input terminal of the analog-to-digital converter; a regulating circuit configured to provide a reference current to a bias terminal of the analog-to-digital converter, wherein the analog-to-digital converter performs analog-to-digital conversion on the first current according to the first current and the reference current, and outputs a first digital output value; a control driving module configured to receive the first digital output value and determine whether the first digital output value matches a target digital output value corresponding to the first current; when the first digital output value does not match the target digital output value, causing the adjustment circuit to adjust the magnitude of the reference current to reduce the degree of mismatch between the first digital output value and the target digital output value; Wherein, the control drive module is further configured as: When the first digital output value is greater than the target digital output value, increasing the reference current to reduce the mismatch between the first digital output value and the target digital output value; or When the first digital output value is smaller than the target digital output value, the reference current is adjusted to decrease so as to reduce the mismatch between the first digital output value and the target digital output value.

Images