Analog-to-digital converter and memory device comprising an analog-to-digital converter

Abstract

This application relates to analog-to-digital converters (ADCs) and memory devices including ADCs. This disclosure relates to electronic devices. An ADC includes: an input voltage provider configured to output an input voltage during multiple phases; a comparator configured to output a comparison result between the input voltage and one of a plurality of comparison reference voltages; a successive approximation register configured to output at least one of a plurality of bits of digital data based on the comparison result; and a digital-to-analog converter (DAC) configured to provide one of a plurality of comparison reference voltages to the comparator based on the at least one bit, wherein the DAC includes a plurality of transistors connected in parallel with each other, and the DAC is configured to selectively receive the plurality of reference voltages to generate a comparison reference voltage.

Description

Technical Field

[0001] Various embodiments of the present invention relate generally to electronic devices, and more specifically to analog-to-digital (ADC) converters, memory devices including ADC converters, and methods of operating the same. Background Technology

[0002] Storage devices can store data in response to control from host devices such as computers or smartphones. Storage devices can include memory devices that store data and memory controllers that control the memory devices. Memory devices can be classified as volatile memory devices and non-volatile memory devices.

[0003] Memory cells included in a memory device may have temperature-dependent operating characteristics. The memory device may include a temperature sensor to compensate for temperature-dependent variations in the operating voltage. The temperature sensor of the memory device may include an analog-to-digital converter (ADC) that senses the temperature as a voltage corresponding to an analog signal and converts the sensed voltage signal into a digital signal. For example, the types of ADCs may include flash ADCs, ADCs using a tracking scheme, successive approximation register (SAR) ADCs (hereinafter referred to as "SAR-ADCs"), and pipelined ADCs. Summary of the Invention

[0004] According to an embodiment, an analog-to-digital converter (ADC) that outputs digital data corresponding to a comparison result between an input voltage (as an analog signal) and a plurality of comparison reference voltages may include: an input voltage provider configured to output an input voltage during multiple phases; a comparator configured to output a comparison result between the input voltage and one of the plurality of comparison reference voltages; a successive approximation register configured to output at least one of a plurality of bits of digital data based on the comparison result; and a digital-to-analog converter (DAC) configured to provide one of the plurality of comparison reference voltages to the comparator based on the at least one bit, wherein the DAC includes a plurality of transistors connected in parallel with each other, and the DAC is configured to selectively receive the plurality of reference voltages to generate a comparison reference voltage.

[0005] An analog-to-digital converter (ADC) may include: a digital-to-analog converter (DAC) configured to generate a plurality of comparison reference voltages based on at least one preset reference voltage, and configured to output the plurality of comparison reference voltages; and a comparator having a first input terminal configured to receive an input voltage and a second input terminal to receive an output from the DAC, the comparator being configured to output a result of comparing the voltage at the first input terminal with the voltage at the second input terminal, wherein the DAC includes a plurality of transistors connected in parallel with each other, the plurality of transistors having an area in a predetermined ratio relative to the area of ​​the transistor receiving the input voltage, and the DAC is configured to selectively receive at least one reference voltage.

[0006] A memory device may include: a memory block having a plurality of memory cells storing data; a voltage generator configured to generate an operating voltage for accessing the plurality of memory cells; a temperature information generator configured to generate a temperature code based on an internal temperature; and control logic configured to control the voltage generator to control the operating voltage based on the temperature code, wherein the temperature information generator includes: a sensor configured to generate a temperature voltage signal, the temperature voltage signal being an analog signal determined based on an internal temperature; and an analog-to-digital converter configured to convert the temperature voltage signal into a digital signal, wherein the analog-to-digital converter includes: a comparator configured to output a comparison result between the temperature voltage signal and one of a plurality of comparison reference voltages; a successive approximation register configured to output at least one bit of a plurality of bits of the temperature code based on the comparison result; and a digital-to-analog converter configured to provide one of a plurality of comparison reference voltages to the comparator based on the at least one bit, and wherein the digital-to-analog converter includes a plurality of transistors connected in parallel with each other, the digital-to-analog converter being configured to selectively receive the plurality of reference voltages to generate a comparison reference voltage. Attached Figure Description

[0007] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the present disclosure;

[0008] Figure 2 This is an example Figure 1 A diagram of the memory device shown;

[0009] Figure 3 This is an example Figure 2 A diagram of the structure of any one of the storage blocks;

[0010] Figure 4 yes Figure 2 A diagram of the temperature information generator;

[0011] Figure 5 This is an example Figure 4 A diagram illustrating an example of an analog-to-digital converter;

[0012] Figure 6 This is an example Figure 5 A diagram illustrating the operation of an analog-to-digital converter;

[0013] Figure 7 This is an example Figure 6 A diagram showing the structure of a digital-to-analog converter;

[0014] Figure 8 This is an example generated in the reference. Figure 6 A diagram illustrating the method for converting temperature voltage Vtemp into temperature code in the first stage, using a comparison reference voltage applied.

[0015] Figure 9A and Figure 9B This is an example generated in the reference. Figure 6 A diagram illustrating the method for applying a comparison reference voltage in the second stage of converting the temperature voltage Vtemp into a temperature code;

[0016] Figure 10A , Figure 10B , Figure 10C and Figure 10D This is an example generated in the reference. Figure 6 A diagram illustrating the method for converting temperature voltage Vtemp into temperature code in the third stage, using a comparison reference voltage applied.

[0017] Figure 11A , Figure 11B , Figure 11C and Figure 11D This is an example generated in the reference. Figure 6 A diagram illustrating the method for converting temperature voltage Vtemp into temperature code in the fourth stage, using a comparison reference voltage applied.

[0018] Figure 12A , Figure 12B , Figure 12C and Figure 12D This is an example generated in the reference. Figure 6 A diagram illustrating the method for converting temperature voltage Vtemp into temperature code in the fourth stage, using a comparison reference voltage applied.

[0019] Figure 13 This is a circuit diagram illustrating one embodiment of a comparator included in an analog-to-digital converter according to an embodiment of the present disclosure;

[0020] Figure 14 This is an example Figure 1 A diagram of another embodiment of the memory controller;

[0021] Figure 15These are diagrams illustrating an embodiment of a memory card system using a storage device according to an embodiment of the present disclosure;

[0022] Figure 16 This is a block diagram illustrating a solid-state drive (SSD) system using a storage device according to an embodiment of the present disclosure; and

[0023] Figure 17 This is a block diagram illustrating a user system using a storage device according to an implementation method. Detailed Implementation

[0024] The specific structural or functional descriptions of the embodiments of the concepts disclosed in this specification are merely illustrative for the purpose of describing the embodiments of the concepts, and the embodiments of the concepts can be implemented in various forms, but the description is not limited to the embodiments described in this specification.

[0025] In the following description of the implementation, when a parameter is referred to as “predetermined,” it can be intended to mean that the value of the parameter is predetermined when it is used in a process or algorithm. The value of the parameter may be set at the start of the process or algorithm, or it may be set during a period of time when the process or algorithm is executed.

[0026] It will be understood that although the terms “first,” “second,” “third,” etc., are used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, a first element in some embodiments may be referred to as a second element in other embodiments.

[0027] Furthermore, it will be understood that when a component is referred to as "connected" or "coupled" to another component, it may be directly connected or coupled to the other component, or there may be intermediate components. Conversely, when a component is referred to as "directly connected" or "directly coupled" to another component, there are no intermediate components.

[0028] Various embodiments relate to analog-to-digital converters with reduced size, memory devices having the analog-to-digital converter, and methods of operating the same.

[0029] Figure 1 This is a diagram illustrating a storage device 50 according to an embodiment of the present disclosure.

[0030] Reference Figure 1Storage device 50 may include memory device 100 and memory controller 200. Storage device 50 may be configured to store data in response to control by host 400. Examples of storage device 50 may include cellular phones, smartphones, MP3 players, laptops, desktop computers, game players, TVs, tablet PCs, and in-vehicle infotainment systems. However, storage device 50 may be configured to store data in response to control by host 400 storing high-volume data in a location such as a server or data center.

[0031] Based on the host interface corresponding to the communication method with host 400, storage device 50 can be manufactured as one of various types of storage devices. For example, storage device 50 can be configured as any of various types of storage devices such as solid-state drives (SSDs); multimedia cards in the form of MMC, eMMC, RS-MMC, and micro MMC; secure digital cards in the form of SD, mini SD, and micro SD; universal serial bus (USB) storage devices; universal flash memory (UFS) devices; PCMCIA card-type storage devices; peripheral component interconnect (PCI) card-type storage devices; PCI-E card-type storage devices; compact flash (CF) cards; smart media cards; and memory sticks.

[0032] Storage device 50 can be manufactured as any of various types of packages. For example, storage device 50 can be manufactured as any of various types of packages such as PoP, System-in-Package (SIP), System-on-Chip (SOC), Multi-Chip Package (MCP), Chip-on-Board (COB), Wafer-Level Fabrication Package (WFP), or Wafer-Level Stacked Package (WSP).

[0033] The memory device 100 can store data. The memory device 100 can operate in response to the control of the memory controller 200. The memory device 100 may include a memory cell array (not shown) that includes a plurality of memory cells for storing data.

[0034] Each memory cell can be a single-level cell (SLC) that stores one data bit, a multi-level cell (MLC) that stores two data bits, a three-level cell (TLC) that stores three data bits, or a four-level cell (QLC) that stores four data bits.

[0035] A memory cell array (not shown) may include multiple memory blocks. Each memory block may include multiple memory cells. Each memory block may include multiple pages. According to an embodiment, a page may be a unit for storing data in the memory device 100 or retrieving data stored in the memory device 100. A memory block may be a unit for erasing data.

[0036] According to embodiments, examples of memory device 100 may include Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR) SDRAM, Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), or Spin-Transfer Torque Random Access Memory (STT-RAM). For ease of explanation, it is assumed that memory device 100 is NAND flash memory.

[0037] Memory device 100 can receive commands and addresses from memory controller 200 and access regions selected in the memory cell array in response to addresses. Memory device 100 can perform operations corresponding to commands on the regions selected in response to addresses. For example, memory device 100 can perform write operations (programming operations), read operations, and erase operations. During a programming operation, memory device 100 can program data into the region selected in response to an address. During a read operation, memory device 100 can read data from the region selected by an address. During an erase operation, memory device 100 can erase data from the region selected by an address.

[0038] The memory device 100 may include a temperature information generator 150. The temperature information generator 150 can generate temperature information reflecting the internal temperature of the memory device 100. According to an embodiment, the temperature information may be a temperature code in the form of a digital signal.

[0039] The characteristics of the memory cells included in the memory device 100 can vary based on temperature. For example, in a cold state with a relatively low temperature, the threshold voltage of the memory cell may increase. On the other hand, in a hot state with a relatively high temperature, the threshold voltage of the memory cell may decrease. Therefore, the memory device 100 can control the read voltage, verification voltage, or programming voltage to compensate for the temperature-based variation of the threshold voltage of the memory cell.

[0040] The memory controller 200 can control the overall operation of the storage device 50.

[0041] When power is applied to storage device 50, memory controller 200 can execute firmware. When storage device 100 is a flash memory device, memory controller 200 can execute firmware such as a flash translation layer (FTL) for controlling communication between host 400 and storage device 100.

[0042] According to the implementation, the memory controller 200 can receive data and logical address LA from the host 400, and convert the logical address LA into a physical address PA that indicates the address of the memory cell storing data in the memory device 100.

[0043] The memory controller 200 can control the memory device 100 to perform programming, reading, or erasing operations in response to requests from the host 400. During a programming operation, the memory controller 200 can provide the memory device 100 with programming commands, physical addresses, and data. During a reading operation, the memory controller 200 can provide the memory device 100 with reading commands and physical addresses. During an erasing operation, the memory controller 200 can provide the memory device 100 with erasing commands and physical addresses.

[0044] According to an implementation, the memory controller 200 can generate commands, addresses, and data independently of requests from the host 400 and transmit these commands, addresses, and data to the memory device 100. For example, the memory controller 200 can provide the memory device 100 with commands, addresses, and data for performing programming operations, read operations, and erase operations associated with wear leveling, read recycling, and garbage collection.

[0045] According to one embodiment, the memory controller 200 can control at least two memory devices 100. The memory controller 200 can control the memory devices 100 based on an interleaving scheme, thereby improving operational performance. Based on the interleaving scheme, operations performed on at least two memory devices 100 can be controlled to overlap with each other.

[0046] The host 400 may communicate with the storage device 50 using at least one of a variety of communication methods, such as Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI-Fast (PCIe), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Lightweight DIMM (LRDIMM).

[0047] Figure 2 This is an example Figure 1 A diagram of the memory device 100 shown.

[0048] Reference Figure 2 The memory device 100 may include a memory cell array 110, a voltage generator 120, an address decoder 130, an input / output circuit (I / O circuit) 140, a temperature information generator 150, and control logic 160.

[0049] The memory cell array 110 may include multiple memory blocks BLK1 to BLKi. The multiple memory blocks BLK1 to BLKi may be connected to the address decoder 130 via row lines RL. The multiple memory blocks BLK1 to BLKi may be connected to the input / output circuitry 140 via column lines CL. According to one embodiment, the row lines RL may include word lines, source select lines, and drain select lines. According to one embodiment, the column lines CL may include bit lines.

[0050] Each of the plurality of memory blocks BLK1 to BLKi may include a plurality of memory cells. According to an embodiment, the plurality of memory cells may be non-volatile memory cells. Among the plurality of memory cells, memory cells connected to the same word line may be defined as a single physical page. In other words, the memory cell array 110 may include a plurality of pages. The memory cells of the memory device 100 may include a single-level cell (SLC) storing a single data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, and a four-level cell (QLC) storing four data bits.

[0051] Some of the multiple storage blocks BLK1 to BLKi can be stored as referenced. Figure 1 The mapped data block described. Other storage blocks can be normal blocks that store data requested by host 400.

[0052] According to the implementation, the voltage generator 120, address decoder 130, and input / output circuitry 140 can be collectively referred to as peripheral circuitry. Peripheral circuitry can drive memory cell array 110 in response to control logic 160. Peripheral circuitry can drive memory cell array 110 to perform programming, reading, and erasing operations.

[0053] Voltage generator 120 can be configured to generate multiple operating voltages by using an external power supply voltage provided to memory device 100. Voltage generator 120 can be controlled by control logic 160.

[0054] According to the embodiment, the voltage generator 120 can generate an internal power supply voltage by adjusting the external power supply voltage. The internal power supply voltage generated by the voltage generator 120 can be used as the operating voltage of the memory device 100.

[0055] According to an embodiment, voltage generator 120 can generate multiple operating voltages by using an external power supply voltage or an internal power supply voltage. Voltage generator 120 can be configured to generate various voltages required by memory device 100. For example, voltage generator 120 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple selected read voltages, and multiple unselected read voltages.

[0056] Voltage generator 120 may include multiple pumping capacitors that receive an internal power supply voltage to generate multiple operating voltages with various voltage levels. Voltage generator 120 can generate multiple operating voltages by selectively activating the multiple pumping capacitors in response to control logic 160.

[0057] The generated operating voltage can be provided to the memory cell array 110 through the address decoder 130.

[0058] Address decoder 130 can be coupled to memory cell array 110 via row lines RL. Address decoder 130 can be configured to operate in response to control logic 160. Address decoder 130 can receive address ADDR from control logic 160. Address decoder 130 can be configured to decode the block address in the received address ADDR. Address decoder 130 can select at least one memory block among memory blocks BLK1 to BLKi based on the decoded block address. Address decoder 130 can be configured to decode the row address in the received address ADDR. Address decoder 130 can select at least one word line of the selected memory block based on the decoded row address. According to an embodiment, address decoder 130 can be configured to decode the column address in the received address ADDR. Address decoder 130 can connect input / output circuitry 140 and memory cell array 110 based on the decoded column address.

[0059] For example, address decoder 130 may include components such as row decoder, column decoder, and address buffer.

[0060] The input / output circuitry 140 may include multiple page buffers. These page buffers can be connected to the memory cell array 110 via bit lines.

[0061] During programming operations, data can be stored in selected memory cells based on data stored in multiple page buffers. During read operations, data stored in the selected memory cells can be sensed via bit lines, and the sensed data can be stored in the page buffer.

[0062] Temperature information generator 150 can measure the internal temperature of memory device 100 and provide a temperature code corresponding to the internal temperature to voltage generator 120 and control logic 160. Control logic 160 can control the level of the operating voltage to be generated by voltage generator 120 based on the temperature code. When the internal temperature of memory device 100 is relatively high, the threshold voltage of the memory cell may decrease. However, when the internal temperature of memory device 100 is relatively low, the threshold voltage of the memory cell may increase. Therefore, in response to a temperature code corresponding to an internal temperature above a critical temperature, control logic 160 can control voltage generator 120 to generate a read voltage that decreases by a predetermined level. However, in response to a temperature code corresponding to an internal temperature below a critical temperature, control logic 160 can control voltage generator 120 to generate a read voltage that increases by a predetermined level.

[0063] According to one implementation, control logic 160 can control voltage generator 120 to generate a programming voltage that increases a predetermined level in response to a temperature code corresponding to an internal temperature above a critical temperature. However, control logic 160 can also control voltage generator 120 to generate a programming voltage that decreases a predetermined level in response to a temperature code corresponding to an internal temperature below a critical temperature.

[0064] According to the implementation method, the temperature code can be an m-digit code.

[0065] Control logic 160 can control voltage generator 120, address decoder 130, input / output circuitry 140, and temperature information generator 150. Control logic 160 can operate in response to a command CMD transmitted from an external device (e.g., a memory controller). Control logic 160 can control peripheral circuitry by generating control signals in response to the command CMD and address ADDR.

[0066] Figure 3 This is an example Figure 2 A diagram showing the structure of one of the storage blocks BLK1 to BLKi.

[0067] Figure 3 It is shown as Figure 2 One of the storage blocks BLK1 to BLKi is a storage block BLKi.

[0068] Reference Figure 3Multiple word lines arranged in parallel to each other can be connected between a first select line and a second select line. The first select line can be a source select line (SSL), and the second select line can be a drain select line (DSL). More specifically, the memory block BLKi can include multiple string STs connected between bit lines BL1 to BLn and the source line SL. Bit lines BL1 to BLn can be individually connected to string STs, and the source line SL can be collectively connected to string STs. String STs can have the same construction. Therefore, a string ST connected to the first bit line BL1 will be described in detail as an example.

[0069] The string ST may include a source selection transistor SST connected in series between the source line SL and the first bit line BL1, a plurality of memory cells MC1 to MC16, and a drain selection transistor DST. Each string ST may include at least one source selection transistor SST, at least one drain selection transistor DST, and, for example... Figure 3 The memory cells shown are MC1 to MC16, and more memory cells.

[0070] The source of the source select transistor (SST) can be connected to the source line SL, while the drain of the drain select transistor (DST) can be connected to the first bit line BL1. Memory cells MC1 to MC16 can be connected in series between the source select transistors SST and Drain select transistors DST. The gate of the source select transistor SST included in different string STs can be connected to the source select line SSL. The gate of the drain select transistor DST can be connected to the drain select line DSL. The gates of memory cells MC1 to MC16 can be connected to multiple word lines WL1 to WL16 respectively. A group of memory cells connected to the same word lines among the memory cells included in different string STs can be called a physical page PG. Therefore, the memory block BLKi can include as many physical pages PG as word lines WL1 to WL16.

[0071] A single memory cell can store one bit of data. This memory cell is usually called a single-level cell (SLC). A physical page (PG) can store one logical page (LPG) of data. An LPG of data can include the same number of data bits as the cells included in a physical page (PG).

[0072] A memory cell can store two or more bits of data. A physical page (PG) can store data corresponding to two or more logical pages (LPGs).

[0073] Figure 4 yes Figure 2 The temperature information generator 150 graph.

[0074] Reference Figure 4The temperature information generator 150 may include a sensor 151 and an analog-to-digital converter 152.

[0075] Sensor 151 can sense the internal temperature of memory device 100. Sensor 151 can generate a temperature voltage Vtemp that reflects the internal temperature of memory device 100, and can provide the generated temperature voltage Vtemp to analog-to-digital converter 152. The temperature voltage Vtemp can be an analog signal.

[0076] The analog-to-digital converter 152 can receive a temperature voltage Vtemp as an analog signal and convert the temperature voltage Vtemp into a temperature code (Temp Code) as a digital signal. According to embodiments, the analog-to-digital converter 152 can be one of a flash analog-to-digital converter, an analog-to-digital converter using a tracking scheme, a SAR ADC, and a pipelined ADC. In this specification, the case where the analog-to-digital converter 152 is a SAR ADC will be described as an example. According to embodiments, based on the implementation method of the analog-to-digital converter 152, the temperature code (Temp Code) can include multiple data bits.

[0077] Figure 5 This is an example Figure 4 A diagram of an example of an analog-to-digital converter 152.

[0078] Reference Figure 5 The analog-to-digital converter 500 may include an input voltage provider 510, a comparator 520, a clock provider 530, a successive approximation register 540, and a digital-to-analog converter 550.

[0079] Input voltage provider 510 can receive and sample input voltage Vin. Input voltage provider 510 can provide the sampled value of input voltage Vin as a voltage Vp to be input to the non-inverting terminal (+) of comparator 520. According to an embodiment, input voltage provider 510 can hold the sampled value of input voltage Vin until the comparison operation of comparator 520 is completed, and can provide the sampled value as the voltage Vp to be input to the non-inverting terminal (+).

[0080] Comparator 520 can compare the voltage Vp input to the non-inverting terminal (+) with the voltage Vn input to the inverting terminal (-), and can provide the comparison result to the successive approximation register 540. The comparison result can be information indicating whether the voltage Vp input to the non-inverting terminal (+) is greater than or less than the voltage Vn input to the inverting terminal (-).

[0081] The successive approximation register 540 can convert the comparison result of the comparator 520 into digital data based on a clock input from the clock provider 530. The output of the successive approximation register 540 can be digital data comprising multiple bits. For example, the output of the successive approximation register 540 can be a temperature code. According to an embodiment, the number of bits of data included in the output of the successive approximation register 540 can be equal to the number of times the comparator 520 compares the voltage Vp input to the non-inverting terminal (+) with the voltage Vn input to the inverting terminal (-). As the number of comparisons between the voltage Vp input to the non-inverting terminal (+) and the voltage Vn input to the inverting terminal (-) increases, the number of bits of data included in the output of the successive approximation register 540 can increase. According to an embodiment, the number of bits of data included in the output of the successive approximation register 540 can be equal to the number of clock cycles input from the clock provider 530. As the number of bits of data included in the output of the successive approximation register 540 increases, it becomes possible to generate a temperature code (Temp Code) with more accurate temperature measurement results.

[0082] The digital-to-analog converter 550 can provide a voltage Vn input to the inverting terminal (-) of the comparator 520. The digital-to-analog converter 550 can generate a reference voltage to be input to the inverting terminal (-) based on data included in the output of the successive approximation register 540. The digital-to-analog converter 550 can convert the data included in the output of the successive approximation register 540 into a comparison reference voltage as an analog signal, and can provide the comparison reference voltage as the voltage Vn input to the inverting terminal (-).

[0083] Figure 6 This is an example Figure 5 A diagram illustrating the operation of the analog-to-digital converter 500.

[0084] Reference Figure 5 and Figure 6 The analog-to-digital converter 500 can convert the temperature voltage Vtemp into a temperature code. The temperature code can be a 4-bit digital data consisting of B3 / B2 / B1 / B0. The most significant bit (MSB) of the temperature code can be B3, and the least significant bit (LSB) can be B0.

[0085] B3 can be determined as the most significant bit (MSB) in the first stage. B2 can be determined in the second stage, B1 can be determined in the third stage, and B0 can be determined as the least significant bit (LSB) in the fourth stage.

[0086] During the first to fourth stages, the input voltage provider 510 can sample the temperature voltage Vtemp, which is the input voltage Vin, and can provide the sampled value of the temperature voltage Vtemp as the voltage Vp input to the non-inverting terminal (+) of the comparator 520.

[0087] The analog-to-digital converter 500 can convert temperature voltage Vtemp into temperature code TempCode using a binary search method.

[0088] Since the Temperature Code corresponding to the output of the analog-to-digital converter 500 has a length of 4 bits, one of 16 (2^4) Temperature Codes can be output. The voltage between the 16 Temperature Codes can correspond to the temperature value obtained by dividing the voltage from the lowest second reference voltage VREF- to the highest first reference voltage VREF+ into 16 voltage values. Therefore, the Temperature Code can be determined based on which of the 16 intervals forming the first comparison reference voltage Vx1 to the fifteenth comparison reference voltage Vx15 the Temperature Code belongs to.

[0089] In the first stage, the digital-to-analog converter 550 can provide a voltage Vn input to the inverting terminal (-) of the comparator 520. In the first stage, the voltage Vn input to the inverting terminal (-) of the comparator 520 can be an eighth comparison reference voltage Vx8 having an intermediate voltage level between the first reference voltage VREF+ and the second reference voltage VREF-. The comparator 520 can compare the magnitudes of the temperature voltage Vtemp and the eighth comparison reference voltage Vx8, and can provide the comparison result to the successive approximation register 540. The successive approximation register 540 can determine B3, as the most significant bit (MSB), as "1" in response to a comparison result where the temperature voltage Vtemp is greater than the eighth comparison reference voltage Vx8. On the other hand, the successive approximation register 540 can determine B3, as the most significant bit (MSB), as "0" in response to a comparison result where the temperature voltage Vtemp is less than or equal to the eighth comparison reference voltage Vx8.

[0090] The digital-to-analog converter 550 can generate the voltage Vn input to the inverting terminal (-) of the comparator 520 in the second stage based on B3, which is the most significant bit (MSB). For example, in response to an output where B3, the most significant bit (MSB) of the successive approximation register 540, is "1", the digital-to-analog converter 550 can output a twelfth comparison reference voltage Vx12, which is the intermediate voltage between the eighth comparison reference voltage Vx8 and the first reference voltage VREF+, as the voltage Vn input to the inverting terminal (-) of the comparator 520. Alternatively, in response to an output where B3, the most significant bit (MSB) of the successive approximation register 540, is "0", the digital-to-analog converter 550 can output a fourth comparison reference voltage Vx4, which is the intermediate voltage between the eighth comparison reference voltage Vx8 and the second reference voltage VREF-, as the voltage Vn input to the inverting terminal (-) of the comparator 520.

[0091] When B3, as the most significant bit (MSB), is assumed to be 1, in the second stage, comparator 520 can compare the magnitudes between the temperature voltage Vtemp and the twelfth comparison reference voltage Vx12, and can provide the comparison result to the successive approximation register 540. The successive approximation register 540 can set B2 to "1" in response to a comparison result where the temperature voltage Vtemp is greater than the twelfth comparison reference voltage Vx12. Conversely, the successive approximation register 540 can set B2 to "0" in response to a comparison result where the temperature voltage Vtemp is less than or equal to the twelfth comparison reference voltage Vx12.

[0092] In response to the output of the successive approximation register 540 where B3, as the most significant bit (MSB), is "1" and B2, as the second bit, is "1", the digital-to-analog converter 550 can output a fourteenth comparison reference voltage Vx14, which is the intermediate voltage between the twelfth comparison reference voltage Vx12 and the first reference voltage VREF+, as a voltage Vn input to the inverting terminal (-) of the comparator 520. On the other hand, in response to the output of the successive approximation register 540 where B3, as the most significant bit (MSB), is "1" and B2, as the second bit, is "0", the digital-to-analog converter 550 can output a tenth comparison reference voltage Vx10, which is the intermediate voltage between the twelfth comparison reference voltage Vx12 and the eighth comparison reference voltage Vx8, as a voltage Vn input to the inverting terminal (-) of the comparator 520.

[0093] When B2, as the second bit, is assumed to be "1", in the third stage, comparator 520 can compare the magnitudes between the temperature voltage Vtemp and the fourteenth comparison reference voltage Vx14, and can provide the comparison result to the successive approximation register 540. The successive approximation register 540 can determine B1 to be "1" in response to a comparison result where the temperature voltage Vtemp is greater than the fourteenth comparison reference voltage Vx14. On the other hand, the successive approximation register 540 can determine B1 to be "0" in response to a comparison result where the temperature voltage Vtemp is less than or equal to the fourteenth comparison reference voltage Vx14.

[0094] In response to the output of the successive approximation register 540 where B3 (MSB) is "1", B2 (MSB) is "1", and B1 (MSB) is "1", the digital-to-analog converter 550 can output a fifteenth comparison reference voltage Vx15, which is the intermediate voltage between the fourteenth comparison reference voltage Vx14 and the first reference voltage VREF+, as a voltage Vn input to the inverting terminal (-) of the comparator 520. Alternatively, in response to the output of the successive approximation register 540 where B3 (MSB) is "1", B2 (MSB) is "1", and B1 (MSB) is "0", the digital-to-analog converter 550 can output a thirteenth comparison reference voltage Vx13, which is the intermediate voltage between the fourteenth comparison reference voltage Vx14 and the twelfth comparison reference voltage Vx12, as a voltage Vn input to the inverting terminal (-) of the comparator 520.

[0095] Assuming that B3 (MSB) is "1", B2 (MSB) is "1", and B1 (MSB) is "1", in the fourth stage, comparator 520 can compare the magnitudes of the temperature voltage Vtemp and the fifteenth comparison reference voltage Vx15, and can provide the comparison result to successive approximation register 540. Successive approximation register 540 can set B0 to "1" in response to a comparison result where the temperature voltage Vtemp is greater than the fifteenth comparison reference voltage Vx15. Conversely, successive approximation register 540 can set B0 to "0" in response to a comparison result where the temperature voltage Vtemp is less than or equal to the fifteenth comparison reference voltage Vx15.

[0096] Using the above method, the temperature voltage Vtemp can be converted into a temperature code, as shown in Table 1 below. Figure 6 The analog-to-digital converter shown in the implementation is called "SAR-ADC".

[0097] Table 1

[0098]

[0099] Figure 7 This is an example Figure 6 A diagram showing the structure of the 550 digital-to-analog converter.

[0100] Reference Figure 5 , Figure 6 and Figure 7 According to an embodiment, the digital-to-analog converter 550 included in the analog-to-digital converter 500 can generate a first comparison reference voltage Vx1 to a fifteenth comparison reference voltage Vx15 in response to the output of the successive approximation register 540. When the temperature code has a data length of more than four bits, the digital-to-analog converter 550 can generate more comparison reference voltages.

[0101] According to an embodiment, the digital-to-analog converter 550 can generate a first comparison reference voltage Vx1 to a fifteenth comparison reference voltage Vx15 by connecting a first reference voltage Vx1 to a fifteenth comparison reference voltage Vx15 with three levels (i.e., a first reference voltage VREF+, an intermediate reference voltage VCM, and a second reference voltage VREF-) connected in parallel with eight transistors. Each of the eight transistors has an area that is 1 / 8 of the area of ​​a switching transistor connected to the non-inverting terminal (+) of the comparator 520. More specifically, reference will be made below. Figures 8 to 12D The method by which the digital-to-analog converter 550 generates a first comparison reference voltage Vx1 to a fifteenth comparison reference voltage Vx15 by connecting a reference voltage with three levels (i.e., a first reference voltage VREF+, an intermediate reference voltage VCM, and a second reference voltage VREF-) connected in parallel with eight transistors, each of the eight transistors having an area of ​​1 / 8 of the area of ​​a switching transistor connected to the non-inverting terminal (+) of the comparator 520.

[0102] Figure 8 This is an example generated in the reference. Figure 6 A diagram illustrating the method of applying a reference voltage in the first stage of converting temperature voltage Vtemp into temperature code (Temp Code).

[0103] Reference Figure 5 , Figure 6 and Figure 8 Different first voltages V1 to V8 can be applied to the gate electrodes of the first to eighth transistors.

[0104] The comparison reference voltage used in the first stage can be an intermediate reference voltage VCM, i.e., the eighth comparison reference voltage Vx8. To generate the eighth comparison reference voltage Vx8, the digital-to-analog converter 550 can bias each of the first voltages V1 to the eighth voltage V8 using the intermediate reference voltage VCM. Therefore, the voltage Vn input to the inverting terminal (-) of the comparator 520 can be (8 / 16). ((First reference voltage (VREF+) - Second reference voltage (VREF-)).

[0105] Figure 9A and Figure 9B This is an example generated in the reference. Figure 6 A diagram illustrating the method of applying a reference voltage in the second stage of converting the temperature voltage Vtemp into a temperature code (Temp Code).

[0106] Reference Figure 5 , Figure 6 , Figure 9A and Figure 9B Different first voltages V1 to V8 can be applied to the gate electrodes of the first to eighth transistors.

[0107] Figure 9A Examples are shown of the voltages applied to the first to eighth transistors when B3, corresponding to the most significant bit (MSB), is 1, and the voltage Vn applied to the inverting terminal (-) of comparator 520.

[0108] When B3 is 1, the comparison reference voltage used in the second stage can be the twelfth comparison reference voltage Vx12. To generate the twelfth comparison reference voltage Vx12, the digital-to-analog converter 550 can apply an intermediate reference voltage VCM to the gates of the first to fourth transistors, and can apply a first reference voltage VREF+ to the gates of the fifth to eighth transistors. As a result, the voltage Vn input to the inverting terminal (-) of comparator 520 can be (12 / 16). ((First reference voltage (VREF+) - Second reference voltage (VREF-)).

[0109] Figure 9B Examples are given of the voltages applied to the first to eighth transistors when B3, corresponding to the most significant bit (MSB), is 0, and the voltage Vn applied to the inverting terminal (-) of comparator 520.

[0110] When B3 is 0, the comparison reference voltage used in the second stage can be a fourth comparison reference voltage Vx4. To generate the fourth comparison reference voltage Vx4, the digital-to-analog converter 550 can apply an intermediate reference voltage VCM to the gates of the first to fourth transistors, and can apply a second reference voltage VREF- to the gates of the fifth to eighth transistors. As a result, the voltage Vn input to the inverting terminal (-) of comparator 520 can be (4 / 16). ((First reference voltage (VREF+) - Second reference voltage (VREF-)).

[0111] Figure 10A , Figure 10B , Figure 10C and Figure 10D This is an example generated in the reference. Figure 6 A diagram illustrating the method for converting temperature voltage Vtemp into temperature code in the third stage, using a comparison reference voltage.

[0112] Reference Figure 5 , Figure 6 , Figure 10A , Figure 10B , Figure 10C and Figure 10D Different first voltages V1 to V8 can be applied to the gate electrodes of the first to eighth transistors.

[0113] Figure 10A Examples are given of the voltages applied to the first to eighth transistors when B3, corresponding to the most significant bit (MSB), is 1 and B2 is 1, and the voltage Vn applied to the inverting terminal (-) of comparator 520.

[0114] When B3 is 1 and B2 is 1, the comparison reference voltage used in the third stage can be the fourteenth comparison reference voltage Vx14. To generate the fourteenth comparison reference voltage Vx14, the digital-to-analog converter 550 can apply an intermediate reference voltage VCM to the gates of the first and second transistors, and can apply a first reference voltage VREF+ to the gates of the third through eighth transistors. As a result, the voltage Vn input to the inverting terminal (-) of comparator 520 can be (14 / 16). ((First reference voltage (VREF+) - Second reference voltage (VREF-)).

[0115] Figure 10B Examples are given of the voltages applied to the first to eighth transistors when B3, corresponding to the most significant bit (MSB), is 1 and B2 is 0, and the voltage Vn applied to the inverting terminal (-) of comparator 520.

[0116] When B3 is 1 and B2 is 0, the comparison reference voltage used in the third stage can be the tenth comparison reference voltage Vx10. To generate the tenth comparison reference voltage Vx10, the digital-to-analog converter 550 can apply an intermediate reference voltage VCM to the gates of the first through sixth transistors, and can apply a first reference voltage VREF+ to the gates of the seventh and eighth transistors. As a result, the voltage Vn input to the inverting terminal (-) of comparator 520 can be (10 / 16). ((First reference voltage (VREF+) - Second reference voltage (VREF-)).

[0117] Figure 10CExamples are given of the voltages applied to the first to eighth transistors when B3, corresponding to the most significant bit (MSB), is 0 and B2 is 0, and the voltage Vn applied to the inverting terminal (-) of comparator 520.

[0118] When B3 is 0 and B2 is 0, the comparison reference voltage used in the third stage can be the second comparison reference voltage Vx2. To generate the second comparison reference voltage Vx2, the digital-to-analog converter 550 can apply an intermediate reference voltage VCM to the gates of the first and second transistors, and can apply a first reference voltage VREF+ to the gates of the third through eighth transistors. As a result, the voltage Vn input to the inverting terminal (-) of comparator 520 can be (2 / 16). ((First reference voltage (VREF+) - Second reference voltage (VREF-)).

[0119] Figure 10D Examples are given of the voltages applied to the first to eighth transistors when B3, corresponding to the most significant bit (MSB), is 0 and B2 is 1, and the voltage Vn applied to the inverting terminal (-) of comparator 520.

[0120] When B3 is 0 and B2 is 1, the comparison reference voltage used in the third stage can be the sixth comparison reference voltage Vx6. To generate the sixth comparison reference voltage Vx6, the digital-to-analog converter 550 can apply an intermediate reference voltage VCM to the gates of the first to sixth transistors, and can apply a second reference voltage VREF- to the gates of the seventh and eighth transistors. As a result, the voltage Vn input to the inverting terminal (-) of comparator 520 can be (6 / 16). ((First reference voltage (VREF+) - Second reference voltage (VREF-)).

[0121] Figure 11A , Figure 11B , Figure 11C and Figure 11D This is an example generated in the reference. Figure 6 A diagram illustrating the method for converting temperature voltage Vtemp into temperature code in the fourth stage, using a comparison reference voltage.

[0122] Reference Figure 5 , Figure 6 , Figure 11A , Figure 11B , Figure 11C and Figure 11D Different first voltages V1 to V8 can be applied to the gate electrodes of the first to eighth transistors.

[0123] Figure 11AExamples are given of the voltages applied to the first to eighth transistors when B3, corresponding to the most significant bit (MSB), is 1, B2 is 1, and B1 is 1, and the voltage applied to the inverting terminal (-) of comparator 520.

[0124] When B3 is 1, B2 is 1, and B1 is 1, the comparison reference voltage used in the fourth stage can be the fifteenth comparison reference voltage Vx15. To generate the fifteenth comparison reference voltage Vx15, the digital-to-analog converter 550 can apply an intermediate reference voltage VCM to the gate of the first transistor and a first reference voltage VREF+ to the gates of the second through eighth transistors. As a result, the voltage Vn input to the inverting terminal (-) of comparator 520 can be (15 / 16). ((First reference voltage (VREF+) - Second reference voltage (VREF-)).

[0125] Figure 11B Examples are given of the voltages applied to the first to eighth transistors when B3 is 1, B2 is 1, and B1 is 0, corresponding to the most significant bit (MSB), and the voltage Vn applied to the inverting terminal (-) of comparator 520.

[0126] When B3 is 1, B2 is 1, and B1 is 0, the comparison reference voltage used in the fourth stage can be the thirteenth comparison reference voltage Vx13. To generate the thirteenth comparison reference voltage Vx13, the digital-to-analog converter 550 can apply an intermediate reference voltage VCM to the gates of the first to third transistors, and can apply a first reference voltage VREF+ to the gates of the fourth to eighth transistors. As a result, the voltage Vn input to the inverting terminal (-) of comparator 520 can be (13 / 16). ((First reference voltage (VREF+) - Second reference voltage (VREF-)).

[0127] Figure 11C Examples are given of the voltages applied to the first to eighth transistors when B3 is 1, B2 is 0, and B1 is 1, corresponding to the most significant bit (MSB), and the voltage Vn applied to the inverting terminal (-) of comparator 520.

[0128] When B3 is 1, B2 is 0, and B1 is 1, the comparison reference voltage used in the fourth stage can be the eleventh comparison reference voltage Vx11. To generate the eleventh comparison reference voltage Vx11, the digital-to-analog converter 550 can apply an intermediate reference voltage VCM to the gates of the first to fifth transistors, and can apply a first reference voltage VREF+ to the gates of the sixth to eighth transistors. As a result, the voltage Vn input to the inverting terminal (-) of comparator 520 can be (11 / 16). ((First reference voltage (VREF+) - Second reference voltage (VREF-)).

[0129] Figure 11D Examples are given of the voltages applied to the first to eighth transistors when B3 is 1, B2 is 0, and B1 is 0, corresponding to the most significant bit (MSB), and the voltage Vn applied to the inverting terminal (-) of comparator 520.

[0130] When B3 is 1, B2 is 0, and B1 is 0, the comparison reference voltage used in the fourth stage can be the ninth comparison reference voltage Vx9. To generate the ninth comparison reference voltage Vx9, the digital-to-analog converter 550 can apply an intermediate reference voltage VCM to the gates of the first through seventh transistors, and can apply a first reference voltage VREF+ to the gate of the eighth transistor. As a result, the voltage Vn input to the inverting terminal (-) of comparator 520 can be (9 / 16). ((First reference voltage (VREF+) - Second reference voltage (VREF-)).

[0131] Figure 12A , Figure 12B , Figure 12C and Figure 12D This is an example generated in the reference. Figure 6 A diagram illustrating the method for converting temperature voltage Vtemp into temperature code in the fourth stage, using a comparison reference voltage.

[0132] Reference Figure 5 , Figure 6 , Figure 12A , Figure 12B , Figure 12C and Figure 12D Different first voltages V1 to V8 can be applied to the gate electrodes of the first to eighth transistors.

[0133] Figure 12A Examples include the voltages applied to the first to eighth transistors and the voltage Vn applied to the inverting terminal (-) of comparator 520 when B3, corresponding to the most significant bit (MSB), is 0, B2 is 0, and B1 is 0.

[0134] When B3, B2, and B1 are all 0, the comparison reference voltage used in the fourth stage can be a first comparison reference voltage Vx1. To generate the first comparison reference voltage Vx1, the digital-to-analog converter 550 can apply an intermediate reference voltage VCM to the gate of the first transistor and a second reference voltage VREF- to the gates of the second through eighth transistors. As a result, the voltage Vn input to the inverting terminal (-) of the comparator 520 can be (1 / 16). ((First reference voltage (VREF+) - Second reference voltage (VREF-)).

[0135] Figure 12B Examples are given of the voltages applied to the first to eighth transistors when B3 is 0, B2 is 0 and B1 is 1 corresponding to the most significant bit (MSB), and the voltage Vn applied to the inverting terminal (-) of comparator 520.

[0136] When B3 is 0, B2 is 0, and B1 is 1, the comparison reference voltage used in the fourth stage can be the third comparison reference voltage Vx3. To generate the third comparison reference voltage Vx3, the digital-to-analog converter 550 can apply an intermediate reference voltage VCM to the gates of the first to third transistors, and can apply a second reference voltage VREF- to the gates of the fourth to eighth transistors. As a result, the voltage Vn input to the inverting terminal (-) of the comparator 520 can be (3 / 16). ((First reference voltage (VREF+) - Second reference voltage (VREF-)).

[0137] Figure 12C Examples are given of the voltages applied to the first to eighth transistors when B3 is 0, B2 is 1, and B1 is 0, corresponding to the most significant bit (MSB), and the voltage Vn applied to the inverting terminal (-) of comparator 520.

[0138] When B3 is 0, B2 is 1, and B1 is 0, the comparison reference voltage used in the fourth stage can be the fifth comparison reference voltage Vx5. To generate the fifth comparison reference voltage Vx5, the digital-to-analog converter 550 can apply an intermediate reference voltage VCM to the gates of the first to fifth transistors, and can apply a second reference voltage VREF- to the gates of the sixth to eighth transistors. As a result, the voltage Vn input to the inverting terminal (-) of comparator 520 can be (5 / 16). ((First reference voltage (VREF+) - Second reference voltage (VREF-)).

[0139] Figure 12D Examples are given of the voltages applied to the first to eighth transistors and the voltage Vn applied to the inverting terminal (-) of comparator 520 when B3 is 0, B2 is 1, and B1 is 1, corresponding to the most significant bit (MSB).

[0140] When B3 is 0, B2 is 1, and B1 is 1, the comparison reference voltage used in the fourth stage can be the seventh comparison reference voltage Vx7. To generate the seventh comparison reference voltage Vx7, the digital-to-analog converter 550 can apply an intermediate reference voltage VCM to the gates of the first through seventh transistors, and can apply a second reference voltage VREF- to the gate of the eighth transistor. As a result, the voltage Vn input to the inverting terminal (-) of comparator 520 can be (7 / 16). ((First reference voltage (VREF+) - Second reference voltage (VREF-)).

[0141] Figure 13 This is a circuit diagram illustrating one embodiment of a comparator 800 included in an analog-to-digital converter 152 according to an embodiment of the present disclosure.

[0142] Reference Figure 13 The comparator 800 can compare the voltage Vp input through the non-inverting terminal (+) with the voltage Vn input through the inverting terminal (-) and can output the comparison result.

[0143] Comparator 800 may include a reference voltage input circuit 810, a target voltage input circuit 820, a comparison operation controller 830, a comparison result storage enable circuit 840, and a comparison result storage 860.

[0144] The reference voltage input circuit 810 may have a first to an eighth transistor connected in parallel to generate the reference voltage as described above. Figures 8 to 12D The comparison reference voltage is described. The reference voltage input circuit 810 can be based on the above reference. Figures 8 to 12D The described method controls the gate voltages (V1 to V8) of the first to eighth transistors. According to an embodiment, the area of ​​the transistors included in the target voltage input circuit 820 may be the same as the sum of the areas of the first to eighth transistors. Alternatively, the area of ​​the transistors included in the target voltage input circuit 820 may be eight times the area of ​​each of the first to eighth transistors. In other words, the area of ​​each of the first to eighth transistors may be 1 / 8 of the area of ​​the transistors included in the target voltage input circuit 820.

[0145] The target voltage input circuit 820 can receive the voltage Vp input through the non-inverting terminal (+).

[0146] The comparator controller 830 can compare the voltage Vp input through the non-inverting terminal (+) with the voltage Vn input through the inverting terminal (-).

[0147] The comparison result storage enable circuit 840 enables the latch to store the comparison result.

[0148] The comparison result storage 860 can store the comparison result between the voltage Vp input through the non-inverting terminal (+) and the voltage Vn input through the inverting terminal (-).

[0149] For reference Figure 13 As described, the other components of comparator 800, except for the reference voltage input circuit 810 and the target voltage input circuit 820, can vary depending on the design.

[0150] Figure 14 This is an example Figure 1 A diagram illustrating an implementation of the memory controller 200.

[0151] Reference Figure 14 The memory controller 1400 may include a processor 1410, RAM 1420, error correction code (ECC) circuitry 1430, host interface 1440, ROM 1450 and flash memory interface 1460.

[0152] The processor 1410 can control the overall operation of the memory controller 1400. The RAM 1420 can be used as buffer memory, cache memory, or working memory.

[0153] ROM 1450 can store various information required to operate memory controller 1400 in firmware form.

[0154] The memory controller 1400 can communicate with external devices (e.g., host 400, application processor, etc.) via host interface 1440.

[0155] The memory controller 1400 can communicate with the memory device 100 via the flash interface 1460. The memory controller 1400 can transmit commands (CMD), addresses (ADDR), and control signals (CTRL) to the memory device 100, and can receive data (DATA). For example, the flash interface 1460 may include a NAND interface.

[0156] Figure 15 This is a block diagram illustrating a memory card system 2000 using a storage device according to an embodiment.

[0157] Reference Figure 15 The memory card system 2000 may include a memory controller 2100, a memory device 2200, and a connector 2300.

[0158] Memory controller 2100 can be coupled to memory device 2200. Memory controller 2100 can access memory device 2200. For example, memory controller 2100 can control read operations, programming operations, erase operations, and background operations of memory device 2200. Memory controller 2100 can be configured to provide an interface between memory device 2200 and a host. Memory controller 2100 can be configured to drive firmware for controlling memory device 2200. Memory controller 2100 can have the same features as described above. Figure 1 The memory controller 200 described has the same configuration.

[0159] In some implementations, the memory controller 2100 may include components such as random access memory (RAM), a processing unit, a host interface, a flash memory interface, and ECC circuitry.

[0160] The memory controller 2100 can communicate with external devices via connector 2300. The memory controller 2100 can communicate with external devices (e.g., a host) based on a specific communication protocol. In embodiments, the memory controller 2100 can communicate with external devices via at least one of various communication protocols such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Fast (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), WiFi, Bluetooth, and High-Speed ​​Non-Volatile Memory (NVMe). In embodiments, connector 2300 can be defined by at least one of the aforementioned communication protocols.

[0161] In implementations, the memory device 2200 may be implemented as any of a variety of non-volatile memory devices such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), spin-transfer torque magnetic RAM (STT-MRAM).

[0162] The memory controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to form a memory card such as the Personal Computer Memory Card International Association (PCMCIA), Compact Flash Card (CF), Smart Media Card (SM or SMC), Memory Stick Multimedia Card (MMC, RS-MMC, or Micro MMC), SD Card (SD, Mini SD, Micro SD, or SDHC), Universal Flash Memory (UFS), etc.

[0163] Figure 16 This is a block diagram illustrating a solid-state drive (SSD) system for use with a storage device according to an implementation method.

[0164] Reference Figure 16 The SSD system 3000 may include a host 3100 and an SSD 3200. The SSD 3200 can exchange signals with the host 3100 through a signal connector 3001 and can receive power through a power connector 3002. The SSD 3200 may include an SSD controller 3210, multiple flash memory modules 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0165] In the implementation, the SSD controller 3210 can perform the above-mentioned reference. Figure 1 The functions of the memory controller 200 are described.

[0166] SSD controller 3210 can control multiple flash memory modules 3221 to 322n in response to signals received from host 3100. In implementations, the signals can be based on the interface between host 3100 and SSD 3200. For example, the signals can be defined by at least one of various interfaces such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Fast (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), WiFi, Bluetooth, and High-Speed ​​Non-Volatile Memory (NVMe) interfaces.

[0167] Auxiliary power supply 3230 can be connected to host 3100 via power connector 3002. Auxiliary power supply 3230 can be supplied with and charged from host 3100. When power supply from host 3100 is not smooth, auxiliary power supply 3230 can provide power to SSD 3200. In implementations, auxiliary power supply 3230 can be located inside or outside SSD 3200. For example, auxiliary power supply 3230 can be located within the motherboard and can provide auxiliary power to SSD 3200.

[0168] Buffer memory 3240 can be used as a buffer memory for SSD 3200. For example, buffer memory 3240 can temporarily store data received from host 3100 or data received from multiple flash memory modules 3221 to 322n, or it can temporarily store metadata (e.g., mapping tables) of flash memory modules 3221 to 322n. Buffer memory 3240 can include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0169] Figure 17 This is a block diagram illustrating a user system 4000 using a storage device according to an embodiment of the present disclosure.

[0170] Reference Figure 17 The user system 4000 may include an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0171] Application processor 4100 may run an operating system (OS), user programs, or components included in user system 4000. In embodiments, application processor 4100 may include controllers, interfaces, graphics engines, etc., for controlling components included in user system 4000. Application processor 4100 may be configured as a system-on-a-chip (SoC).

[0172] The memory module 4200 can be used as the main memory, working memory, buffer memory, or cache memory of the user system 4000. The memory module 4200 may include volatile RAM such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile RAM such as PRAM, ReRAM, MRAM, and FRAM. In an embodiment, the application processor 4100 and the memory module 4200 may be packaged based on a stacked package (POP) and may then be configured as a single semiconductor package.

[0173] Network module 4300 can communicate with external devices. For example, network module 4300 can support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, or WiFi communication. In some implementations, network module 4300 may be included in application processor 4100.

[0174] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Alternatively, storage module 4400 can send data stored in storage module 4400 to application processor 4100. In embodiments, storage module 4400 can be implemented as a non-volatile semiconductor memory device such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory with a three-dimensional (3D) structure. In embodiments, storage module 4400 can be configured as a removable storage medium (i.e., a removable drive) of user system 4000, such as a memory card or external drive.

[0175] For example, storage module 4400 may include multiple non-volatile memory devices, and the multiple non-volatile memory devices may be related to the above-mentioned references. Figure 1 The described memory device 100 operates in the same manner. The storage module 4400 can be compared with the above-mentioned reference. Figure 1 The described storage device 50 operates in the same manner.

[0176] User interface 4500 may include an interface for inputting data or instructions to application processor 4100 or outputting data to external devices. In embodiments, user interface 4500 may include user input interfaces such as a keyboard, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric device. User interface 4500 may also include user output interfaces such as liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active-matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0177] According to this disclosure, an analog-to-digital converter with reduced size, a memory device having the analog-to-digital converter, and a method of operating the same can be provided.

[0178] Cross-references to related applications

[0179] This application claims priority to Korean Patent Application No. 10-2020-0128203, filed on October 5, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. An analog-to-digital converter (ADC) that outputs digital data corresponding to a comparison result between an input voltage as an analog signal and a plurality of comparison reference voltages, the ADC comprising: An input voltage provider that outputs the input voltage during multiple phases; A comparator that outputs a comparison result between the input voltage and one of the plurality of comparison reference voltages; A successive approximation register, which outputs at least one bit of the plurality of bits of the digital data based on the comparison result; as well as A digital-to-analog converter (DAC) provides one of the plurality of comparison reference voltages to the comparator based on the at least one bit. The digital-to-analog converter includes multiple transistors connected in parallel with each other, and selectively receives multiple reference voltages to generate the comparison reference voltage. Wherein, each of the plurality of transistors has the same area as the others, and The sum of the areas of the plurality of transistors is the same as the area of ​​the transistor receiving the input voltage.

2. The analog-to-digital converter according to claim 1, wherein, The plurality of reference voltages are less than the plurality of comparison reference voltages.

3. The analog-to-digital converter according to claim 1, wherein, The number of bits is equal to the number of times the input voltage is compared with one of the plurality of comparison reference voltages.

4. The analog-to-digital converter according to claim 1, wherein, The successive approximation register outputs the most significant bit among the plurality of bits based on the comparison result between the input voltage and the comparison reference voltage corresponding to the median value among the plurality of comparison reference voltages.

5. The analog-to-digital converter according to claim 4, wherein, The digital-to-analog converter provides the comparator with a comparison reference voltage corresponding to the median value among the plurality of comparison reference voltages determined based on the most significant bit.

6. The analog-to-digital converter according to claim 5, wherein, The comparator compares the input voltage with a reference voltage corresponding to the median value among the reference voltages determined based on the most significant bit, and The successive approximation register outputs the next bit of the most significant bit among the plurality of bits based on the comparison result between the input voltage and the comparison reference voltage corresponding to the median value among the comparison reference voltages determined based on the most significant bit.

7. An analog-to-digital converter, the analog-to-digital converter comprising: A digital-to-analog converter, wherein the digital-to-analog converter generates a plurality of comparison reference voltages based on at least one preset reference voltage and outputs the plurality of comparison reference voltages; as well as A comparator having a first input terminal for receiving an input voltage and a second input terminal for receiving an output from the digital-to-analog converter, the comparator outputting a result comparing the voltage at the first input terminal with the voltage at the second input terminal. The digital-to-analog converter includes a plurality of transistors connected in parallel with each other, and selectively receives the at least one reference voltage. Wherein, each of the plurality of transistors has the same area as the others, and The sum of the areas of the plurality of transistors is the same as the area of ​​the transistor receiving the input voltage.

8. The analog-to-digital converter according to claim 7, further comprising: An input voltage provider samples the input voltage and provides the sampled input voltage to the comparator.

9. The analog-to-digital converter according to claim 7, further comprising: A successive approximation register, which outputs a portion of digital data corresponding to the input voltage based on the output of the comparator.

10. The analog-to-digital converter according to claim 9, further comprising: A clock provider that provides a clock signal corresponding to the number of times the successive approximation register outputs the portion of the digital data.

11. A memory device comprising: A storage block having multiple memory units for storing data; A voltage generator that generates operating voltages for accessing the plurality of memory cells; A temperature information generator that generates a temperature code based on internal temperature; as well as The control logic controls the voltage generator to control the operating voltage based on the temperature code. The temperature information generator includes: A sensor that generates a temperature-voltage signal, the temperature-voltage signal being an analog signal determined based on the internal temperature; and An analog-to-digital converter (ADC) converts the temperature-voltage signal into a digital signal. The analog-to-digital converter includes: A comparator that outputs a comparison result between the temperature voltage signal and one of a plurality of comparison reference voltages; A successive approximation register, which outputs at least one bit of the temperature code based on the comparison result; and A digital-to-analog converter (DAC) provides one of the plurality of comparison reference voltages to the comparator based on the at least one bit. The digital-to-analog converter includes multiple transistors connected in parallel with each other, and selectively receives multiple reference voltages to generate the comparison reference voltage. Wherein, each of the plurality of transistors has the same area as the others, and The sum of the areas of the plurality of transistors is the same as the area of ​​the transistor receiving the temperature voltage signal.

12. The memory device according to claim 11, wherein, The plurality of reference voltages are less than the plurality of comparison reference voltages.

13. The memory device according to claim 11, wherein, The number of bits is equal to the number of times the temperature voltage signal is compared with one of the plurality of comparison reference voltages.

14. The memory device according to claim 11, wherein, The successive approximation register outputs the most significant bit among the plurality of bits based on the comparison result between the temperature voltage signal and the comparison reference voltage corresponding to the median value among the plurality of comparison reference voltages.

15. The memory device according to claim 14, wherein, The digital-to-analog converter provides the comparator with a comparison reference voltage corresponding to the median value among the plurality of comparison reference voltages determined based on the most significant bit.

16. The memory device according to claim 11, wherein, The operating voltage includes a programming voltage for storing data in the plurality of memory cells and a read voltage for reading data stored in the plurality of memory cells.

17. The memory device according to claim 16, wherein, The control logic, in response to the temperature code indicating that the internal temperature is above a critical temperature, controls the voltage generator to reduce the read voltage to a predetermined level.

18. The memory device according to claim 16, wherein, The control logic, in response to the temperature code indicating that the internal temperature is below a critical temperature, controls the voltage generator to increase the read voltage by a predetermined level.

19. The memory device according to claim 16, wherein, The control logic responds to the temperature code indicating that the internal temperature is above a critical temperature by controlling the voltage generator to increase the programmed voltage by a predetermined level.

20. The memory device according to claim 16, wherein, The control logic, in response to the temperature code indicating that the internal temperature is below a critical temperature, controls the voltage generator to reduce the programmed voltage to a predetermined level.

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