A memory controller verification apparatus and verification system

Abstract

The embodiment of the present application provides a memory controller verification device and a verification system, the memory controller verification device comprises: a mode register module, comprising mode registers respectively constructed in correspondence with each memory particle in a memory, wherein the memory is a memory actually accessed by a memory controller to be verified; and at least one access control module configured to access a target mode register included in the mode register module through a pointer, wherein one access control module is arranged in correspondence with one memory sub-channel of the memory. The verification device and the verification system of some embodiments of the present application simplify the processing procedure required when the verification environment (i.e. the access environment of the memory controller to the mode register) accesses the mode register, and accelerate the simulation and debugging efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip product verification, and in particular, the embodiments of the present application relate to a memory controller verification device and a verification system. BACKGROUND

[0002] Memory controllers have single-channel types and double-channel types. For example, a DDR5 memory controller is a double-channel controller, because DDR5 UDIMM memory is divided into two memory sub-channels. In an actual DDR storage subsystem, a DDR5 memory controller and a UDIMM strip are connected by a DDR PHY. Different numbers of sub-channels increase the complexity of the access of the memory controller to the mode register. Different memories have a large difference in the number of mode registers contained, thus causing a large difference in the access mode of the memory controller to the mode registers of different memories.

[0003] For example, a DDR4 SDRAM memory has 8 mode registers MR0-MR7, and the operation of the mode register is completed indirectly through a MPR (Multi Purpose Register), while each memory particle of a DDR5 SDRAM has 256 mode registers, and the number of mode registers is very large.

[0004] Therefore, how to design a reasonable verification model for DDR5 to verify the access process of the memory controller to each mode register has become a technical problem to be solved urgently. SUMMARY

[0005] The purpose of the embodiments of the present application is to provide a memory controller verification device and a verification system, which simplify the processing required when the verification device and the verification system access the mode register in the verification environment (i.e., the access environment of the memory controller to the mode register), and accelerate the simulation and debugging efficiency of the process of the memory controller accessing the memory mode register.

[0006] In a first aspect, some embodiments of the present application provide a memory controller verification device, which comprises: a mode register module comprising mode registers respectively corresponding to each memory particle in a memory, wherein the memory is a storage to be actually accessed by a memory controller to be verified; and at least one access control module configured to access a target mode register included in the mode register module through a pointer, wherein one access control module is set corresponding to one memory sub-channel of the memory.

[0007] Some embodiments of the present application are directed to the same memory sub-channel, and in the verification process, the virtual RANK (i.e. through the pointer set in the access control module) can set the granularity in the mode register (i.e. the mode register module) of the actual constructed memory granularity, so that the access control operation of the memory controller to each mode register can be effectively verified, and the design structure simplifies the processing required when the verification environment accesses the mode register, and accelerates the simulation and debugging efficiency.

[0008] In some embodiments, the memory includes N RANKs, each RANK includes M memory granularities, and each memory granularity includes L mode registers, wherein the mode register module is configured to include N constructed mode register instances, wherein each mode register instance includes L mode registers constructed for each of the M memory granularities, and one mode register instance is set corresponding to one RANK, N is an integer greater than or equal to 1, and M and L are integers greater than 1.

[0009] Some embodiments of the present application construct mode registers for all memory granularities included in the memory, and construct mode register instances for each bank of the memory, and the design structure can simplify the processing required when the verification environment accesses the mode register.

[0010] In some embodiments, the memory includes A memory banks, and one memory sub-channel includes B RANKs distributed on the A memory banks; wherein the mode register module is configured to include A constructed memory banks, and the mode register for one memory sub-channel is configured to include B constructed RANKs, wherein the B constructed RANKs are located on the A constructed memory banks; the access control module is configured to include B virtual RANKs, wherein one virtual RANK corresponds to one constructed RANK, and each virtual RANK corresponds to a unique code; wherein A and B are integers greater than or equal to 1.

[0011] Some embodiments of the present application completely copy all RANKs in the actual memory in the mode register, including the memory bank number, whether on the front or back of the memory bank, etc., and the access control module does not need to construct elements and information related to the memory bank, but only directly constructs virtual RANKs corresponding to all RANKs of one memory sub-channel, and uniquely codes the virtual RANKs, and through this design method, the access speed of each constructed RANK can be accelerated, and the verification speed can be ultimately improved.

[0012] In some embodiments, each virtual RANK is accessed through the code, and each virtual RANK accesses the corresponding target RANK on the mode register module through the RANK access pointer.

[0013] Some embodiments of the present application find the target virtual RANK by the encoding assigned to the virtual RANK, and access the RANK built on the mode register module through the RANK corresponding to the virtual RANK, which makes the access to each built RANK independent of the distribution form of the RANK on the DIMM (memory bank), thereby realizing the direct access to the memory grain at the RANK level.

[0014] In some embodiments, each virtual RANK includes a group of pointers, wherein the target mode register located on the mode register module can be accessed through the mode register access pointer included in each group of pointers.

[0015] Some embodiments of the present application can access the target mode register built on the mode register module through the mode register access pointer included in the virtual RANK, thereby realizing the fast access to the mode register.

[0016] In some embodiments, the mode register is configured to include a plurality of fields of different sizes, and each field corresponds to a different name, wherein each field included in the mode register is accessed through the name of the field.

[0017] Some embodiments of the present application define a plurality of fields for each built mode register, thereby realizing the access to different fields of each mode register, refining the access granularity, and enriching the verification parameters of the memory controller to be verified.

[0018] In some embodiments, the mapping relationship between the memory grain serial number and the PDA ID encoding on the mode register module can be dynamically configured.

[0019] Some embodiments of the present application can dynamically configure the mapping between the memory grain serial number and the single memory grain access encoding, thereby extremely conveniently realizing the test of any combination of the memory grain PDA ID encoding.

[0020] In some embodiments, different memory sub-channels included in the memory are distinguished through different identification signals.

[0021] Some embodiments of the present application can access different memory sub-channels through different identification numbers, thereby realizing the verification operation for different memory sub-channels, and some embodiments of the present application can dynamically configure the relationship between the single memory grain access encoding (i.e. the PDA ID encoding) and the memory grain serial number.

[0022] In some embodiments, the access control module further comprises: an instruction decoder configured to parse the memory granule operation instruction from the interface signal according to an interface protocol, wherein the interface protocol is a protocol adopted by a downward interface unit of the memory controller to be verified; a mode register operation instruction parsing unit configured to parse the memory granule operation instruction to obtain a parsing result, and to filter target operation instruction related to mode register operation according to the parsing result; and a sub-channel mode register application method module configured to obtain a target virtual RANK corresponding to the target operation, and to access a target RANK located on the mode register module according to a RANK access pointer corresponding to the target virtual RANK to complete the target operation on all mode registers on the target RANK, or to obtain a target virtual RANK and a target mode register corresponding to the target operation, to access a target RANK according to a RANK access pointer corresponding to the target virtual RANK, and to access the target mode register on the target RANK according to a mode register access pointer included in the target virtual RANK to complete the target operation on the target mode register.

[0023] Some embodiments of the present application can filter out operation instructions related to mode registers through interface protocol analysis by the instruction decoder and the mode register operation instruction parsing unit provided for each memory sub-channel, and can complete the operation on the constructed mode registers according to the access method and operation function integrated on the sub-channel mode register application method module, thereby better verifying the performance of the memory controller to be verified.

[0024] In some embodiments, the sub-channel mode register application method module at least includes: an implementation function corresponding to all operation instructions of the mode register, and a logical conversion mapping table between the memory sub-channel and a target memory granule, wherein the distribution position of the target mode register on the mode register module is obtained by looking up the logical conversion mapping table, and the target operation is completed by the implementation function corresponding to the target operation.

[0025] Some embodiments of the present application can conveniently and quickly realize the access and target operation on the constructed mode registers by encapsulating various operation functions and mapping relationships on the sub-channel mode register application method module, thereby more quickly completing the verification work on the memory controller.

[0026] In some embodiments, the interface protocol is a DFI protocol, and the memory is a UDIMM, wherein the mode register operation instruction parsing unit is further configured to: screen the memory particle operation instruction to obtain an MPC instruction, and obtain an MPC instruction parsing result; and if it is determined according to the MPC instruction parsing result that the PDA operation state is present, obtain the target mode register according to the PDA operation state.

[0027] Some embodiments of the present application can also complete various mode register operation instructions in the PDA operation state through the mode register operation instruction parsing unit, and thus more comprehensively verify the performance of the memory controller.

[0028] In some embodiments, the memory controller verification apparatus further comprises a constructed shadow register, wherein if it is determined according to the mode register operation instruction parsing unit that the PDA state is present, the sub-channel mode register application method module is further configured to realize target operation corresponding to the shadow register through the shadow register and the target mode register.

[0029] Some embodiments of the present application can also realize shadow register operation, and thus more comprehensively verify the performance of the memory controller.

[0030] In some embodiments, the sub-channel mode register application method module is further configured to generate error prompt information when it is determined that the target mode register belongs to a prohibited access mode register.

[0031] Some embodiments of the present application can also realize shadow register operation, and thus more comprehensively verify the performance of the memory controller.

[0032] In some embodiments, the mode register operation instruction parsing unit comprises a plurality of target type instruction screening units, wherein each unit in the plurality of target type instruction screening units is configured to screen any target type mode register operation instruction from the memory particle operation instruction.

[0033] Some embodiments of the present application can more comprehensively verify various operations of the memory controller on the mode register through the plurality of types of instruction screening units.

[0034] In some embodiments, if the memory is a UDIMM, the mode register operation instruction parsing unit comprises: an MPC command processing unit, an input end of which is connected with an output end of the instruction decoder, and which is configured to acquire an MPC instruction from the output result of the instruction decoder and parse the MPC instruction to obtain an MPC instruction parsing result; an MRW command processing unit, an output end of which is connected with the output end of the MPC command processing unit, and which is configured to detect an MRW instruction from the input signal and parse the MRW instruction to obtain an MRW instruction parsing result; an MRR command processing unit, an output end of which is connected with the output end of the MPC command processing unit, and which is configured to detect an MRR instruction from the input signal and parse the MRR instruction to obtain an MRR instruction parsing result; and a VrefcA / VrefcS command processing unit, an output end of which is connected with the output end of the MPC command processing unit, and which is configured to detect a VrefcA and / or VrefcS instruction from the input signal and parse the VrefcA and / or VrefcS instruction to obtain a VrefcA and / or VrefcS instruction parsing result.

[0035] Some embodiments of the present application can complete the verification of various commands including the MPC command for the UDIMM type memory.

[0036] In some embodiments, the interface protocol is a DFI protocol, and the mode register operation instruction parsing unit further comprises: a PDA monitoring module configured to confirm that the memory is in a PDA operation state; wherein an output end of the MPC command processing unit is connected with an input end of the PDA monitoring module, wherein the PDA monitoring module confirms that the memory is in the PDA operation state through the MPC instruction parsing result; an input end of the MRW command processing unit is connected with an output end of the PDA monitoring module; an input end of the MRR command processing unit is connected with the output end of the PDA monitoring module; and an input end of the VrefcA / VrefcS command processing unit is connected with the output end of the PDA monitoring module.

[0037] The PDA monitoring module in some embodiments of the present application confirms that the memory is in the PDA operation state, and can perform more complete performance verification on the memory controller to be verified.

[0038] In a second aspect, some embodiments of the present disclosure provide a memory mode register modeling method for constructing the memory controller verification apparatus according to any of the embodiments of the first aspect. The memory mode register modeling method comprises: constructing a mode register space of each memory sub-channel in a memory; and creating an access tool for accessing a target memory mode register included in the mode register space, wherein the access tool is configured to access the target mode register included in the mode register space according to a pointer and complete at least one operation on the target mode register, the at least one operation comprising one or more of the following operations: a read or write operation on various fields included in the target mode register, a read or write operation on the target mode register as a whole, and a shadow register access operation.

[0039] In some embodiments, the constructing the mode register space of each memory sub-channel in the at least one memory channel comprises: modeling a spatial relationship of memory grains based on a DFI interface, and mapping all constructed mode register arrays corresponding to the memory grains included in a same memory sub-channel to a virtual RANK mode register array corresponding to the DFI interface.

[0040] In some embodiments, after the creating the access tool for accessing the target memory mode register included in the mode register space, the memory mode register modeling method further comprises: adding a behavior model, and adding the access tool and the behavior model to a memory sub-channel model, wherein the behavior model is used to simulate behaviors of at least part of the mode registers.

[0041] In some embodiments, after the adding the access tool and the behavior model to the memory sub-channel model, the memory mode register modeling method further comprises: encapsulating the memory sub-channel model and a memory controller.

[0042] In some embodiments, the space relationship of the memory particles is modeled, including: creating field types of a pattern register to be constructed and names of the field types; creating a pattern register according to the field types, obtaining a constructed pattern register; creating a plurality of the constructed pattern registers according to a number of all pattern registers included in a memory particle, obtaining a memory particle pattern register group; creating a plurality of the memory particle pattern register groups according to a total number of memory particles included on a RANK, obtaining a RANK pattern register group, wherein the RANK is located on a memory actually connected to a memory controller to be verified; creating a plurality of the RANK pattern register groups according to a type of each memory sub-channel included in the memory, obtaining a memory sub-channel pattern register group, wherein the memory particle, the RANK, and the memory sub-channel are all located on the memory, and the memory is an access device actually accessed by the memory controller to be verified.

[0043] In some embodiments, the fields respectively correspond to different bit numbers, a length of a longest field is equal to a length of a pattern register, a length of a shortest field is 1, and a total number of the fields is the same as the length of the longest field.

[0044] In a third aspect, some embodiments of the present application provide a verification method for verifying a process of a memory controller to access a pattern register, based on the memory controller verification apparatus provided in any of the embodiments of the first aspect. The verification method includes: for each memory sub-channel, completing current instruction decoding of a DFI interface to obtain an instruction decoding result; according to the instruction decoding result, confirming that the current instruction belongs to a memory pattern register operation instruction related to memory pattern register operation; and confirming that the memory pattern register operation instruction is for a target addressable pattern register, then accessing a target RANK through a RANK access pointer corresponding to a target virtual RANK and accessing the target pattern register through a memory particle access pointer included in the target virtual RANK to complete operation on the target pattern register; wherein the operation is a function corresponding to the current instruction, the target pattern register is located on the target RANK, the target RANK is located on a pattern register module, the target virtual RANK is a pointer group constructed for accessing each pattern register on the target RANK, and the pattern register module includes pattern registers constructed for each memory particle in a memory, and the memory is a storage device actually accessed by a memory controller to be verified.

[0045] In some embodiments, the verification method further comprises: if it is confirmed that the memory mode register operation instruction is for a target virtual RANK, then completing the operation on all mode registers included in the target RANK by accessing the all mode registers through a RANK access pointer corresponding to the target virtual RANK.

[0046] In some embodiments, the verification method further comprises: if it is confirmed that the memory mode register operation instruction is for an operation on a shadow mode register, then completing the operation by calling a shadow register processing function.

[0047] In some embodiments, the verification method further comprises: if it is confirmed that the virtual RANK to be accessed by the memory mode register operation instruction does not exist or the target mode register belongs to prohibited access, then generating an error prompt information.

[0048] In the fourth aspect, some embodiments of the present application provide a verification system, which comprises: a memory controller to be verified, configured to convert an operation for accessing a memory particle to each independent sub-memory channel included in the memory; a controller downward interface unit, configured to connect each independent memory sub-channel included in the memory controller to be verified to a target interface protocol environment of a corresponding memory channel; and the memory controller verification device as any of the embodiments of the first aspect; wherein the memory controller verification device is connected to the memory controller to be verified through the controller downward interface unit.

[0049] In some embodiments, the controller downward interface unit comprises a DFI interface unit. BRIEF DESCRIPTION OF DRAWINGS

[0050] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0051] Figure 1 One of the composition schematic diagrams of the system for verifying the memory controller provided by the embodiments of the present application;

[0052] Figure 2 The flow chart of the memory mode register modeling method provided by the embodiments of the present application;

[0053] Figure 3 One of the composition schematic diagrams of the device for verifying the memory controller provided by the embodiments of the present application;

[0054] Figure 4One of the component schematic diagrams of the mode register operation instruction analysis unit provided by the embodiments of the present application;

[0055] Figure 5 The second component schematic diagram of the mode register operation instruction analysis unit provided by the embodiments of the present application;

[0056] Figure 6 The system component schematic diagram between the actual DDR5 SDRAM Controller and PHY and DRAM memory provided by the embodiments of the present application;

[0057] Figure 7A And Figure 7B The device component schematic diagram of the system shown in the above for verifying the memory controller at the DFI interface level provided by the embodiments of the present application; Figure 6

[0058] Figure 8 The modeling and verification process schematic diagram provided by the embodiments of the present application. DETAILED DESCRIPTION

[0059] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

[0060] It should be noted that: similar labels and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. Meanwhile, in the description of the present application, the terms "first", "second", etc. are only used for distinguishing description, and cannot be understood as indicating or implying relative importance.

[0061] The meanings of the English abbreviations involved in some embodiments of the present application will be briefly described below.

[0062] DDR5 SDRAM (or DDR5 memory): the fifth generation of double data rate synchronous dynamic random access memory, which is the main memory of a computer system.

[0063] SDRAM Mode Registers: the mode registers of DDR5 SDRAM, which are used to configure the memory particles. There are 256 mode registers for each memory particle on the DDR5 SDRAM.

[0064] Dual Channels: the DDR5 DIMM itself changes from a single channel to a dual channel (i.e. two memory sub-channels), and the data buses on the left and right sides are independent channels. There will be two channels for each DDR5 DIMM, and the width of each channel is 40 bits.

[0065] ​DIMM: Dual Inline Memory Module, dual inline memory module.

[0066] UDIMM: Unbuffered DIMM, unbuffered dual inline memory module, whose address and control signals do not pass through a buffer and do not need to be adjusted in timing.

[0067] RDIMM: Registered DIMM, registered dual inline memory module, which adds a register on the memory bar between the CPU and the memory particles to register the address and control signals.

[0068] LRDIMM: Load Reduced DIMM, load reduced dual inline memory module, which does not use a relatively complex register but uses a simple buffer. The buffer reduces the power load on the underlying motherboard, but has little effect on energy and memory performance.

[0069] PHY: Port Physical Layer, port physical layer. PHY connects a data link layer device to a physical medium. For the storage subsystem of DDR5, it is the intermediate device connecting the DDR5 memory controller and the DDR5 SDRAM.

[0070] DFI: DDR PHY Interface, DDR PHY interface, that is, the interface between the memory controller and the PHY.

[0071] ECC: Error Checking and CorrecTIng, error checking and correction. ECC memory technology can detect and correct some bit errors, thereby improving system stability.

[0072] CS_n: Chip Select, RANK chip select signal.

[0073] PDA: Per SDRAM Addressability, single memory particle access.

[0074] UVC: Universal Verification Component, universal verification component. For UVM, it is the UVM verification component UVM Verification Component.

[0075] MPC: Multi-Purpose Command, multi-purpose command.

[0076] VrefCA: Address Line Reference Voltage Instruction.

[0077] VrefCS: chip select line reference voltage command.

[0078] ECC: short for Error Checking and Correcting, the Chinese name is "Error Checking and Correction.

[0079] MRR: Mode Register Read, mode register read.

[0080] MRW: Mode Register Write, mode register write.

[0081] The technical problems to be solved by some embodiments of the present application are described below in combination with DDR4 and DDR5.

[0082] DDR4 SDRAM memory has 8 mode registers MR0-MR7, and the operation of the mode registers is indirectly completed through MPR (Multi Purpose Register). At the same time, DDR4 SDRAM is a single-channel memory, and its processing method on the DFI protocol interface is to attribute the memory on each DIMM to the same single memory sub-channel. Therefore, it can be understood that the processing method of attributing the memory on each DIMM to the same single memory sub-channel for DDR4 cannot handle the case of attributing the memory on DDR5 SDRAM UDIMM to two independent memory channels.

[0083] DDR5 memory controller is a dual-channel controller, and DDR5 UDIMM is also divided into two memory sub-channels. In the actual DDR storage subsystem, the DDR5 memory controller and the UDIMM are connected by DDR PHY. The SDRAM grain density on the DDR5 UDIMM usually has three types of X4, X8 and X16. When the ECC function is not enabled, 8, 4 and 2 SDRAM grains are needed for each channel respectively, and when the ECC function is enabled, 2, 1 and 1 additional SDRAM grains are needed for each channel respectively, and the additional memory grains are used to store ECC data.

[0084] A DR5 SDRAM memory chip has 256 mode registers, which are used to complete the mode configuration of each memory chip or interact with the functional state of the external memory chip. The DDR5 UDIMM is a dual-channel (i.e., including two memory sub-channels), and the RANK belongs to two independent memory sub-channels. Each sub-channel of the DDR5 memory controller supports multiple RANKs, which are distributed across multiple UDIMMs and composed of SDRAM chips located in the same memory sub-channel. Therefore, each sub-memory channel of the DDR5 memory controller needs to access multiple UDIMMs, and can only access those SDRAM chips of the corresponding channel on each UDIMM, and cannot affect the SDRAM chips of the other channel.

[0085] The inventors of the present application found in research that the design of the DDR5 memory controller, which spans multiple DIMMs, specific chips, and then normalizes to the RANK of a single memory channel, makes it difficult to simulate and verify the DFI protocol layer, and the verification component based on the DFI protocol interface must simulate the design logic of the DDR5 memory channel spanning multiple DIMMs, spanning the front and back of the DIMM, and being divided into two independent sub-channels, as well as implementing shadow registers or PDA and other features.

[0086] Based on the above analysis, it is not difficult to find that the verification idea of the DDR4 SDRAM memory mode register is not suitable for the modeling of the DDR5 SDRAM memory mode register, and has obvious defects and limitations.

[0087] Please refer to Figure 1 , Figure 1 The verification system provided for some embodiments of the present application includes a memory controller to be verified 1-2, a controller downward interface unit 1-3, and a memory controller verification device 2-5.

[0088] The memory controller to be verified 1-2 is at least configured to convert operations for accessing memory chips to each independent memory controller sub-channel (the number of memory controller sub-channels is the same as the number of memory sub-channels included in the memory to be actually accessed, and one memory control sub-channel is arranged and communicated with one memory sub-channel), to finally realize access and operation of the mode register on the memory controller verification device 2-5. It should be noted that all operation types between the memory controller and the memory included in the memory chip include data transmission and state control and maintenance and other operations. The embodiments of the present application are used to verify the access and operation of the memory controller to the mode register on the memory, and it can be understood that the operation of accessing the mode register on the memory is part of the "state control and maintenance" operation.

[0089] For example, when the memory to be verified accessed by the memory controller to be verified includes multiple independent memory sub-channels, the memory controller to be verified also includes sub-channels equal in number to the memory sub-channels, so that the memory controller to be verified can access multiple RANKs of the memory through a sub-channel.

[0090] The controller downward interface unit is configured to connect each independent memory controller sub-channel included in the memory controller to be verified to a target interface protocol environment of a corresponding memory sub-channel. For example, the memory controller downward interface unit includes a DFI interface unit.

[0091] The memory controller verification device 2-5 is connected to the memory controller to be verified 1-2 through the controller downward interface unit 1-3. In some embodiments of the present application, the memory controller verification device 2-5 is at least configured to: based on the modeling of the mode register of the single memory, map to the logical channel (for example, one logical channel includes Figure 6 the first instruction decoder 2-7-1, the first mode register operation instruction parsing unit 2-8-1, the first single memory sub-channel model 2-9-1, and the mode register module 2-23) at the DFI protocol (or other controller downward interface protocol) level, and implement the verification idea and implementation method of directly accessing the mode register corresponding to the memory particle at the memory sub-channel level.

[0092] It should be noted that the verification system of some embodiments of the present application can be applied to the verification scheme of UDIMM, RDIMM, LRDIMM, etc., and can also be applied to other devices other than DDR5 SDRAM. For example, through some embodiments of the present application, a model of a memory controller to be verified and two sub-memory channels thereof can be packaged to simulate the real memory controller working scene.

[0093] First, the memory mode register modeling method provided by some embodiments of the present application is introduced below, which is used to build a memory controller verification device 2-5 as shown in Figure 1 .

[0094] As shown in Figure 2 , in some embodiments of the present application, the memory mode register modeling method includes: S101, constructing the mode register space of each memory sub-channel in the memory; and S102, creating an access tool for accessing the target memory mode register included in the mode register space. It can be understood that the memory involved in S101 is the memory to be accessed by the memory controller to be verified when it actually works, and by constructing the same mode register space as the actual memory, the access operation process of the memory controller to be verified to each mode register can be better simulated and verified.

[0095] It is to be noted that the access tool involved in S102 is configured to access the target mode register included in the mode register space constructed in S101 according to the pointer and complete at least one operation on the target mode register, the at least one operation including one or more of the following operations: a read or write operation on various fields included in the target mode register, a read or write operation on the target mode register as a whole, and a shadow register access operation.

[0096] In order to quickly access each RANK, in some embodiments of the present application, S101 exemplarily includes: based on the DFI interface, modeling the spatial relationship of the memory grain (for example, the spatial relationship includes: which memory bank, the front or back of the memory bank, which RANK, etc.), and mapping all the constructed mode register arrays corresponding to the memory grain included in the same memory sub-channel to the virtual RANK mode register array corresponding to the DFI interface. It is to be noted that this mapping relationship needs to be recorded (for example, stored by the subsequent constructed sub-channel mode register application method module), and through this mapping relationship, the target RANK located on the mode register module can be accessed through the RANK access pointer in the subsequent verification process.

[0097] In order to simulate some operations of the mode register, in some embodiments, after the access tool for accessing the target memory mode register included in the mode register space is created, the memory mode register modeling method further includes: adding a behavior model, and adding the access tool and the behavior model to the memory sub-channel model, wherein the behavior model is used to simulate the behavior of at least part of the mode register.

[0098] For example, the memory grain of the actual memory updates the temperature state in real time to the mode register MR4, and updates the low bit and high bit of the DQS oscillator count (DRAM DQS Oscillator count) to the two mode registers MR46 and MR47 respectively. MR4, MR46 and MR47 are all read-only, and therefore can only be read through the MRR instruction. Some embodiments of the present application encapsulate the behavior model when modeling, so that when the MRR operation on the registers similar to MR4, MR46 and MR47 is captured, the constructed memory mode register verification device can simulate the possible temperature or technical state of the real memory grain, and return a corresponding random number from the mode register model as the return value of the MRR.

[0099] That is, some embodiments of the present application can simulate the return of a random value by the relevant mode register through the encapsulated behavior model. Such a function for simulating the behavior state of the memory grain is also referred to as "behavior model" for short.

[0100] In some embodiments of the present application, after the access tool and the behavior model are added to the memory sub-channel model, the memory mode register modeling method further comprises: encapsulating the memory sub-channel model and a memory controller.

[0101] In some embodiments, the modeling of the spatial relationship of the memory particles comprises: creating field types of a mode register to be constructed and names of the field types; creating a mode register according to the field types, obtaining a constructed mode register; creating a plurality of the constructed mode registers according to a number of all mode registers included in a memory particle, obtaining a memory particle mode register group; creating a plurality of the memory particle mode register groups according to a total number of memory particles included in a RANK, obtaining a RANK mode register group, wherein the RANK is located on a memory actually connected to a memory controller to be verified; creating a plurality of the RANK mode register groups according to a type of each memory sub-channel included in the memory, obtaining a memory sub-channel mode register group, wherein the memory particle, the RANK and the memory sub-channel are all located on the memory, and the memory is an access device actually accessed by the memory controller to be verified.

[0102] In some embodiments of the present application, the fields respectively correspond to different bit numbers, the length of the longest field is equal to the length of a mode register, the length of the shortest field is 1, and the total number of the fields is the same as the length of the longest field.

[0103] For example, some embodiments of the present application provide a channel consistency DDR5 UDIMM SDRAM memory mode register modeling method, which comprises:

[0104] Firstly, based on the DFI interface, the spatial relationship of the UDIMM SDRAM memory particle is modeled, then the SDRAM memory belonging to the same memory channel is mapped to the RANK corresponding to the DFI interface, and the construction of the mode register space of a single memory channel is completed.

[0105] Secondly, the DDR5 SDRAM memory mode register access tool is created, the behavior model is added, and then encapsulated into the memory channel model. These access tools and behavior models fully analyze the relationship between the spatial relationship of the SDRAM memory particle and the DFI interface of the memory channel, so that the DFI environment of the memory channel can directly access each SDRAM mode register simply and directly, without further concerning the problem of the SDRAM memory particle position distribution.

[0106] Thus, the channel consistency modeling of the DDR5 UDIMM SDRAM memory mode register is realized.

[0107] It can be understood that the modeling and packaging of the DDR5 SDRAM mode register can be realized by the modeling method described above; the modeling and packaging of the memory channel of the DDR5 SDRAM mode register are realized, which facilitates reuse in a verification environment; the packaging of the memory channel model of the DDR5 SDRAM mode register and the DDR5 SDRAM controller is realized, which facilitates expansion according to the number of memory channels and expansion according to the number of memory controllers; PDA function is supported; Shadow Registers function is supported; X4, X8, X16 devices are supported; MR4, MR46, MR47 and other functions are supported; the model structure supports the expansion and implementation of RDIMM and LRDIMM.

[0108] It should be noted that the memory mode register modeling method will be further exemplarily described below in combination with a memory controller verification device that has been constructed and a development program. To avoid repetition, the implementation details of the modeling method will not be described here.

[0109] The following will be described below in combination with Figure 3 Exemplarily describe the exemplary architecture of the memory controller verification device 2-5 that has been constructed.

[0110] As Figure 3 shown, some embodiments of the application provide a memory controller verification device 2-5, which comprises a mode register module 2-23 and at least one access control module 2-6-1.

[0111] The mode register module 2-23 comprises mode registers respectively constructed for each memory particle in the memory, wherein the memory is the memory to be actually accessed by the memory controller to be verified.

[0112] It should be noted that the memory to be actually accessed by the memory controller to be verified refers to the memory that needs to be accessed by the memory controller to be verified when it actually works, that is, the memory to be accessed by the memory mode register to be verified in a non-verification environment. For example, the memory to be actually accessed by the memory controller to be verified includes five memory particles, and the mode register module 2-23 constructed by some embodiments of the application comprises mode registers respectively constructed for the five memory particles. It can be understood that the performance of the memory controller to be verified can be verified by the constructed mode register, and the memory controller to be verified is connected to the memory for actual access control after the performance meets the requirements.

[0113] The at least one access control module (such as Figure 3N access control modules, the N access control modules comprising: a first access control module 2-6-1 corresponding to a first memory sub-channel,..., and an Nth access control module 2-6-N corresponding to an Nth memory sub-channel, wherein each access control module is configured to access a target mode register included in a pointer access mode register module 2-23.

[0114] Some embodiments of the present application do not limit the specific number of target mode registers to be accessed by the access control modules. For example, when a plurality of RANKs are constructed on the mode register module (corresponding to all RANKs included in the actual memory to be accessed), in some embodiments of the present application, the target mode register is all registers on the entire RANK (as described below, these mode registers are accessed by the RANK access pointer corresponding to the virtual RANK). In some embodiments of the present application, the target mode register to be accessed by the access controller module is one register. In some embodiments of the present application, the target mode register can also be all mode registers corresponding to the sub-channel in which the access control module is located.

[0115] It should be noted that one access control module is provided corresponding to one memory sub-channel to be accessed by the memory controller to be verified, and thus the number of access control modules provided can be determined according to the number of memory controllers to be verified or the number of memory sub-channels included in one memory controller to be verified, so that the application scenario of the technical solution can be expanded. It can be understood that, in some embodiments of the present application, for the same memory sub-channel, the granularity in the virtual RANK (that is, the pointer provided in the access control module) can be set to the mode register (that is, the mode register module) of the actual constructed memory granularity in the verification process, so that the access control operation of the memory controller on each mode register can be effectively verified, and the design structure simplifies the processing process required when the verification environment accesses the mode register, and accelerates the simulation and debugging efficiency.

[0116] The exemplary structure of each access control module and the mode register module is described below.

[0117] It can be understood that each unit (including the constructed memory bank, RANK, mode register, etc.) on the mode register module is consistent with the memory structure to be actually accessed by the memory controller to be verified.

[0118] In some embodiments of the present application, the memory to be accessed by the memory controller to be verified includes N RANKs, each RANK includes M memory particles, and each memory particle includes L mode registers. The mode register module 2-23 includes N mode register instances, each mode register instance includes L mode registers for each of the M memory particles, one mode register instance corresponds to one RANK, N is an integer greater than or equal to 1, and M and L are integers greater than 1.

[0119] For example, the memory is DDR5, the DDR5 includes 8 RANKs, each RANK includes 10 memory particles SDRAM, and each memory particle corresponds to 256 mode registers. The mode register module 2-23 includes 8 mode register instances (corresponding to RANKs), and each mode register instance includes 10*256 mode registers for all memory particles.

[0120] That is, some embodiments of the present application construct mode registers for all memory particles included in the memory, and construct mode register instances for each RANK of the memory. This design structure can simplify the processing required when the verification environment accesses the mode registers.

[0121] In some embodiments of the present application, the memory to be accessed by the memory controller to be verified includes A memory banks, and one memory sub-channel includes B RANKs distributed on the A memory banks. The mode register module includes A memory banks, the mode register module for one memory sub-channel includes B RANKs, the B RANKs are located on the A memory banks, and the access control module includes B virtual RANKs, one virtual RANK corresponds to one RANK constructed on the mode register module, and each virtual RANK corresponds to a unique code. It should be noted that A and B are integers greater than or equal to 1.

[0122] For example, the memory includes two memory ranks and includes two memory sub-channels, and in one memory sub-channel, the memory includes a total of 4 RANKs located on the two memory ranks, the mode register module includes two constructed memory ranks and 4 constructed RANKs, the 4 constructed RANKs are located on the front and back of the two constructed memory ranks respectively, and the access control module includes 4 constructed virtual RANKs (the reason for being called virtual RANK is that the virtual RANK corresponds to an access pointer, and does not actually correspond to a memory space), one virtual RANK corresponds to one constructed RANK, and one constructed RANK corresponding to the virtual RANK can be accessed through the virtual RANK. For example, when verifying the to-be-verified memory controller, each virtual RANK can be accessed through the unique code provided for each virtual RANK, and ultimately the purpose of accessing one constructed RANK is achieved. For example, each virtual RANK is accessed through the code, and each virtual RANK accesses one constructed RANK on the mode register module through a RANK access pointer.

[0123] That is, the mode register module of some embodiments of the application completely replicates all RANKs in the actual memory, including the memory rank number where each RANK is distributed, whether on the front or back of the memory rank, and the like, and the access control module does not need to construct elements and information related to the memory rank, but only directly constructs virtual RANKs of all RANKs corresponding to one memory sub-channel (the virtual RANK corresponds to a RANK access pointer through which the corresponding target RANK on the mode register module can be accessed, and the virtual RANK includes a group of mode register access pointers through which a specific mode register on the mode register module can be accessed), and the virtual RANK is uniquely coded. Through this design, the access speed of each constructed RANK (i.e., each RANK on the mode register module) can be accelerated, and ultimately the verification speed can be improved. Some embodiments of the application find the target virtual RANK through the code assigned to the virtual RANK, and access the constructed RANK (i.e., each RANK on the mode register module) through the RANK access pointer corresponding to the virtual RANK, which makes the access of each RANK independent of the distribution form of the RANK on the DIMM (i.e., each memory rank on the mode register module), thereby realizing direct access to the SDRAM memory particle at the RANK level. Compared with the cumbersome operation of related technologies that must first determine the memory rank to be accessed, and then confirm whether the RANK is on the front or back of the memory rank, and the like, the embodiments of the application obviously improve the access speed of the RANK, making the verification process faster.

[0124] For example, each virtual RANK is accessed by the code assigned to the virtual RANK, and each virtual RANK accesses the corresponding target RANK on the mode register module through the RANK access pointer. Each virtual RANK includes a set of pointers, wherein the target mode register on the mode register module is accessed through the mode register access pointer included in each set of pointers. It is not difficult to understand that when the instruction from the memory controller to be verified is an operation on all mode registers on a RANK, only the RANK access pointer corresponding to the target virtual RANK (the pointer is obtained by looking up the pre-stored mapping table, which is used to store the correspondence between each virtual RANK and the constructed RANK) is needed to access the target RANK and complete the target operation on all mode registers on the target RANK. When the instruction from the memory controller to be verified is an operation on a certain mode register (i.e., the target mode register), the RANK access pointer corresponding to the target virtual RANK (the pointer is obtained by looking up the pre-stored mapping table, which is used to store the correspondence between each virtual RANK and the constructed RANK) and the mode register access pointer stored on the target virtual RANK are needed to access the target mode register and complete the target operation.

[0125] In order to refine the access granularity of each mode register of the constructed mode register module, in some embodiments of the present application, each mode register on the mode register module is further configured to include a plurality of fields of different sizes, and each field corresponds to a different name, wherein each field included in the mode register is accessed through the name of the field. That is, some embodiments of the present application define a plurality of fields for each mode register of the constructed mode register module, thereby achieving access to different fields of each mode register, refining the access granularity, and enriching the verification parameters of the memory controller to be verified. The definition process of each field will be further refined in the following program, and will not be described in detail here to avoid repetition.

[0126] To facilitate testing of arbitrary combinations of PDA ID codes for memory chips, in some embodiments of this application, the mapping relationship between the memory chip serial numbers and PDA ID codes on the mode register module can be dynamically configured. It should be noted that each memory chip on a memory module has a unique identification code. At the factory, the manufacturer assigns a unique PDA identification code (i.e., PDA ID) to each memory chip. Correspondingly, in the embodiments of this application, the mode registers established on the mode register module for each memory chip also contain this PDA identification code. Simultaneously, the memory controller can rewrite a new identification code for each memory chip using the PDA Enumerate instruction. Some embodiments of this application achieve extremely convenient testing of arbitrary combinations of PDA ID codes for memory chips by dynamically configuring the mapping between memory chip serial numbers and PDA ID codes.

[0127] To verify the memory controller's access to different memory sub-channels, in some embodiments of this application, different identification signals are used to distinguish the different memory sub-channels included in the memory.

[0128] In some embodiments of this application, the access control module includes: an instruction decoder, a mode register operation instruction parsing unit, and a single-memory sub-channel model (for example, the single-memory sub-channel model further includes: multiple virtual RANKs and a sub-channel mode register application method module).

[0129] For example, such as Figure 3 As shown, the first access control module 2-6-1, corresponding to the first memory sub-channel, includes: a first instruction decoder 2-7-1, a first mode register operation instruction parsing unit 2-8-1, and a first single memory sub-channel model 2-9-1. The Nth access control module 2-6-N includes: an Nth instruction decoder 2-7-N, an Nth mode register operation instruction parsing unit 2-8-N, and an Nth single memory sub-channel model 2-9-N. It should be noted that the structure of the access control modules for each memory sub-channel is the same; the following explanation uses only the first access control module of the first memory sub-channel as an example to illustrate the structure of the access control module.

[0130] The first instruction decoder 2-7-1 is configured at least to parse interface signals to obtain memory chip operation instructions according to an interface protocol, wherein the interface protocol is the protocol used by the downward interface unit of the memory controller to be verified. For example, in some embodiments, the downward interface unit is a DFI interface, and the corresponding protocol is the DFI interface protocol.

[0131] The first mode register operation instruction parsing unit 2-8-1 is configured to: parse the memory particle operation instructions and obtain the parsing results; and filter the instructions based on the parsing results to obtain target operation instructions related to the mode register operation. For example, when the memory is UDIMM memory, these target operation instructions include: MPC, MRW, MRR, VREFCA, etc. It is understood that in these embodiments, the first mode register operation instruction parsing unit 2-8-1 includes all command processing units that need to interact with the mode register, such as the MPC command processing unit, MRW command processing unit, MRR command processing unit, VrefCA / VrefCS command processing unit, and a PDA monitoring module that monitors whether the PDA is in a PDA state.

[0132] The first single-memory subchannel model 2-9-1 includes at least multiple virtual RANKs ( Figure 3 Not shown, please refer to Figure 7B Virtual RANK0 2-11-1, Virtual RANK1 2-12-1, etc.) and sub-channel mode register application method module ( Figure 3 Not shown, please refer to Figure 7B The channel Register Utilities 2-24-1), and the virtual RANK is configured to access the target mode register located on the mode register module via the RAKN access pointer or the mode register access pointer located on each virtual RANK, so that the memory controller to be verified can perform the target operation on the target mode register.

[0133] In some embodiments, the sub-channel mode register application method module includes at least: implementation functions corresponding to all operation instructions of the mode register, and a logical conversion mapping table from memory sub-channel to target memory particle, wherein the distribution position of the target mode register on the mode register module is obtained by looking up the logical conversion mapping table, and the target operation is completed by the implementation function corresponding to the target operation.

[0134] For example, the sub-channel mode register application method module is configured to: acquire a target virtual RANK corresponding to the target operation, and access a target RANK located on the mode register module according to a RANK access pointer corresponding to the target virtual RANK, to complete the target operation on all mode registers on the target RANK; or acquire a target virtual RANK and a target mode register corresponding to the target operation, access a target RANK through a RANK access pointer corresponding to the target virtual RANK, and access the target mode register on the target RANK through a mode register access pointer included in the target virtual RANK, to complete the target operation on the target mode register.

[0135] To enrich the verification content of the memory controller to be verified, in some embodiments of the present application, the memory controller verification apparatus further comprises a set of shadow registers (not shown in the figure), wherein if it is confirmed by the mode register operation instruction parsing unit that a PDA state exists, the sub-channel mode register application method module is further configured to implement a target operation corresponding to the shadow register through the shadow register and the target mode register. It should be noted that the mode register operation instruction parsing unit confirms that at least part of the memory particles contained in a certain RANK on the memory bank are in a PDA state.

[0136] For example, the mode register operation instruction parsing unit determines whether the current is in the PDA state according to the decoded instruction. The DDR5 part of the memory mode register is special, and can only be written through the VrefCA, VrefCS, MPC Set RTT_CA / CS / CK instructions. When these instructions attempt to write these mode registers, the data is actually first written into a temporary register. Without issuing the MPC plus 8'b0001_1111 operation word, the values of these mode registers are not immediately updated, and if a read operation is performed, the previous values are returned; only when the MPC plus 8'b0001_1111 operation word is issued, the memory particles in the temporary register are written into the corresponding mode register one by one, and after the read operation, the real latest written value is returned. These temporary registers, also known as shadow registers, have the same access method as ordinary mode registers. For example, in some embodiments of the present application, the shadow register is constructed with the same specifications as the mode register module 2-23, so as to realize the assignment operation from the shadow register to the ordinary register; at the same time, in some embodiments of the present application, the sub-channel mode register application method module encapsulates the operation from the shadow register to the mode register, so that the assignment and operation of the target register can be completed by simply calling the related method function during verification, without considering the details of the shadow register to the target register, thereby greatly simplifying the complexity of the verification. It should be noted that the part of the shadow register is not marked in the drawings of the present application, but this does not affect the understanding of the technical solution by those skilled in the art.

[0137] In order to avoid the memory controller to be verified accessing the mode register which is prohibited from being accessed, in some embodiments of the present application, the sub-channel mode register application method module is further configured to generate an error prompt information when it is confirmed that the target mode register belongs to the mode register which is prohibited from being accessed.

[0138] It can be understood that the sub-channel mode register application method module belongs to an access tool, which encapsulates all operations related to the mode register, including mode register word or field level read and write operations, register level read and write operations, and shadow register access operations. The sub-channel mode register application method module also encapsulates a mapping table, from which the specific location of the target mode register on the mode register module can be obtained according to the target operation selected by the mode register operation instruction parsing unit, and the target mode register is accessed through the RANK access pointer and the mode register access frame, and the target operation on the target mode register is implemented. For example, the target operation is MRR, and the target operation is for the operation of all mode registers on a RANK on the back of the first memory bank. The sub-channel mode register can obtain the specific location of the target operation by searching the mapping table, obtain the virtual RANK to which the target operation is directed, and access the target RANK according to the RANK access pointer corresponding to the virtual RANK and complete the mode register read operation.

[0139] That is, some embodiments of the present application can enable each logical channel to independently access the memory grain by setting the instruction decoder, the mode register operation instruction parsing unit and the single memory sub-channel model for each memory sub-channel.

[0140] It should be noted that the above only exemplarily describes the first instruction decoder, the first mode register operation instruction parsing unit and the first single memory sub-channel model, and the functions of the instruction decoder, the mode register operation instruction parsing unit and the single memory sub-channel model included in other access control modules are similar to those of the corresponding units. To avoid repetition, the other modules are not described in detail.

[0141] The structure of the mode register operation instruction parsing unit will be exemplarily described below in combination with a specific memory grain instruction type.

[0142] In some embodiments of the present application, the interface protocol is the DFI protocol, and the memory is UDIMM. The mode register operation instruction parsing unit is further configured to: screen the MPC instruction from the memory grain operation instruction, and obtain an MPC instruction parsing result; if it is confirmed to be in a PDA operation state according to the MPC instruction parsing result, obtain the target mode register according to the PDA operation state.

[0143] That is, some embodiments of the present application can also complete various mode register operation instructions in the PDA operation state by setting the mode register operation instruction parsing unit, which more comprehensively verifies the performance of the memory controller.

[0144] In order to screen as many mode register related operation instructions as possible, and to comprehensively verify the access process of the memory controller to the mode register, in some embodiments of the present application, the mode register operation instruction parsing unit comprises: a plurality of target type instruction screening units, wherein each of the plurality of target type instruction screening units is configured to screen any target type of mode register operation instruction from the memory particle operation instruction. Some embodiments of the present application can comprehensively verify various operations of the memory controller to the mode register by setting a plurality of instruction screening units.

[0145] Specifically, in some embodiments of the present application, as shown in Figure 4 if the memory is a UDIMM, the plurality of target instruction screening units comprises: an MPC command processing unit, the input end of which is connected with the output end of the instruction decoder (for receiving input DDR5 commands), and which is configured to obtain MPC instructions from the output results of the instruction decoder, and parse the MPC instructions to obtain MPC instruction parsing results; an MRW command processing unit, which is connected with the output end of the MPC command processing unit, and which is configured to detect MRW instructions from the input signals, and parse the MRW instructions to obtain MRW instruction parsing results; an MRR command processing unit, which is connected with the output end of the MPC command processing unit, and which is configured to detect MRR instructions from the input signals, and parse the MRR instructions to obtain MRR instruction parsing results; and a VrefcA / VrefcS command processing unit, which is connected with the output end of the MPC command processing unit, and which is configured to detect VrefcA and / or VrefcS instructions from the input signals, and parse the VrefcA and / or VrefcS instructions to obtain VrefcA and / or VrefcS instruction parsing results.

[0146] Some embodiments of the present application can complete the verification of various commands including MPC commands for UDIMM type memory.

[0147] In some embodiments of the present application, as shown in Figure 5 the interface protocol is a DFI protocol, and the mode register operation instruction parsing unit further comprises: a PDA monitoring module (i.e. PDAmonitor of Figure 4 ), which is configured to confirm that the memory (or all memory particles contained in a certain RANK on the memory bank) is in a PDA operation state; wherein the output end of the MPC command processing unit (i.e. MPC of Figure 5 ) is connected with the input end of the PDA monitoring module, wherein the PDA monitoring module confirms that it is in the PDA operation state through the MPC instruction parsing result; the MRW command processing unit (i.e. MRW of Figure 5The input terminal of the MRW (MRW) is connected to the output terminal of the PDA monitoring module; the MRR command processing unit (i.e., Figure 5 The input terminal of the MRR is connected to the output terminal of the PDA monitoring module; the VrefcA / VrefcS command processing unit (i.e., Figure 5 The input terminals of the VrefcA and VrefcS are connected to the output terminals of the PDA monitoring module. It should be noted that these connections can be bus-based.

[0148] Some embodiments of this application have a separately configured functional module, namely the PDA monitoring module, which confirms that the PDA is in operation and can perform more complete performance verification of the memory controller to be verified.

[0149] The following is combined Figure 6 and Figure 7A and Figure 7B The structure of a memory controller verification system (including a device for memory controller verification) provided in some embodiments of this application is illustrated by way of example. Figure 7A and Figure 7B This is presented as an example where the memory controller has two memory sub-channels (i.e., Figure 7A The two outputs are connected to the first connection 2-5-1 and the second connection 2-5-2 respectively. Figure 7B Communicating with certain parts, specifically Figure 7A The first DFI channel 1-3-1 output is connected to the first connection 2-5-1. Figure 7B Corresponding memory sub-channel communication, Figure 7A The output of the second DFI channel 1-3-2 is connected to the second connection 2-5-2. Figure 7B (Another memory sub-channel communication), therefore, a model of a memory controller to be verified, and its two sub-memory channels, can be encapsulated to simulate the actual working scenario of a memory controller (i.e., simulation). Figure 6 (Work scenario).

[0150] Figure 6 This example provides a system configuration for a memory controller (i.e., a DDR5 SDRAM controller), a memory physical interface PHY, and DRAM memory in practice. Figure 6 The difference is, Figure 7A and Figure 7B The apparatus for verifying a memory controller provided by some embodiments of this application and Figure 6 The memory controller is connected to form a verification memory controller system.

[0151] exist Figure 6In this configuration, each DDR5 memory controller has two memory sub-channels, each supporting four ranks, and the memory accessed by the memory controller is of x8 density memory chip type. It should be noted that when using x4 density memory chip type, Figure 6 The number of memory chips on the first memory module DIMM0 and the second memory module DIMM1 should be doubled. When using X16 density chips, only 8 chips are needed on each memory module DIMM.

[0152] System bus 1-1 (i.e. Figure 6 The System Bus is used to connect the processor (e.g., CPU) and memory controller 1-2, through which instructions and data can be transferred between the processor and the memory controller.

[0153] Memory controllers 1-2 (i.e. Figure 6 The DDR5 SDRAM Controller 0 is configured to generate operation signals for each memory controller sub-channel, and the memory controller has two independent memory controller sub-channels, namely the first memory controller sub-channel 1-2-1 (i.e., Figure 6 The memory controller sub-channels 1-2-2 (i.e., Sub-Channel B) are used to convert operation signals into corresponding interface signals. This is because the memory to be accessed by the memory controller is DDR5, and DDR5 is dual-channel.

[0154] It is easy to understand that, on the one hand, memory controllers 1-2 need to convert the instructions and data of the system bus into instructions and data for the relevant memory chips in the memory sub-channel; on the other hand, the memory controllers also return the data and status of the memory chips in the memory sub-channel to the system bus.

[0155] Memory physical interfaces 1-4 (i.e.) Figure 6 The physical layer (PHY0) of the port is the physical medium of the data link layer. This memory physical interface is used to connect memory controllers 1-2 and the first memory module 1-11 (i.e., Figure 6 DIMM0), and connect memory controllers 1-2 and the second memory module 1-17 (i.e. Figure 6 (DIMM1). The memory physical interface 1-4 is also divided into two channels: the first memory physical interface sub-channel 1-4-1 and the second memory physical interface sub-channel 1-4-2.

[0156] The first memory controller sub-channel 1-2-1 handles instruction transmission, data access, and status maintenance between the memory controller and the first memory sub-channel. The first memory controller sub-channel connects to the first DFI channel 1-3-1 (i.e....).Figure 6 The first memory physical interface subchannel 1-4-1 is connected with the first memory controller subchannel 1-2-1 through a first DFI channel 1-3-1 (i.e.

[0157] The second memory controller subchannel 1-2-2 accomplishes command sending, data access, and state maintenance between the memory controller and the second memory subchannel. The second memory controller subchannel is connected with the second memory physical interface subchannel 1-4-2 through a second DFI channel 1-3-2 (i.e. Figure 6 The first memory physical interface subchannel 1-4-1 is connected with the first memory controller subchannel 1-2-1 through a first DFI channel 1-3-1 (i.e.

[0158] The first memory bank 1-11 and the second memory bank 1-17 are both memory units DIMM, commonly known as memory banks, which are accessed by the memory controller. DIMM, also known as dual in-line memory module, is a substrate on which multiple DRAM memory particles are installed for storing data. Taking the example of DDR5 supporting 4 RANKs per memory subchannel, each DIMM has two RANKs, so the memory controller 1-2 needs two DIMMs in total, such as the first memory bank 1-11 and the second memory bank 1-17.

[0159] As shown in FIG. 1, the first memory bank DIMM0 has a first memory bank front side 1-8 (i.e. Figure 6 The first memory bank front side 1-8 contains a first memory particle 1-6-1 to a tenth memory particle 1-6-2 (only two memory particles are marked in the figure), and there are totally 10 memory particles on the first memory bank front side, which are arranged in two groups of 5 on the left and right sides, respectively belonging to the first memory bank front side first memory subchannel 1-7-1 and the first memory bank front side second memory subchannel 1-7-2. The first memory bank back side 1-10 also has totally 10 memory particles, which are arranged in two groups of 5 on the left and right sides, respectively belonging to the first memory bank back side first subchannel 1-9-1 and the first memory bank back side second subchannel 1-9-2. Figure 6 Figure 6 Figure 5

[0160] ​​​The second memory DIMM DIMM1 has a second memory DIMM front side 1-14 and a second memory DIMM back side 1-16, wherein the second memory DIMM front side 1-14 contains ten memory particles from the first memory particle 1-12-1 to the tenth memory particle 1-12-2, which are divided into two groups of five on the left and right sides of the second memory DIMM front side, and belong to the second memory DIMM front side first sub-channel 1-13-1 and the second memory DIMM front side second sub-channel 1-13-2 respectively. The second memory DIMM back side 1-16 also has a total of ten memory particles, which are divided into two groups of five on the left and right sides of the second memory DIMM back side, and belong to the second memory DIMM back side first sub-channel 1-15-1 and the second memory DIMM back side second sub-channel 1-15-2 respectively.

[0161] The first memory physical interface sub-channel 1-4-1 completes access to four RANKs (including Figure 6 RANK0, RANK1, RANK2 and RANK3) on the left half part through the first DDR5 SDRAM interface 1-5-1, which span the first memory DIMM DIMM0 and the second memory DIMM DIMM1 and belong to the same memory sub-channel respectively.

[0162] The first memory DIMM front side first memory sub-channel 1-7-1 corresponds to the memory particles SDRAM0 / 1 / 2 / 3 / 8 of the first memory DIMM DIMM0 to form RANK0.

[0163] The first memory DIMM back side first memory sub-channel 1-9-1 corresponds to the memory particles SDRAM7 / 6 / 5 / 4 / 9 of the first memory DIMM DIMM0 to form RANK1.

[0164] The second memory DIMM front side first memory sub-channel 1-13-1 corresponds to the memory particles SDRAM0 / 1 / 2 / 3 / 8 of the second memory DIMM DIMM1 to form RANK2.

[0165] The second memory DIMM back side first memory sub-channel 1-15-1 corresponds to the memory particles SDRAM7 / 6 / 5 / 4 / 9 of the second memory DIMM DIMM1 to form RANK3.

[0166] It should be noted that the above-mentioned first memory DIMM front side first memory sub-channel 1-7-1, first memory DIMM back side first memory sub-channel 1-9-1, second memory DIMM front side first memory sub-channel 1-13-1 and second memory DIMM back side first memory sub-channel 1-15-1 all belong to the first memory sub-channel (or referred to as Sub-Channel A).

[0167] Similarly, the second memory physical interface sub-channel 1-4-2 completes access to four RANKs (includingFigure 6 RANK0, RANK1, RANK2 and RANK3 of the right half part, the four RANKs span the first memory bank DIMM0 and the second memory bank DIMM1 and all belong to the same memory sub-channel, which are respectively:

[0168] The first memory bank back side second memory sub-channel 1-7-2 corresponds to the memory particles SDRAM 9 / 4 / 5 / 6 / 7 of the first memory bank DIMM0, constituting RANK0.

[0169] The first memory bank back side second memory sub-channel 1-9-2 corresponds to the memory particles SDRAM 8 / 3 / 2 / 1 / 0 of the first memory bank DIMM0, constituting RANK1.

[0170] The second memory bank front side second memory sub-channel 1-13-2 corresponds to the memory particles SDRAM 9 / 4 / 5 / 6 / 7 of the second memory bank DIMM1, constituting RANK2.

[0171] The second memory bank back side second memory sub-channel 1-15-2 corresponds to the memory particles SDRAM 8 / 3 / 2 / 1 / 0 of the second memory bank DIMM1, constituting RANK3.

[0172] It should be noted that the above-mentioned first memory bank back side second memory sub-channel 1-7-2, first memory bank back side second memory sub-channel 1-9-2, second memory bank front side second memory sub-channel 1-13-2 and second memory bank back side second memory sub-channel 1-15-2 all belong to the second memory sub-channel (or referred to as Sub-Channel B).

[0173] Therefore, it can be seen that, Figure 6 The memory particles accessed by each memory sub-channel of the memory controller span multiple DIMM banks (DIMM0 and DIMM1), span the front and back sides (Back Side and Front Side) of the DIMM bank, and span the left and right sides (left side and right side) of the DIMM bank. It can be understood that each memory sub-channel must also implement access to a single memory particle (i.e. Figure 6 Each SDRAM unit of the memory controller) such as shadow registers, PDA and other characteristics. Therefore, the memory controller needs complex logic design to enable the memory sub-channel to access the memory particle. In order to verify whether the logic for accessing the memory particle of the memory control design is accurate, the memory particle access logic of the memory controller to be verified needs to be verified, so that the mode register access logic of the designed memory controller is accurate, which is also a technical problem to be solved by some embodiments of the present application.

[0174] When the DFI interface layer is accessed from the memory controller layer, Figure 7AWhen the memory controller is verified by the dfi_controller0_channel_a or dfi_controller0_channel_b, the verification device needs to process the mapping relationship between the memory grain and the memory channel at any place where access to the memory grain mode register is required, thereby complicating the verification. Therefore, an innovative solution is needed to enable the device for verifying the memory controller to simplify the operation on the mode register and achieve consistency between the memory channel and the memory grain.

[0175] The following describes the structure of the device for verifying the memory controller provided by some embodiments of the present application in conjunction with Figure 7B and Figure 7A The device for verifying the memory controller provided by some embodiments of the present application is used to verify the performance of the memory controller working in Figure 6 Unlike Figure 7B , the memory stick and the mode register on the memory stick are all generated by simulation. Through Figure 7B the model can verify the access performance of the memory controller to be verified to the mode register corresponding to the memory grain. That is, Figure 6 the actual physical connection diagram described in Figure 7B , Figure 7B the modeling form of the memory stick in the verification environment, Figure 7A the mode register in is the mode register of the real memory stick simulated by the testbench through program code.

[0176] Figure 7B As shown in Figure 7B , the diagram exemplarily provides the controller0_UVC (i.e., the memory controller verification device 2-5) developed based on the DFI test environment DFI Testbench environment. Figure 7B The memory controller verification device includes a single memory grain mode register group 2-16-1 corresponding to a single memory grain (the mode register group includes 256 mode registers), a single RANK mode register group 2-17-1 (i.e., a single RANK model) constructed corresponding to the RANK on the memory, a mode register module 2-23 (i.e., the Model of SDRAM registers for dual DIMM in FIG. 7, the module includes a multi-DIMM physical model), a single memory sub-channel model of a single memory sub-channel (for example, a first single memory sub-channel model 2-9-1 corresponding to the first memory sub-channel is established, the model corresponds to Figure 7B the Virtual Logical Model of Sub-Channel a), a mapping algorithm between the multi-DIMM physical model of the mode register and the memory sub-channel (i.e., Figure 7AThe DFI interface controls the mode register (including MRW, MRR, VrefCA, VrefCS or MPC instructions, Shadow registers function, PDA function, etc.) according to the algorithm of the four thick solid lines with bidirectional arrows on the left and right sides.

[0177] Please refer to Figure 7B and Figure 7A , the system for verifying the memory controller of some embodiments of the present application includes:

[0178] a system bus 1-1 (i.e., the System Bus of Figure 7A ) and a memory controller 1-2 (i.e., the DDR5 SDRAM Controller 0 of Figure 7A ) to be verified. It should be noted that, in order to avoid repeated description of the same contents of Figure 7B and Figure 6 and Figure 7B , the following will focus on the exemplary structure of the device 2-5 for verifying the memory controller.

[0179] The DFI top-level verification environment 2-4 (i.e., the DFI Testbench environment of Figure 7B ) includes a verification memory controller environment or a device 2-5 for verifying the memory controller (i.e., the Controller0_UVC of Figure 7B ), which is used to simulate the behavior of the real memory physical interface PHY and the memory bank, so that the verification work can be independent of the actual memory physical PHY and the actual memory bank model.

[0180] The device 2-5 for verifying the memory controller includes: a verification environment of a first memory sub-channel 2-6-1 (i.e., an access control module corresponding to one memory sub-channel), a verification environment of a second memory sub-channel 2-6-2 (i.e., another access control module corresponding to another memory sub-channel), and a mode register module 2-23 (which is used to build a mode register model of all DIMM SDRAMs on the memory to be accessed by the memory controller to be verified). It should be noted that the structures of the access control modules are the same.

[0181] The verification environment 2-6-1 of the first memory sub-channel (corresponding to Figure 7BThe `dfi_env_channel_a` parameter is used to simulate the responses of the memory physical interface PHY and memory module DIMM on the first memory subchannel (or memory subchannel A). The verification environment 2-6-1 for this first memory subchannel includes a first DFI instruction decoder 2-7-1 (as a specific example of an instruction decoder), an accessor 2-8-1 for the first memory channel model (as a specific example of a mode register operation instruction parsing unit), and a first single memory subchannel model 2-9-1 (including multiple virtual RANKs and a subchannel mode register application method module). It should be noted that each single memory subchannel model is used to implement the DFI interface's control method for the mode register.

[0182] For example, when the memory controller accesses the mode register through a memory subchannel, the memory controller verification device first assigns the operation of that memory subchannel to the virtual RANK of the corresponding memory subchannel; then through... Figure 7B The Subchannel Mode Register Application Method Module 2-24-1, Channel Register Utilities, implements the mapping and access to the actual memory particle mode registers. Module 2-24-1 encapsulates all operation instructions for the mode registers and the logical conversion between sub-memory channels and specific memory particles. This allows the Testbench to simply call the relevant function calls, avoiding frequent conversions between memory channels and specific memory modules, front / back, and left / right sub-channel spatial relationships.

[0183] Verification environment 2-6-2 for the second memory sub-channel (corresponding to Figure 7B The dfi_env_channel_b) is used to simulate the response of the memory physical interface PHY and memory module DIMM on the second memory subchannel. The verification environment 2-6-2 of the second memory subchannel includes the second DFI instruction decoder 2-7-2 (as a specific example of an instruction decoder), the accessor of the second memory channel model 2-8-2 (as a specific example of a mode register operation instruction parsing unit), and the second single memory subchannel model 2-9-2 (including multiple virtual RANKs and subchannel mode register application modules).

[0184] First DFI instruction decoder 2-7-1 (corresponding to...) Figure 7BThe first DFI command decoder 2-7-1 (Decode DDR5 SDRAM Command) is configured to decode the signals of the DFI interface to obtain the operation command of the memory controller to be verified on the memory particle DRAM, the input of the first DFI command decoder 2-7-1 includes the chip select signal CS_n and the address CA[13:0] in the DFI interface, and the output is the operation command of the DDR5 obtained after decoding (for example, the first command decoder obtains the current operation command by looking up the operation command mapping table according to the voltage characteristics of the input multi-bit signal). For example, the operation command includes an active command, an RFU command, a model register write command (MRW), a model register read command (MRR), an MPC command, a VerfCA command, a VerfCS command, a read command, a write command, and the like. It can be understood that some of the operation commands are operations on the model register (for example, the model register write command MRW, the model register read command MRR, and the MPC command), and the others are not operations on the model register (for example, the read command, the write command, and the like). Therefore, the embodiment of the present application only needs to focus on the operation command related to the model register in order to better verify the access or operation of the memory controller to be verified on the model register.

[0185] It should be noted that the DFI interface here is the DFI5.0 or DFI5.1 of the DDR5, and the signals thereof include command interface signals, write data interface signals, read data interface signals, update interface signals, and status interface signals.

[0186] The second DFI command decoder 2-7-2 has the same function as the first DFI command decoder 2-7-1, and therefore the function and structure of the second DFI command decoder 2-7-2 can be referred to the foregoing description of the first DFI command decoder 2-7-1. To avoid repetition, no more details will be given here.

[0187] The first memory sub-channel model access 2-8-1 (corresponding to the first memory sub-channel model 2-8) is configured to access the first memory sub-channel model 2-8, and the second memory sub-channel model access 2-8-2 (corresponding to the second memory sub-channel model 2-9) is configured to access the second memory sub-channel model 2-9. The first memory sub-channel model access 2-8-1 and the second memory sub-channel model access 2-8-2 can be configured to access the memory sub-channel model through the DFI interface, and the specific access method can be referred to the foregoing description of the DFI interface. Figure 7BThe Proces Command to SDRAM Model Register) is used to monitor the operation command outputted by the DFI command decoder connected thereto, and if the accessor monitors the operation command related to the operation of the mode register (for example, the operation command related to the functions of PDA, MRR, MRW, MPC, VrefCA, VrefCS, ShadowRegister, etc.), the method provided by the sub-channel mode register application module (i.e., the method provided by the Channel Register Utilities module) in the memory channel register model is immediately invoked to match the mode register related operation command to the corresponding target mode register. It should be noted that the method provided by the sub-channel mode register application method module Channel Register Utilities parses which memory bank in DIMM0 / 1, which side in the front side and back side, which side in the left side and right side (which memory sub-channel), and which memory particle in a single RANK, where the current operation should occur, so that the Testbench only needs to know the currently accessed RANK, greatly simplifying the complexity of the testbench.

[0188] It should be noted that the input of the accessor 2-8-1 of the first memory channel model is all operation commands outputted by the corresponding DFI command decoder, and the output is all target operation commands related to the operation of the mode register screened out. For example, the target operation commands include MPC commands, MRW commands, etc.

[0189] It can be understood that the accessor 2-8-2 of the second memory channel model is similar in structure and function to the accessor 2-8-1 of the first memory channel model, and will not be described in detail here to avoid repetition.

[0190] The first single memory sub-channel model 2-9-1 (i.e., Figure 7B The virtual Logical Model of Sub-Channel a) of the first memory sub-channel points to the virtual memory mode register channel model of the first memory sub-channel, which implements a data structure that declares references to other data types, completes the reference to the corresponding data entity (i.e., each mode register constructed on the mode register module, or each RANK), saves memory consumption, and improves simulation speed. These data structure references, including single particle register model references (for example, the single particle register model reference can access the single particle register model of the corresponding memory particle), the RANK model reference can access the RANK model of the corresponding RANK, and the mode register model reference can access the mode register model of the corresponding mode register, etc. Figure 7BEach of the memory granules shown includes any one of the 256 mode registers MR[0:255] that it contains, but can also include other types of data structure references (e.g., all mode registers on any one RANK within the corresponding memory subchannel can be accessed). The virtual memory register channel model for the first memory subchannel declares the mode register references for all of the memory granules that the channel contains, while correspondingly grouping onto four virtual RANKs, respectively, as follows:

[0191] The first virtual logical module 2-11-1 accessible to the first memory subchannel includes SDRAM 0 / 1 / 2 / 3 / 8, which constitutes virtual RANK 0 for the corresponding subchannel of the first single memory subchannel model 2-9-1.

[0192] The second virtual logical module 2-12-1 accessible to the first memory subchannel includes SDRAM 7 / 6 / 5 / 4 / 9, which constitutes virtual RANK 1 for the corresponding subchannel of the first single memory subchannel model 2-9-1.

[0193] The third virtual logical module 2-14-1 accessible to the first memory subchannel includes SDRAM 0 / 1 / 2 / 3 / 8, which constitutes virtual RANK 2 for the corresponding subchannel of the first single memory subchannel model 2-9-1.

[0194] The third virtual logical module 2-15-1 accessible to the first memory subchannel includes SDRAM 7 / 6 / 5 / 4 / 9, which constitutes virtual RANK 3 for the corresponding subchannel of the first single memory subchannel model 2-9-1.

[0195] The second single memory channel model 2-9-2 points to the virtual memory mode register channel model for the second memory subchannel. Correspondingly, the mode register references declared thereby correspond to the following four virtual RANKs, respectively, as follows:

[0196] The first virtual logical module 2-11-2 accessible to the second memory subchannel includes SDRAM 0 / 1 / 2 / 3 / 8, which constitutes virtual RANK 0 for the corresponding subchannel of the second single memory subchannel model 2-9-2.

[0197] The second virtual logical module 2-12-2 accessible to the second memory subchannel includes SDRAM 7 / 6 / 5 / 4 / 9, which constitutes virtual RANK 1 for the corresponding subchannel of the second single memory subchannel model 2-9-2.

[0198] The third virtual logical module 2-14-2 accessible to the second memory subchannel includes SDRAM 0 / 1 / 2 / 3 / 8, which constitutes virtual RANK 2 for the corresponding subchannel of the second single memory channel model 2-9-2.

[0199] The fourth virtual logic module 2-15-2 accessible by the second memory subchannel includes SDRAM 7 / 6 / 5 / 4 / 9, which constitutes the virtual RANK 3 of the corresponding subchannel of the second single memory channel model 2-9-2.

[0200] The first subchannel mode register application module 2-24-1 (corresponding to Figure 7B The Channel Register Utilities) is used to implement the access method of the mode register of the first single memory subchannel model 2-9-1, and is used to parse the memory subchannel and the target RANK to which the current mode register operation instruction of the memory controller to be verified is directed, and access a single mode register or multiple mode registers (for example, all mode registers located on the same RANK) on the mode register module 2-23 according to the parsing result and perform related operations on the mode register. It can be understood that the operation here is the operation instruction output by the accessor 2-8-1 of the first memory channel model.

[0201] The second subchannel register application module 2-24-2 is similar in structure and function to the first subchannel register application module 2-24-1, and to avoid repetition, it will not be described in detail.

[0202] The mode register module 2-23 (corresponding to Figure 7B The Model of SDRAM register for dual DIMMs) includes mode register modeling instances of all DRAM memory particles (that is, Figure 6 M[0:255] marked on each small block corresponding to SDRAMi, i takes a value from 0 to 9), and the mode register module builds all mode register models included on all DIMMs and all RANKs to be accessed by the memory controller 1-2 to be verified. That is, Figure 6 All mode registers including all memory particles on the first memory DIMM0 and the second memory DIMM1 built by the mode register module 2-23.

[0203] The following describes the correspondence between the four RANKs built for the first memory subchannel and the second memory subchannel and Figure 7B the actual RANKs distributed on the actual memory DIMM, and the correspondence is as follows:

[0204] Figure 6 The RANK0 2-17-1 on the first memory subchannel built corresponds to Figure 6 the RANK0 of the FrontSide 1-8 of the first memory DIMM0, and specifically corresponds to Figure 7BThe first memory sub-channel RANK 1 1-9-1 on the first memory bank includes SDRAM 7 / 6 / 5 / 4 / 9.

[0205] Figure 6 The first memory sub-channel RANK 2 2-20-1 corresponds to Figure 6 The first memory sub-channel RANK 2 2-20-1 corresponds to Figure 7B The first memory sub-channel RANK 1 1-9-1 on the first memory bank includes SDRAM 7 / 6 / 5 / 4 / 9.

[0206] Figure 6 The first memory sub-channel RANK 2 2-20-1 corresponds to Figure 6 The first memory sub-channel RANK 2 2-20-1 corresponds to Figure 6 The first memory sub-channel RANK 1 1-9-1 on the first memory bank includes SDRAM 7 / 6 / 5 / 4 / 9.

[0207] By analogy, it can be understood that Figure 7B Each RANK and each memory particle of the actual memory corresponds to a mode register, which is found in the mode register module 2-23. Figure 7B That is, the mode register module 2-23 simulates the mode registers of all RANKs and memory particles on the actual memory. Figure 7B That is, the mode register module 2-23 simulates the mode registers of all RANKs and memory particles on the actual memory.

[0208] The following is an example of a program that illustrates how to construct the device of the verification memory controller of some embodiments of the present application as shown in Figure 5 The following is an example of a program that illustrates how to construct the device of the verification memory controller of some embodiments of the present application as shown in

[0209] 3.1 Create a lightweight mode register word type (i.e., field type simple_reg_field).

[0210] The memory particle size of DDR5 SDRAM is large, and X8 type with ECC function requires 5 memory particles per RANK, and each memory sub-channel supports 4 RANKs, so a total of 20 memory particles are required, and two memory sub-channels of a single memory controller require a total of 40 memory particles, as shown in Figure 8X4 type with ECC function needs 10 memory particles per RANK, each memory channel supports 4 RANKs, so a total of 40 memory particles are needed, and two memory sub-channels of a single memory control need a total of 80 memory particles. The X16 type particle does not enable ECC, each memory channel supports 4 RANKs, a total of 8 memory particles are needed, and two sub-channels of a single memory control need a total of 16 memory particles.

[0211] DDR5 SDRAM has 256 8-bits mode registers per memory particle, when modeling, X8 type needs a total of 40x256 = 10240 mode registers; X4 type needs 80x256 = 20480 mode registers; X16 type needs 16x256 = 4096 mode registers. Each mode register can have multiple fields, and the read-write attributes, initial values, response modes, etc. of the fields are different from each other.

[0212] In order to reduce the memory consumption of modeling and speed up the simulation, some embodiments of the present application propose a fast register field type to reuse and construct the mode register type. Considering that this is based on the verification application requirements of the DFI interface, and the common read-write access type of the mode register of the DDR5 SDRAM memory particle, the field type of some embodiments of the present application includes methods for each field: read, write, read-write attribute, boundary check, register and field two-level synchronization, name setting, etc. Compared with the built-in method of UVM, it is more simple and efficient. It should be noted that these fields are declared and defined according to the description of the mode register in the DDR5 protocol. Some embodiments of the present application define a unique name for each field, so that the corresponding field can be accessed according to the field name during verification. Setting different fields can facilitate accurate access to the corresponding fields, improve efficiency, and precise control. The two-level synchronization refers to the synchronization and refresh between the implementation of the field and the entire register. For example, after rewriting a certain field of the mode register, the value of the entire mode register is also immediately synchronized and updated; and rewriting the value of the entire mode register, then the value of each field in the register is also immediately synchronized and updated.

[0213] The specific method and schematic code are as follows:

[0214]

[0215] (1). Declare the basic attributes of the field type field, including:

[0216] The name of the field field_name, the name of the field field_name and the field value field_val, the read-write attribute of the field field, the starting address of the field field_lsb and the ending address field_msb, the default value of the field field_val_def.

[0217] That is, some embodiments of the present application set the "read, write, read-write attribute, field address range name setting" fields for each mode register built on the mode register module 2-23 as described above.

[0218] (2). Implement the write new() of the field field, field_write(), read field_read() and other functions;

[0219] The new() of the field field is to access the specific bits range through field_lsb and field_msb, and then write the default value of the field field_val_def into the corresponding bits bits through the reference of the register value reg_val. It should be noted that the default value of the field is the default value specified in the DDR5 protocol, and the field value refers to the value that some embodiments of the present application can write independently when declaring the field.

[0220] The write field_write() of the field field is to access the specific bits range through the index of filed_name, and then write the field value field_val into the corresponding bits bits through the reference of the register value reg_val. It should be noted that reg_val is the value corresponding to the 8 bits of the mode register, and if a 8-bit mode register contains multiple fields, the value field_val of a certain field is only a part of reg_val.

[0221] The read field_read() of the field field is to access the specific bits range through the index of filed_name, and then read the value of the corresponding bits in reg_val to field_val through the reference of the register value reg_val.

[0222] (3). Implement the field boundary check.

[0223] Ensure that field_lsb and field_msb are within the 8-bits space of the mode register MR bit0 to bit7, while field_val and field_val_def should not exceed the value range that bits[field_msb-field_lsb:field_lsb] can express.

[0224] That is, when declaring a field for a mode register, the space occupied by each field is arranged one by one, and the total space of all fields cannot exceed the total 8-bits space of a mode register.

[0225] (4). Implement the check and compatibility operation of read-write attribute access_type, details as follows:

[0226] DDR5 SDRAM mode registers mainly have read-only R, write-only W, read-write R / W, read-set-write SR / W or reserved RFU, wherein,

[0227] Read-only R: field_read() can read its value, and field_write() cannot write.

[0228] Write-only W: field_write() can write values, and field_read() cannot read.

[0229] Read-write R / W: field_read() can read its value, and field_write() can write values.

[0230] Read-set-write SR / W: field_read() can read its value, and then all bits of the field are set to 1, and field_write() can write values;

[0231] Reserved RFU: reserved for future use of the field field. The memory controller will ignore the bits of the RFU, in order to avoid writing unsupported values into the DRAM, the upper register Mode Register must write all zeros to the RFU field when calling field_write(), and the field must return all bits of the field to zero when field_read().

[0232] 3.2 Create a simple mode register type simple_register based on a simple register field type simple_reg_field. That is, to build any one of the 256 mode registers of each memory particle on module 2-23.

[0233] The read, write, reset and other operations of the main creation mode register are created, and the specific method and schematic code are as follows:

[0234]

[0235] The specific method is:

[0236] (1). Declare the basic attributes of the register simple_register type, including:

[0237] The group name to which the current single mode register belongs, that is, which memory particle SDRAM the mode register belongs to, the mode register address MA, and the mode register value reg_val;

[0238] (2). Implement new(), reg_read(), reg_write() of simple_register.

[0239] Implement the write reg_field_write() and read reg_field_read() of field through simple_register.

[0240] Implement reg_upd_val_to_fields() to update the value of simple_register to the field field, and reg_upd_fields_to_val() to synchronize the value of the field field to the value of simple_register.

[0241] Implement the method reg_field_add() to add the field filed to the current register simple_register. The method specifies the name name, access type access_type, high bit msb, low bit lsb, and value val of the new filed, and then adds a new field filed object to the simple_register object. The simple_register type integrates the name / type / msb / lsb / val information of the field.

[0242] For the field field of RFU, simple_register must ensure that the write to the field is all zeros, and the value read from the field must also be all zeros.

[0243] (3). Implement the capacity check of the mode register.

[0244] There are up to 256 mode registers, some of which are not defined. For example, 20 mode registers such as MR117 / 119 / 125 / 127 / 135 / 143 / 155 / 159 / 167 / 175 / 183 / 191 / 199 / 207 / 215 / 223 / 231 / 239 / 247 / 255 are not defined in JESD79-5. When the operation command of the memory control to be verified tries to access these mode registers, the simulation model will report an error message to ensure that the memory controller does not access the SDRAM mode registers declared, so as to avoid unexpected errors.

[0245] (4). Check and compatible operation of read-write attribute access_type.

[0246] The DDR5 SDRAM mode register mainly has read-only R, write-only W, readable and writable R / W, read set bit writable SR / W, and reserved RFU, wherein,

[0247] Read-only R: only read, not write.

[0248] Write-only W: only write, not read.

[0249] Read and write R / W: read and write.

[0250] Read set bit writable SR / W: read the value, and then all bits of the field are set to 1, which can be written.

[0251] Reserved RFU: reserved field for future use. The memory controller will ignore the bits of the RFU, in order to avoid writing unsupported values into the DRAM, the upper register Mode Register must write all zeros to the RFU field when writing, and must ensure that the field returns zero when reading.

[0252] 3.3 Create SDRAM particle mode register model dram_mode_registers based on simple mode register type simple_register.

[0253] Each SDRAM memory particle has 256 registers. Based on the single mode register simple_register type, the complete mode register model code of a single memory particle SDRAM is as follows:

[0254]

[0255] (1). Each SDRAM memory particle has 256 mode registers. Based on the single mode register ModeRegister type, the space of all mode registers of a single SDRAM memory particle is declared as follows:

[0256] simple_register mode_regs[REG_NUM];

[0257] (2). Since the DDR5 SDRAM mode registers access MR11 for VrefCA, access MR12 for VrefCS, access MR32 for RTT_CK, access MR32 for RTT_CS, and access MR33 for RTT_CA, shadow register operations are performed, that is, the operation instruction first writes the value into the shadow mode register, and then waits for the MPC_APPVERFRTT to be issued, and the value is written from the shadow register to the corresponding mode register MR11 / MR12 / MR32 / MR33. Therefore, the corresponding shadow registers are specially declared for the intermediate cache of the operation. It should be noted that in order to realize the operation related to the shadow register, in some embodiments of the present application, a register module (not shown in the figure) with the same structure as the mode register module 2-23 can be constructed on the memory controller verification device to serve as a temporary shadow register for storing data. In some other embodiments of the present application, a plurality of shadow registers can also be created according to actual needs to realize the operation related to the shadow register.

[0258] simple_register mode_regshd[4];

[0259] In order to save the space of the shadow registers, the corresponding operation instruction and the address of the original mode register can be encoded, and the output is the corresponding four addresses of mode_regshd. For example:

[0260]

[0261]

[0262] (3). The initialization function mode_regs_init() of the dram_mode_registers is realized. According to the description of the mode register in the DDR5 SDRAM protocol specification, the field name, value, and access type of the mode register are declared by calling the adding method of the field.

[0263] Some embodiments of the present application construct field adding scheme, which is convenient and fast for data model of MR0 mode register:

[0264] mode_regs[0].reg_field_add(“burst_length”,R / W,1,0,2’b0);

[0265] mode_regs[0].reg_field_add(“cas_latency”,R / W,6,2,5’b0);

[0266] mode_regs[0].reg_field_add(“rfu”,R / W,7,7,1’b0);

[0267] Similarly, the data model of MR1 register can be established by the following declaration:

[0268] mode_regs[1].reg_field_add(“pda_enum_id”,R,3,0,4’hF);

[0269] mode_regs[1].reg_field_add(“pda_sel_id”,R,7,4,4’hF);

[0270] Similarly, all 256 mode registers of a single memory particle are declared one by one and stored in mode_regs[0:255] one by one. For the mode registers not defined in the protocol, an 8-bit wide single field type field of rfu type with a value of 8’h0 can be declared in the corresponding MR[] unit to improve software robustness.

[0271] For example, “burst_length” above belongs to field name field_name;

[0272] R / W belongs to field read-write attribute, access_type;

[0273] 1: The position of the high bit of the field in the register is encoded as field_msb;

[0274] 0: The position of the low bit of the field in the register is encoded as field_lsb;

[0275] 2’b0: It belongs to the default value of the field field_val_def.

[0276] Figure 7 shows 2-16-1 SDRAM0 MR[0:255], 2-16-2 SDRAM7 MR[0:255], 2-19-1 SDRAM0 MR[0:255], 2-19-2 SDRAM7 MR[0:255], etc. are all the models of the mode registers of a single SDRAM memory particle.

[0277] 3.4 Create the memory channel type dimm_regs_per_channel of the single DIMM mode register based on the model of the mode register of the SDRAM memory particle dram_mode_registers.

[0278] As introduced in the background, there are 4 RANKs in a sub-memory channel of the memory controller, and a RANK is composed of multiple memory particles in the same memory sub-channel.

[0279] Some embodiments of the present application create a highly parameterized type dimm_regs_per_channel to model the mode registers of the SDRAM particles of a RANK, and to realize the direct access to the SDRAM memory particles at the RANK level. The first single memory channel model 2-9-1 and the second single memory channel model 2-9-2 of Figure 7 are the models of two memory sub-channels in the verification environment, and the code is as follows:

[0280] class dim_regs_per_channel#(int MAX_RANKS_PER_CHANNEL=4,int MAX_DRAM_PER_RANK=10,int REG_NUM=256,int MAX_CHANNELS_PER_DIMM=2);

[0281] dram_mode_registers#(REG_NUM)

[0282] dram_mode_regs[MAX_RANKS_PER_CHANNEL][MAX_DRAMS_PER_RANK];

[0283] / / If there are other register channel structures, they can be declared here for expansion

[0284] / / Function&task definition and declaration

[0285] endclass

[0286] (1). The memory sub-channel type declares the mode registers of the memory particles on each RANK:

[0287] dram_mode_registers#(REG_NUM)dram_mode_regs[MAX_RANKS_PER_CHANNEL][MAX_DRAMS_PER_RANK];

[0288] Taking MAX_RANKS_PER_CHANNEL = 4 and MAX_DRAMS_PER_RANK = 5 in some embodiments of the present application as an example, the above method declares the SDRAM grain relationship corresponding to the 4 RANKs of the sub-channel A:

[0289] The five memory grains of mode_regs[0][0][0:4] in FIG. 7 constitute a virtual RANK0 2-11-1 of the first single memory channel model 2-9-1; the five memory grains of mode_regs[0][1][0:4] in FIG. 7 constitute a virtual RANK1 2-12-1 of the first single memory channel model 2-9-1; the five memory grains of mode_regs[0][2][0:4] in FIG. 7 constitute a virtual RANK2 2-14-1 of the first single memory channel model 2-9-1; and the five memory grains of mode_regs[0][3][0:4] in FIG. 7 constitute a virtual RANK3 2-15-1 of the first single memory channel model 2-9-1.

[0290] It should be noted that mode_regs[0][0][0:4], mode_regs[0][1][0:4], mode_regs[0][2][0:4] and mode_regs[0][3][0:4] in FIG. 7 are program space instances created for all mode registers of the five memory grains of the third RANK (i.e., RANK2) of the memory sub-channel A. Each memory grain on the virtual RANK is pointed to these program spaces through a pointer, thereby avoiding repeated declaration of memory space and reducing consumption.

[0291] These virtual RANKs can be directly accessed through the ID of the RANK, and the access to these virtual RANKs is independent of the distribution form of the corresponding constructed RANK on the DIMM. It should be noted that,

[0292] (2). The first sub-channel register application module 2-24-1 is used to implement the access method of the memory channel model to the mode register. With these methods, the verification environment can directly access the memory grain from the memory channel, saving many intermediate conversion links.

[0293] Some embodiments of the present application create a perfect channel model access mode register method, which realizes setting the memory particles in the virtual RANK to the actual memory particles on the DIMM. Set the channel identification signal to distinguish different memory sub-channels, for example, distinguish whether the memory sub-channel is channel A or channel B. Set the DIMM type to X4 / X8 / X16. Set the mapping between the sequence number of the SDRAM memory particle and the PDAID code. Realize the access to the specific mode register of a single SDRAM particle on a single virtual RANK, that is, support the access to the whole mode register granularity of the memory controller to be verified, and support the access to all field granularity on each mode register. That is, support the unified operation of all memory particles on the whole RANK, and support the PDA operation of the mode register corresponding to the target memory particle on the target RANK. This design structure simplifies the processing process required when the verification environment accesses the mode register, and speeds up the simulation and debugging efficiency.

[0294] (3). At the same time, the design structure of some embodiments of the present application can expand other types of registers in the memory sub-channel model, and at the same time realize the corresponding method, so that the memory channel model can also directly access these registers, for example, it can be very convenient to be applied to RDIMM and LRDIMM.

[0295] 3.5 Based on the SDRAM memory particle mode register model dram_mode_registers, create an instance controller_dram_mode_regs[] set for the mode register of all memory particles.

[0296] (1). The schematic code of declaring the mode register space of all memory particles on all DIMMs is as follows:

[0297] dram_mode_registers controller_dram_mode_regs[dimm][channel][side][dram];

[0298] wherein, dimm is the number of all DIMMs accessed by a single memory controller. Some embodiments of the present application take two DIMMs accessed by each memory controller as an example, dimm = 2, which corresponds to the first memory bank DIMM0 and the second memory bank DIMM1 of FIG. 7, side is whether the RANK on each DIMM is divided into front and back two side packages, and the memory particles on the front and back two sides belong to different RANKs. Some embodiments of the present application take each DIMM bank as a front and back two side package as an example, side = 2. channel_ is the number of memory sub-channels of a single memory controller, which is also the number of memory sub-channels on each DDR5 DIMM bank. Some embodiments of the present application take two memory sub-channels of each memory controller as an example, channel = 2; dram is the number of particles per RANK determined by the particle density on the DIMM. In order to support the random enabling of ECC function in actual simulation, the simulation model instantiates the model under the condition of enabling ECC. Therefore, the X4 type of DIMM needs 10 memory particles per RANK; the X8 type needs 5; and the X16 type can use 2 due to the current industry ECC scheme. As shown in FIG. 7, some embodiments of the present application take the X8 type of DIMM as an example, i.e., dram = 5.

[0299] FIG. 7 is an example of a mode register model established for a total of 40 memory particles on two DIMMs in a memory sub-channel. In the modeling scheme of some embodiments of the present application, only the mode register module 2-23 declares the instantiation of all register models, and the types of other modules are referenced. Such a method can greatly save the memory consumption of the simulation environment, eliminate the simulation time consumption caused by model data copying, assignment, etc., and improve the simulation efficiency.

[0300] (2). After the channel mode register is instantiated, all mode registers of each memory particle are initialized.

[0301] (3). At the same time, the channel consistency model is declared for the current two memory channels:

[0302] dimm_regs_per_channel([x,x,x]

[0303] controller_dimm_regs_per_chan[CHANNEL_PER_Controller];

[0304] 3.6 Establish a mapping relationship between the memory channel dimm_regs_per_channel[] and the actual memory particle controller_dram_mode_regs[].

[0305] The first solid line 2-22-1 and the second solid line 2-22-2 of FIG. 7 respectively represent mapping the mode register model corresponding to the memory granules of the first memory sub-channel and the second memory sub-channel to the virtual RANK corresponding to the memory sub-channel.

[0306] Some embodiments of the present application create a method of remapping type reference, which quickly completes mapping. The schematic code is as follows:

[0307]

[0308] The mode register instance of the first mode register instance 2-17-1 of FIG. 7 is mapped to the virtual RANK0 2-11-1 of the first single memory channel model 2-9-1.

[0309] The mode register instance of the second mode register instance 2-18-1 of FIG. 7 is mapped to the virtual RANK1 2-12-1 of the first single memory channel model 2-9-1.

[0310] The mode register instance of the third mode register 2-20-1 of FIG. 7 is mapped to the virtual RANK2 2-14-1 of the first single memory channel model 2-9-1.

[0311] The mode register instance of the fourth mode register 2-21-1 of FIG. 7 is mapped to the virtual RANK3 2-15-1 of the first single memory channel model 2-9-1.

[0312] The mapping principle of the mode register of other RANK granules is the same.

[0313] In this way, the modeling and connection of channel consistency are completed, facilitating access and debugging.

[0314] Some embodiments of the present application provide a verification method for verifying a memory controller based on a constructed memory controller verification device, the verification method comprising: for each memory sub-channel, completing current instruction decoding at a DFI interface to obtain an instruction decoding result; determining, according to the instruction decoding result, that the current instruction belongs to a memory mode register operation instruction related to a memory mode register operation; and determining that the memory mode register operation instruction is for a target mode register of an addressable target RANK, then accessing the target RANK through a RANK access pointer corresponding to a target virtual RANK and accessing the target mode register through a memory particle access pointer included in the target virtual RANK to complete an operation on the target mode register; wherein the operation is a function corresponding to the current instruction, the target mode register is located on the target RANK, the target RANK is located on a mode register module, the target virtual RANK is a pointer group constructed for accessing each mode register on the target RANK, and the mode register module includes a mode register constructed for each memory particle in the memory, and the memory is a storage device actually accessed by the memory controller to be verified.

[0315] In some embodiments of the present application, the verification method further comprises: determining that the memory mode register operation instruction is for a target virtual RANK, then accessing all mode registers included in a target RANK through a RANK access pointer corresponding to the target virtual RANK to complete an operation on the all mode registers.

[0316] In some embodiments of the present application, the verification method further comprises: determining that the memory mode register operation instruction is for an operation on a shadow mode register, then completing the operation by calling a shadow register processing function.

[0317] In some embodiments of the present application, the verification method further comprises: if it is determined that a virtual RANK to be accessed by the memory mode register operation instruction does not exist or a target mode register belongs to a prohibited access, then generating an error prompt information.

[0318] As shown in Figure 8 , the figure provides a process of constructing two memory sticks and two memory sub-channels and a process of verifying a memory controller based on the constructed model.

[0319] As shown in ​ , the memory controller verification method of some embodiments of the present application comprises:

[0320] S201, according to system configuration, declare two memory sticks on all memory particle mode register spaces.

[0321] S202, map the actual mode register space on the memory stick to the virtual space of the two independent memory channels respectively.

[0322] S203, complete the DFI interface instruction decoding for each memory channel.

[0323] S204, judge whether it is the instruction for the DRAM memory mode register, if yes, execute S205, otherwise execute other subsequent verification work of S213.

[0324] S205, judge whether it is the operation for a single DRAM grain, if yes, execute S206, otherwise execute S212 and S211.

[0325] S212, call the unified access method for the normal European register in the present scheme, and the target of each operation is all DRAM memory grains in the designated target RANK.

[0326] S211, complete the access of the normal mode register.

[0327] S206, judge whether it is the operation for the shadow mode register, if yes, only go to S207; otherwise, execute the PDA access method for the normal mode register in the present scheme of S210, and the target of each operation is a single DRAM memory grain, and then execute the above S211.

[0328] S207, call the PDA access method for the shadow mode register in the present scheme, and the target of each operation is a single DRAM memory grain.

[0329] S208, judge whether the value of the shadow mode register is to be written back to the shadow mode register, if yes, only go to S209, otherwise return to S206.

[0330] S209, copy the value of all shadow mode registers to the corresponding normal mode register.

[0331] S213, other subsequent verification operation.

[0332] It should be noted that the modeling method provided by some embodiments of the present application has high adaptability, which is based on single-memory mode register modeling, mapping to a logical channel at the DFI protocol (or other controller downward interface protocol) level, and implementing direct access of the grain at the channel level. The verification thinking and implementation method can be conveniently applied to other scenarios with cross and channel access media. The model structure has strong expandability and can be used as a basis for modeling and verification of other controllers on other DIMM types (such as RDIMM and LRDIMM), constituting part of a combination patent. The model has high multiplicity, so that the verification environment can easily support multiple bandwidth expansion schemes, such as multiple controller parallel schemes. The model has good portability, which realizes package packaging and facilitates other UVCs in the verification environment to access the unified global memory grain mode register. The model is very flexible and can seamlessly support mixed insertion schemes of different density DIMMs, such as an X4 DIMM and an X8 DIMM, in addition to supporting the same type of DIMM. Some embodiments of the present application provide register and filed two granularities of access to the memory mode register, that is, the entire register can be read and written, and the corresponding field can be directly read and written, which simplifies the access method and optimizes the code of the verification environment.

[0333] In the modeling scheme of some embodiments of the present application, a simple and light register field and register modeling scheme is created. In addition, some embodiments of the present application are based on single-memory mode register modeling, mapping to a logical channel at the DFI protocol (or other controller downward interface protocol) level, and implementing direct access of the grain at the channel level. Therefore, a person skilled in the art can define other forms of register field and register modeling methods. The modeling scheme proposed by some embodiments of the present application is also applicable to other devices other than DDR5 SDRAM. The modeling scheme proposed by some embodiments of the present application can constitute a basic scheme for verifying UDIMM, RDIMM, LRDIMM, etc.

[0334] In several embodiments provided in the present application, it should be understood that the disclosed apparatus and method can also be implemented by other means. The apparatus embodiments described above are only illustrative, for example, the flowcharts and block diagrams in the drawings show the possible implementation architecture, function and operation of the apparatus, method and computer program product according to the embodiments of the present application. In this regard, each block in the flowchart or block diagram can represent a module, a program segment or a part of code, which contains one or more executable instructions for implementing the specified logic function. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur in different order from that shown in the drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and sometimes they can be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0335] In addition, the functional modules in the embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0336] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various program code storage media.

[0337] The above merely provides an example of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application. It should be noted that similar reference numerals and letters represent similar items in the following drawings, and thus, once an item is defined in one drawing, it need not be further defined and explained in subsequent drawings.

[0338] The above merely provides an example of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application. It should be noted that similar reference numerals and letters represent similar items in the following drawings, and thus, once an item is defined in one drawing, it need not be further defined and explained in subsequent drawings.

[0339] It should be noted that the relational terms herein such as first and second and the like are used solely to distinguish one entity or action from another, without necessarily requiring or implying any actual relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

Claims

1. A memory controller verification apparatus, comprising: The memory controller verification device comprises: a mode register module comprising mode registers respectively corresponding to each memory particle in the memory, wherein the memory is a memory actually accessed by the memory controller to be verified; at least one access control module configured to access a target mode register included in the mode register module through a pointer included in a virtual RANK, wherein one access control module is provided corresponding to one memory sub-channel of the memory; wherein the memory comprises A memory banks, and one memory sub-channel can access B RANKs distributed on the A memory banks; the mode register module is configured to include the A memory banks; for one memory sub-channel, the mode register module is configured to include B RANKs, wherein the B RANKs are located on the A memory banks; the access control module is configured to include B virtual RANKs, wherein one virtual RANK corresponds to one constructed RANK, and each virtual RANK corresponds to a unique code; wherein A and B are both integers greater than or equal to 1; each virtual RANK comprises a group of pointers, wherein a target mode register located on the mode register module can be accessed through a mode register access pointer included in each group of pointers.

2. The memory controller verification apparatus of claim 1, wherein Each virtual RANK is accessed through the code, and each virtual RANK accesses a corresponding target RANK on the mode register module through a RANK access pointer.

3. The memory controller verification apparatus of claim 2, wherein, The mode register is configured to include a plurality of fields of different sizes and each field corresponds to a different name, wherein each field of the mode register is accessed through the name of the field.

4. The memory controller verification apparatus of any of claims 1-3, wherein, The mapping relationship between the serial number of each memory particle on the mode register module and the access code of a single memory particle can be dynamically configured.

5. The memory controller verification apparatus of any of claims 1-3, wherein, Different memory sub-channels included in the memory are distinguished through different identification signals.

6. The memory controller verification apparatus of any of claims 2-3, wherein The access control module further comprises: an instruction decoder configured to parse an interface signal according to an interface protocol to obtain a memory particle operation instruction, wherein the interface protocol is a protocol adopted by a downward interface unit of the memory controller to be verified; a mode register operation instruction parsing unit configured to: parse the memory particle operation instruction to obtain a parsing result; perform instruction screening according to the parsing result to obtain a target operation instruction related to a mode register operation; a sub-channel mode register application method module configured to: obtain a target virtual RANK corresponding to the target operation, and access a target RANK located on the mode register module according to a RANK access pointer corresponding to the target virtual RANK to complete the target operation on all mode registers on the target RANK; or, The target operation on the target mode register is completed by accessing a target RANK through a RANK access pointer corresponding to the target virtual RANK and accessing the target mode register on the target RANK through a mode register access pointer included in the target virtual RANK.

7. The memory controller verification apparatus of claim 6, wherein, The sub-channel mode register application method module at least includes: an implementation function corresponding to all operation instructions of the mode register, and a logical conversion mapping table between the memory sub-channel and a target memory particle, wherein the distribution position of the target mode register on the mode register module is obtained by searching the logical conversion mapping table, and the target operation is completed by the implementation function corresponding to the target operation.

8. The memory controller verification apparatus of claim 7, wherein, The interface protocol is a DFI protocol, and the memory is a UDIMM, wherein The mode register operation instruction analysis unit is further configured to: obtain an MPC instruction by screening the memory particle operation instruction, and obtain an MPC instruction analysis result; if it is confirmed according to the MPC instruction analysis result that the memory is in a PDA operation state, the target mode register is obtained according to the PDA operation state.

9. The memory controller verification apparatus of claim 8, wherein, The memory controller verification device further includes a constructed shadow register, wherein if it is confirmed by the mode register operation instruction analysis unit that the memory is in a PDA state, the sub-channel mode register application method module is further configured to implement a target operation corresponding to the shadow register through the shadow register and the target mode register.

10. The memory controller verification apparatus of claim 7, wherein, The sub-channel mode register application method module is further configured to generate an error prompt information when it is confirmed that the target mode register belongs to a prohibited access mode register.

11. The memory controller verification apparatus of claim 6, wherein, If the memory is a UDIMM, the mode register operation instruction analysis unit includes: an MPC command processing unit configured to obtain an MPC instruction from the output result of the instruction decoder, and analyze the MPC instruction to obtain an MPC instruction analysis result; an MRW command processing unit connected to the output end of the MPC command processing unit and configured to detect an MRW instruction from the input signal, and analyze the MRW instruction to obtain an MRW instruction analysis result; an MRR command processing unit connected to the output end of the MPC command processing unit and configured to detect an MRR instruction from the input signal, and analyze the MRR instruction to obtain an MRR instruction analysis result; a VrefcA / VrefcS command processing unit connected to the output end of the MPC command processing unit and configured to detect a VrefcA and / or VrefcS instruction from the input signal, and analyze the VrefcA and / or VrefcS instruction to obtain a VrefcA and / or VrefcS instruction analysis result.

12. The memory controller verification apparatus of claim 11, wherein, The interface protocol is a DFI protocol, The mode register operation instruction analysis unit further includes: a PDA monitoring module configured to confirm that the memory is in a PDA operation state; wherein An output end of the MPC command processing unit is connected with an input end of the PDA monitoring module, wherein the PDA monitoring module confirms the PDA operation state through the MPC instruction analysis result; An input end of the MRW command processing unit is connected with an output end of the PDA monitoring module; An input end of the MRR command processing unit is connected with an output end of the PDA monitoring module; An input end of the VrefcA / VrefcS command processing unit is connected with an output end of the PDA monitoring module.

13. A memory mode register modeling method for constructing the memory controller verification apparatus according to any one of claims 1-12, characterized in that, The memory mode register modeling method comprises: constructing a mode register space of each memory sub-channel in the memory; creating an access tool for accessing a target memory mode register included in the mode register space, wherein the access tool is configured to access a target mode register included in the mode register space according to a pointer and complete at least one operation on the target mode register, the at least one operation including one or more of the following operations: a read or write operation on various fields included in the target mode register, a read or write operation on the whole target mode register, and a shadow register access operation.

14. The memory model register modeling method of claim 13, wherein, The constructing a mode register space of each memory sub-channel in the memory comprises: based on a DFI interface, modeling a spatial relationship of memory particles, and mapping all constructed mode register arrays corresponding to the memory particles included in a same memory sub-channel to a virtual RANK mode register array corresponding to the DFI interface.

15. The memory model register modeling method of any of claims 13-14, wherein, After the creating an access tool for accessing a target memory mode register included in the mode register space, the memory mode register modeling method further comprises: adding a behavior model, and adding the access tool and the behavior model to a memory sub-channel model, wherein the behavior model is used to simulate the behavior of at least part of the mode register.

16. The memory model register modeling method of claim 15, wherein, After the adding the access tool and the behavior model to the memory sub-channel model, the memory mode register modeling method further comprises: encapsulating the memory sub-channel model and a memory controller to be verified.

17. The memory model register modeling method of claim 14, wherein, The modeling a spatial relationship of memory particles comprises: creating various field types of a mode register to be constructed and names of the various field types; creating a mode register according to the various field types, to obtain a constructed mode register; creating a plurality of the constructed mode registers according to a number of all mode registers included in a memory particle, to obtain a memory particle mode register group; creating a plurality of the memory particle mode register groups according to a total number of memory particles included in a RANK, to obtain a RANK mode register group, wherein the RANK is located on a memory actually connected with a memory controller to be verified; creating a plurality of the RANK mode register groups according to various memory sub-channel types included in the memory, to obtain a memory sub-channel mode register group; wherein the memory particle, the RANK, and the memory sub-channel are all located on the memory, and the memory is an access device actually accessed by the memory controller to be verified.

18. The memory model register modeling method of claim 17, wherein, The fields respectively correspond to different bit numbers, the length of the longest field is equal to the length of a mode register, the length of the shortest field is 1, and the total number of fields is the same as the length of the longest field.

19. A verification method for verifying a process of a memory controller verification apparatus as claimed in any one of claims 1-12 for verifying an access pattern register of a memory controller to be verified, characterized in that, The verification method comprises: For each memory sub-channel, a current instruction decoding on a DFI interface is completed to obtain an instruction decoding result, wherein the current instruction is from the memory controller to be verified; According to the instruction decoding result, it is confirmed that the current instruction belongs to a memory mode register operation instruction related to memory mode register operation; If it is confirmed that the memory mode register operation instruction is for an addressable target mode register, then the target RANK is accessed through the RANK access pointer corresponding to the target virtual RANK, and the target mode register is accessed through the memory particle access pointer included in the target virtual RANK, to complete the operation on the target mode register; The operation is a function corresponding to the current instruction, the target mode register is located on the target RANK, the target RANK is located on a mode register module, the target virtual RANK is a pointer group constructed for accessing each mode register on the target RANK, the mode register module includes mode registers constructed for each memory particle in the memory, and the memory is a storage device actually accessed by the memory controller to be verified.

20. The method of claim 19, wherein, The verification method further comprises: If it is confirmed that the memory mode register operation instruction is for a target virtual RANK, then all mode registers included in the target RANK are accessed through the RANK access pointer corresponding to the target virtual RANK to complete the operation on all mode registers.

21. The method of verification of claim 20, wherein, The verification method further comprises: If it is confirmed that the memory mode register operation instruction is for an operation on a shadow mode register, then the operation is completed by calling a shadow register processing function.

22. The method of verification of any of claims 19-21, wherein, The verification method further comprises: if it is confirmed that the virtual RANK to be accessed by the memory mode register operation instruction does not exist or the target mode register belongs to prohibited access, then an error prompt information is generated.

23. A verification system characterized by, The verification system comprises: A memory controller to be verified, configured to convert an operation for accessing a memory particle to each independent sub-memory channel included in the memory; A controller downward interface unit, configured to connect each independent sub-memory channel included in the memory controller to be verified to a target interface protocol environment of a corresponding memory sub-channel; and The memory controller verification device according to any one of claims 1-12; The memory controller verification device is connected to the memory controller to be verified through the controller downward interface unit.

24. The verification system of claim 23, wherein, The controller downward interface unit comprises a DFI interface unit.

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