A semiconductor packaging structure and a method for forming the same

Abstract

The present embodiment discloses a semiconductor packaging structure and a method for forming the same, wherein the semiconductor packaging structure includes: a first semiconductor chip; a plurality of first contact pads are formed on the surface of the first semiconductor chip; a dielectric layer is located on the first semiconductor chip; a plurality of second contact pads are formed in the dielectric layer; a second semiconductor chip stacking structure is located on the dielectric layer; the second semiconductor chip stacking structure includes a plurality of second semiconductor chips stacked in sequence; a plurality of third contact pads are formed on the surface of the first layer of second semiconductor chips; the first semiconductor chip and the first layer of second semiconductor chips are bonded to each other in a one-to-one correspondence through the first contact pad, the second contact pad and the third contact pad; wherein the width of each second contact pad is inconsistent with the width of the corresponding first contact pad, and / or the width of the third contact pad.

Description

Technical Field

[0001] The present disclosure relates to the field of three-dimensional process technology, and in particular to a semiconductor packaging structure and a method for forming the same. Background Art

[0002] As people's requirements for electronic products develop towards miniaturization and multi-functions, packaging is also developing towards high density and high integration, and integrated circuit products are also developing from two-dimensional to three-dimensional. However, during the chip bonding process, misalignment may occur between contact pads, affecting the performance of the device. Summary of the invention

[0003] In view of this, an embodiment of the present disclosure provides a semiconductor package structure and a method for forming the same.

[0004] According to a first aspect of an embodiment of the present disclosure, there is provided a semiconductor package structure, including:

[0005] A first semiconductor chip; a plurality of first contact pads are formed on a surface of the first semiconductor chip;

[0006] A dielectric layer, located on the first semiconductor chip; a plurality of second contact pads are formed in the dielectric layer;

[0007] A second semiconductor chip stacking structure is located on the dielectric layer; the second semiconductor chip stacking structure comprises a plurality of second semiconductor chips stacked in sequence; a plurality of third contact pads are formed on the surface of the first layer of second semiconductor chips;

[0008] The first semiconductor chip and the first layer second semiconductor chip are bonded to each other via the first contact pad, the second contact pad and the third contact pad in a one-to-one correspondence; wherein,

[0009] The width of each of the second contact pads is inconsistent with the width of the corresponding first contact pad and / or the third contact pad.

[0010] In some embodiments, each of the first contact pads has the same width as the corresponding third contact pad.

[0011] In some embodiments, the first contact pad is formed on the active surface of the first semiconductor chip, the third contact pad is formed on the active surface of the first layer second semiconductor chip, and the active surface of the first semiconductor chip is bonded to the active surface of the first layer second semiconductor chip; wherein the active surface is a side of the chip forming a device layer.

[0012] In some embodiments, the widths of the plurality of first contact pads are not uniform; the widths of the plurality of second contact pads are not uniform; and the widths of the plurality of third contact pads are not uniform.

[0013] In some embodiments, the first contact pad includes a first first contact pad and a second first contact pad;

[0014] The second contact pad includes a first second contact pad and a second second contact pad, and the width of the first second contact pad is greater than the width of the second second contact pad;

[0015] The third contact pad includes a first third contact pad and a second third contact pad; wherein,

[0016] The width of the first second contact pad is greater than the width of the corresponding first first contact pad and / or the first third contact pad; the width of the second second contact pad is less than the width of the corresponding second first contact pad and / or the second third contact pad.

[0017] In some embodiments, the material of the dielectric layer includes a silicon-containing compound.

[0018] In some embodiments, it also includes:

[0019] a fourth contact pad located within the plurality of second semiconductor chips above the first plurality of second semiconductor chips;

[0020] The widths of the corresponding fourth contact pads between two adjacent layers of second semiconductor chips are inconsistent.

[0021] In some embodiments, it also includes:

[0022] The insulating layer is located between the side wall of the second contact pad and the dielectric layer; the Young's modulus of the insulating layer is smaller than the Young's modulus of the dielectric layer.

[0023] According to a second aspect of an embodiment of the present disclosure, a method for forming a semiconductor package structure is provided, comprising:

[0024] forming a first semiconductor chip; forming a plurality of first contact pads on a surface of the first semiconductor chip;

[0025] forming a dielectric layer on the first semiconductor chip; and forming a plurality of second contact pads in the dielectric layer;

[0026] A second semiconductor chip stacking structure is formed on the dielectric layer; the second semiconductor chip stacking structure comprises a plurality of second semiconductor chips stacked in sequence; and a plurality of third contact pads are formed on the surface of the first layer of the second semiconductor chips;

[0027] The first semiconductor chip and the first layer second semiconductor chip are bonded one by one through the first contact pad, the second contact pad and the third contact pad; wherein,

[0028] The width of each of the second contact pads is inconsistent with the width of the corresponding first contact pad and / or the third contact pad.

[0029] In some embodiments, each of the first contact pads has the same width as the corresponding third contact pad.

[0030] In some embodiments, a first contact pad is formed on an active surface of the first semiconductor chip;

[0031] forming a third contact pad on the active surface of the second semiconductor chip of the first layer;

[0032] The active surface of the first semiconductor chip is bonded to the active surface of the second semiconductor chip of the first layer; wherein the active surface is the side of the chip forming the device layer.

[0033] In some embodiments, a dielectric layer is formed on the first semiconductor chip by spin coating, and a material of the dielectric layer includes a silicon-containing compound.

[0034] In some embodiments, it also includes:

[0035] forming a fourth contact pad in the plurality of layers of second semiconductor chips above the first layer of second semiconductor chips;

[0036] The widths of the corresponding fourth contact pads between two adjacent layers of second semiconductor chips are inconsistent.

[0037] In some embodiments, forming a plurality of second contact pads in the dielectric layer comprises:

[0038] Etching the dielectric layer to form a plurality of through holes;

[0039] forming a second contact pad in the through hole;

[0040] The method further comprises:

[0041] After forming the second contact pad, the second contact pad is etched so that a gap is formed between a sidewall of the second contact pad and a sidewall of the through hole.

[0042] In some embodiments, it also includes:

[0043] An insulating material is filled in the gap to form an insulating layer; the Young's modulus of the insulating layer is smaller than the Young's modulus of the dielectric layer.

[0044] In the disclosed embodiment, a dielectric layer is provided between the first semiconductor chip and the second semiconductor chip of the first layer, and the size of the second contact pad in the dielectric layer is inconsistent with the size of the first contact pad corresponding thereto, and / or the size of the third contact pad, so that during alignment, the contact pad with a smaller size can be in contact with the contact pad with a larger size, thereby improving the accuracy of alignment. In addition, the provision of the dielectric layer can increase the insulation between adjacent contact pads, reduce the possibility of coupling between adjacent contact pads, and solve the problem of metal diffusion. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1a A schematic diagram of the structure of a semiconductor package provided by an embodiment of the present disclosure;

[0047] Figure 1b A schematic structural diagram of a semiconductor packaging structure provided by another embodiment of the present disclosure;

[0048] Figure 2 A schematic diagram of a process for forming a semiconductor packaging structure provided by an embodiment of the present disclosure;

[0049] Figures 3a to 3i A schematic diagram of the structure of a semiconductor package structure during the formation process provided by an embodiment of the present disclosure.

[0050] Description of reference numerals:

[0051] 10-first semiconductor chip; 20-dielectric layer;

[0052] 30-second semiconductor chip stacking structure; 31-first layer second semiconductor chip;

[0053] 40 - a first contact pad; 41 - a first first contact pad; 42 - a second first contact pad;

[0054] 50 - second contact pad; 51 - first second contact pad; 52 - second second contact pad; 501 - through hole;

[0055] 60 - third contact pad; 61 - first third contact pad; 62 - second third contact pad;

[0056] 70- fourth contact pad;

[0057] 80-insulating layer; 801-gap;

[0058] 91 - through silicon via; 92 - fifth contact pad; 93 - solder ball;

[0059] 100-Encapsulation compound structure. DETAILED DESCRIPTION

[0060] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0061] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0062] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. The same reference numerals denote the same elements throughout.

[0063] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0064] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0065] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0066] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0067] Based on this, the present disclosure provides a semiconductor packaging structure. Figure 1a A schematic diagram of the structure of a semiconductor package provided in an embodiment of the present disclosure.

[0068] See also Figure 1aThe semiconductor packaging structure includes: a first semiconductor chip 10; a plurality of first contact pads 40 are formed on the surface of the first semiconductor chip; a dielectric layer 20 is located on the first semiconductor chip 10; a plurality of second contact pads 50 are formed in the dielectric layer 20; a second semiconductor chip stacking structure 30 is located on the dielectric layer 20; the second semiconductor chip stacking structure 30 includes a plurality of second semiconductor chips stacked in sequence; a plurality of third contact pads 60 are formed on the surface of the first layer of second semiconductor chips 31; the first semiconductor chip 10 and the first layer of second semiconductor chips 31 are bonded to each other through the first contact pads 40, the second contact pads 50 and the third contact pads 60 in a one-to-one correspondence; wherein the width of each second contact pad 50 is inconsistent with the width of the corresponding first contact pad 40 and / or the third contact pad 60.

[0069] In the disclosed embodiment, a dielectric layer is provided between the first semiconductor chip and the second semiconductor chip of the first layer, and the size of the second contact pad in the dielectric layer is inconsistent with the size of the first contact pad corresponding thereto, and / or the size of the third contact pad, so that during alignment, the contact pad with a smaller size can be in contact with the contact pad with a larger size, thereby improving the accuracy of alignment. In addition, the provision of the dielectric layer can increase the insulation between adjacent contact pads, reduce the possibility of coupling between adjacent contact pads, and solve the problem of metal diffusion.

[0070] The first semiconductor chip 10 is a logic chip, and the second semiconductor chip is a dynamic random access memory (DRAM) chip. The logic chip can be one or more processors configured to communicate with multiple DRAM chips to access data from the DRAM chips and store data in the multiple DRAM chips. The logic chip includes but is not limited to a graphics processing unit (GPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a central processing unit (CPU), or other known electronic circuits used as processors.

[0071] In one embodiment, the first contact pad 40 includes a first first contact pad 41 and a second first contact pad 42; the second contact pad 50 includes a first second contact pad 51 and a second second contact pad 52, and the width of the first second contact pad 51 is greater than the width of the second second contact pad 52; the third contact pad 60 includes a first third contact pad 61 and a second third contact pad 62; wherein the width of the first second contact pad 51 is greater than the width of the corresponding first first contact pad 41, and / or the width of the first third contact pad 61; the width of the second second contact pad 52 is less than the width of the corresponding second first contact pad 42, and / or the width of the second third contact pad 62.

[0072] In a group of corresponding first contact pads, second contact pads and third contact pads, if the size of the second contact pad is larger, the size of the first contact pad or the third contact pad is smaller, and if the size of the second contact pad is smaller, the size of the first contact pad or the third contact pad is larger. In this way, the size of the second contact pad is opposite to the corresponding first contact pad or the third contact pad, ensuring that the contact area of ​​the contact pad between the first semiconductor chip and the first layer second semiconductor chip after bonding is relatively constant, solving the problem of different contact areas due to misalignment.

[0073] It should be explained that the width is the width in a direction parallel to the plane of the first semiconductor chip.

[0074] In one embodiment, each first contact pad 40 has the same width as the corresponding third contact pad 60. The corresponding two first contact pads and the third contact pad have the same size, so that the contact area between the first contact pad and the third contact pad and the corresponding second contact pad is relatively consistent.

[0075] For example, see Figure 1a , the width of the first first contact pad 41 is consistent with the width of the first third contact pad 61 , and the width of the second first contact pad 42 is consistent with the width of the second third contact pad 62 .

[0076] In some other embodiments, the widths of the first contact pad and the corresponding third contact pad may also be inconsistent.

[0077] In one embodiment, the widths of the plurality of first contact pads 40 are not consistent; the widths of the plurality of second contact pads 50 are not consistent; and the widths of the plurality of third contact pads 60 are not consistent. In this way, even if there are size differences between the pads, between the corresponding contact pads, the smaller contact pad can be in contact with the larger contact pad, thereby ensuring that the contact area between the contact pads is relatively constant.

[0078] In one embodiment, the first contact pad 40 is formed on the active surface of the first semiconductor chip 10, and the third contact pad 60 is formed on the active surface of the first layer second semiconductor chip 31, and the active surface of the first semiconductor chip 10 is bonded to the active surface of the first layer second semiconductor chip 31; wherein the active surface is a side of the chip forming a device layer. Compared with bonding the active surface to the back surface, bonding the active surface of the first semiconductor chip to the active surface of the first layer second semiconductor chip shortens the transmission path between the chips and improves the transmission speed.

[0079] In some other embodiments, the first contact pad 40 is formed on the active surface of the first semiconductor chip 10, and the third contact pad 60 is formed on the inactive surface of the first layer second semiconductor chip 31; the active surface of the first semiconductor chip 10 is bonded to the inactive surface of the first layer second semiconductor chip 31, wherein the inactive surface is the surface opposite to the active surface. In this packaging structure, the active surfaces of the first semiconductor chip and the first layer second semiconductor chip are facing the same side. Compared with the method of bonding the active surfaces of the chips to the active surfaces, this embodiment does not need to additionally flip the first layer second semiconductor chip, thereby simplifying the packaging process.

[0080] In one embodiment, the material of the dielectric layer 20 includes a silicon-containing compound. The silicon-containing compound has a low Young's modulus, which can reduce packaging stress and reduce the possibility of chip warping.

[0081] The silicon-containing compound may be a spin-on silicon oxide (SOG), a silicon-containing spin-on dielectric (SOD), or other silicon-containing spin-on materials.

[0082] In one embodiment, if Figure 1b As shown, the packaging structure further includes: an insulating layer 80 located between the side wall of the second contact pad 50 and the dielectric layer 20 ; the Young's modulus of the insulating layer 80 is smaller than the Young's modulus of the dielectric layer 20 .

[0083] In the actual manufacturing process, the material of the insulating layer can be an organic polymer, such as synthetic rubber, synthetic fiber, polyethylene, polyvinyl chloride, etc. By providing an insulating layer between the second contact pad and the dielectric layer, the insulating layer has good ductility and can be used as a buffer layer, which can reduce the pressure of the dielectric layer on the contact pad, thereby reducing bonding defects and improving bonding quality.

[0084] In some other embodiments, such as Figure 1a As shown, the semiconductor package structure may not include an insulating layer.

[0085] The number of second semiconductor chips stacked in the second semiconductor chip stacking structure 30 may be two, four, eight, twelve or sixteen. Figure 1a As shown, the number of the second semiconductor chips stacked in the second semiconductor chip stacking structure 30 is four.

[0086] In one embodiment, the semiconductor package structure further includes: fourth contact pads 70 located in the multi-layer second semiconductor chips above the first layer of second semiconductor chips 31; and the widths of the corresponding fourth contact pads 70 between two adjacent layers of second semiconductor chips are inconsistent.

[0087] like Figure 1aAs shown, the fourth contact pad 70 also includes a contact pad located on the side of the first-layer second semiconductor chip 31 away from the dielectric layer 20 .

[0088] By setting the sizes of the corresponding contact pads between two adjacent layers of second semiconductor chips to be inconsistent, it can be ensured that when the two adjacent layers of second semiconductor chips are aligned, the smaller contact pad can be in full contact with the larger contact piece, thereby improving the alignment accuracy and ensuring the relative constancy of the contact area.

[0089] In some embodiments, the widths of the fourth contact pads 70 in the same layer may be equal. In other embodiments, such as Figure 1a As shown, the widths of the fourth contact pads 70 in the same layer may also be different.

[0090] The semiconductor packaging structure further includes: a through silicon via 91 (TSV), which is located in the first semiconductor chip and the second semiconductor chip, specifically, between two opposite contact pads, and interconnects the chips through the contact pads and the TSV.

[0091] The semiconductor package structure further includes a fifth contact pad 92 located on a surface of the first semiconductor chip 10 away from the first contact pad 40 . The fifth contact pad 92 is connected to the first contact pad 40 via a through silicon via 91 .

[0092] A solder ball 93 is formed on the fifth contact pad 92 , and the solder ball 93 is used to connect the semiconductor package structure with other components.

[0093] The semiconductor packaging structure further includes: a packaging compound structure 100; the packaging compound structure 100 is located on the dielectric layer 20 and the second semiconductor chip stacking structure 30, and wraps the second semiconductor chip stacking structure 30. The packaging compound structure 100 may include a silicon-containing compound. By forming the packaging compound structure 100 that wraps the second semiconductor chip stacking structure 30, and the material of the packaging compound structure 100 is a silicon-containing compound, the warping problem of the second semiconductor chip stacking structure 30 can be reduced, thereby further improving the warping problem of the overall packaging structure.

[0094] The silicon-containing compound may be a spin-on silicon oxide (SOG), a silicon-containing spin-on dielectric (SOD), or other silicon-containing spin-on materials.

[0095] In the disclosed embodiment, hybrid bonding stacking is achieved by using a hybrid bond process technology between the first semiconductor chip and the second semiconductor chip, and between a plurality of second semiconductor chips, thereby improving the integration of the packaging structure.

[0096] The present disclosure also provides a method for forming a semiconductor packaging structure. Figure 2 , as shown in the figure, the method comprises the following steps:

[0097] Step 201: forming a first semiconductor chip; forming a plurality of first contact pads on a surface of the first semiconductor chip;

[0098] Step 202: forming a dielectric layer on the first semiconductor chip; forming a plurality of second contact pads in the dielectric layer;

[0099] Step 203: forming a second semiconductor chip stacking structure on the dielectric layer; the second semiconductor chip stacking structure comprises a plurality of second semiconductor chips stacked in sequence; forming a plurality of third contact pads on the surface of the first layer of second semiconductor chips;

[0100] Step 204: Bond the first semiconductor chip and the first layer second semiconductor chip one by one through the first contact pad, the second contact pad and the third contact pad; wherein the width of each second contact pad is inconsistent with the width of its corresponding first contact pad, and / or the width of the third contact pad.

[0101] The method for forming the semiconductor packaging structure provided by the embodiment of the present disclosure is further described in detail below in conjunction with specific embodiments.

[0102] Figures 3a to 3i A schematic diagram of the structure of a semiconductor package structure during the formation process provided by an embodiment of the present disclosure.

[0103] First, see Figure 3a , perform step 201 to form a first semiconductor chip 10; and form a plurality of first contact pads 40 on a surface of the first semiconductor chip.

[0104] Specifically, before forming the first contact pad 40, a plurality of silicon through vias 91 penetrating the first semiconductor chip 10 are first formed, and then one side surface of the first semiconductor chip 10 at the location where the silicon through vias 91 are formed is etched to form a plurality of first contact pad through holes (not shown in the figure); and then the first contact pad 40 is formed in the first contact pad through holes.

[0105] Continue to see Figure 3a After forming the first contact pad 40 , the method further includes: forming a fifth contact pad 92 on a surface of the first semiconductor chip 10 away from the first contact pad 40 . The fifth contact pad 92 is connected to the first contact pad 40 via a through silicon via 91 .

[0106] Continue to see Figure 3aThe method further includes: forming a solder ball 93 on the fifth contact pad 92, wherein the solder ball is used to connect the semiconductor package structure with other components.

[0107] Next, see Figure 3b and Figure 3c , executing step 202 , forming a dielectric layer 20 on the first semiconductor chip 10 ; and forming a plurality of second contact pads 50 in the dielectric layer 20 .

[0108] Specifically, the dielectric layer 20 is formed on the first semiconductor chip 10 by spin coating, and the material of the dielectric layer 20 includes a silicon-containing compound. The silicon-containing compound has a low Young's modulus, which can reduce packaging stress and reduce the possibility of chip warping.

[0109] The silicon-containing compound may be a spin-on silicon oxide (SOG), a silicon-containing spin-on dielectric (SOD), or other silicon-containing spin-on materials.

[0110] The method of forming a plurality of second contact pads 50 in the dielectric layer 20 includes: etching the dielectric layer 20 to form a plurality of through holes 501 ; and forming the second contact pads 50 in the through holes 501 .

[0111] Next, see Figure 3d The method further includes: after forming the second contact pad 50 , etching the second contact pad 50 , so that a gap 801 is formed between a side wall of the second contact pad 50 and a side wall of the through hole 501 .

[0112] In some other embodiments, the semiconductor package structure may not include the gap 801 .

[0113] Next, participate Figure 3e The method further includes: filling the gap 801 with an insulating material to form an insulating layer 80 ; the Young's modulus of the insulating layer 80 is smaller than the Young's modulus of the dielectric layer 20 .

[0114] In the actual manufacturing process, the material of the insulating layer can be an organic polymer, such as synthetic rubber, synthetic fiber, polyethylene, polyvinyl chloride, etc. By providing an insulating layer between the second contact pad and the dielectric layer, the insulating layer has good ductility and can be used as a buffer layer, which can reduce the pressure of the dielectric layer on the contact pad, thereby reducing bonding defects and improving bonding quality.

[0115] In some other embodiments, the semiconductor package structure may not include the insulating layer 80 .

[0116] Next, see Figure 3f, execute step 203 to form a second semiconductor chip stacking structure 30 on the dielectric layer 20; the second semiconductor chip stacking structure 30 includes multiple layers of second semiconductor chips stacked in sequence; and a plurality of third contact pads 60 are formed on the surface of the first layer of second semiconductor chips 31.

[0117] It should be noted that in Figure 3f to Figure 3h In the illustrated embodiment, a first layer of second semiconductor chips 31 is first formed, and then the first layer of second semiconductor chips 31 is bonded to the first semiconductor chip 10, and then other layers of second semiconductor chips are formed on the first layer of second semiconductor chips 31. In some other embodiments, a second semiconductor chip stacking structure 30 may be first formed, and then the second semiconductor chip stacking structure 30 is bonded to the first semiconductor chip 10.

[0118] The first semiconductor chip 10 is a logic chip, and the second semiconductor chip is a dynamic random access memory (DRAM) chip. The logic chip can be one or more processors configured to communicate with multiple DRAM chips to access data from the DRAM chips and store data in the multiple DRAM chips. The logic chip includes but is not limited to a graphics processing unit (GPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a central processing unit (CPU), or other known electronic circuits used as processors.

[0119] Specifically, see Figure 3f First, a first-layer second semiconductor chip 31 is formed, and then a plurality of silicon through vias 91 penetrating the first-layer second semiconductor chip 31 are formed. Next, a side surface of the first-layer second semiconductor chip 31 at the location where the silicon through vias 91 are formed is etched to form a plurality of third contact pad through holes (not shown in the figure), and then a third contact pad 60 is formed in the third contact pad through holes.

[0120] Next, see Figure 3g , execute step 204, and bond the first semiconductor chip 10 and the first-layer second semiconductor chip 31 one by one through the first contact pad 40, the second contact pad 50 and the third contact pad 60; wherein the width of each of the second contact pads 50 is inconsistent with the width of the corresponding first contact pad 40 and / or the third contact pad 60.

[0121] A dielectric layer is provided between the first semiconductor chip and the second semiconductor chip of the first layer, and the size of the second contact pad in the dielectric layer is inconsistent with the size of the corresponding first contact pad and / or the size of the third contact pad, so that during alignment, the contact pad with a smaller size can be in contact with the contact pad with a larger size, thereby improving the accuracy of alignment. In addition, the dielectric layer can increase the insulation between adjacent contact pads, reduce the possibility of coupling between adjacent contact pads, and solve the problem of metal diffusion.

[0122] In one embodiment, see Figure 3g The first contact pad 40 includes a first first contact pad 41 and a second first contact pad 42; the second contact pad 50 includes a first second contact pad 51 and a second second contact pad 52, and the width of the first second contact pad 51 is greater than the width of the second second contact pad 52; the third contact pad 60 includes a first third contact pad 61 and a second third contact pad 62; wherein the width of the first second contact pad 51 is greater than the width of the corresponding first first contact pad 41, and / or the width of the first third contact pad 61; the width of the second second contact pad 52 is less than the width of the corresponding second first contact pad 42, and / or the width of the second third contact pad 62.

[0123] In a group of corresponding first contact pads, second contact pads and third contact pads, if the size of the second contact pad is larger, the size of the first contact pad or the third contact pad is smaller, and if the size of the second contact pad is smaller, the size of the first contact pad or the third contact pad is larger. In this way, the size of the second contact pad is opposite to the corresponding first contact pad or the third contact pad, ensuring that the contact area of ​​the contact pad between the first semiconductor chip and the first layer second semiconductor chip after bonding is relatively constant, solving the problem of different contact areas due to misalignment.

[0124] In one embodiment, each first contact pad 40 has the same width as the corresponding third contact pad 60. The corresponding two first contact pads and the third contact pad have the same size, so that the contact area between the first contact pad and the third contact pad and the corresponding second contact pad is relatively consistent.

[0125] For example, see Figure 3g , the width of the first first contact pad 41 is consistent with the width of the first third contact pad 61 , and the width of the second first contact pad 42 is consistent with the width of the second third contact pad 62 .

[0126] In some other embodiments, the widths of the first contact pad and the corresponding third contact pad may also be inconsistent.

[0127] In one embodiment, the widths of the plurality of first contact pads 40 are not consistent; the widths of the plurality of second contact pads 50 are not consistent; and the widths of the plurality of third contact pads 60 are not consistent. In this way, even if there are size differences between the pads, between the corresponding contact pads, the smaller contact pad can be in contact with the larger contact pad, thereby ensuring that the contact area between the contact pads is relatively constant.

[0128] In one embodiment, a first contact pad 40 is formed on the active surface of the first semiconductor chip 10; a third contact pad 60 is formed on the active surface of the first layer second semiconductor chip 31; the active surface of the first semiconductor chip 10 is bonded to the active surface of the first layer second semiconductor chip 31; wherein the active surface is the side of the chip forming the device layer. Compared with bonding the active surface to the back surface, bonding the active surface of the first semiconductor chip to the active surface of the first layer second semiconductor chip shortens the transmission path between the chips and improves the transmission speed.

[0129] In some other embodiments, a first contact pad 40 is formed on the active surface of the first semiconductor chip 10, and a third contact pad 60 is formed on the inactive surface of the first layer second semiconductor chip 31; the active surface of the first semiconductor chip 10 is bonded to the inactive surface of the first layer second semiconductor chip 31, wherein the inactive surface is the surface opposite to the active surface. In this packaging structure, the active surfaces of the first semiconductor chip and the first layer second semiconductor chip are facing the same side. Compared with the method of bonding the active surfaces of the chips to the active surfaces, this embodiment does not require additional flipping of the first layer second semiconductor chip, thereby simplifying the packaging process.

[0130] Next, see Figure 3h , one or more layers of second semiconductor chips are stacked on the first layer of second semiconductor chips 31 to form a second semiconductor chip stacking structure 30 .

[0131] The number of second semiconductor chips stacked in the second semiconductor chip stacking structure 30 may be two, four, eight, twelve or sixteen. Figure 3h As shown, the number of the second semiconductor chips stacked in the second semiconductor chip stacking structure 30 is four.

[0132] In one embodiment, see Figure 3h , fourth contact pads 70 are formed in the multiple layers of second semiconductor chips above the first layer of second semiconductor chips 31; and the widths of the corresponding fourth contact pads 70 between two adjacent layers of second semiconductor chips are inconsistent.

[0133] like Figure 3hAs shown, the fourth contact pad 70 also includes a contact pad located on the side of the first-layer second semiconductor chip 31 away from the dielectric layer 20 .

[0134] By setting the sizes of the corresponding contact pads between two adjacent layers of second semiconductor chips to be inconsistent, it can be ensured that when the two adjacent layers of second semiconductor chips are aligned, the smaller contact pad can be in full contact with the larger contact piece, thereby improving the alignment accuracy and ensuring the relative constancy of the contact area.

[0135] Specifically, each layer of second semiconductor chips is formed first, and then a plurality of silicon through vias 91 penetrating each layer of the second semiconductor chips are formed. Next, the surface of the second semiconductor chip at the location where the silicon through vias 91 are formed is etched to form a plurality of fourth contact pad through holes (not shown in the figure); then, fourth contact pads 70 are formed in the fourth contact pad through holes, and then each layer of the second semiconductor chips is bonded one by one through the fourth contact pads 70.

[0136] The through silicon via 91 is located in the second semiconductor chip, specifically, between two opposite contact pads, and the chips are interconnected through the contact pads and the through silicon via.

[0137] Next, see Figure 3i , forming an encapsulation compound structure 100 on the dielectric layer 20 and the second semiconductor chip stacking structure 30, wherein the encapsulation compound structure 100 encapsulates the second semiconductor chip stacking structure 30. The encapsulation compound structure 100 may include a silicon-containing compound. By forming the encapsulation compound structure 100 encapsulating the second semiconductor chip stacking structure 30, and the material of the encapsulation compound structure 100 is a silicon-containing compound, the warping problem of the second semiconductor chip stacking structure 30 can be reduced, thereby further improving the warping problem of the overall packaging structure.

[0138] The silicon-containing compound may be a spin-on silicon oxide (SOG), a silicon-containing spin-on dielectric (SOD), or other silicon-containing spin-on materials.

[0139] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A semiconductor packaging structure, characterized in that: include: a first semiconductor chip; A plurality of first contact pads are formed on the surface of the first semiconductor chip; A plurality of through silicon vias, each of the through silicon vias penetrates the first semiconductor chip, and each of the through silicon vias is provided with the first contact pad on one side surface thereof; a dielectric layer, located on the first semiconductor chip; A plurality of second contact pads are formed in the dielectric layer; A second semiconductor chip stacking structure is located on the dielectric layer; the second semiconductor chip stacking structure comprises a plurality of second semiconductor chips stacked in sequence; A plurality of third contact pads are formed on the surface of the second semiconductor chip of the first layer; The first semiconductor chip and the first layer second semiconductor chip are bonded to each other via the first contact pad, the second contact pad and the third contact pad in a one-to-one correspondence; wherein, The first contact pads include a first first contact pad and a second first contact pad; The second contact pad includes a first second contact pad corresponding to the first first contact pad and a second second contact pad corresponding to the second first contact pad, and a width of the first second contact pad is greater than a width of the second second contact pad; The third contact pads include a first third contact pad corresponding to the first first contact pad and a second third contact pad corresponding to the second first contact pad; The width of the first second contact pad is greater than the width of the first first contact pad and the first third contact pad; the width of the second second contact pad is less than the width of the second first contact pad and the second third contact pad; The first first contact pad has the same width as the first third contact pad, and the second first contact pad has the same width as the second third contact pad.

2. The semiconductor package structure according to claim 1, wherein: The first contact pad is formed on the active surface of the first semiconductor chip, the third contact pad is formed on the active surface of the first layer second semiconductor chip, and the active surface of the first semiconductor chip is bonded to the active surface of the first layer second semiconductor chip; wherein the active surface is a side of the chip forming a device layer.

3. The semiconductor package structure according to claim 1, wherein: The material of the dielectric layer includes a silicon-containing compound.

4. The semiconductor package structure according to claim 1, wherein: Also includes: a fourth contact pad located within the plurality of second semiconductor chips above the first plurality of second semiconductor chips; The widths of the corresponding fourth contact pads between two adjacent layers of second semiconductor chips are inconsistent.

5. The semiconductor package structure according to claim 1, wherein: Also includes: an insulating layer, located between the side wall of the second contact pad and the dielectric layer; The Young's modulus of the insulating layer is smaller than the Young's modulus of the dielectric layer.

6. A method for forming a semiconductor packaging structure, characterized in that: include: forming a first semiconductor chip, wherein a plurality of through silicon vias penetrating the first semiconductor chip are formed in the first semiconductor chip; forming a corresponding first contact pad on a side surface of each of the through silicon vias; forming a dielectric layer on the first semiconductor chip; forming a plurality of second contact pads in the dielectric layer; forming a second semiconductor chip stacking structure on the dielectric layer; the second semiconductor chip stacking structure comprises a plurality of second semiconductor chips stacked in sequence; forming a plurality of third contact pads on the surface of the second semiconductor chip of the first layer; The first semiconductor chip and the first layer second semiconductor chip are bonded one by one through the first contact pad, the second contact pad and the third contact pad; wherein, The first contact pads include a first first contact pad and a second first contact pad; The second contact pad includes a first second contact pad corresponding to the first first contact pad and a second second contact pad corresponding to the second first contact pad, and a width of the first second contact pad is greater than a width of the second second contact pad; The third contact pads include a first third contact pad corresponding to the first first contact pad and a second third contact pad corresponding to the second first contact pad; The width of the first second contact pad is greater than the width of the first first contact pad and the first third contact pad; the width of the second second contact pad is less than the width of the second first contact pad and the second third contact pad; The width of each of the first contact pads is consistent with that of the corresponding third contact pad.

7. The method according to claim 6, characterized in that forming a first contact pad on an active surface of the first semiconductor chip; forming a third contact pad on the active surface of the second semiconductor chip of the first layer; The active surface of the first semiconductor chip is bonded to the active surface of the second semiconductor chip of the first layer; wherein the active surface is the side of the chip forming the device layer.

8. The method according to claim 6, characterized in that A dielectric layer is formed on the first semiconductor chip by spin coating, wherein the material of the dielectric layer includes a silicon-containing compound.

9. The method according to claim 6, characterized in that Also includes: forming a fourth contact pad in the plurality of layers of second semiconductor chips above the first layer of second semiconductor chips; The widths of the corresponding fourth contact pads between two adjacent layers of second semiconductor chips are inconsistent.

10. The method according to claim 6, characterized in that The method of forming a plurality of second contact pads in the dielectric layer comprises: Etching the dielectric layer to form a plurality of through holes; forming a second contact pad in the through hole; The method further comprises: After forming the second contact pad, the second contact pad is etched so that a gap is formed between a sidewall of the second contact pad and a sidewall of the through hole.

11. The method according to claim 10, characterized in that Also includes: Filling the gap with insulating material to form an insulating layer; The Young's modulus of the insulating layer is smaller than the Young's modulus of the dielectric layer.

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