Memory system package structure and method of manufacture

Abstract

Embodiments of the present disclosure provide a memory system package structure and a manufacturing method thereof. The memory system package structure includes at least one memory chip molding assembly, a memory controller, a plastic package layer encapsulating the memory chip molding assembly and the memory controller, and a redistribution layer. Each memory chip molding assembly includes a plurality of stacked memory dies, a molding layer encapsulating the plurality of memory dies, and one or more conductive pillars. The conductive pillars extend through the molding layer from a first end so that a second end of the conductive pillars is disposed on a first surface of the redistribution layer and in physical and electrical contact with the redistribution layer. A surface of the memory controller is provided with a plurality of external pads, and the memory controller is disposed on the first surface of the redistribution layer and in electrical contact with the redistribution layer via the external pads.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor memory technology, and more specifically, to a memory system packaging structure and manufacturing method. Background Technology

[0002] A memory system primarily consists of a memory die and a memory controller. In a specific example, a memory system may include a solid-state drive (SSD). The main function of the memory system package structure is to enclose the memory die and memory controller in a housing. This not only serves to install, fix, seal, and protect the memory die and memory controller, and enhance their electrical and thermal performance, but also connects wires to the pins of the package through bonding pads on the memory die and lead pads on the memory controller. These pins, in turn, connect to other devices on the circuit board, thus enabling the memory system to connect to external circuits. Since the quality of the memory system packaging technology directly affects the performance of the memory system itself, as well as the design and manufacturing of the circuit boards connected to the memory system, memory system packaging is of paramount importance.

[0003] However, traditional memory system packaging processes have many problems, which severely restrict the development of memory system packaging technology. Therefore, there is an urgent need to provide a new memory system packaging structure and manufacturing method. Summary of the Invention

[0004] In view of this, the present disclosure aims to provide a memory system packaging structure and manufacturing method.

[0005] The memory system packaging structure provided in this disclosure includes: at least one memory chip molding assembly, a memory controller, a molding layer encapsulating the memory chip molding assembly and the memory controller, and a redistribution layer; wherein,

[0006] Each of the memory chip molding assemblies includes a plurality of stacked memory dies, a molding layer encapsulating the plurality of memory dies, and one or more conductive pillars; a first end of the conductive pillar is disposed on and electrically contacts a bonding pad of at least one of the memory dies, and the conductive pillar extends from the first end through the molding layer such that a second end of the conductive pillar is disposed on a first surface of the redistribution layer and physically contacts and is electrically connected to the redistribution layer.

[0007] The memory controller has lead-out pads on its surface. The memory controller is disposed on the first surface of the redistribution layer and electrically connected to the redistribution layer via the lead-out pads.

[0008] In the above scheme, the at least one memory chip molding component includes a first memory chip molding component and a second memory chip molding component, and the memory controller is located between the first memory chip molding component and the second memory chip molding component.

[0009] In the above scheme, the distance between the memory controller and the first memory chip molding component is a first distance, and the distance between the memory controller and the second memory chip molding component is a second distance; the first distance and the second distance are equal.

[0010] In the above scheme, the first memory chip molding assembly, the second memory chip molding assembly, and the memory controller are located on a first straight line within the first surface.

[0011] In the above scheme, the first memory chip molding assembly includes a plurality of first memory dies offset by a third distance along a first direction, and the second memory chip molding assembly includes a plurality of second memory dies offset by a fourth distance along a second direction; the first direction and the second direction are both perpendicular to the direction in which the plurality of memory dies are stacked, and the first direction is opposite to the second direction.

[0012] In the above scheme, the number of the first memory dies is the same as the number of the second memory dies; the third distance is equal to the fourth distance.

[0013] In the above scheme, the memory system packaging structure includes a memory chip molding assembly, and the memory controller is located on one side of the memory chip molding assembly.

[0014] In the above scheme, each memory chip molding assembly includes a conductive post, the first end of which is disposed on and electrically contacted with the bonding pad of one of the plurality of memory dies, and the remaining memory dies in the plurality of memory dies are electrically connected to the first end of the conductive post through bonding leads;

[0015] or,

[0016] Each of the memory chip molding components includes a plurality of conductive pillars, and for each of the memory dies, the first end of the plurality of conductive pillars is respectively disposed on and electrically contacted on the bonding pad of the corresponding memory die.

[0017] In the above scheme, the memory system packaging structure further includes:

[0018] Metal solder balls located on the second surface of the redistribution layer and electrically connected to the memory chip molding assembly and the memory controller through the redistribution layer; the second surface is opposite to the first surface.

[0019] In the above scheme, the memory system packaging structure further includes passive devices encapsulated in the molding layer, the passive devices being disposed on the first surface of the redistribution layer and electrically connected to the redistribution layer.

[0020] In the above scheme, the memory die includes a three-dimensional NAND flash memory die.

[0021] In the above scheme, the material of the encapsulation layer is the same as the material of the molding layer.

[0022] In the above scheme, the at least one memory chip molding component includes a first memory chip molding component and a second memory chip molding component, the first memory chip molding component and the second memory chip molding component are arranged on both sides of the memory controller and are substantially symmetrical about the center line of the memory controller.

[0023] In the above scheme, the at least one memory chip molding component includes a first memory chip molding component and a second memory chip molding component, and the first memory chip component and the second memory chip component have the same internal structure.

[0024] This disclosure also provides a method for manufacturing a memory system package structure, the method comprising:

[0025] At least one memory chip molding assembly and a memory controller are provided; wherein each memory chip molding assembly includes a plurality of stacked memory dies, a molding layer encapsulating the plurality of memory dies, and one or more conductive pillars; a first end of the conductive pillar is disposed on and electrically contacts a bonding pad of at least one of the memory dies; and the surface of the memory controller is provided with lead-out pads;

[0026] The at least one memory chip molding assembly and the memory controller are encapsulated in a molding layer; wherein the conductive post extends from the first end through the molding layer such that the second end of the conductive post and the lead pad are both exposed on the same surface of the molding layer;

[0027] A redistribution layer is formed on the same surface of the molding compound; wherein the second end of the conductive pillar and the lead-out pad are both disposed on the first surface of the redistribution layer and electrically connected to the redistribution layer.

[0028] In the above solution, providing at least one memory chip molding component includes:

[0029] Provide the primary carrier;

[0030] Multiple memory dies are sequentially stacked on the first carrier;

[0031] One or more conductive posts are formed on at least one bonding pad of the plurality of memory dies, with the first end electrically connected to the bonding pad;

[0032] A molding layer is formed to encapsulate the plurality of memory dies and the conductive pillars;

[0033] Remove the first carrier;

[0034] Remove part of the molding layer to expose the second end of the one or more conductive pillars.

[0035] In the above scheme, at least one memory chip molding component includes a first memory chip molding component and a second memory chip molding component; providing at least one memory chip molding component includes:

[0036] Provide the primary carrier;

[0037] Multiple first memory dies and multiple second memory dies are stacked sequentially on the first carrier; the multiple first memory dies and multiple second memory dies are arranged side by side on the first carrier;

[0038] One or more conductive posts are formed on at least one bonding pad of the plurality of first memory dies, with the first end electrically connected to the bonding pad;

[0039] One or more conductive posts are formed on at least one bonding pad of the plurality of second memory dies, with the first end electrically connected to the bonding pad;

[0040] A molding layer is formed to encapsulate the plurality of first memory dies, the plurality of second memory dies, and the conductive pillars;

[0041] Remove the first carrier;

[0042] Remove part of the molding layer to expose the second end of the one or more conductive pillars;

[0043] Cut the molding layer to obtain a first memory chip molding assembly including a plurality of first memory dies and a second memory chip molding assembly including a plurality of second memory dies.

[0044] In the above solution, encapsulating the at least one memory chip molding component and the memory controller in a molding compound includes:

[0045] Provide a second carrier;

[0046] At least one memory chip molding assembly and a memory controller are mounted on the surface of the second carrier, such that the second end of the conductive pillar in the memory chip molding assembly and the lead-out pad of the memory controller are both located on the same surface of the second carrier.

[0047] A molding layer is formed to encapsulate the memory chip molding assembly and the memory controller;

[0048] Remove the second carrier.

[0049] The method in the above scheme further includes:

[0050] Metal solder balls are formed on the second surface of the redistribution layer, and the metal solder balls are electrically connected to the memory chip molding assembly and the memory controller located on the first surface of the redistribution layer through the redistribution layer; the second surface and the first surface are opposite to each other.

[0051] In the above scheme, the memory system packaging structure includes a first memory chip molding assembly and a second memory chip molding assembly;

[0052] The process of encapsulating the at least one memory chip molding component and the memory controller in a molding compound includes:

[0053] The first memory chip molding assembly, the second memory chip molding assembly, and the memory controller are encapsulated in the molding layer; wherein the memory controller is located between the first memory chip molding assembly and the second memory chip molding assembly.

[0054] In the above scheme, the distance between the memory controller and the first memory chip molding component is a first distance, and the distance between the memory controller and the second memory chip molding component is a second distance; the first distance and the second distance are equal.

[0055] In the above scheme, the first memory chip molding assembly, the second memory chip molding assembly, and the memory controller are located on a first straight line within the first surface.

[0056] In the above scheme, the first memory chip molding assembly includes a plurality of first memory dies offset by a third distance along a first direction, and the second memory chip molding assembly includes a plurality of second memory dies offset by a fourth distance along a second direction; the first direction and the second direction are both perpendicular to the direction in which the plurality of memory dies are stacked; the first direction is opposite to the second direction.

[0057] In the above scheme, the number of the first memory dies is the same as the number of the second memory dies; the third distance is equal to the fourth distance.

[0058] In the above scheme, the memory system packaging structure includes a memory chip molding assembly;

[0059] The process of encapsulating the at least one memory chip molding component and the memory controller in a molding compound includes:

[0060] A memory chip molding assembly and a memory controller are encapsulated in a molding layer; wherein the memory controller is located on one side of the memory chip molding assembly. Attached Figure Description

[0061] Figure 1a This is a schematic diagram of the packaging structure of a memory die wire bonding process in related technologies;

[0062] Figure 1b This is a schematic diagram of the TSV process packaging structure for memory dies in related technologies;

[0063] Figure 1c This is a schematic diagram of the appearance of a memory die fan-out package structure provided in an embodiment of the present disclosure;

[0064] Figure 1d This is a schematic diagram of the layer structure of a memory die fan-out package structure provided in an embodiment of the present disclosure;

[0065] Figure 2 A schematic flowchart illustrating a method for manufacturing a memory system packaging structure according to an embodiment of this disclosure;

[0066] Figures 3a-3l A schematic diagram illustrating the implementation steps of a method for manufacturing a memory system packaging structure according to an embodiment of this disclosure;

[0067] Figure 4a This is a cross-sectional schematic diagram of a memory system packaging structure provided in an embodiment of the present disclosure;

[0068] Figure 4b This is a top view schematic diagram of a memory system packaging structure provided in an embodiment of the present disclosure;

[0069] Figure 5 This is a cross-sectional schematic diagram of a memory system packaging structure provided in an embodiment of the present disclosure;

[0070] Figure 6a A cross-sectional schematic diagram of another memory system packaging structure provided in this disclosure embodiment;

[0071] Figure 6bA cross-sectional schematic diagram of another memory system packaging structure provided in this disclosure embodiment;

[0072] Figure 6c This is a cross-sectional schematic diagram of another memory system packaging structure provided in an embodiment of the present disclosure. Detailed Implementation

[0073] The technical solution of this disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0074] In the description of this disclosure, it should be understood that the terms “length,” “width,” “depth,” “upper,” “lower,” “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0075] In embodiments of this disclosure, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include various semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0076] In embodiments of this disclosure, the term "layer" refers to a portion of material including a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0077] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0078] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0079] In related technologies, traditional packaging technologies for memory dies generally use wire bonding (WB) and through-silicon via (TSV) processes. For example... Figure 1a As shown, the wire bonding process includes bonding multiple memory dies and forming wire loops on the surface of the memory dies; as Figure 1b The TSV process shown includes forming multiple through-silicon vias (TSVs) through the memory dies in a stack of multiple memory dies. However, traditional packaging technologies for memory dies have the following problems: (1) The wire bonding process increases the area of ​​the entire package structure by more than 20% due to the presence of bent wires between the pads and the substrate; (2) The wire bonding process has a long conductive path, which limits the high-frequency performance of the memory die; (3) The wire arcs in the wire bonding process occupy a certain package height, which affects the design of the package structure; (4) The wire bonding process has a long production time (CT), requiring a certain number of wire bonding machines; (5) The semiconductor substrate (SBT) needs to have ultra-small line width / space, and the cost increases exponentially with the reduction of line width / space size; (6) The SBT fabrication process requires drilling holes, which will not be filled with metal in subsequent fabrication processes, thereby increasing the resistance and affecting the high-frequency performance of the product; (7) The TSV process requires the coordination of chip design and chip packaging, which is technically difficult and costly.

[0080] The emergence of fan-out packaging structures for memory dies and the development of packaging materials in recent years are expected to drive the development of memory die packaging technology. Figure 1c This is a schematic diagram of the external appearance of a memory die fan-out package structure in one embodiment; Figure 1d This is a schematic diagram of the layers of a memory die fan-out package structure in one embodiment. For example... Figure 1c and Figure 1d As shown, the manufacturing method of a fan-out package structure for a memory die generally includes: providing a substrate and forming an adhesive layer on the substrate surface; photolithographically and electroplating a redistribution layer (RDL) on the adhesive layer; mounting the memory die onto the redistribution layer using a bonding process; encapsulating the memory die in a molding compound layer using an injection molding process; removing the substrate and adhesive layer; photolithographically and electroplating an under bump metal layer (UBM) on the redistribution layer; and performing ball reflow on the UBM to form metal solder balls.

[0081] Fan-out packaging structures for memory dies can effectively save package space. Furthermore, the redistribution layer in a fan-out package can enhance performance, such as heat dissipation and high frequency. However, current fan-out packaging structures generally do not support system-in-a-package (SIP) for stacked memory dies; and the manufacturing process for SIP in related technologies is relatively complex.

[0082] In the memory system packaging structure provided in this embodiment, the memory chip molding assembly is physically contacted and electrically connected to the redistribution layer through conductive pillars. The memory controller is disposed on the first surface of the redistribution layer and electrically connected to the redistribution layer. On the one hand, since both the memory chip molding assembly and the memory controller are disposed on the first surface of the redistribution layer and electrically connected to the redistribution layer, the overall line spacing is relatively short, which shortens the signal transmission path between the memory chip molding assembly and the memory controller and external devices. Therefore, the resulting memory system packaging structure has better high-frequency performance. On the other hand, the memory controller does not need to be wire-bonded, which simplifies the memory system packaging process.

[0083] This disclosure provides a method for manufacturing a memory system package structure. Figure 2 This is a schematic diagram of a manufacturing method for a memory system packaging structure provided in an embodiment of this application. Figure 2 As shown, the method includes the following steps:

[0084] Step 201: Provide at least one memory chip molding assembly and a memory controller; wherein each memory chip molding assembly includes a plurality of stacked memory dies, a molding layer encapsulating the plurality of memory dies, and one or more conductive pillars; a first end of the conductive pillar is disposed on and electrically contacts a bonding pad of at least one memory die; the surface of the memory controller is provided with lead-out pads;

[0085] Step 202: Encapsulate the at least one memory chip molding assembly and memory controller in a molding compound; wherein the conductive post extends from the first end through the molding compound such that the second end of the conductive post and the lead-out pad are both exposed on the same surface of the molding compound;

[0086] Step 203: A redistribution layer is formed on the same surface of the molding compound; wherein the second end of the conductive pillar and the lead-out pad are both disposed on the first surface of the redistribution layer and electrically connected to the redistribution layer.

[0087] Figures 3a-3l This is a cross-sectional schematic diagram illustrating the implementation steps of a method for manufacturing a memory system packaging structure according to an embodiment of this disclosure. It should be understood that... Figure 2 The operations shown are not exclusive; other operations can be performed before, after, or between any of the operations shown. The following is in conjunction with... Figure 2 , Figures 3a-3l This embodiment describes a method for manufacturing the memory system package structure.

[0088] First, perform step 201, such as... Figure 3f As shown, at least one memory chip molding assembly 10 is provided; each memory chip molding assembly 10 includes a plurality of stacked memory dies 102, a molding layer 104 encapsulating the plurality of memory dies 102, and at least one conductive post 103 extending from the memory die 102 through the molding layer 104; each memory die 102 has at least one bonding pad 105 not covered by adjacent memory dies 102 on its surface; a first end of the conductive post 103 is disposed on and electrically contacts the bonding pad 105 of at least one memory die, and a second end may be exposed on the surface of the molding layer 104.

[0089] In one specific example, the plurality of memory dies 102 may be, but are not limited to, NAND flash memory dies; each of the plurality of memory dies 102 includes an insulating layer on its side and bottom surfaces to isolate each memory die 102; the material of the molding layer 104 may include epoxy molding compound (EMC); the conductive pillars 103 are perpendicular to the surface of the memory die 102, and the material of the conductive pillars 103 may include at least one conductive material, such as gold, copper, aluminum, silver and / or other suitable metallic materials.

[0090] In one specific example, each of the memory chip molding components 10 includes a plurality of memory dies 102, and the electrical connection between the plurality of memory dies 102 and the conductive posts 103 includes a variety of methods.

[0091] In one embodiment, each of the memory chip molding components 10 includes a conductive post 103, which is electrically contacted with a bonding pad 105 of one of the plurality of memory dies 102, and the remaining memory dies 102 are electrically connected to the conductive post 103 via bonding leads.

[0092] In a specific example, when each of the memory chip molding components 10 includes a plurality of conductive pillars 103, the electrical connection between the plurality of memory dies 102 and the plurality of conductive pillars 103 can include a variety of methods.

[0093] In one embodiment, each memory chip molding assembly 10 includes a plurality of conductive pillars 103, which are electrically contacted with bonding pads 105 of a portion of the memory dies 102, and the remaining memory dies 102 are electrically connected to the plurality of conductive pillars 103 via bonding leads.

[0094] In one embodiment, each of the memory chip molding components 10 includes a plurality of conductive posts 103, and for each of the memory dies 102, the plurality of conductive posts 103 are electrically contacted with the bonding pads 105 of the corresponding memory die 102.

[0095] In one embodiment, providing at least one memory chip molding assembly 10 includes:

[0096] Provide the first carrier 101;

[0097] Multiple memory dies 102 are sequentially stacked on the first carrier 101;

[0098] One or more conductive posts 103 are formed on at least one bonding pad 105 of the plurality of memory dies 102, with the first end electrically connected to the bonding pad 105;

[0099] A molding layer 104 is formed to encapsulate the plurality of memory dies 102 and the conductive pillars 103;

[0100] Remove the first carrier 101;

[0101] Remove part of the molding layer 104 to expose the second end of the one or more conductive pillars 103.

[0102] In a specific example, such as Figure 3a As shown, a first carrier 101 is provided. In a specific example, the first carrier 101 further includes a temporary bonding film.

[0103] like Figure 3b As shown, next, a plurality of memory dies 102 are stacked sequentially on the first carrier 101, and each memory die 102 has at least one bonding pad 105 not covered by the adjacent memory die 102 on its surface.

[0104] In one specific example, the plurality of memory dies 102 are attached face up to a temporary bonding film on a first carrier 101. Here, the side of the memory die 102 containing the bonding pads 105 is the front side of the memory die 102.

[0105] In one specific example, the plurality of memory dies 102 can be offset in any direction parallel to the surfaces of the plurality of memory dies 102. Specifically, the bonding pads 105 on the surface of the other memory die 102 can be exposed by offsetting one of the two adjacent memory dies 102 along the stacking direction.

[0106] Next, as Figure 3c As shown, at least one conductive post 103 is formed on at least one bonding pad 105 of the plurality of memory dies 102, one end of which is electrically connected to the bonding pad 105.

[0107] In one specific example, the conductive post 103 is perpendicular to the surface of the memory die 102 and makes electrical contact with at least one bonding pad 105 of the memory die 102. Here, electrical contact can be understood as two structures contacting and being electrically connected.

[0108] Next, as Figure 3d As shown, a molding layer 104 is formed to encapsulate the plurality of memory dies 102 and the conductive pillars 103. In a specific example, the molding layer 104 may completely cover the plurality of memory dies 102 and the conductive pillars 103, and the molding layer 104 may protect the plurality of memory dies 102 and reduce physical and / or chemical damage (such as oxidation, damage caused by moisture) to the plurality of memory dies 102.

[0109] In one specific example, the material of the molding layer 104 includes EMC, and it will be understood that the specific material used for the molding layer 104 is not limiting.

[0110] Next, as Figure 3e As shown, the first carrier 101 is removed.

[0111] Next, as Figure 3f As shown, a portion of the molding layer 104 is removed to expose the second ends of the one or more conductive pillars 103. In an alternative embodiment, a portion of the molding layer 104 may be removed first, followed by the removal of the first carrier 101.

[0112] In one specific example, a portion of the molding layer 104 can be removed by grinding, thereby exposing the second end of the at least one conductive pillar 103, thus forming the memory chip molding assembly 10. In another specific example, when the molding layer 104 simultaneously encapsulates multiple memory chip molding assemblies 10, it can also be divided into multiple portions that individually encapsulate a single memory chip molding assembly 10, depending on subsequent process requirements. For example, […]. Figure 3fThe molding layer 104 is divided into two parts, each part encapsulating a memory chip molding assembly 10. It should be noted that... Figures 3b to 3l The number of memory chip molding components 10 shown is for illustrative purposes only and is not intended to limit the number of memory chip molding components 10 in the embodiments of this disclosure.

[0113] In one specific example, a first carrier 101 is provided; a plurality of first memory dies and a plurality of second memory dies are sequentially stacked on the first carrier 101; the plurality of first memory dies and the plurality of second memory dies are arranged side by side on the first carrier 101; one or more conductive pillars 103 with first ends electrically connected to the bonding pads 105 are formed on at least one bonding pad 105 of the plurality of first memory dies; one or more conductive pillars 103 with first ends electrically connected to the bonding pads are formed on at least one bonding pad 105 of the plurality of second memory dies; a molding layer 104 is formed to encapsulate the plurality of first memory dies, the plurality of second memory dies, and the conductive pillars 103; the first carrier 101 is removed; a portion of the molding layer 104 is removed to expose the second ends of the one or more conductive pillars 103; the molding layer 104 is cut to obtain a plurality of first memory chip molding assemblies including a plurality of first memory dies and / or a plurality of second memory chip molding assemblies including a plurality of second memory dies. In an alternative embodiment, multiple sequentially stacked memory dies 102 can be formed in the same molding layer 104, and the molding layer 104 can be cut to obtain multiple memory chip molding assemblies 10.

[0114] In the above embodiments, multiple memory chip molding components 10 can be formed through the same molding layer 104. That is, multiple memory chip molding components 10 can be formed in the same process, i.e., multiple memory chip molding components 10 can be formed simultaneously, thereby greatly improving production efficiency and reducing production costs.

[0115] In a specific example, because multiple memory dies 102 are stacked together, the footprint of the memory chip molding assembly 10 can be reduced. The memory chip molding assembly 10 uses conductive post 103 connection technology, instead of conventional wire bonding technology (i.e., bent wires bonded between pads and bonding substrates), which further reduces the offset dimensions of each memory chip in the memory chip molding assembly 10 (because the ends of the bent wires cannot be too close together), and also shortens the signal transmission path between the memory chip molding assembly 10 and external devices. Furthermore, the conductive post connection technology avoids the bonding substrate used in conventional wire bonding technology, saving the time and economic costs associated with bonding substrates. In addition, in the manufacturing process of the memory chip molding assembly 10, conventional wire bonding technology is more complex than conductive post connection technology; therefore, when there is offset of the memory die 102, the reliability of the conductive post 103 formation is higher than that of conventional wire bonding technology.

[0116] In step 201, a memory controller 21 for controlling the plurality of memory chip molding assemblies 10 is also required, wherein the surface 211 of the memory controller 21 is provided with lead-out pads 210.

[0117] In a specific example, such as Figure 3h As shown, the memory system package structure also includes one or more passive devices 212 encapsulated in the molding compound 22. The passive devices 212 are disposed on the first surface 231 of the redistribution layer 23 and electrically connected to the redistribution layer 23. In a specific example, the passive devices 212 include capacitors, resistors, inductors, etc. It will be understood that the specific number, arrangement position on the first surface 231, and type of the passive devices 212 can be specifically selected and set according to the function of the memory system package structure.

[0118] Next, proceed to step 202, refer to... Figure 3j The at least one memory chip molding assembly 10 and the memory controller 21 are encapsulated in a molding compound 22. The second ends of the conductive pillars 103 in the memory chip molding assembly 10 and the lead-out pads 210 of the memory controller 21 are both exposed on the same surface 221 of the molding compound 22. By exposing the second ends of the conductive pillars 103 in the memory chip molding assembly 10 and the lead-out pads 210 of the memory controller 21 on the same surface 221 of the molding compound 22, in subsequent manufacturing processes, while the second ends of the conductive pillars 103 in the memory chip molding assembly 10 are in electrical contact with the redistribution layer 23, the lead-out pads 210 of the memory controller 21 can be directly electrically connected to the redistribution layer 23, thereby shortening the signal transmission path of the memory controller 21.

[0119] In one embodiment, encapsulating the at least one memory chip molding assembly 10 and the memory controller 21 in a molding compound 22 includes:

[0120] Provide a second carrier 201;

[0121] At least one memory chip molding assembly 10 and a memory controller 21 are mounted on the surface of the second carrier 201, such that the second end of the conductive post 103 in the memory chip molding assembly 10 and the lead-out pad 210 of the memory controller 21 are both located on the same surface of the second carrier 201.

[0122] A molding layer 22 is formed to encapsulate the memory chip molding assembly 10 and the memory controller 21;

[0123] Remove the second carrier 201.

[0124] In a specific example, such as Figure 3g As shown, a second carrier 201 is provided. In a specific example, the second carrier 201 further includes a temporary bonding film. Here, the temporary bonding film includes an adhesive layer for bonding the memory chip molding assembly 10 and the memory controller 21 in subsequent processes.

[0125] Next, at least one memory chip molding assembly 10 and a memory controller 21 are mounted on the surface of the second carrier 201, such that the second end of the conductive post 103 in the memory chip molding assembly 10 and the lead-out pad 210 of the memory controller 21 are both located on the same surface of the second carrier 201.

[0126] In a specific example, the memory chip molding assembly 10 and the memory controller 21 are attached face down to the temporary bonding film of the first carrier 101. Here, the side containing the second end of the conductive post 103 of the memory chip molding assembly 10 is the front side of the memory chip molding assembly 10; the side containing the lead-out pad 210 of the memory controller 21 is the front side of the memory controller 21. It is understood that when the first carrier 101 and the temporary bonding film on the first carrier 101 are removed in subsequent processes, the second end of the conductive post 103 of the memory chip molding assembly 10 and the lead-out pad 210 of the memory controller 21 will be exposed, thereby facilitating electrical connection with the redistribution layer 23.

[0127] In one specific example, the memory system package structure may include one or more memory chip molding components 10. When the memory system package structure includes multiple memory chip molding components 10, the arrangement of the memory chip molding components 10 and the memory controller 21 mounted on the surface of the second carrier 201 may include various methods. The following will describe the arrangement of the memory system package structure including two memory chip molding components 10 and one memory chip molding component 10.

[0128] In one embodiment, such as Figure 3h As shown, at least one memory chip molding assembly includes a first memory chip molding assembly 10A and a second memory chip molding assembly 10B. The first memory chip molding assembly 10A, the second memory chip molding assembly 10B, and the memory controller 21 are attached face down to a temporary bonding film on the first carrier 101; wherein, the memory controller 21 is located between the first memory chip molding assembly 10A and the second memory chip molding assembly 10B.

[0129] In one embodiment, the distance between the memory controller 21 and the first memory chip molding assembly 10A is a first distance, and the distance between the memory controller 21 and the second memory chip molding assembly 10B is a second distance; the first distance and the second distance are equal.

[0130] It is understood that the memory controller 21 is located between the first memory chip molding assembly 10A and the second memory chip molding assembly 10B, and the first memory chip molding assembly 10A and the second memory chip molding assembly 10B are arranged substantially symmetrically based on the memory controller 21. That is, the signal path from the first memory chip molding assembly 10A to the memory controller 21 and the signal path from the second memory chip molding assembly 10B to the memory controller 21 can be substantially symmetrical and consistent, thereby improving the high-frequency performance of the memory system packaging structure.

[0131] It should be noted that, in the embodiments of this disclosure, the basic symmetrical arrangement of the first memory chip molding assembly 10A and the second memory chip molding assembly 10B based on the memory controller 21 can be understood as follows: excluding cases where some components are not perfectly symmetrically arranged due to manufacturing processes, the main components in the first memory chip molding assembly 10A and the main components in the second memory chip molding assembly 10B are symmetrically arranged based on the memory controller 21, but a certain offset is allowed within a certain error range. Specifically, when there is a certain offset between the components in the first memory chip molding assembly 10A or the components in the second memory chip molding assembly 10B, it does not affect the symmetrical distribution of the signal paths from the first memory chip molding assembly 10A and the second memory chip molding assembly 10B to the memory controller 21.

[0132] In one embodiment, the first distance and the second distance are equal, and the first memory chip molding assembly 10A, the second memory chip molding assembly 10B, and the memory controller 21 are located on a first straight line within the first surface 231. That is, compared to the case where the first memory chip molding assembly 10A, the second memory chip molding assembly 10B, and the memory controller 21 are not located on the same straight line, the signal path from the first memory chip molding assembly 10A to the memory controller 21 is shorter than the signal path from the second memory chip molding assembly 10B to the memory controller 21.

[0133] In one embodiment, the first memory chip molding assembly 10A includes a plurality of first memory dies 102A offset by a third distance along a first direction, and the second memory chip molding assembly 10B includes a plurality of second memory dies 102B offset by a fourth distance along a second direction; the first direction and the second direction are both perpendicular to the direction in which the plurality of memory dies 102 are stacked; the first direction is opposite to the second direction.

[0134] It is understood that in the above embodiments, not only are the first memory chip molding assembly 10A and the second memory chip molding assembly 10B arranged symmetrically based on the memory controller 21, but also the plurality of memory dies 102 in the first memory chip molding assembly 10A and the plurality of memory dies 102 in the second memory chip molding assembly 10B are arranged substantially symmetrically based on the center line AA of the memory controller 21. Thus, the signal path from the first memory chip molding assembly 10A to the memory controller 21 and the signal path from the second memory chip molding assembly 10B to the memory controller 21 can be substantially symmetrical and consistent, further improving signal integrity and the high-frequency performance of the memory system packaging structure.

[0135] In one embodiment, such as Figure 3h As shown, the number of first memory dies 102A is the same as the number of second memory dies 102B; the third distance is equal to the fourth distance. Here, the number of memory dies included in the first memory chip molding assembly 10A and the second memory chip molding assembly 10B is the same, and the distance by which the plurality of first memory dies 102A in the first memory chip molding assembly 10A are offset along the first direction is equal to the distance by which the plurality of second memory dies 102B in the second memory chip molding assembly 10B are offset along the second direction. The first memory chip molding assembly 10A and the second memory chip molding assembly 10B can have the same internal structure. The multiple memory dies 102 in the first memory chip molding assembly 10A and the multiple memory dies 102 in the second memory chip molding assembly 10B are arranged symmetrically based on the center line AA of the memory controller 21. Thus, the signal paths from each memory die in the first memory chip molding assembly 10A to the memory controller 21 are symmetrical and consistent with the signal paths from each memory die in the second memory chip molding assembly 10B to the memory controller 21, resulting in good signal integrity from the perspective of the memory system.

[0136] In one embodiment, the first memory chip molding assembly 10A and the second memory chip molding assembly 10B may be the same memory chip module, which has the same internal structure, the same memory die, etc., and is respectively arranged around the two sides of the memory controller 21 where the corresponding lead-out pads 210 are provided, and is arranged symmetrically based on the center line AA of the memory controller 21.

[0137] The above describes the arrangement of two memory chip molding components 10 in a memory system package structure. It should be noted that... Figure 3h The diagram shows an example of a memory system package (MSP) structure including two memory chip molding assemblies 10. The following describes an MSP structure including a single memory chip molding assembly 10.

[0138] In one embodiment, the memory system packaging structure includes a memory chip molding assembly 10. The memory chip molding assembly 10 and a memory controller 21 are attached face down to a temporary bonding film on a first carrier 101; wherein the memory controller 21 is located on one side of the memory chip molding assembly 10.

[0139] Next, as Figure 3i As shown, a molding layer 22 is formed to encapsulate the memory chip molding assembly 10 and the memory controller 21.

[0140] In one specific example, the molding compound 22 encapsulates the memory chip molding assembly 10 and the memory controller 21. The molding compound 22 protects the memory chip molding assembly 10 and the memory controller 21 and reduces physical and / or chemical damage (such as oxidation or moisture-induced damage) to them. The molding compound 22 includes, but is not limited to, EMC (Electromagnetic Compatibility) protection.

[0141] In one specific example, the molding layer 22 and the molding layer 104 may be made of the same or different materials. Specifically, the materials of both the molding layer 22 and the molding layer 104 may include EMC or Ajinomoto Build-up Film (ABF film).

[0142] Next, as Figure 3j As shown, the second carrier 201 is removed, so that the second end of the conductive post 103 in the memory chip molding assembly 10 and the lead-out pad 210 of the memory controller 21 are both exposed on the same surface 221 of the molding compound 22. Here, the same surface 221 of the molding compound 22 is the surface of the molding compound 22 that contacts the second carrier 201.

[0143] Next, proceed to step 203, as follows: Figure 3k As shown, a redistribution layer 23 is formed on the same surface 221 of the molding compound; wherein, the memory chip molding assembly 10 is physically in contact with and electrically connected to the redistribution layer 23 through the second end of the conductive post 103, and the memory controller 21 is disposed on the first surface 231 of the redistribution layer 23 through the lead-out pad 210 and electrically connected to the redistribution layer 23.

[0144] In one specific example, the redistribution layer 23 may include at least one conductive layer and at least one insulating layer. The conductive layer may be electrically connected to a second end of the conductive post 103. The conductive layer may include a metal, any other suitable conductive material, or a combination thereof, and the insulating layer may include organic or inorganic materials (such as silicon oxide, silicon nitride, silicon oxynitride, any other suitable insulating material, or a combination thereof).

[0145] It is understood that in the aforementioned process, the second end of the conductive pillar 103 in the memory chip molding assembly 10 and the lead-out pad 210 of the memory controller 21 are both exposed on the same surface 221 of the molding layer 22. Thus, when the redistribution layer 23 is formed in step 203, the memory controller 21 can be electrically connected to the redistribution layer 23 by soldering, thereby shortening the signal transmission path of the memory controller 21 and improving the high-frequency performance of the memory system packaging structure.

[0146] Next, as Figure 3l As shown, metal solder balls 24 are formed on the second surface 232 of the redistribution layer 23. The metal solder balls 24 are electrically connected to the memory chip molding assembly 10 and the memory controller 21 located on the first surface 231 of the redistribution layer 23 through the redistribution layer 23. The second surface 232 and the first surface 231 are opposite to each other.

[0147] In one specific example, in the redistribution layer 23, the insulating layer may have multiple openings to expose multiple portions of the conductive layer. The memory system package structure may further include multiple solder balls 24 in contact with the exposed portions of the conductive layer. That is, the solder balls 24 correspond to the multiple openings in the insulating layer. In this case, the solder balls 24 can function as signal input / output terminals. Through the solder balls 24 (i.e., signal input / output terminals), signals from external devices can be input into the memory system package structure, and / or signals from the memory system package structure can be output to external devices. Here, the solder balls 24 can be electrically connected to the at least one conductive post 103 and the memory controller 21.

[0148] It should be noted that although an exemplary method for forming a memory system package structure is described herein, it is understood that one or more steps may be omitted from the process of forming this memory system package structure.

[0149] Based on the above-described method for manufacturing a memory system packaging structure, this disclosure also provides a memory system packaging structure. Figure 4a This is a cross-sectional schematic diagram of a memory system packaging structure provided in an embodiment of the present disclosure; Figure 4b This is a top view schematic diagram of a memory system packaging structure provided in an embodiment of this disclosure. Figure 4a and Figure 4b As shown, the memory system packaging structure includes: at least one memory chip molding assembly 10, a memory controller 21, a molding layer 22 encapsulating the memory chip molding assembly 10 and the memory controller 21, and a redistribution layer 23; wherein, each memory chip molding assembly 10 includes a plurality of stacked memory dies 102, a molding layer 104 encapsulating the plurality of memory dies 102, and one or more conductive pillars 103; a first end of the conductive pillar 103 is disposed on and electrically contacts a bonding pad 105 of at least one memory die 102, and the conductive pillar 103 extends from the first end through the molding layer 104 such that a second end of the conductive pillar 103 can be disposed on a first surface 231 of the redistribution layer 23 and physically contact and electrically connect with the redistribution layer 23;

[0150] The memory controller 21 has a lead-out pad 210 on its surface 211. The memory controller 21 is disposed on the first surface 231 of the redistribution layer 23 through the lead-out pad 210 and is electrically connected to the redistribution layer 23.

[0151] In one specific example, each of the plurality of memory dies 102 includes an insulating layer on its side and bottom surfaces, which serves to provide insulation and protection while increasing the mechanical strength of the memory die 102, thereby making the resulting memory system package structure more reliable.

[0152] In one specific example, the plurality of memory dies 102 can be offset in any direction parallel to the surfaces of the plurality of memory dies 102. Specifically, the bonding pads 105 on the surface of the other memory die 102 can be exposed by offsetting one of the two adjacent memory dies 102 along the stacking direction.

[0153] In one embodiment, the plurality of memory dies 102 are stacked in a stepped manner. Each memory die 102 has a plurality of bonding pads 105 on its exposed stepped surface. Except for the bottommost memory die 102, all other memory dies 102 are offset along a first direction, thereby exposing the bonding pads 105 on the surface of the plurality of memory dies 102. The first direction is perpendicular to the stacking direction of the plurality of memory dies 102.

[0154] In one embodiment, such as Figure 5 As shown, the memory system packaging structure includes a first memory chip molding assembly 10A and a second memory chip molding assembly 10B, and the memory controller 21 is located between the first memory chip molding assembly 10A and the second memory chip molding assembly 10B.

[0155] In one embodiment, the distance between the memory controller 21 and the first memory chip molding assembly 10A is a first distance, and the distance between the memory controller 21 and the second memory chip molding assembly 10B is a second distance; the first distance and the second distance are equal.

[0156] It is understood that the memory controller 21 is located between the first memory chip molding assembly 10A and the second memory chip molding assembly 10B, and the first memory chip molding assembly 10A and the second memory chip molding assembly 10B are arranged substantially symmetrically based on the memory controller 21. That is, the signal path from the first memory chip molding assembly 10A to the memory controller 21 and the signal path from the second memory chip molding assembly 10B to the memory controller 21 can be substantially symmetrical and consistent, thereby improving the high-frequency performance of the memory system packaging structure.

[0157] In one embodiment, the first distance and the second distance are equal, and the first memory chip molding assembly 10A, the second memory chip molding assembly 10B, and the memory controller 21 are located on a first straight line within the first surface 231. That is, compared to the case where the first memory chip molding assembly 10A, the second memory chip molding assembly 10B, and the memory controller 21 are not located on the same straight line, the signal path from the first memory chip molding assembly 10A to the memory controller 21 is shorter than the signal path from the second memory chip molding assembly 10B to the memory controller 21.

[0158] In one embodiment, the first memory chip molding assembly 10A includes a plurality of first memory dies 102A offset by a third distance along a first direction, and the second memory chip molding assembly 10B includes a plurality of second memory dies 102B offset by a fourth distance along a second direction; the first direction and the second direction are both perpendicular to the direction in which the plurality of memory dies 102 are stacked, and the first direction is opposite to the second direction.

[0159] It is understood that in the above embodiments, not only are the first memory chip molding assembly 10A and the second memory chip molding assembly 10B arranged symmetrically based on the memory controller 21, but also the plurality of memory dies 102 in the first memory chip molding assembly 10A and the plurality of memory dies 102 in the second memory chip molding assembly 10B are arranged substantially symmetrically based on the center line AA of the memory controller 21. Thus, the signal path from the first memory chip molding assembly 10A to the memory controller 21 and the signal path from the second memory chip molding assembly 10B to the memory controller 21 can be substantially symmetrical and consistent, further improving signal integrity and the high-frequency performance of the memory system packaging structure.

[0160] In one embodiment, such as Figure 5As shown, the number of first memory dies 102A is the same as the number of second memory dies 102B; the third distance is equal to the fourth distance. Here, the number of memory dies included in the first memory chip molding assembly 10A and the second memory chip molding assembly 10B is the same, and the distance by which the plurality of first memory dies 102A in the first memory chip molding assembly 10A are offset along the first direction is equal to the distance by which the plurality of second memory dies 102B in the second memory chip molding assembly 10B are offset along the second direction. In other words, the first memory chip molding assembly 10A and the second memory chip molding assembly 10B have the same internal structure. The multiple memory dies 102 in the first memory chip molding assembly 10A and the multiple memory dies 102 in the second memory chip molding assembly 10B are arranged symmetrically based on the center line AA of the memory controller 21. Thus, the signal paths from each memory die in the first memory chip molding assembly 10A to the memory controller 21 are symmetrical and consistent with the signal paths from each memory die in the second memory chip molding assembly 10B to the memory controller 21, resulting in good signal integrity from the perspective of the memory system.

[0161] In one embodiment, the memory system package structure includes a memory chip molding assembly 10, and the memory controller 21 is located on one side of the memory chip molding assembly 10.

[0162] In one specific example, each of the memory chip molding components 10 includes a plurality of memory dies 102, and the electrical connection between the plurality of memory dies 102 and the conductive posts 103 includes a variety of methods.

[0163] In one embodiment, each of the memory chip molding components 10 includes a conductive post 103, which is electrically contacted with a bonding pad 105 of one of the plurality of memory dies 102, and the remaining memory dies 102 are electrically connected to the conductive post 103 via bonding leads.

[0164] In a specific example, when each of the memory chip molding components 10 includes a conductive post 103, the memory system package structure may include at least one bonding wire. The remaining memory dies 102 among the plurality of memory dies 102 can be electrically connected to the conductive post 103 through various bonding wires. Two methods for achieving electrical connection between the plurality of memory dies 102 and the conductive post 103 will be described below.

[0165] Method 1: For example Figure 6aAs shown, any two adjacent memory dies among the plurality of memory dies 102 are electrically connected via bonding leads. A conductive post 103 makes electrical contact with the bonding pad 105 of one of the memory dies 102. The remaining memory dies are electrically connected to the conductive post via other memory dies. Thus, each memory die 102 in the memory chip molding assembly 10 can be electrically connected to the redistribution layer 23 via the conductive post 103.

[0166] Method 2: One conductive post 103 is electrically connected to the bonding pad 105 of one of the plurality of memory dies 102, and the remaining memory dies are directly electrically connected to the conductive post through bonding leads.

[0167] In a specific example, when each of the memory chip molding components 10 includes multiple conductive pillars 103, the electrical connection between the multiple memory dies 102 and the multiple conductive pillars 103 can be achieved in various ways. Two methods for achieving the electrical connection between the multiple memory dies 102 and the multiple conductive pillars 103 will be described below.

[0168] Method 1: For example Figure 6b As shown, each memory chip molding assembly 10 includes a plurality of conductive pillars 103, which are electrically connected to the bonding pads 105 of a portion of the memory dies 102. The remaining memory dies 102 are electrically connected to the plurality of conductive pillars 103 via bonding leads.

[0169] Method 2: For example Figure 6c As shown, each of the memory chip molding components 10 includes a plurality of conductive pillars 103, and for each of the memory dies 102, the plurality of conductive pillars 103 are electrically contacted with the bonding pads 105 of the corresponding memory die 102.

[0170] In one specific example, the conductive post 103 is formed on each of the plurality of memory dies 102. Each memory die 102 is electrically connected to the redistribution layer 23 through the conductive post 103. That is, each memory die 102 does not require additional bonding leads to transmit signals to external devices, thereby improving the reliability of the memory system package structure manufacturing process.

[0171] In one embodiment, the memory system package structure further includes: metal solder balls 24 located on the second surface 232 of the redistribution layer 23 and electrically connected to the memory chip molding assembly 10 and the memory controller 21 through the redistribution layer 23; the second surface 232 and the first surface 231 are opposite to each other.

[0172] In one embodiment, the memory system package structure further includes one or more passive devices 212 encapsulated in the molding compound 22. The passive devices 212 are disposed on the first surface 231 of the redistribution layer 23 and electrically connected to the redistribution layer 23. In a specific example, the passive devices 212 include capacitors, resistors, inductors, etc. It will be understood that the specific number, arrangement position on the first surface 231, and type of the passive devices 212 can be specifically selected and configured according to the function of the memory system package structure.

[0173] In one embodiment, the memory die 102 may be a three-dimensional NAND flash memory die device.

[0174] It should be noted that the memory system packaging structure described above can be used to form various memory system products, such as Universal Flash Memory (UFS), embedded multimedia cards (eMMC), PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, Memory Sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), SSDs, etc. The memory controller 21 in the memory system packaging structure can control the operation of one or more memory die 102s in the memory chip molding assembly 10, such as read, write, and erase operations. The memory controller 21 can be configured to control the operation of the memory die 102, such as read operations, erase operations, and programming operations; the memory controller 21 can also be configured to manage various functions regarding data stored or to be stored in the memory die 102, including but not limited to bad block management, garbage collection, wear leveling, etc.; the memory controller 21 can also perform any other suitable function, such as formatting the memory die 102; the memory controller 21 can communicate with external devices (e.g., host 108) according to a specific communication protocol; for example, the memory controller 21 can communicate with external devices through at least one of various interface protocols, such as USB protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, Serial Bus (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial-ATA protocol, Parallel-ATA20 protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, etc.

[0175] This disclosure provides a memory system packaging structure and manufacturing method. The method includes: providing at least one memory chip molding assembly and a memory controller; wherein each memory chip molding assembly includes a plurality of stacked memory dies, a molding layer encapsulating the plurality of memory dies, and one or more conductive pillars; a first end of each conductive pillar is disposed on and electrically contacts a bonding pad of at least one memory die; a lead-out pad is provided on the surface of the memory controller; encapsulating the at least one memory chip molding assembly and the memory controller in a molding layer; wherein the conductive pillar extends from its first end through the molding layer such that a second end of the conductive pillar and the lead-out pad are both exposed on the same surface of the molding layer; a redistribution layer is formed on the same surface of the molding layer; wherein the second end of the conductive pillar and the lead-out pad are both disposed on the first surface of the redistribution layer and electrically connected to the redistribution layer. In the memory system packaging structure provided in this embodiment, the memory chip molding assembly is physically contacted and electrically connected to the redistribution layer through conductive pillars. The memory controller is disposed on the first surface of the redistribution layer and electrically connected to the redistribution layer. On the one hand, since both the memory chip molding assembly and the memory controller are disposed on the first surface of the redistribution layer and electrically connected to the redistribution layer, the overall line spacing is relatively short, which shortens the signal transmission path between the memory chip molding assembly and the memory controller and external devices. Therefore, the resulting memory system packaging structure has better high-frequency performance. On the other hand, the memory controller does not need to be wire-bonded, which simplifies the memory system packaging process.

[0176] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory system packaging structure, characterized in that, include: At least one memory chip molding assembly, a memory controller, a molding layer encapsulating the memory chip molding assembly and the memory controller, and a redistribution layer; wherein, Each of the memory chip molding assemblies includes a plurality of stacked memory dies, a molding layer encapsulating the plurality of memory dies, and one or more conductive pillars; a first end of the conductive pillar is disposed on and electrically contacts a bonding pad of at least one of the memory dies, and the conductive pillar extends from the first end through the molding layer such that a second end of the conductive pillar is disposed on a first surface of the redistribution layer and physically contacts and is electrically connected to the redistribution layer. The memory controller has lead-out pads on its surface. The memory controller is disposed on the first surface of the redistribution layer and electrically connected to the redistribution layer via the lead-out pads. The at least one memory chip molding assembly includes a first memory chip molding assembly and a second memory chip molding assembly, and the memory controller is located between the first memory chip molding assembly and the second memory chip molding assembly; or, The memory system packaging structure includes a memory chip molding assembly, and the memory controller is located on one side of the memory chip molding assembly along a first direction; wherein the first direction is perpendicular to the direction of the stacking of the plurality of memory dies.

2. The memory system packaging structure according to claim 1, characterized in that, The at least one memory chip molding assembly includes a first memory chip molding assembly and a second memory chip molding assembly, and the memory controller is located between the first memory chip molding assembly and the second memory chip molding assembly; the distance between the memory controller and the first memory chip molding assembly is a first distance, and the distance between the memory controller and the second memory chip molding assembly is a second distance; the first distance and the second distance are equal.

3. The memory system packaging structure according to claim 2, characterized in that, The first memory chip molding assembly, the second memory chip molding assembly, and the memory controller are located on a first straight line within the first surface.

4. The memory system packaging structure according to claim 3, characterized in that, The first memory chip molding assembly includes a plurality of first memory dies offset by a third distance along a first direction, and the second memory chip molding assembly includes a plurality of second memory dies offset by a fourth distance along a second direction; the first direction and the second direction are both perpendicular to the direction in which the plurality of memory dies are stacked, and the first direction is opposite to the second direction.

5. The memory system packaging structure according to claim 4, characterized in that, The number of the first memory dies is the same as the number of the second memory dies; the third distance is equal to the fourth distance.

6. The memory system packaging structure according to claim 1, characterized in that, Each of the memory chip molding components includes a conductive post, the first end of which is disposed on and electrically in contact with a bonding pad of one of the plurality of memory dies, and the remaining memory dies of the plurality of memory dies are electrically connected to the first end of the conductive post via bonding leads; or, Each of the memory chip molding components includes a plurality of conductive pillars, and for each of the memory dies, the first end of the plurality of conductive pillars is respectively disposed on and electrically contacted on the bonding pad of the corresponding memory die.

7. The memory system packaging structure according to claim 1, characterized in that, The memory system packaging structure also includes: Metal solder balls located on the second surface of the redistribution layer and electrically connected to the memory chip molding assembly and the memory controller through the redistribution layer; the second surface is opposite to the first surface.

8. The memory system packaging structure according to claim 1, characterized in that, The memory system packaging structure also includes passive devices encapsulated in the molding layer, the passive devices being disposed on the first surface of the redistribution layer and electrically connected to the redistribution layer.

9. The memory system packaging structure according to claim 1, characterized in that, The memory die includes a three-dimensional NAND flash memory die.

10. The memory system packaging structure according to claim 1, characterized in that, The material of the encapsulation layer is the same as the material of the molding layer.

11. The memory system packaging structure according to claim 1, characterized in that, The at least one memory chip molding assembly includes a first memory chip molding assembly and a second memory chip molding assembly, the first memory chip molding assembly and the second memory chip molding assembly being arranged on both sides of the memory controller and substantially symmetrical about the centerline of the memory controller.

12. The memory system packaging structure according to claim 1 or 11, characterized in that, The at least one memory chip molding assembly includes a first memory chip molding assembly and a second memory chip molding assembly, and the memory controller is located between the first memory chip molding assembly and the second memory chip molding assembly; the first memory chip molding assembly and the second memory chip molding assembly have the same internal structure.

13. A method for manufacturing a memory system package structure, characterized in that, The method includes: At least one memory chip molding assembly and a memory controller are provided; wherein each memory chip molding assembly includes a plurality of stacked memory dies, a molding layer encapsulating the plurality of memory dies, and one or more conductive pillars; a first end of each conductive pillar is disposed on and electrically contacts a bonding pad of at least one memory die; the surface of the memory controller is provided with lead-out pads; wherein the at least one memory chip molding assembly includes a first memory chip molding assembly and a second memory chip molding assembly, and the memory controller is located between the first memory chip molding assembly and the second memory chip molding assembly; or, the at least one memory chip molding assembly includes a single memory chip molding assembly, and the memory controller is located on one side of the single memory chip molding assembly along a first direction; wherein the first direction is perpendicular to the direction in which the plurality of memory dies are stacked; The at least one memory chip molding assembly and the memory controller are encapsulated in a molding layer; wherein the conductive post extends from the first end through the molding layer such that the second end of the conductive post and the lead pad are both exposed on the same surface of the molding layer; A redistribution layer is formed on the same surface of the molding compound; wherein the second end of the conductive pillar and the lead-out pad are both disposed on the first surface of the redistribution layer and electrically connected to the redistribution layer.

14. The manufacturing method according to claim 13, characterized in that, The provision of at least one memory chip molding component includes: Provide the primary carrier; Multiple memory dies are sequentially stacked on the first carrier; One or more conductive posts are formed on at least one bonding pad of the plurality of memory dies, with the first end electrically connected to the bonding pad; A molding layer is formed to encapsulate the plurality of memory dies and the conductive pillars; Remove the first carrier; Remove part of the molding layer to expose the second end of the one or more conductive pillars.

15. The manufacturing method according to claim 13, characterized in that, The at least one memory chip molding component includes a first memory chip molding component and a second memory chip molding component; The provision of at least one memory chip molding component includes: Provide the primary carrier; Multiple first memory dies and multiple second memory dies are stacked sequentially on the first carrier; the multiple first memory dies and multiple second memory dies are arranged side by side on the first carrier; One or more conductive posts are formed on at least one bonding pad of the plurality of first memory dies, with the first end electrically connected to the bonding pad; One or more conductive posts are formed on at least one bonding pad of the plurality of second memory dies, with the first end electrically connected to the bonding pad; A molding layer is formed to encapsulate the plurality of first memory dies, the plurality of second memory dies, and the conductive pillars; Remove the first carrier; Remove part of the molding layer to expose the second end of the one or more conductive pillars; Cut the molding layer to obtain a first memory chip molding assembly including a plurality of first memory dies and a second memory chip molding assembly including a plurality of second memory dies.

16. The manufacturing method according to claim 13, characterized in that, The process of encapsulating the at least one memory chip molding component and the memory controller in a molding compound includes: Provide a second carrier; At least one memory chip molding assembly and a memory controller are mounted on the surface of the second carrier, such that the second end of the conductive pillar in the memory chip molding assembly and the lead-out pad of the memory controller are both located on the same surface of the second carrier. A molding layer is formed to encapsulate the memory chip molding assembly and the memory controller; Remove the second carrier.

17. The manufacturing method according to claim 13, characterized in that, The method further includes: Metal solder balls are formed on the second surface of the redistribution layer, and the metal solder balls are electrically connected to the memory chip molding assembly and the memory controller located on the first surface of the redistribution layer through the redistribution layer; the second surface and the first surface are opposite to each other.

18. The manufacturing method according to claim 13, characterized in that, The at least one memory chip molding assembly includes a first memory chip molding assembly and a second memory chip molding assembly, and the memory controller is located between the first memory chip molding assembly and the second memory chip molding assembly; the distance between the memory controller and the first memory chip molding assembly is a first distance, and the distance between the memory controller and the second memory chip molding assembly is a second distance; the first distance and the second distance are equal.

19. The manufacturing method according to claim 18, characterized in that, The first memory chip molding assembly, the second memory chip molding assembly, and the memory controller are located on a first straight line within the first surface.

20. The manufacturing method according to claim 19, characterized in that, The first memory chip molding assembly includes a plurality of first memory dies offset by a third distance along a first direction, and the second memory chip molding assembly includes a plurality of second memory dies offset by a fourth distance along a second direction; both the first direction and the second direction are perpendicular to the direction in which the plurality of memory dies are stacked; the first direction is opposite to the second direction.

21. The manufacturing method according to claim 20, characterized in that, The number of the first memory dies is the same as the number of the second memory dies; the third distance is equal to the fourth distance.

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