Intelligent power module, manufacturing method thereof and home appliance

Abstract

The application discloses an intelligent power module, a preparation method thereof and household electrical appliances, and relates to the technical field of intelligent power modules.The intelligent power module comprises a power device, a drive control module and a switching power supply, wherein the power device, the drive control module and the switching power supply are integrated at the chip level to form a chip, and are manufactured by adopting an SOI-BCD process for one-time wafer production.Thus, the intelligent power module according to the embodiment of the application is manufactured by adopting an SOI-BCD process for one-time wafer production, chip-level integration of the power device, the drive control module and the switching power supply is achieved, the manufacturing cost of the intelligent power module is reduced, the miniaturization requirement of the intelligent power module is met, and meanwhile, the performance of the intelligent power module is improved.

Description

Technical Field

[0001] This invention relates to the field of intelligent power module technology, and in particular to an intelligent power module, a home appliance, and a method for preparing an intelligent power module. Background Technology

[0002] Currently, intelligent power module (IPM) packages typically contain multiple chips. This leads to several problems. First, the production of multiple chips usually involves different designs and tape-out processes, resulting in numerous steps and increased manufacturing costs. Second, the packaged and integrated intelligent power module system is still too large, which is not conducive to miniaturizing the electronic control system. Third, the connection between multiple chips is often achieved through wire bonding, resulting in long traces that are susceptible to interference from parasitic parameters, affecting the stability of the intelligent power module system and significantly reducing its performance. Summary of the Invention

[0003] This invention aims to at least partially solve one of the technical problems in related technologies. Therefore, the first objective of this invention is to provide an intelligent power module manufactured using a single-chip SOI-BCD process, achieving chip-level integration of power devices, drive control modules, and switching power supplies. This reduces the manufacturing cost of the intelligent power module, meets the miniaturization requirements of intelligent power modules, and simultaneously improves the performance of the intelligent power module.

[0004] The second objective of this invention is to provide a household appliance.

[0005] The third objective of this invention is to provide a method for preparing an intelligent power module.

[0006] To achieve the above objectives, the intelligent power module proposed in the first aspect of the present invention includes a power device, a drive control module, and a switching power supply, wherein the power device, the drive control module, and the switching power supply are integrated at the chip level to form a single chip, and are fabricated in a single fabrication process using SOI-BCD technology.

[0007] According to embodiments of the present invention, the intelligent power module integrates power devices, drive control modules, and switching power supplies at the chip level to form a single chip, and is fabricated in a single fabrication process using SOI-BCD technology. This reduces the manufacturing cost of the intelligent power module, meets the miniaturization requirements of the intelligent power module, and at the same time reduces the packaging steps of wire bonding and printing, thereby improving the performance of the intelligent power module.

[0008] In addition, the intelligent power module according to the above embodiments of the present invention may also have the following additional technical features:

[0009] According to one embodiment of the present invention, the chip further integrates a reference power supply module and a detection and protection module. The switching power supply generates a power signal for the drive control module, the reference power supply module, and the detection and protection module. The reference power supply module generates a reference power signal for the drive control module based on the power signal. The drive control module generates a drive signal for the power device based on the power signal and the reference power signal to drive the power device to turn on or off. The detection and protection module detects the operating state of the power device and generates a protection signal for the drive control module to stop the chip from working.

[0010] According to an embodiment of the present invention, the drive control module includes: a control unit for outputting a first control signal and a second control signal; a rectification and filtering unit for rectifying and filtering the first control signal and the second control signal according to the reference power supply signal; a high-voltage side drive output unit for outputting a high-voltage drive signal according to the power supply signal and the rectified and filtered first control signal; and a low-voltage side drive output unit for outputting a low-voltage drive signal according to the power supply signal and the rectified and filtered second control signal.

[0011] According to an embodiment of the present invention, the detection and protection module includes: an undervoltage detection unit for outputting an undervoltage protection signal; an overvoltage detection unit for outputting an overvoltage protection signal; an overtemperature detection unit for outputting an overtemperature protection signal; an overcurrent detection unit for outputting an overcurrent protection signal; and a NAND gate unit for outputting protection signals to the drive control module based on the undervoltage protection signal, the overvoltage protection signal, the overtemperature protection signal, and the overcurrent protection signal.

[0012] According to one embodiment of the present invention, the power device is a vertically oriented MOSFET.

[0013] According to one embodiment of the present invention, in fabricating the chip, an N-type silicon substrate is formed, and oxidation, partial etching, and silicon epitaxy are performed on the N-type silicon substrate to form a buried oxide layer; trench etching is performed on the buried oxide layer to form a trench region; photoresist is deposited on the trench region, and etching, ion implantation, and annealing operations are performed to form a deep P-well; the trench surface and the deep P-well surface are subjected to high-temperature treatment to form an oxide layer; a polysilicon layer is deposited on the oxide layer; multiple ion implantation and annealing operations are performed to form an LDMOS region, a VDMOS region, and a CMOS region; photoresist is deposited, and photolithography and etching are performed to form a gate.

[0014] According to one embodiment of the present invention, the trench region includes a first channel and a second channel, wherein the first channel is located between the LDMOS region and the VDMOS region, and the second channel is located between the VDMOS region and the CMOS region.

[0015] According to one embodiment of the present invention, during the formation of the LDMOS region, VDMOS region, and CMOS region, a first ion implantation and annealing operation is performed to form a P-well; a second ion implantation and annealing operation is performed to form an N+ region; a third ion implantation and annealing operation is performed to form an N-well of the LDMOS region; a fourth ion implantation and annealing operation is performed to form a P-well of the LDMOS region; a fifth ion implantation and annealing operation is performed to form an N+ region of the LDMOS region; and a sixth ion implantation and annealing operation is performed to form a P+ region of the CMOS region.

[0016] According to one embodiment of the present invention, during the formation of the LDMOS region, VDMOS region, and CMOS region, a first ion implantation and annealing operation is performed to form a P-well; a second ion implantation and annealing operation is performed to form an N+ region; a third ion implantation and annealing operation is performed to form the P+ region of the CMOS region; a fourth ion implantation and annealing operation is performed to form the N-well of the LDMOS region; a fifth ion implantation and annealing operation is performed to form the P-well of the LDMOS region; and a sixth ion implantation and annealing operation is performed to form the N+ region of the LDMOS region.

[0017] To achieve the above objectives, the second aspect of the present invention provides a home appliance that includes the intelligent power module as described in the first aspect.

[0018] According to embodiments of the present invention, by employing the aforementioned intelligent power module, the manufacturing cost of the home appliances can be reduced, the miniaturization requirements of the home appliances can be met, and the performance of the home appliances can be improved.

[0019] To achieve the above objectives, a third aspect of the present invention provides a method for fabricating an intelligent power module, wherein the intelligent power module includes a power device, a drive control module, and a switching power supply, the power device, the drive control module, and the switching power supply are integrated at the chip level to form a chip, and the fabrication method includes: fabricating the chip in a single fabrication process using SOI-BCD technology.

[0020] According to the method for fabricating a smart power module according to an embodiment of the present invention, the chip is fabricated in one step using SOI-BCD process, and the power devices, drive control module and switching power supply are integrated at the chip level. This reduces the manufacturing cost of the smart power module, meets the miniaturization requirements of the smart power module, and improves the performance of the smart power module.

[0021] In addition, the method for fabricating the intelligent power module according to the above embodiments of the present invention may also have the following additional technical features:

[0022] According to one embodiment of the present invention, the chip is fabricated in a single-pass fabrication using an SOI-BCD process, comprising: forming an N-type silicon substrate, and performing oxidation, partial etching, and silicon epitaxy on the N-type silicon substrate to form a buried oxide layer; performing trench etching on the buried oxide layer to form a trench region; depositing photoresist on the trench region, and performing etching, ion implantation, and annealing operations to form a deep P-well; performing high-temperature treatment on the trench surface and the deep P-well surface to form an oxide layer; depositing a polysilicon layer on the oxide layer; performing multiple ion implantation and annealing operations to form an LDMOS region, a VDMOS region, and a CMOS region; depositing photoresist, and performing photolithography and etching to form a gate.

[0023] According to one embodiment of the present invention, the trench region includes a first channel and a second channel, wherein the first channel is located between the LDMOS region and the VDMOS region, and the second channel is located between the VDMOS region and the CMOS region.

[0024] According to one embodiment of the present invention, multiple ion implantation and annealing operations are performed to form an LDMOS region, a VDMOS region, and a CMOS region, including: performing a first ion implantation and annealing operation to form a P-well; performing a second ion implantation and annealing operation to form an N+ region; performing a third ion implantation and annealing operation to form an N-well of the LDMOS region; performing a fourth ion implantation and annealing operation to form a P-well of the LDMOS region; performing a fifth ion implantation and annealing operation to form an N+ region of the LDMOS region; and performing a sixth ion implantation and annealing operation to form a P+ region of the CMOS region.

[0025] According to one embodiment of the present invention, multiple ion implantation and annealing operations are performed to form an LDMOS region, a VDMOS region, and a CMOS region, including: performing a first ion implantation and annealing operation to form a P-well; performing a second ion implantation and annealing operation to form an N+ region; performing a third ion implantation and annealing operation to form a P+ region of the CMOS region; performing a fourth ion implantation and annealing operation to form an N-well of the LDMOS region; performing a fifth ion implantation and annealing operation to form a P-well of the LDMOS region; and performing a sixth ion implantation and annealing operation to form an N+ region of the LDMOS region.

[0026] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0027] Figure 1 This is a block diagram of an intelligent power module according to an embodiment of the present invention;

[0028] Figure 2 This is a block diagram of an intelligent power module according to an embodiment of the present invention;

[0029] Figure 3 This is a block diagram of an intelligent power module according to an embodiment of the present invention;

[0030] Figure 4 This is a block diagram of an intelligent power module according to an embodiment of the present invention;

[0031] Figure 5 This is a block diagram of an intelligent power module according to an embodiment of the present invention;

[0032] Figure 6 This is a schematic diagram of the structure of an intelligent power module according to an embodiment of the present invention;

[0033] Figure 7 This is a block diagram of a household appliance according to an embodiment of the present invention;

[0034] Figure 8 This is a schematic flowchart of a method for fabricating a smart power module according to an embodiment of the present invention;

[0035] Figure 9 This is a schematic flowchart of a method for fabricating a smart power module according to an embodiment of the present invention;

[0036] Figure 10 This is a schematic flowchart of a method for fabricating a smart power module according to an embodiment of the present invention. Detailed Implementation

[0037] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0038] Before introducing the intelligent power module in the embodiments of the present invention, we will first introduce the existing intelligent power modules.

[0039] Existing intelligent power modules typically include at least one driver chip and multiple power chips (MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and IGBT (Insulated Gate Bipolar Transistor)). Transistor (Insulated Gate Bipolar Transistor), FRD (Fast Recovery Diode). Taking a common IPM (Integrated Power Module) driving a three-phase motor as an example, the types and number of chips are: 1 HVIC, 6 IGBTs, and 6 FRDs. In addition, the power supply for the driver chip (usually 15V) is a switching power supply chip. Therefore, the entire intelligent power module system includes up to 14 chips. However, the existing multi-chip solutions have the following shortcomings: 1. High manufacturing cost of multi-chips: Due to the different designs and tape-out processes for various chips, the manufacturing steps of existing intelligent power modules are numerous. 2. Insufficient operating performance of multi-chips: Since multiple chips are often connected by bonding wires, the traces between chips are long and easily affected by parasitic parameters, causing instability in the operating state of the intelligent power module and resulting in a decrease in the performance of the intelligent functional module. 3. The packaged size of multi-chips is still relatively large: Due to the packaging and integration of multiple chips, the size of the intelligent power module is still limited by large components, which is not conducive to meeting the miniaturization requirements of the power control system.

[0040] To address this, embodiments of the present invention propose to improve the packaged and integrated intelligent power module into a chip-level integrated intelligent power module. Specifically, by integrating the drive control module, power chip (MOSFET, IGBT, FRD) and switching power supply onto a single chip, packaging steps such as wire bonding and printing are reduced, which significantly reduces the manufacturing cost of the intelligent power module. Furthermore, the size of the intelligent power module is further reduced, resulting in significantly improved performance and lower power consumption.

[0041] The following description, with reference to the accompanying drawings, describes an embodiment of the present invention: a smart power module, a home appliance, and a method for preparing the smart power module.

[0042] Figure 1 This is a block diagram of an intelligent power module according to an embodiment of the present invention.

[0043] like Figure 1 As shown, the intelligent power module 100 includes a power device 10, a drive control module 20, and a switching power supply 30.

[0044] Specifically, in the embodiments of the present invention, by integrating the power device 10, the drive control module 20 for generating drive signals to the power device 10, and the switching power supply 30 for generating stable power signals at the chip level, and fabricating a single chip of the intelligent power module 100 using SOI-BCD process in one fabrication, the manufacturing cost of the intelligent power module 100 is reduced, the miniaturization requirements of the intelligent power module 10 are met, and the performance of the intelligent power module 100 is improved.

[0045] Furthermore, such as Figure 2 As shown, the chip may also integrate a reference power supply module 40 for generating a reference power supply signal and a detection and protection module 50 for performing operating condition detection and real-time protection of the chip.

[0046] Specifically, in embodiments of the present invention, the chip can generate a power signal through the switching power supply 30 and transmit it to the drive control module 20 for driving the power device 10, the reference power supply module 40 for generating a reference power signal, and the detection and protection module 50 for performing operating condition detection and real-time protection on the chip. Furthermore, the chip can generate a corresponding reference power signal through the reference power supply module 40 based on the power signal generated by the switching power supply 30, and transmit the reference power signal to the drive control module 20. Then, the chip can use the drive control module 20 to generate a reference power signal based on the power signal generated by the switching power supply 30 and the reference power supply module 40. The chip generates a reference power supply signal, produces a corresponding drive signal, and transmits the drive signal to the power device 10, thereby controlling the power device 10 to turn on or off. At the same time, the chip can also detect the real-time operating condition of the power device 10 through the detection and protection module 50. The detection and protection module 50 can generate a corresponding protection signal based on the operating state of the power device 10 and transmit it to the drive control module 20. The drive control module 20 can then stop the chip from working in abnormal conditions based on the protection signal, thereby ensuring the stability of the intelligent power module 100 and extending the working life of the intelligent power module 100.

[0047] Optionally, the switching power supply 30 for generating a stable power signal may further include a bootstrap circuit, wherein the bootstrap circuit is used for energy storage and power supply to provide a stable power supply for the drive control module 20 for driving the power device 10, the reference power supply module 40 for generating a reference power signal, and the detection and protection module 50 for performing operating condition detection and real-time protection of the chip. In addition, the reference power supply module 40 may further include a bandgap reference unit, a comparator, and a transistor, wherein the first input terminal (+) of the comparator is connected to one end of the bandgap reference unit, the second input terminal (-) of the comparator is grounded, and the output terminal of the comparator is connected to the control terminal of the transistor, for controlling the switching on and off of the transistor to generate a corresponding reference power signal according to the power signal generated by the switching power supply 30.

[0048] Furthermore, such as Figure 3 As shown, the drive control module 20 may include: a control unit 201, a rectifier and filter unit 202, a high-voltage side drive output unit 203, and a low-voltage side drive output unit 204.

[0049] Specifically, the drive control module 20 can output a first control signal for controlling the high-voltage side power devices and a second control signal for controlling the low-voltage side power devices through the control unit 201. Based on the reference power signal generated by the reference power supply module 40, both the first and second control signals can be filtered and rectified by the rectifier-filter unit 202. The rectified and filtered first control signal is then transmitted to the high-voltage side drive output unit 203. The high-voltage side drive output unit 203, in conjunction with the power signal generated by the switching power supply 30, outputs a corresponding high-voltage drive signal to drive the corresponding high-voltage side power devices to switch on and off. The rectified and filtered first control signal is also transmitted to the low-voltage side drive output unit 204. The low-voltage side drive output unit 204, in conjunction with the power signal generated by the switching power supply 30, outputs a corresponding low-voltage drive signal to drive the corresponding low-voltage side power devices to switch on and off.

[0050] Optionally, the drive control module 20 may further include an electrostatic discharge protection unit and a penetration protection and dead zone unit, wherein the electrostatic discharge protection unit is used to discharge the first control signal and the second control signal, and the penetration protection and dead zone unit is used to adjust the first control signal and the second control signal to avoid penetration or dead zone of the power device 10.

[0051] Furthermore, such as Figure 4 As shown, the detection and protection module 50 may include: an undervoltage detection unit 501, an overvoltage detection unit 502, an overtemperature detection unit 503, an overcurrent detection unit 504, and a NAND gate unit 505.

[0052] Specifically, the detection and protection module 50 can detect and protect the real-time operating status of the chip. When the chip experiences an undervoltage condition (e.g., the chip's operating voltage is lower than a preset lower voltage threshold), the undervoltage detection unit 501 can output an undervoltage protection signal to the NAND gate unit 505. When the chip experiences an overvoltage condition (e.g., the chip's operating voltage is higher than a preset upper voltage threshold), the overvoltage detection unit 502 can output an overvoltage protection signal to the NAND gate unit 505. When the chip experiences an overtemperature condition (e.g., the chip's operating temperature is higher than a preset temperature threshold), the overtemperature detection unit 503 can output an overtemperature protection signal to the NAND gate unit 505. When the chip experiences an overcurrent condition (e.g., the chip's operating current is higher than a preset current threshold), the overcurrent detection unit 504 can output an overcurrent protection signal to the NAND gate unit 505. The NOT gate unit 505 can protect the chip based on the undervoltage protection signal output by the undervoltage detection unit 501 when the chip is undervoltage, the overvoltage protection signal output by the overvoltage detection unit 502 when the chip is overvoltage, the overtemperature protection signal output by the overtemperature detection unit 503 when the chip is overtemperature, and the overcurrent protection signal output by the overcurrent detection unit 504 when the chip is overcurrent. For example, when the NAND gate unit 505 receives any one or more of the overvoltage protection signal, overcurrent protection signal, overtemperature protection signal, and undervoltage protection signal, it can output a protection signal to the drive control module 20. The drive control module 20 can then control the chip to stop working in abnormal conditions (e.g., under overvoltage, overcurrent, undervoltage, and overtemperature conditions) based on the protection signal issued by the NAND gate unit 505.

[0053] Optionally, the detection and protection module 50 may also include a temperature display unit, which is used to display the chip's operating temperature in real time, so that staff can understand the chip's temperature status in a timely manner and reduce the difficulty of chip maintenance.

[0054] Furthermore, the power device 10 can be a vertically structured MOSFET.

[0055] It should be noted that, compared with the existing intelligent power modules, the intelligent power module 100 of this application adopts a (vertical structure) MOS transistor that is different from the existing MOS transistor structure, which makes the intelligent power module 100 have greater power and better heat dissipation performance.

[0056] Optionally, in embodiments of the present invention, the power device 10 may further include an IGBT+FRD, or a MOSFET, or a thyristor.

[0057] For example, such as Figure 5As shown, the intelligent power module 100 of this embodiment can generate a stable power signal through the switching power supply 30, and after being connected to an external circuit, it generates signal 1 as shown in the figure, which is output to the reference power module 40, the detection and protection module 50 and the drive control module 20 respectively. The reference power module 40 also generates an internal reference power signal, signal 3 as shown in the figure (usually generating a 5V or 7V power signal), and outputs it to the drive control module 20. Then, after receiving the MCU control signal, the drive control module 20 generates signal 2 (a first control signal or a second control signal) as shown in the figure and outputs the value to the power device 10 to control the power device 10 to turn on or off. At the same time, the detection and protection module 50 monitors the power status of the chip in real time. When the chip experiences abnormal operating conditions such as undervoltage, overtemperature, overvoltage, or overcurrent, it generates control signal 4 (protection signal) and transmits it to the drive control module 20 to stop the chip from working.

[0058] Furthermore, in the chip fabrication process, firstly, an N-type silicon substrate is formed, and oxidation, partial etching, and silicon epitaxy are sequentially performed on the N-type silicon substrate to form a buried oxide layer. Then, trench etching is performed on the formed buried oxide layer to form a trench region. Subsequently, photoresist deposition, etching, ion implantation, and annealing are sequentially performed on the silicon wafer with the trench region to form a deep P-well. Then, the surface of the formed trench and the surface of the formed deep P-well are subjected to high-temperature treatment to form an oxide layer. Subsequently, a polysilicon layer is deposited on the formed oxide layer, and multiple ion implantation and annealing operations are performed to form the LDMOS region, VDMOS region, and CMOS region. Finally, photoresist deposition, photolithography, and etching are sequentially performed to form the gate of the chip.

[0059] Specifically, when integrating the smart power module 100 at the chip level, the N-type silicon substrate of the chip is first formed. Then, the N-type silicon substrate is processed (oxidation, partial etching, and silicon epitaxy) to form the buried oxide layer of the chip. The buried oxide layer is then processed (trench etching) to form the trench region of the chip. The silicon wafer with the trench region is then processed (photoresist deposition, etching, ion implantation, and annealing) to form the deep P-well of the chip. The trench surface and the deep P-well surface are then processed (high-temperature treatment) to form the oxide layer of the chip. The oxide layer is then processed (polysilicon layer deposition, multiple ion implantations, and annealing) to form the LDMOS region, VDMOS region, and CMOS region of the chip, respectively. Finally, the chip is processed (photoresist deposition, photolithography, and etching) to form the gate of the chip.

[0060] Furthermore, the trench region includes a first channel for isolating the LDMOS region and the VDMOS region and a second channel for isolating the VDMOS region and the CMOS region, wherein the first channel may be located between the LDMOS region and the VDMOS region, and the second channel may be located between the VDMOS region and the CMOS region.

[0061] It should be understood that the first channel located between the LDMOS region and the VDMOS region can be used to isolate the LDMOS region and the VDMOS region, so that the LDMOS region and the VDMOS region can work independently, avoiding mutual interference between the high voltage and low current of the LDMOS region and the high voltage and high current of the VDMOS region. Similarly, the second channel located between the VDMOS region and the CMOS region can be used to isolate the VDMOS region and the CMOS region, so that the VDMOS region and the CMOS region can work independently, avoiding mutual interference between the high voltage and high current of the VDMOS region and the low voltage and low current of the CMOS region. This improves the stability and reliability of the intelligent power module 100.

[0062] Furthermore, in embodiments of the present invention, the aforementioned LDMOS region, VDMOS region, and CMOS region can be formed in the following manner, wherein the LDMOS region corresponds to the working area of ​​the switching power supply 30, the VDMOS region corresponds to the working area of ​​the power device 10, and the CMOS region corresponds to the working area of ​​the drive control module 20:

[0063] In one embodiment of the present invention, the formation of the aforementioned LDMOS region, VDMOS region, and CMOS region includes: first, forming a P-well by performing a first photolithography operation, an ion implantation operation, and an annealing operation; then, forming an N+ region by performing a second photolithography operation, an ion implantation operation, and an annealing operation; further, forming an N-well corresponding to the LDMOS region by performing a third photolithography operation, an ion implantation operation, and an annealing operation; then, forming a P-well corresponding to the LDMOS region by performing a fourth photolithography operation, an ion implantation operation, and an annealing operation; and finally, forming a P+ region corresponding to the CMOS region by performing a sixth photolithography operation, an ion implantation operation, and an annealing operation.

[0064] Specifically, according to embodiments of the present invention, when forming the LDMOS region, VDMOS region, and CMOS region of the chip, the P-well of the chip is first formed, then the N+ region of the chip is formed, then the N-well corresponding to the LDMOS region is formed, then the P-well corresponding to the LDMOS region is formed, and then the N+ region corresponding to the LDMOS region is formed, and finally the P+ region corresponding to the CMOS region is formed. The P-well of the chip is formed through a first photolithography operation, an ion implantation operation, and an annealing operation; the N+ region of the chip is formed through a second photolithography operation, an ion implantation operation, and an annealing operation; the N-well corresponding to the LDMOS region is formed through a third photolithography operation, an ion implantation operation, and an annealing operation; the P-well corresponding to the LDMOS region is formed through a fourth photolithography operation, an ion implantation operation, and an annealing operation; the N+ region corresponding to the LDMOS region is formed through a fifth photolithography operation, an ion implantation operation, and an annealing operation; and the P+ region corresponding to the CMOS region is formed through a sixth photolithography operation, an ion implantation operation, and an annealing operation.

[0065] It is understood that the intelligent power module 100 according to embodiments of the present invention, such as Figure 6 As shown, it includes: an N-type silicon substrate, a buried oxide layer, a trench region (a first channel located between the LDMOS region and the VDMOS region, and a second channel located between the VDMOS region and the CMOS region), a deep P-well, an oxide layer (deposited polysilicon layer), an LDMOS region (N-well, P-well, N+ region), a VDMOS region and a CMOS region (P+ region), and a gate.

[0066] In another embodiment of the present invention, the formation of the aforementioned LDMOS region, VDMOS region, and CMOS region further includes: first, forming a P-well by performing a first photolithography operation, an ion implantation operation, and an annealing operation; then, forming an N+ region by performing a second photolithography operation, an ion implantation operation, and an annealing operation; further, forming a P+ region corresponding to the CMOS region by performing a third photolithography operation, an ion implantation operation, and an annealing operation; then, forming an N-well corresponding to the LDMOS region by performing a fourth photolithography operation, an ion implantation operation, and an annealing operation; and finally, forming an N+ region corresponding to the LDMOS region by performing a fifth photolithography operation, an ion implantation operation, and an annealing operation.

[0067] Specifically, according to embodiments of the present invention, when forming the LDMOS region, VDMOS region, and CMOS region of the chip, the P-well of the chip is first formed, then the N+ region of the chip is formed, then the P+ region corresponding to the CMOS region is formed, then the N-well corresponding to the LDMOS region is formed, and then the P-well corresponding to the LDMOS region is formed, and finally the N+ region corresponding to the LDMOS region is formed. The P-well of the chip is formed through a first photolithography operation, an ion implantation operation, and an annealing operation; the N+ region of the chip is formed through a second photolithography operation, an ion implantation operation, and an annealing operation; the P+ region corresponding to the CMOS region is formed through a third photolithography operation, an ion implantation operation, and an annealing operation; the N-well corresponding to the LDMOS region is formed through a fourth photolithography operation, an ion implantation operation, and an annealing operation; the P-well corresponding to the LDMOS region is formed through a fifth photolithography operation, an ion implantation operation, and an annealing operation; and the N+ region corresponding to the LDMOS region is formed through a sixth photolithography operation, an ion implantation operation, and an annealing operation.

[0068] It should be understood that in the embodiments of the present invention, the LDMOS region is formed with N-well, P-well and N+ region, the VDMOS region is formed with P-well and N+ region, and the CMOS region is formed with P+ region.

[0069] It should be noted that the intelligent power module 100 prepared by the method of the present invention has chip-level integration of the power device 10, the drive control module 20 and the switching power supply 30, which is beneficial to meeting the miniaturization requirements of the intelligent power module 100. At the same time, compared with the multi-chip integrated intelligent power modules in the prior art, which need to connect the drive current to the power device by means of wire bonding, and the wire bonding points need to be opened and copper printed, the intelligent power module 100 of this application can further reduce the packaging steps such as wire bonding and printing through chip-level integration, which is beneficial to reducing the manufacturing cost of the intelligent power module 100. In addition, the chips are connected by internal wires, which are short and have small parasitic parameters, which is beneficial to improving the performance of the intelligent power module 100.

[0070] In summary, the intelligent power module according to the embodiments of the present invention achieves chip-level integration of power devices, drive control modules and switching power supplies by fabricating chips in a single process using SOI-BCD technology. This reduces the manufacturing cost of the intelligent power module, meets the miniaturization requirements of the intelligent power module, and at the same time reduces the packaging steps of wire bonding and printing, thereby improving the performance of the intelligent power module.

[0071] Figure 7 This is a block diagram of a household appliance according to an embodiment of the present invention.

[0072] like Figure 7As shown, the home appliance 1000 includes the intelligent power module 100 as described in the aforementioned embodiment of the present invention.

[0073] It should be noted that since the home appliance 1000 of this embodiment adopts the intelligent power module 100 of the above embodiment of this invention, the specific implementation of the home appliance 1000 of this embodiment of this invention can be referred to the specific implementation of the intelligent power module 100 of the above embodiment of this invention, and will not be repeated here.

[0074] In summary, the home appliances according to embodiments of the present invention, by employing the aforementioned intelligent power module, can reduce the manufacturing cost of the home appliances, meet the miniaturization requirements of the home appliances, and improve the performance of the home appliances.

[0075] Furthermore, based on the intelligent power module 100 of the aforementioned embodiments of the present invention, the present invention also proposes a method for fabricating the intelligent power module 100, wherein the fabrication method includes: fabricating a chip in a single fabrication process using SOI-BCD technology.

[0076] Furthermore, such as Figure 8 As shown, the chip is fabricated using the SOI-BCD process in a single fabrication process, including:

[0077] S101, forming an N-type silicon substrate, and performing oxidation, partial etching, and silicon epitaxy operations on the N-type silicon substrate to form a buried oxide layer.

[0078] Specifically, a buried oxide layer is formed by sequentially performing oxidation, partial etching, and silicon epitaxy operations on an N-type silicon substrate.

[0079] S102, trench etching is performed on the buried oxide layer to form a trench area.

[0080] Specifically, trench areas are formed by performing trench etching on the formed buried oxide layer.

[0081] S103 involves depositing photoresist on the trench region and performing etching, ion implantation, and annealing operations to form a deep P-well.

[0082] Specifically, a deep P-well is formed by sequentially performing photoresist deposition, photolithography, etching, ion implantation, and annealing operations on the silicon wafer forming the trench region.

[0083] S104 involves high-temperature treatment of the trench surface and the deep P-well surface to form an oxide layer.

[0084] Specifically, an oxide layer is formed by performing high-temperature treatment on the surface of the formed trench and the surface of the formed deep P-well.

[0085] S105, depositing a polycrystalline silicon layer on the formed oxide layer.

[0086] S106 undergoes multiple ion implantation and annealing operations to form the LDMOS, VDMOS, and CMOS regions, respectively.

[0087] Specifically, a polysilicon layer is deposited on the formed oxide layer, and multiple ion implantation and annealing operations are performed to form the LDMOS region, VDMOS region, and CMOS region, respectively.

[0088] S107, photoresist deposition operation, and photolithography and etching operations are performed to form the gate.

[0089] Specifically, photoresist is deposited sequentially in the LDMOS region, VDMOS region, and CMOS region, followed by photolithography and etching operations to form the gate of the smart power module 100.

[0090] Specifically, in chip-level integration, the N-type silicon substrate of the chip is first formed. Then, the N-type silicon substrate is processed (oxidation, partial etching, and silicon epitaxy) to form the buried oxide layer of the chip. The buried oxide layer is then processed (trench etching) to form the trench region of the chip. Next, the silicon wafer with the trench region is processed (photoresist deposition, etching, ion implantation, and annealing) to form the deep P-well of the chip. Then, the trench surface and the deep P-well surface are processed (high-temperature treatment) to form the oxide layer of the chip. Then, the oxide layer is processed (polysilicon layer deposition, multiple ion implantations, and annealing) to form the LDMOS region, VDMOS region, and CMOS region of the chip, respectively. Finally, the chip is processed (photoresist deposition, photolithography, and etching) to form the gate of the chip.

[0091] Furthermore, the trench region may include a first channel and a second channel, wherein the first channel is located between the LDMOS region and the VDMOS region, and the second channel is located between the VDMOS region and the CMOS region.

[0092] It should be understood that the first channel located between the LDMOS region and the VDMOS region can be used to isolate the LDMOS region and the VDMOS region, so that the LDMOS region and the VDMOS region can work independently, avoiding mutual interference between the high voltage and low current of the LDMOS region and the high voltage and high current of the VDMOS region. Similarly, the second channel located between the VDMOS region and the CMOS region can be used to isolate the VDMOS region and the CMOS region, so that the VDMOS region and the CMOS region can work independently, avoiding mutual interference between the high voltage and high current of the VDMOS region and the low voltage and low current of the CMOS region. This improves the stability and reliability of the intelligent power module 100.

[0093] Furthermore, in embodiments of the present invention, the aforementioned LDMOS region, VDMOS region, and CMOS region can be formed in the following manner:

[0094] In one embodiment of the present invention, such as Figure 9 As shown, multiple ion implantation and annealing operations are performed to form the LDMOS region, VDMOS region, and CMOS region, including:

[0095] S201, the first photolithography operation, ion implantation operation, and annealing operation are performed to form a P-trap.

[0096] Specifically, after performing the first photolithography, ion implantation, and annealing operations on the oxide layer after the polysilicon layer has been deposited, a P-well on the chip is formed.

[0097] S202, a second photolithography operation, ion implantation operation, and annealing operation are performed to form the N+ region.

[0098] Specifically, after performing a second photolithography operation, ion implantation operation, and annealing operation on the oxide layer after the polysilicon layer has been deposited, the N+ region on the chip is formed.

[0099] S203, a third photolithography operation, ion implantation operation, and annealing operation are performed to form the N-well corresponding to the LDMOS region.

[0100] Specifically, after performing a third photolithography operation, ion implantation operation, and annealing operation on the oxide layer after the polysilicon layer has been deposited, the N-well corresponding to the LDMOS region on the chip is formed.

[0101] S204, performs the fourth photolithography operation, ion implantation operation, and annealing operation to form the P-well corresponding to the LDMOS region.

[0102] Specifically, after performing a fourth photolithography operation, ion implantation operation, and annealing operation on the oxide layer after the polysilicon layer has been deposited, the P-well corresponding to the LDMOS region on the chip is formed.

[0103] S205 performs the fifth photolithography operation, ion implantation operation, and annealing operation to form the N+ region corresponding to the LDMOS region.

[0104] Specifically, after performing a fifth photolithography operation, ion implantation operation, and annealing operation on the oxide layer after the polysilicon layer has been deposited, the N+ region corresponding to the LDMOS region on the chip is formed.

[0105] S206, the sixth photolithography operation, ion implantation operation and annealing operation are performed to form the P+ region corresponding to the CMOS region.

[0106] Specifically, after performing a sixth photolithography operation, ion implantation operation, and annealing operation on the oxide layer after the polysilicon layer has been deposited, the P+ region corresponding to the CMOS region on the chip is formed.

[0107] It is understood that, in the embodiments of the present invention, firstly, a P-well is formed by performing a first photolithography operation, an ion implantation operation, and an annealing operation; then, an N+ region is formed by performing a second photolithography operation, an ion implantation operation, and an annealing operation; then, an N-well corresponding to the LDMOS region is formed by performing a third photolithography operation, an ion implantation operation, and an annealing operation; then, a P-well corresponding to the LDMOS region is formed by performing a fourth photolithography operation, an ion implantation operation, and an annealing operation; and finally, an N+ region corresponding to the LDMOS region is formed by performing a fifth photolithography operation, an ion implantation operation, and an annealing operation; and finally, a P+ region corresponding to the CMOS region is formed by performing a sixth ion photolithography operation, an implantation operation, and an annealing operation.

[0108] Specifically, according to embodiments of the present invention, when forming the LDMOS region, VDMOS region, and CMOS region of the chip, the P-well of the chip is first formed, then the N+ region of the chip is formed, then the N-well corresponding to the LDMOS region is formed, then the P-well corresponding to the LDMOS region is formed, and then the N+ region corresponding to the LDMOS region is formed, and finally the P+ region corresponding to the CMOS region is formed. The P-well of the chip is formed through a first photolithography operation, an ion implantation operation, and an annealing operation; the N+ region of the chip is formed through a second photolithography operation, an ion implantation operation, and an annealing operation; the N-well corresponding to the LDMOS region is formed through a third ion photolithography operation, an implantation operation, and an annealing operation; the P-well corresponding to the LDMOS region is formed through a fourth photolithography operation, an ion implantation operation, and an annealing operation; the N+ region corresponding to the LDMOS region is formed through a fifth photolithography operation, an ion implantation operation, and an annealing operation; and the P+ region corresponding to the CMOS region is formed through a sixth photolithography operation, an ion implantation operation, and an annealing operation.

[0109] In another embodiment of the invention, such as Figure 10 As shown, multiple ion implantation and annealing operations are performed to form the LDMOS region, VDMOS region, and CMOS region. This also includes:

[0110] S301, the first photolithography operation, ion implantation operation and annealing operation are performed to form a P-trap.

[0111] Specifically, after performing the first photolithography, ion implantation, and annealing operations on the oxide layer after the polysilicon layer has been deposited, a P-well on the chip is formed.

[0112] S302, a second photolithography operation, ion implantation operation, and annealing operation are performed to form the N+ region.

[0113] Specifically, after performing a second photolithography operation, ion implantation operation, and annealing operation on the oxide layer after the polysilicon layer has been deposited, the N+ region on the chip is formed.

[0114] S303 performs a third photolithography operation, ion implantation operation, and annealing operation to form the P+ region corresponding to the CMOS region.

[0115] Specifically, after performing a third photolithography operation, ion implantation operation, and annealing operation on the oxide layer after the polysilicon layer has been deposited, the P+ region corresponding to the CMOS region on the chip is formed.

[0116] S304 performs the fourth photolithography, ion implantation, and annealing operation to form the N-well corresponding to the LDMOS region.

[0117] Specifically, after performing a fourth photolithography operation, ion implantation operation, and annealing operation on the oxide layer after the polysilicon layer has been deposited, the N-well corresponding to the LDMOS region on the chip is formed.

[0118] S305 performs the fifth photolithography operation, ion implantation operation, and annealing operation to form the P-well corresponding to the LDMOS region.

[0119] Specifically, after performing a fifth photolithography operation, ion implantation operation, and annealing operation on the oxide layer after the polysilicon layer has been deposited, the P-well corresponding to the LDMOS region on the chip is formed.

[0120] S306 performs the sixth photolithography operation, ion implantation operation, and annealing operation to form the N+ region corresponding to the LDMOS region.

[0121] Specifically, after performing a sixth photolithography operation, ion implantation operation, and annealing operation on the oxide layer after the polysilicon layer has been deposited, the N+ region corresponding to the LDMOS region on the chip is formed.

[0122] It is understood that, in the embodiments of the present invention, firstly, a P-well is formed by performing a first photolithography operation, an ion implantation operation, and an annealing operation; then, an N+ region is formed by performing a second photolithography operation, an ion implantation operation, and an annealing operation; then, a P+ region corresponding to the CMOS region is formed by performing a third photolithography operation, an ion implantation operation, and an annealing operation; then, an N-well corresponding to the LDMOS region is formed by performing a fourth photolithography operation, an ion implantation operation, and an annealing operation; then, a P-well corresponding to the LDMOS region is formed by performing a fifth photolithography operation, an ion implantation operation, and an annealing operation; finally, an N+ region corresponding to the LDMOS region is formed by performing a sixth photolithography operation, an ion implantation operation, and an annealing operation.

[0123] Specifically, according to embodiments of the present invention, when forming the LDMOS region, VDMOS region, and CMOS region of the chip, the P-well of the chip is first formed, then the N+ region of the chip is formed, then the P+ region corresponding to the CMOS region is formed, then the N-well corresponding to the LDMOS region is formed, and then the P-well corresponding to the LDMOS region is formed, and finally the N+ region corresponding to the LDMOS region is formed. The P-well of the chip is formed through a first photolithography operation, an ion implantation operation, and an annealing operation; the N+ region of the chip is formed through a second ion photolithography operation, an implantation operation, and an annealing operation; the P+ region corresponding to the CMOS region is formed through a third photolithography operation, an ion implantation operation, and an annealing operation; the N-well corresponding to the LDMOS region is formed through a fourth photolithography operation, an ion implantation operation, and an annealing operation; the P-well corresponding to the LDMOS region is formed through a fifth photolithography operation, an ion implantation operation, and an annealing operation; and the N+ region corresponding to the LDMOS region is formed through a sixth photolithography operation, an ion implantation operation, and an annealing operation.

[0124] It is understood that, in the process of fabricating the intelligent power module using the intelligent power module fabrication method of the present invention, the P+ region corresponding to the CMOS region can be fabricated first, and then the N-well, P-well and N+ region corresponding to the LDMOS region can be fabricated sequentially. Alternatively, the N-well corresponding to the LDMOS region can be fabricated sequentially first, then the P-well and N+ region corresponding to the LDMOS region can be formed, and then the P+ region corresponding to the CMOS region can be fabricated.

[0125] It should be noted that the intelligent power module 100 prepared by the method of the present invention has chip-level integration of the power device 100, the drive control module 20, and the switching power supply 30, which is beneficial to meeting the miniaturization requirements of the intelligent power module 100. At the same time, compared with the multi-chip integrated intelligent power modules in the prior art, which need to connect the drive current to the power device by means of wire bonding, and the wire bonding points need to be opened and copper printed, the intelligent power module 100 of this application can further reduce the packaging steps such as wire bonding and printing through chip-level integration, which is beneficial to reducing the manufacturing cost of the intelligent power module 100. In addition, the chips are connected by internal wiring, which has short distance and small parasitic parameters, which is beneficial to improving the performance of the intelligent power module 100.

[0126] In addition, in the method for fabricating the intelligent power module described in the above embodiments of the present invention, the chip process can preferably be 0.8μm.

[0127] It should be understood that the method for fabricating the smart power module disclosed in the embodiments of the present invention achieves electrical isolation between components of different power levels by forming a buried oxide layer at the bottom of an N-type silicon substrate, and forming a first channel between the LDMOS region and the VDMOS region on the buried oxide layer, and a second channel between the VDMOS region and the CMOS region. In addition, by using vertically structured MOS transistors as power devices, the power level of the smart power module is improved, and the heat dissipation capability of the smart power module is enhanced.

[0128] It should be noted that the intelligent power module of this embodiment is obtained by using the intelligent power module preparation method described in this embodiment. Therefore, other specific implementations of the intelligent power module preparation method of this embodiment can be found in the specific implementation of the intelligent power module 100 described above, and will not be repeated here.

[0129] In summary, the intelligent power module fabrication method according to the embodiments of the present invention achieves chip-level integration of power devices, drive control modules and switching power supplies by fabricating chips in a single process using SOI-BCD technology. This reduces the manufacturing cost of intelligent power modules, meets the miniaturization requirements of intelligent power modules, and improves the performance of intelligent power modules.

[0130] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0131] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0132] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0133] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0134] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0135] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0136] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0137] Although embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention. In other words, the above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A smart power module, comprising power devices, a drive control module, and a switching power supply, characterized in that, The power device, the drive control module, and the switching power supply are integrated at the chip level to form a single chip, and are fabricated in a single fabrication process using SOI-BCD technology. The chip also integrates a detection and protection module, which detects the operating status of the power device and generates a protection signal to the drive control module to stop the chip from working. The detection and protection module includes a temperature display unit, which is used to display the operating temperature of the chip in real time. The chip also integrates a reference power supply module, wherein the switching power supply is used to generate a power signal to the drive control module, the reference power supply module and the detection and protection module, the reference power supply module generates a reference power signal to the drive control module according to the power signal, and the drive control module generates a drive signal to the power device according to the power signal and the reference power signal to drive the power device to turn on or off. The drive control module includes: A control unit, wherein the control unit is used to output a first control signal and a second control signal; A rectification and filtering unit is used to rectify and filter the first control signal and the second control signal respectively according to the reference power supply signal; A high-voltage side drive output unit is used to output a high-voltage drive signal according to the power supply signal and the first control signal after rectification and filtering. A low-voltage side drive output unit is used to output a low-voltage drive signal according to the power supply signal and the rectified and filtered second control signal.

2. The intelligent power module as described in claim 1, characterized in that, The detection and protection module includes: An undervoltage detection unit, which is used to output an undervoltage protection signal; An overvoltage detection unit is used to output an overvoltage protection signal; An over-temperature detection unit is used to output an over-temperature protection signal; An overcurrent detection unit is used to output an overcurrent protection signal; The NAND gate unit outputs the protection signal to the drive control module based on the undervoltage protection signal, overvoltage protection signal, overtemperature protection signal and overcurrent protection signal.

3. The intelligent power module as described in any one of claims 1-2, characterized in that, The power device is a vertically structured MOSFET.

4. The intelligent power module as described in any one of claims 1-2, characterized in that, During the fabrication of the chip An N-type silicon substrate is formed, and oxidation, partial etching, and silicon epitaxy are performed on the N-type silicon substrate to form a buried oxide layer; The buried oxide layer is etched with trenches to form a trench region; Photoresist is deposited on the trench region, followed by etching, ion implantation, and annealing to form a deep P-well; The surfaces of the trenches and deep P-wells are subjected to high-temperature treatment to form an oxide layer; A polycrystalline silicon layer is deposited on the oxide layer; Multiple ion implantation and annealing operations are performed to form the LDMOS region, VDMOS region, and CMOS region; Photoresist is deposited, and photolithography and etching are performed to form the gate.

5. The intelligent power module as described in claim 4, characterized in that, The trench region includes a first channel and a second channel, wherein the first channel is located between the LDMOS region and the VDMOS region, and the second channel is located between the VDMOS region and the CMOS region.

6. The intelligent power module as described in claim 5, characterized in that, When forming the LDMOS region, VDMOS region, and CMOS region The first photolithography, ion implantation, and annealing processes are performed to form a P-well; A second photolithography, ion implantation, and annealing process is performed to form the N+ region; A third photolithography, ion implantation, and annealing process is performed to form the N-well of the LDMOS region. A fourth photolithography, ion implantation, and annealing operation is performed to form the P-well of the LDMOS region. A fifth photolithography, ion implantation, and annealing operation is performed to form the N+ region of the LDMOS region. A sixth photolithography, ion implantation, and annealing operation is performed to form the P+ region of the CMOS region.

7. The intelligent power module as described in claim 5, characterized in that, When forming the LDMOS region, VDMOS region, and CMOS region The first photolithography, ion implantation, and annealing processes are performed to form a P-well; A second photolithography, ion implantation, and annealing process is performed to form the N+ region; A third photolithography, ion implantation, and annealing operation is performed to form the P+ region of the CMOS region. A fourth photolithography, ion implantation, and annealing operation is performed to form the N-well of the LDMOS region. A fifth photolithography, ion implantation, and annealing process is performed to form the P-well of the LDMOS region. A sixth photolithography, ion implantation, and annealing operation is performed to form the N+ region of the LDMOS region.

8. A household appliance, characterized in that, Includes the smart power module as described in any one of claims 1-7.

9. A method for fabricating an intelligent power module, characterized in that, The intelligent power module includes power devices, a drive control module, and a switching power supply. The power devices, drive control module, and switching power supply are integrated at the chip level to form a single chip. The chip also integrates a detection and protection module. This module detects the operating status of the power devices and generates a protection signal to the drive control module, causing the chip to stop operating. The detection and protection module includes a temperature display unit for real-time display of the chip's operating temperature. The chip also integrates a reference power supply module. The switching power supply generates a power signal for the drive control module, the reference power supply module, and the detection and protection module. The reference power supply module generates a reference power signal based on the power signal and sends it to the drive control module. A drive control module is provided, which generates a drive signal for the power device based on the power signal and the reference power signal to drive the power device to turn on or off. The drive control module includes: a control unit for outputting a first control signal and a second control signal; a rectification and filtering unit for rectifying and filtering the first control signal and the second control signal based on the reference power signal; a high-voltage side drive output unit for outputting a high-voltage drive signal based on the power signal and the rectified and filtered first control signal; and a low-voltage side drive output unit for outputting a low-voltage drive signal based on the power signal and the rectified and filtered second control signal. The fabrication method includes: The chip was fabricated in a single fabrication process using SOI-BCD.

10. The method as described in claim 9, characterized in that, The chip is fabricated in a single fabrication process using SOI-BCD technology, including: An N-type silicon substrate is formed, and oxidation, partial etching, and silicon epitaxy are performed on the N-type silicon substrate to form a buried oxide layer; The buried oxide layer is etched with trenches to form a trench region; Photoresist is deposited on the trench region, followed by etching, ion implantation, and annealing to form a deep P-well; The surfaces of the trenches and deep P-wells are subjected to high-temperature treatment to form an oxide layer; A polycrystalline silicon layer is deposited on the oxide layer; Multiple ion implantation and annealing operations are performed to form the LDMOS region, VDMOS region, and CMOS region; Photoresist is deposited, and photolithography and etching are performed to form the gate.

11. The method as described in claim 10, characterized in that, The trench region includes a first channel and a second channel, wherein the first channel is located between the LDMOS region and the VDMOS region, and the second channel is located between the VDMOS region and the CMOS region.

12. The method as described in claim 11, characterized in that, Multiple ion implantation and annealing operations are performed to form LDMOS, VDMOS, and CMOS regions, including: The first photolithography, ion implantation, and annealing processes are performed to form a P-well; A second photolithography, ion implantation, and annealing process is performed to form the N+ region; A third photolithography, ion implantation, and annealing process is performed to form the N-well of the LDMOS region. A fourth photolithography, ion implantation, and annealing operation is performed to form the P-well of the LDMOS region. A fifth photolithography, ion implantation, and annealing operation is performed to form the N+ region of the LDMOS region. A sixth photolithography, ion implantation, and annealing operation is performed to form the P+ region of the CMOS region.

13. The method as described in claim 11, characterized in that, Multiple ion implantation and annealing operations are performed to form LDMOS, VDMOS, and CMOS regions, including: The first photolithography, ion implantation, and annealing processes are performed to form a P-well; A second photolithography, ion implantation, and annealing process is performed to form the N+ region; A third photolithography, ion implantation, and annealing operation is performed to form the P+ region of the CMOS region. A fourth photolithography, ion implantation, and annealing operation is performed to form the N-well of the LDMOS region. A fifth photolithography, ion implantation, and annealing process is performed to form the P-well of the LDMOS region. A sixth photolithography, ion implantation, and annealing operation is performed to form the N+ region of the LDMOS region.

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