Light-emitting element

Abstract

The present invention discloses a light-emitting element, comprising a semiconductor structure, which includes a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; a surrounding portion located on and / or surrounding the semiconductor structure to expose a surface of the first semiconductor layer; a first insulating structure located on the semiconductor structure, including a plurality of protruding portions to cover a part of the surface of the first semiconductor layer and a plurality of recessed portions to expose other parts of the surface of the first semiconductor layer; a first contact portion formed on the surrounding portion and contacting other parts of the surface of the first semiconductor layer through the plurality of recessed portions; a first bonding pad formed on the semiconductor structure; and a second bonding pad formed on the semiconductor structure.

Description

[0001] This application is a divisional application of a Chinese patent application (Application No.: 201810058016.6, Application Date: January 22, 2018, Invention Title: Light-Emitting Element). Technical Field

[0002] The present invention relates to a structure of a light-emitting element, and particularly to a light-emitting element including a semiconductor structure and a pad located on the semiconductor structure. Background Art

[0003] A light-emitting diode (LED) is a solid-state semiconductor light-emitting element, which has the advantages of low power consumption, low heat generation, long working life, shock resistance, small size, fast response speed, and good optoelectronic properties, such as a stable emission wavelength. Therefore, light-emitting diodes are widely used in household appliances, device indicators, and optoelectronic products, etc. Summary of the Invention

[0004] A light-emitting element includes a semiconductor structure, which includes a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; a surrounding portion located on and / or surrounding the semiconductor structure to expose a surface of the first semiconductor layer; a first insulating structure located on the semiconductor structure, including a plurality of protruding portions to cover a part of the surface of the first semiconductor layer and a plurality of recessed portions to expose other parts of the surface of the first semiconductor layer; a first contact portion formed on the surrounding portion and contacting other parts of the surface of the first semiconductor layer through the plurality of recessed portions; a first pad formed on the semiconductor structure; and a second pad formed on the semiconductor structure. Description of the Drawings

[0005] Figure 1 Is a top view of a light-emitting element 2 disclosed in an embodiment of the present invention;

[0006] Figure 2 Is along Figure 1 The cross-sectional view of the light-emitting element 2 disclosed along the line B-B';

[0007] Figure 3 Is along Figure 1 The cross-sectional view of the light-emitting element 2 disclosed along the line C-C';

[0008] Figure 4 Is Figure 1 The top view of each layer of the light-emitting element 2 disclosed;

[0009] Figure 5 Is a top view of the burned area of the light-emitting element 2 disclosed in an embodiment of the present invention;

[0010] Figure 6 Top view of the burned area of the conventional light-emitting element 3;

[0011] Figure 7 Voltage waveform diagram of a surge under an electrical over stress (EOS) test;

[0012] Figure 8 Graph of the maximum applied voltage of the surge against the forward voltage (Vf) that can be turned on;

[0013] Figure 9 Graph of the maximum applied voltage of the surge against the reverse current (Ir);

[0014] Figure 10 Schematic diagram of a light-emitting device 30 according to an embodiment of the present invention;

[0015] Figure 11 Schematic diagram of a light-emitting device 4 according to an embodiment of the present invention.

[0016] Symbol description

[0017] 2 Light-emitting element

[0018] 3 Conventional light-emitting element

[0019] 4 Light-emitting device

[0020] 10b Semiconductor stack

[0021] 11b Substrate

[0022] 20b, 20b' First insulating structure

[0023] 30 Light-emitting device

[0024] 30b Transparent conductive layer

[0025] 40b Reflective layer

[0026] 41b Barrier layer

[0027] 50b, 50b' Second insulating structure

[0028] 60b Contact layer

[0029] 60b' Contact layer

[0030] 70b Third insulating structure

[0031] 80b First pad

[0032] 90b Second bonding pad

[0033] 100b Through hole

[0034] 101b First semiconductor layer

[0035] 102b Second semiconductor layer

[0036] 102sb Surface

[0037] 103b Active layer

[0038] 111b Surrounding part

[0039] 201b Surrounding insulating part

[0040] 203b Annular covering area

[0041] 301tb Opening

[0042] 401tb Opening

[0043] 411tb Opening

[0044] 501b Opening

[0045] 503b Opening

[0046] 505b Periphery

[0047] 600b First contact part

[0048] 601b Second contact part

[0049] 602b Third contact part

[0050] 701b First opening

[0051] 702b Second opening

[0052] 1000b Semiconductor structure

[0053] 1002b Inner side wall

[0054] 1001b Second outer side wall

[0055] 1003b First outer side wall

[0056] 1011b First surface

[0057] 1012b Second surface

[0058] 2011b Protrusion

[0059] 2012b Depression

[0060] 5051b protrusion Detailed implementation mode

[0061] To make the description of the present invention more detailed and complete, please refer to the description of the following embodiments and cooperate with the relevant drawings. However, the embodiments shown below are used to illustrate the light-emitting elements of the present invention, and the present invention is not limited to the following embodiments. Moreover, the dimensions, materials, shapes, relative configurations, etc. of the constituent parts described in the embodiments of this specification are not limited without specific descriptions, and the scope of the present invention is not limited thereto, but is only for simple illustration. Also, the sizes or positional relationships of the components shown in the drawings may be exaggerated for the sake of clear illustration. Furthermore, in the following description, for the sake of appropriately omitting detailed descriptions, the same or similar components are denoted by the same names and symbols.

[0062] As Figures 1 to 4 shown Figure 1 is a top view of a light-emitting element 2 disclosed in an embodiment of the present invention. Figure 2 is a cross-sectional view of the light-emitting element 2 taken along line B-B' of Figure 1 . Figure 3 is a cross-sectional view of the light-emitting element 2 taken along line C-C' of Figure 1 . Figure 4 is Figure 1 a flowchart of the light-emitting element 2 disclosed.

[0063] The light-emitting element 2 includes a substrate 11b; one or more semiconductor structures 1000b located on the substrate 11b; a surrounding portion 111b located on and / or surrounding one or more semiconductor structures 1000a; a first insulating structure 20b located on the semiconductor structure 1000b and formed along the surrounding portion 111b; a transparent conductive layer 30b located on one or more semiconductor structures 1000b; a reflective structure including a reflective layer 40b and a barrier layer 41b located on the transparent conductive layer 30b; a second insulating structure 50b covering the reflective layer 40b and the barrier layer 41b; a contact layer 60b located on the second insulating structure 50b; a third insulating structure 70b located on the contact layer 60b; and a first pad 80b and a second pad 90b located on the contact layer 60b.

[0064] As Figures 1 to 4 shown, in the manufacturing process of the light-emitting element 2, first, a semiconductor stack 10b is formed on the substrate 11b. The substrate 11b can be a sapphire substrate, but is not limited thereto. In one embodiment, the substrate 11b includes a patterned surface. The patterned surface includes a plurality of patterns. The shapes of the patterns include cone, pyramid, or hemisphere.

[0065] In an embodiment of the present invention, the substrate 11b is a growth substrate for epitaxially growing a semiconductor stack 10b, including a gallium arsenide (GaAs) wafer for growing aluminum gallium indium phosphide (AlGaInP), or a sapphire (Al 2 O 3 ) wafer, a gallium nitride (GaN) wafer, or a silicon carbide (SiC) wafer.

[0066] In an embodiment of the present invention, the substrate 11b includes a patterned surface located between the semiconductor structure 1000b and the substrate 11b, which can improve the light extraction efficiency of the light-emitting element. The exposed surface of the substrate 11b may include a patterned surface (not shown in the figure). The patterned surface can be various patterns, such as an irregular pattern, a microlens, a microarray, a scattering region, or other optical regions. For example, the patterned surface includes a plurality of protrusions, each protrusion having a height between 0.5 and 2.5 μm, a width between 1 and 3.5 μm, and a pitch between 1 and 3.5 μm between the plurality of protrusions.

[0067] In an embodiment of the present invention, the substrate 11b includes a sidewall, which includes a flat surface and / or a rough surface to improve the light extraction efficiency of the light-emitting element. In an embodiment of the present invention, the sidewall of the substrate 11b is inclined with respect to a surface of the substrate 11b adjacent to the semiconductor structure 1000b to adjust the light field distribution of the light-emitting element.

[0068] In an embodiment of the present invention, the semiconductor stack 10b includes optical characteristics, such as a light-emitting angle or a wavelength distribution, and electrical characteristics, such as a forward voltage or a forward current. The semiconductor stack 10b is formed on the substrate 11b by metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), physical vapor deposition (PVD), or ion plating methods, where the physical vapor deposition method includes sputtering or evaporation methods.

[0069] One or more semiconductor structures 1000b each include a semiconductor stack 10b, which includes a first semiconductor layer 101b, a second semiconductor layer 102b, and an active layer 103b located between the first semiconductor layer 101b and the second semiconductor layer 102b. The semiconductor structure 1000b also includes one or more vias 100b passing through the second semiconductor layer 102b and the active layer 103b to expose the first semiconductor layer 101b. The first semiconductor layer 101b and the second semiconductor layer 102b may each be composed of a single layer or multiple sub-layers. In addition, the active layer 103b may be a single quantum well structure or a multiple quantum well structure. The semiconductor stack 10b may be formed of a group III nitride compound semiconductor layer on a substrate 11b by metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or physical vapor deposition (PVD).

[0070] In an embodiment of the present invention, before forming the semiconductor stack 10b, a buffer structure (not shown in the figure) may be formed on the substrate 11b to improve the lattice mismatch between the substrate 11b and the semiconductor stack 10b. The buffer structure may be composed of materials of the gallium nitride (GaN) series, such as gallium nitride and aluminum gallium nitride, or materials of the aluminum nitride (AlN) series. The buffer structure may be a single layer or multiple layers. The buffer structure may be formed by metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or physical vapor deposition (PVD). Physical vapor deposition (PVD) includes sputtering methods, such as reactive sputtering, or evaporation methods, such as electron beam evaporation and thermal evaporation. In one embodiment, the buffer structure includes an aluminum nitride (AlN) buffer layer and is formed by sputtering. The aluminum nitride (AlN) buffer layer is formed on a growth substrate having a patterned surface. The sputtering method can form a dense buffer layer with high uniformity, so the aluminum nitride (AlN) buffer layer can be conformally deposited on the patterned surface of the substrate 11b.

[0071] In an embodiment of the present invention, the first semiconductor layer 101b and the second semiconductor layer 102b may be cladding layers, having different conduction types, electrical properties, polarities, or providing electrons or holes according to the doped elements. For example, the first semiconductor layer 101b is an n-type semiconductor layer, and the second semiconductor layer 102b is a p-type semiconductor layer. The active layer 103b is formed between the first semiconductor layer 101b and the second semiconductor layer 102b. Electrons and holes recombine in the active layer 103b under a current drive and convert electrical energy into light energy to emit a light ray. By changing the physical and chemical composition of one or more layers of the semiconductor stack 10b, the wavelength of the light ray emitted by the light-emitting element 2 is adjusted. The material of the semiconductor stack 10b includes group III-V semiconductor materials, such as Al xIn y Ga (1-x-y) N or Al x In y Ga (1-x-y) P, where 0 ≤ x, y ≤ 1; (x + y) ≤ 1. Depending on the material of the active layer 103b, when the material of the semiconductor stack 10b is of the AlInGaP series, the active layer 103b can emit red light with a wavelength between 610 nm and 650 nm, or yellow light with a wavelength between 530 nm and 570 nm. When the material of the semiconductor stack 10b is of the InGaN series, the active layer 103b can emit blue light, deep blue light with a wavelength between 400 nm and 490 nm, or green light with a wavelength between 490 nm and 550 nm. When the material of the semiconductor stack 10b is of the AlGaN series, the active layer 103b can emit ultraviolet light with a wavelength between 250 nm and 400 nm. The active layer 103b can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well structure (MQW). The material of the active layer 103b can be a semiconductor with neutral, p-type, or n-type electrical properties.

[0072] After the semiconductor stack 10b is formed on the substrate 11b, the semiconductor stack 10b is patterned by photolithography and etching processes to form a plurality of vias 100b and a surrounding portion 111b. Through photolithography and etching processes, a part of the interior of the second semiconductor layer 102b and the active layer 103b is removed to form a plurality of vias 100b, and the plurality of vias 100b correspondingly expose the second surface 1012b of the first semiconductor layer 101b. Herein, the via 100b is defined by an inner sidewall 1002b and the second surface 1012b. One end of the inner sidewall 1002b is connected to the second surface 1012b of the first semiconductor layer 101b, and the other end of the inner sidewall 1002b is connected to the surface 102sb of the second semiconductor layer 102b.

[0073] In the same or another photolithography and etching process, the second semiconductor layer 102b and the active layer 103b surrounding the semiconductor structure 1000b are removed to form a surround portion 111b, and the surround portion 111b exposes the first surface 1011b of the first semiconductor layer 101b. In another embodiment, in the photolithography and etching process, a portion of the first semiconductor layer 101b is further etched to a deeper etching depth to expose the second surface 1012b and the first surface 1011b. Specifically, the surround portion 111b includes the exposed surface of the substrate 11b, the first surface 1011b of the first semiconductor layer 101b exposed, and the first outer sidewall 1003b and the second outer sidewall 1001b formed by the side surfaces of the second semiconductor layer 102b, the active layer 103b, and the first semiconductor layer 102b exposed, wherein one end of the first surface 1011b is connected to the first outer sidewall 1003b, and the other end of the first surface 1011b is connected to the second outer sidewall 1001b. The first outer sidewall 1003b and the second outer sidewall 1001b are inclined with respect to the first surface 1011b. The surround portion 111b is formed along a periphery of the semiconductor structure 1000b and is located at and / or around the periphery of one or more semiconductor structures 1000b. In one embodiment, the first outer sidewall 1003b is inclined with respect to the exposed surface of the substrate 11b (not shown in the figure). An acute angle is included between the first outer sidewall 1003b and the exposed surface of the substrate 11b. In one embodiment, an obtuse angle is included between the first outer sidewall 1003b and the exposed surface of the substrate 11b.

[0074] After the semiconductor structure 1000b is formed, the first insulating structure 20b is formed on the semiconductor stack 10b, covering a portion of the surface 102sb of the second semiconductor layer 102b and extending to the second outer sidewall 1001b, and covering the first surface 1011b. In other words, the first insulating structure 20b covers multiple portions of the surround portion 111b. The first insulating structure 20b protects the sidewalls of the semiconductor structure 1000b and prevents the active layer 103b from being damaged by subsequent fabrication processes. As Figure 4As shown, in a top view, the first insulating structure 20b includes a surrounding insulating portion 201b and a plurality of annular covering regions 203b. Herein, in a top view, the surrounding insulating portion 201b includes a plurality of protrusions 2011b and a plurality of recesses 2012b. The plurality of annular covering regions 203b are surrounded by the surrounding insulating portion 201b, and the plurality of annular covering regions 203b are respectively formed in a plurality of through holes 100b and correspond to the plurality of through holes 100b. Each of the plurality of annular covering regions 203b has an opening (not labeled in the figure) to expose the second surface 1012b of the first semiconductor layer 101b. In one embodiment, the surrounding insulating portion 201b of the first insulating structure 20b is disposed along the first surface 1011b of the first semiconductor layer 101b and surrounds the semiconductor structure 1000b. In this embodiment, the plurality of protrusions 2011b and the plurality of recesses 2012b of the surrounding insulating portion 201b are alternately arranged along the surrounding portion 111b, and the positions of the plurality of annular covering regions 203b correspond to the positions of the plurality of through holes 100b, but the present invention is not limited thereto. In one embodiment, a region between two protrusions 2011b constitutes a recess 2012b. In another embodiment, the surrounding insulating portion 201b further includes a secondary protrusion extending from the protrusion 2011b, and / or further includes a secondary recess recessed from the recess 2012b. In this embodiment, the plurality of protrusions 2011b extend from the upper surface 102sb of the second semiconductor layer 102b, directly contact and cover a plurality of portions of the first surface 1011b of the first semiconductor layer 101b and a plurality of corners of the first surface 1011b of the first semiconductor layer 102b. The plurality of recesses 2012b expose other portions of the first surface 1011b of the first semiconductor layer 101b that are not covered by the plurality of protrusions 2011b. In one embodiment, the plurality of recesses 2012b expose the first surface 1011b located on the plurality of sides of the semiconductor structure 1000b. As Figure 2 shown, in a cross-sectional view, the recess 2012b of the first insulating structure 20b exposes a portion of the first surface 1011b of the first semiconductor layer 101b. As Figure 3As shown, in a cross-sectional view, the protrusions 2011b of the first insulating structure 20b cover the first surface 1011b of the first semiconductor layer 101b and the multiple sidewalls of the semiconductor structure 1000b. In other words, the multiple protrusions 2011b and the multiple recesses 2012b alternately cover a part of the first surface 1011b of the first semiconductor layer 101b and expose another part of the first surface 1011b of the first semiconductor layer 101b. In this embodiment, the exposed portions of the first surface 1011b are discontinuous, and the total area of the exposed portions of the first surface 1011b is smaller than the total area of the first surface 1011b. Most of the second semiconductor layer 102b is not covered by the first insulating structure 20b. In a top view, the shape of the surrounding insulating portion 201b includes a ring shape, such as a rectangle, a circle, or a polygon. The shape of one of the multiple protrusions 2011b or the multiple recesses 2012b includes a triangle, a rectangle, a semi-circle, a circle, or a polygon. The material of the first insulating structure 20b includes a non-conductive material. The non-conductive material includes an organic material, an inorganic material, or a dielectric material. The organic material includes Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polyimide (PI), polycarbonate (PC), polyetherimide (Polyetherimide), or fluorocarbon polymer (Fluorocarbon Polymer). The inorganic material includes silicone or glass. The dielectric material includes aluminum oxide (Al 2 O 3 ), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium oxide (TiO x ), or magnesium fluoride (MgF x ). The first insulating structure 20b includes one or more layers. The first insulating structure 20b can protect the sidewalls of the semiconductor structure 1000b and prevent the active layer 103b from being damaged by subsequent manufacturing processes. When the first insulating structure 20b includes multiple layers, the first insulating structure 20b can be a distributed Bragg reflector (DBR) structure including multiple pairs of film layers to protect the sidewalls of the semiconductor structure 1000b and selectively reflect light of a specific wavelength emitted by the active layer 103b to the outside of the light-emitting element 2 to improve the brightness, and each film layer has a refractive index different from that of an adjacent film layer. Specifically, the first insulating structure 20b can be formed by alternately stacking SiO x layers and TiO xIt is formed by layers. By adjusting the refractive index difference between the high refractive index and the low refractive index of each pair of film layers, the Bragg reflector (DBR) has a high reflectivity for a specific wavelength or within a specific wavelength range. The two layers in each pair of film layers have different thicknesses. The thicknesses of the layers with the same material in each pair of film layers may be the same or different.

[0075] After the first insulating structure 20b is formed, a transparent conductive layer 30b is formed on the second semiconductor layer 102b, including a plurality of openings 301tb to expose the second surface 1012b of the first semiconductor layer 101b. In this embodiment, in a top view, the shape of the transparent conductive layer 30b corresponds to the shape of the second semiconductor layer 102b, and the positions of the plurality of openings 301tb correspond to the positions of the plurality of annular covering regions 203b and the plurality of through holes 100b. The transparent conductive layer 30b contacts and covers the second semiconductor layer 102b to diffuse current and inject current into the second semiconductor layer 102b. In addition, the transparent conductive layer 30b does not contact the first semiconductor layer 101b. In one embodiment, the light-emitting element 2 includes another transparent conductive layer (not shown in the figure) that contacts the first semiconductor layer 101b of the surrounding portion 111b. The material of the transparent conductive layer 30b includes a transparent material that is transparent to the light emitted from the active layer 103b, such as indium zinc oxide (IZO) or indium tin oxide (ITO). The transparent conductive layer 30b can form a low-resistance contact with the second semiconductor layer 102b, such as an ohmic contact. The transparent conductive layer 30b includes one or more sub-layers. For example, when the transparent conductive layer 30b includes a plurality of sub-layers, the transparent conductive layer 30b can be a Bragg reflector (DBR) structure including multiple pairs of sub-layers, and each sub-layer has a refractive index different from that of the adjacent sub-layer. Specifically, the transparent conductive layer 30b can form a Bragg reflector (DBR) structure by alternately stacking two sub-layers with different refractive indices.

[0076] After the transparent conductive layer 30b is formed, a reflective structure including a reflective layer 40b and a barrier layer 41b is correspondingly formed on the transparent conductive layer 30b. In one embodiment, the reflective structure is aligned with the transparent conductive layer 30b, and the sides of the reflective structure are aligned with the sides of the transparent conductive layer 30b. In one embodiment, the reflective structure is not aligned with the transparent conductive layer 30b, and the sides of the reflective structure are located inside or outside the sides of the transparent conductive layer 30b. In one embodiment, the transparent conductive layer 30b and the reflective structure extend onto the first insulating structure 20b.

[0077] The reflective layer 40b and the barrier layer 41b respectively include a plurality of openings 401tb and 411tb. The plurality of openings 401tb of the reflective layer 40b and the plurality of openings 411tb of the barrier layer 41 expose a plurality of annular coverage areas 203b, a plurality of vias, and a second surface 1012b of the first semiconductor layer 101b. The barrier layer 41b is formed and covers the reflective layer 40b, and the barrier layer 41b can prevent the migration, diffusion, or oxidation of the metal elements of the reflective layer 40b. The shapes of the reflective layer 40b and the barrier layer 41b of the reflective structure correspond to the shape of the transparent conductive layer 30b. In one embodiment, the shapes of the reflective layer 40b and the barrier layer 41b of the reflective structure are close to a rectangle, and the corners of the reflective layer 40b and the barrier layer 41b are arc-shaped. The reflective layer 40b includes a single-layer structure or a multi-layer structure, and the material of the reflective layer 40b includes a metal material having a high reflectivity for the light emitted by the active layer 103b, such as silver (Ag), gold (Au), aluminum (Al), titanium (Ti), chromium (Cr), copper (Cu), nickel (Ni), platinum (Pt), or an alloy of the above materials. The barrier layer 41b includes a single-layer structure or a multi-layer structure, and the material of the barrier layer includes chromium (Cr), platinum (Pt), titanium (Ti), tungsten (W), or zinc (Zn). When the barrier layer 41b is a multi-layer structure, the barrier layer 41b is formed by alternately stacking a first barrier layer (not shown in the figure) and a second barrier layer (not shown in the figure), such as Cr / Pt, Cr / Ti, Cr / TiW, Cr / W, Cr / Zn, Ti / Pt, Ti / W, Ti / TiW, Ti / Zn, Pt / TiW, Pt / W, Pt / Zn, TiW / W, TiW / Zn, or W / Zn. The reflective structure may further include a distributed Bragg reflector (DBR) formed under the reflective layer 40b. The distributed Bragg reflector (DBR) structure includes a plurality of pairs of sub-layers, and each sub-layer has a refractive index different from that of the adjacent sub-layer. In one embodiment, the plurality of pairs of sub-layers can be formed by alternately stacking SiO x layers and TiO x layers. By adjusting the refractive index difference between the high refractive index and the low refractive index of each pair of sub-layers, the distributed Bragg reflector (DBR) has a high reflectivity for a specific wavelength or within a specific wavelength range. The two layers of each pair of sub-layers have different thicknesses. The thicknesses of the layers having the same material in each pair of sub-layers can be the same or different.

[0078] After the reflective structure is formed, a second insulating structure 50b is formed on the reflective structure to cover a part of the upper surface of the reflective structure (reflective layer 40b or barrier layer 41b) and the peripheral region of the second semiconductor layer 102b located between the reflective structure and the first insulating structure 20b. The second insulating structure 50b contacts and covers the first insulating structure 20b, such that the first outer sidewall 1003b and the second outer sidewall 1001b of the surrounding portion 111b and the part of the first surface 1011b covered by the first insulating structure 20b are also covered by the second insulating structure 50b. The second insulating structure 50b can protect the sidewalls of the semiconductor structure 1000b and prevent the active layer 103b from being damaged by subsequent fabrication processes. Since the second insulating structure 50b covers the first insulating structure 20b, the second insulating structure 50b can prevent the first insulating structure 20b from being etched and removed during subsequent fabrication processes. As Figure 4 shown, the second insulating structure 50b includes a plurality of openings 501b and an opening 503b. Herein, the second insulating structure 50b includes a periphery 505b having a plurality of protrusions 5051b and a plurality of recesses 5052b. The opening 503b exposes a part of the reflective layer 40b or the barrier layer 41b of the reflective structure, and the plurality of openings 501b expose the second surface 1012b of the first semiconductor layer 101b. As Figures 2 to 4As shown, in this embodiment, the periphery 505b of the second insulating structure 50b contacts, covers, and aligns with the first insulating structure 20b. The positions of the plurality of openings 501b correspond to the positions of the multi-openings 401tb, 411tb, 301tb, and the plurality of vias 100b. In addition, a plurality of protrusions 5051b and a plurality of recesses 5052b located on the periphery 505b of the second insulating structure 50b are alternately arranged along the surrounding insulating portion 201b or the surrounding portion 111b of the first insulating structure 20b to respectively cover and expose different portions of the first surface 1011b of the first semiconductor layer 101b. In one embodiment, the region between two protrusions 5051b constitutes a recess 5052b. In another embodiment, the second insulating structure 50b further includes a primary protrusion extending from the protrusion 5051b, and / or further includes a primary recess recessed from the recess 5052b. In addition, in one embodiment, the shape of the periphery 505b of the second insulating structure 50b corresponds to the shape of the surrounding insulating portion 201b of the first insulating structure 20b to discontinuously expose a portion of the first surface 1011b of the first semiconductor layer 101b located on the surrounding portion 111b. In other words, the shapes and positions of the plurality of protrusions 5051b and the plurality of recesses 5052b correspond to the shapes and positions of the plurality of protrusions 2011b and the plurality of recesses 2012b of the surrounding insulating portion 201b. The portion of the first surface 1011b exposed by the plurality of recesses 2012b is also exposed by the plurality of recesses 5052b. The portion of the first surface 1011b covered by the plurality of protrusions 2011b is also covered by the plurality of protrusions 5051b. When the first surface 1011b is discontinuously exposed by the first insulating structure 20b and the second insulating structure 50b, in one embodiment, the shapes or positions of the protrusions 5051b and the recesses 5052b may be different from the shapes or positions of the protrusions 2011b and the recesses 2012b. In one embodiment, the areas of the protrusions 5051b and the recesses 5052b may be greater than or less than the areas of the protrusions 2011b and the recesses 2012b. The portion of the first surface 1011b exposed by the recesses 2012b and the recesses 5052b is adjusted by the shapes, positions, or areas of the protrusions 2011b, 5051b and the recesses 2012b, 5052b.

[0079] As Figure 2As shown, in a cross-sectional view, a part of the first surface 1011b of the first semiconductor layer 101b is exposed by the plurality of recesses 2012b of the first insulating structure 20b and is also exposed by the plurality of recesses 5052b of the second insulating structure 50b. In other words, the plurality of recesses 5052b of the second insulating structure 50b expose the portion of the first surface 1011b of the first semiconductor layer 101b that is not covered by the plurality of protrusions 2011b and 5051b and is exposed by the plurality of recesses 2012b. As Figure 3 shown, in a cross-sectional view, the plurality of protrusions 5051b cover the plurality of protrusions 2011b of the first insulating structure 20b on the first surface 1011b of the first semiconductor layer 101b, and cover the surrounding insulating portion 201b formed on the first outer sidewall 1003b and the second outer sidewall 1001b and the corners of the first surface 1011b of the first semiconductor layer 101b, where the first outer sidewall 1003b and the second outer sidewall 1001b are formed by the side surfaces exposed by the second semiconductor layer 102b, the active layer 103b, and the first semiconductor layer 101b. Specifically, in this embodiment, the plurality of protrusions 5051b are in direct contact with the plurality of protrusions 2011b of the first insulating structure 20b, the plurality of recesses 5052b expose the first surface 1011b of the first semiconductor layer 101b, and the plurality of protrusions 5051b and the plurality of recesses 5052b are alternately arranged to discontinuously expose a part of the first surface 1011b of the first semiconductor layer 101b. In other words, the portion of the first surface 1011b exposed by the plurality of recesses 5052b is discontinuous, and the first surface 1011b has a total exposed area. The total exposed area of the first surface 1011b is smaller than the overall area of the first surface 1011b.

[0080] In one embodiment, the shape of one of the plurality of protrusions 5051b includes a triangle, a rectangle, a semi-circle, a circle, or a polygon. The material of the second insulating structure 50b includes a non-conductive material. The non-conductive material includes an organic material, an inorganic material, or a dielectric material. The organic material includes Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polyimide (PI), polycarbonate (PC), polyetherimide (Polyetherimide), or fluorocarbon polymer (Fluorocarbon Polymer). The inorganic material includes silicone or glass. The dielectric material includes aluminum oxide (Al 2 O 3 ), silicon nitride (SiN x ), silicon oxide (SiOx ), titanium oxide (TiO x ), or magnesium fluoride (MgF x ). The second insulating structure 50b includes one or more layers. The second insulating structure 50b can protect the sidewalls of the semiconductor structure 1000b, prevent the active layer 103b from being damaged by subsequent manufacturing processes, and selectively reflect light of a specific wavelength emitted by the active layer 103b to the outside of the light-emitting element 2 to increase the brightness. When the second insulating structure 50b includes multiple layers, the second insulating structure 50b can be a distributed Bragg reflector (DBR) structure including multiple pairs of film layers, and each film layer has a refractive index different from that of an adjacent film layer. In one embodiment, the second insulating structure 50b can be formed by alternately stacking SiO x layers and TiO x layers. By adjusting the refractive index difference between the high refractive index and the low refractive index of each pair of film layers, the distributed Bragg reflector (DBR) has a high reflectivity for a specific wavelength or within a specific wavelength range. The two layers in each pair of film layers have different thicknesses. The thicknesses of the layers with the same material in each pair of film layers can be the same or different.

[0081] Reference Figures 1 to 4, the contact layer 60b is located on the second insulating structure 50b and the reflective structure (reflective layer 40b and barrier layer 41b), and includes a first contact portion 600b, a second contact portion 601b, and a third contact portion 602b. In one embodiment, in a top view, the second contact portion 601b is located at the geometric center of the semiconductor structure. The first contact portion 600b and the third contact portion 602b are separated from each other. The third contact portion 602b is surrounded by the first contact portion 600b. The first contact portion 600b is electrically connected to the first semiconductor layer 101b, the third contact portion 602b is electrically connected to the second semiconductor layer 102b, and the second contact portion 601b is electrically insulated from the first semiconductor layer 101b and the second semiconductor layer 102b. In one embodiment, the second contact portion 601b is electrically connected to one of the first contact portion 600b and the third contact portion 602b. In one embodiment, the first contact portion 600b contacts the second surface 1012b and the first surface 1011b through the plurality of openings 501b and the plurality of recesses 5052b of the second insulating structure 50b and is electrically connected to the first semiconductor layer 101b. In addition, in a cross-sectional view of the surrounding portion 111b, the first contact portion 600b has a concavo-convex upper surface along a periphery 505b of the first insulating structure 20b or the second insulating structure 50b. The first contact portion 600b is formed on the plurality of protrusions 5051b and the plurality of recesses 5052b along the periphery 505b, and the concavo-convex upper surface is formed corresponding to the plurality of protrusions 5051b and the plurality of recesses 5052b. The first contact portion 600b discontinuously contacts the first surface 1011b through the plurality of recesses 2012b of the surrounding insulating portion 201b and the plurality of recesses 5052b of the second insulating structure 50b. The first contact portion 600b and the first surface 1011b of the first semiconductor layer 101b include a plurality of discontinuous first contact regions (not shown). The first contact portion 600b and the second surface 1012b of the first semiconductor layer 101b include a plurality of first contact regions (not shown).

[0082] In this embodiment, the second contact portion 601b and the third contact portion 602b are surrounded by the first contact portion 600b, and in a top view, the shape of the second contact portion 601b includes a geometric shape, such as a rectangle, a circle, or an irregular shape. The third contact portion 602b contacts the reflective structure through the opening 503b of the second insulating structure 50b and is electrically connected to the second semiconductor layer 102b. There is a second contact area (not shown in the figure) between the third contact portion 602b and the reflective structure. In one embodiment, the second contact portion 601b can be connected to the first contact portion 600b or the third contact portion 602b. The contact layer 60b can be a single layer or composed of multiple sub-layers. The contact layer 60b includes a metal material, such as aluminum (Al), chromium (Cr), platinum (Pt), titanium (Ti), tungsten (W), or zinc (Zn).

[0083] Reference Figures 1 to 4 , after the contact layer 60b is formed, the third insulating structure 70b is formed on the contact layer 60b and covers the contact layer 60b. The third insulating structure 70b includes a first opening 701b and a second opening 702b. The first opening 701b of the third insulating structure 70b exposes the first contact portion 600b of the contact layer 60b. The second opening 702b exposes the third contact portion 602b of the contact layer 60b. The material of the third insulating structure 70b includes a non-conductive material. The non-conductive material includes an organic material, an inorganic material, or a dielectric material. The organic material includes Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polyimide (PI), polycarbonate (PC), polyetherimide, or fluorocarbon polymer. The inorganic material includes silicone or glass. The dielectric material includes aluminum oxide (Al 2 O 3 ), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium oxide (TiO x ), or magnesium fluoride (MgF x ). The first insulating structure 20b, the second insulating structure 50b, and the third insulating structure 70b can be formed by screen printing, evaporation, or sputtering.

[0084] After the third insulating structure 70b is formed, the first pad 80b and the second pad 90b are formed on the semiconductor stack 10b to complete the fabrication of the light-emitting element 2. The positions of the first pad 80b and the second pad 90b respectively correspond to the positions of the first opening 701b and the second opening 702b of the third insulating structure 70b. In one embodiment, the positions and shapes of the first pad 80b and the second pad 90b respectively correspond to the positions and shapes of the first opening 701b and the second opening 702b of the third insulating structure 70b. The first pad 80b passes through the first opening 701b of the third insulating structure 70b to contact the first contact portion 600b of the contact layer 60b and is electrically connected to the first semiconductor layer 101b. The second pad 90b passes through the second opening 702b of the third insulating structure 70b to contact the third contact portion 602b of the contact layer 60b and is electrically connected to the second semiconductor layer 102b. In one embodiment, when viewed from a top view of the light-emitting element, the first pad 80b has the same shape as the second pad 90b. For example, the first pad 80b and the second pad 90b include a comb shape, but the invention is not limited thereto. In one embodiment, the shape or size of the first pad 80b may be different from the shape or size of the second pad 90b. For example, the shape of the first pad 80b is rectangular, the shape of the second pad 90b is comb-shaped, and the area of the first pad 80b is larger than the area of the second pad 90b. In one embodiment, the first pad 80b and the second pad 90b include a structure having a single layer or multiple layers. The first pad 80b and the second pad 90b include a metal material, such as chromium (Cr), titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), or an alloy of the above materials. When the first pad 80b and the second pad 90b include multiple layers, the first pad 80b includes a first upper pad and a first lower pad, and the second pad 90b includes a second upper pad and a second lower pad. The upper pad and the lower pad have different functions. The function of the upper pad is for soldering and wiring. The light-emitting element 2 can be flipped and mounted onto a packaging substrate through the upper pad by solder or AuSn eutectic bonding. The upper pad includes a metal material having high ductility, such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), copper (Cu), gold (Au), tungsten (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), osmium (Os). The upper pad can be a single layer, multiple layers, or an alloy of the above materials. In one embodiment of the present invention, the material of the upper pad preferably includes nickel (Ni) and / or gold (Au), and the upper pad can be a single layer or multiple layers.The function of the lower solder pad is to form a stable interface with the contact layer 60b, the reflective layer 40b, or the barrier layer 41b. For example, it improves the interface bonding strength between the first lower solder pad and the contact layer 60b, or improves the interface bonding strength between the second lower solder pad and the reflective layer 40b or the barrier layer 41b. Another function of the lower solder pad is to prevent the diffusion of solder or tin (Sn) in AuSn into the reflective structure and damage the reflectivity of the reflective structure. Therefore, the lower solder pad preferably contains metal elements other than gold (Au) and copper (Cu), such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), tungsten (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), osmium (Os). The lower solder pad can be a single layer, multiple layers, or an alloy of the above materials. In an embodiment of the present invention, the lower solder pad preferably includes a multi-layer film of titanium (Ti) and aluminum (Al), or a multi-layer film of chromium (Cr) and aluminum (Al).

[0085] In one embodiment, when the light-emitting element 2 is operated, an external power source is electrically connected to the first pad 80b and the second pad 90b, respectively. At this time, current is injected into the light-emitting element 2, and the current is diffused through the first contact portion 600b and the third contact portion 602b, and is injected into the first semiconductor layer 101b and the second semiconductor layer 102b via the first contact region and the second contact region, respectively. In order to improve the current distribution of the light-emitting element 2, the area and position of the first contact region between the first contact portion 600b and the first surface 1011b of the first semiconductor layer 101b can be adjusted to avoid current concentration in certain regions of the first surface 1011b, such as the corners of the first surface 1011b. In one embodiment, since the surrounding insulating portion 201b of the first insulating structure 20b and the periphery 505b of the second insulating structure 50b cover a part of the first surface 1011b of the first semiconductor layer 101b, the area and position of the first contact region between the contact layer 60b and the first surface 1011b can be adjusted by the surrounding insulating portion 201b and the second insulating structure 50b. In other words, the area and position of the first contact region are adjusted by the exposed portion of the first surface 1011b exposed by the recesses 2012b and 5052b of the surrounding insulating portion 201b and the second insulating structure 50b. However, when designing the surrounding insulating portion 201b of the first insulating structure 20b and the second insulating structure 50b, the forward voltage (Vf) and current distribution of the light-emitting element 2 must be considered and a trade-off must be made. Specifically, the larger the area of the first contact region, the lower the forward voltage of the light-emitting element 2. However, if the area of the first contact region is too large, the light-emitting element 2 will have a current congestion effect. In order to achieve an acceptable forward voltage (Vf) and a better current distribution, the first contact portion 600b is designed to discontinuously contact the first surface 1011b through a plurality of recesses 2012b and 5052b, and is electrically insulated from a part of the first surface 1011b through a plurality of protrusions 2011b and 5051b. In one embodiment, the first contact portion 600b is designed to avoid contacting the corners of the first surface 1011b of the first semiconductor layer 101b. Accordingly, current is injected into the first semiconductor layer 101b through the discontinuous first contact region of the first contact portion 600b, and cannot be directly injected into the region covered by the first insulating structure 20b and the second insulating structure 50b. Therefore, the current can be diffused through the first contact portion 600b and further diffused through the discontinuous first contact region. In other words, the design of the surrounding insulating portion 201b and the periphery 505b of the second insulating structure 50b can affect the forward voltage value and change the current path, forcing the current to flow into the first surface exposed by the plurality of recesses 2012b and the plurality of recesses 5052b, thereby changing the current distribution.In this embodiment, the area of the first contact portion 600b is sufficient to achieve an acceptable forward voltage value, such as 2.15V to 2.4V, and an expected current distribution can be achieved under this first contact area. Details will be described below.

[0086] As Figure 5 and Figure 6 shown, Figure 5 is a top view of the burned area of the light-emitting element 2. Figure 6 is a top view of the burned area of the conventional light-emitting element 3. The difference between the light-emitting element 2 and the conventional light-emitting element 3 is that the first insulating structure 20b' and the second insulating structure 50b' of the conventional light-emitting element 3 do not have a plurality of protrusions 2011b, 5051b and a plurality of depressions 2012b, 5052b like those of the light-emitting element 2. In the conventional light-emitting element 3, the first surface 1011b of the first semiconductor layer 101b is entirely exposed to contact the contact layer 60b, such that the contact layer 60b continuously contacts the first surface 1011b of the first semiconductor layer 101b and directly contacts the corners (not shown in the figure) of the first surface 1011b of the first semiconductor layer 101b.

[0087] As Figure 6 shown, when a surge is applied to the conventional light-emitting element 3, the conventional light-emitting element 3 cannot withstand this high voltage and effectively disperse the current, causing the current to concentrate at the corners. Therefore, the conventional light-emitting element 3 is prone to burnout. Referring to Figure 6 , the voltage of the surge exceeds the normal operating voltage of the conventional light-emitting element 3, and this surge burns out the conventional light-emitting element 3 through a plurality of fault regions labeled f3. Compared with other regions, the current of the conventional light-emitting element 3 tends to gather more at the corners. When a surge exceeding its tolerance is applied to the light-emitting element 2, as Figure 5 shown, the fault region of the light-emitting element 2 is labeled f2. The distribution of the fault region f2 is different from the distribution of the fault region f3 of the conventional light-emitting element 3. The current of the light-emitting element 2 does not gather at the corners of the first surface 1011b of the first semiconductor layer 101b. The current distribution of the light-emitting element 2 is more uniform than that of the conventional light-emitting element 3 and can withstand a surge of a higher voltage.

[0088] In this embodiment, the discontinuous first contact region between the contact layer 60b and the first surface 1011b of the first semiconductor layer 101b is beneficial to the current diffusion of the light-emitting element 2 and avoids breakdown of the light-emitting element 2. In addition, through the discontinuous first contact region, the light-emitting element 2 has an acceptable forward voltage, for example, 2.15V - 2.4V, and an expected current distribution. In one embodiment, the light-emitting element 2 and a conventional light-emitting element 3 are subjected to an Electrical Over Stress (EOS) test under different applied voltages. Please refer to Figure 7 , Figure 8 and Figure 9 . Figure 7 is a voltage waveform diagram of a surge under an Electrical Over Stress (EOS) test. Figure 8 is a graph of the surge of the maximum applied voltage versus the forward voltage (Vf) that can be turned on for the light-emitting element 2 and the existing light-emitting element 3 under an Electrical Over Stress (EOS) test. Figure 9 is a graph of the surge of the maximum applied voltage versus the reverse current (Ir) for the light-emitting element 2 and the existing light-emitting element 3 under an Electrical Over Stress (EOS) test. To further compare the light-emitting element 2 of the present invention and the conventional light-emitting element 3, as Figure 8 shown, samples 1 and 2 of the light-emitting element 2 and samples 1 and 2 of the conventional light-emitting element 3 are subjected to an Electrical Over Stress (EOS) test. In the EOS test (compliant with the IEC 61000-4-5 standard), as Figure 7 shown, a surge having a voltage waveform is applied to the light-emitting element 2 and the conventional light-emitting element 3 respectively. The voltage of each surge changes with time, and each surge has a maximum applied voltage Va(max). As Figure 8 shown, a plurality of samples are subjected to different maximum applied voltages Va(max), such as 0V, 20V, 30V, 35V, 40V, 45V, 50V, 55V, 60V, and 65V. For each maximum applied voltage Va(max), 5 surges are applied at a frequency of 1 time per second, and each surge lasts for about 10 -4 seconds. The size of each sample is approximately 38×38 mil 2 . After the surge test with the maximum applied voltage, each sample is driven at a fixed current of 10 μA, and the forward voltage (Vf) of each sample is measured and recorded in Figure 8in the table. As Figure 8 shown, samples 1 and 2 of the light-emitting element 2 were respectively subjected to EOS tests under surges with maximum applied voltages of 65 V and 60 V, and the measured forward voltage Vf was less than 2.15 V. Samples 1 and 2 of the conventional light-emitting element 3 were subjected to EOS tests under a surge with a maximum applied voltage of 50 V, and the measured forward voltage Vf was less than 2.15 V. In addition, since the acceptable forward voltage value is between 2.15 V and 2.4 V, after the sample 1 of the light-emitting element 2 was subjected to a surge with a maximum applied voltage equal to or less than 60 V, the measured forward voltage was greater than 2.15 V and less than 2.4 V, that is, the sample 1 of the light-emitting element 2 could still operate normally after the EOS test. After the sample 2 of the light-emitting element 2 was subjected to a surge with a maximum applied voltage equal to or less than 55 V, the measured forward voltage was greater than 2.15 V and less than 2.4 V, that is, the sample 2 could still operate normally after the EOS test. Compared with the conventional light-emitting element 3, the light-emitting element 2 can withstand a surge with a maximum applied voltage of 60 V. Therefore, the performance of the light-emitting element 2 in the electrical over stress (EOS) test is better than that of the conventional light-emitting element 3.

[0089] In an embodiment, similar to the above embodiment, as Figure 9 shown, samples 1, 2, 3, and 4 of the light-emitting element 2 and samples 1, 2, 3, and 4 of the existing light-emitting element 3 were used for electrical over stress (EOS) tests. Different maximum voltages of 0 V, 60 V, 65 V, 70 V, 75 V, and 80 V were applied to perform a surge test on each sample. After the surge test with the maximum voltage was applied, the samples were driven at a reverse voltage of -5 V, and the reverse current (Ir) of each sample was measured. The measured values were recorded in Figure 9 In this embodiment, the acceptable reverse current (Ir) of the light-emitting element is less than 0.3 μA. As Figure 9 shown, when the light-emitting element is damaged, such as breakdown, the reverse current (Ir) will occur and will be measured in this embodiment as Figure 9The read value of 100 μA as shown. The over-electrical stress (EOS) test was carried out under surges of maximum applied voltages of 75 V and 80 V. For samples 1, 2, 3, and 4 of the light-emitting element 2, the reverse current Ir (μA) was greater than 0.3 μA at 100 μA. In other words, the maximum applied voltage of the surge that the light-emitting element 2 can withstand is below 75 V. The over-electrical stress (EOS) test was carried out under surges of maximum applied voltages from 65 V to 80 V. For samples 1, 2, 3, and 4 of the light-emitting element 3, the reverse current Ir (μA) was greater than 0.3 μA. In other words, the maximum applied voltage of the surge that the light-emitting element 3 can withstand is below 65 V. In addition, since the acceptable reverse current (Ir) is less than 0.3 μA, after applying a surge with a maximum applied voltage equal to or less than 70 V, the test results of samples 1, 2, 3, and 4 of the light-emitting element 2 showed that the reverse current Ir was zero, that is, samples 1, 2, 3, and 4 of the light-emitting element 2 could still operate normally and pass the over-electrical stress (EOS) test. Compared with the light-emitting element 3, the light-emitting element 2 can withstand a maximum applied voltage of 70 V. Therefore, the performance of the light-emitting element 2 in the over-electrical stress (Electrical Over Stress, EOS) test is better than that of the conventional light-emitting element 3.

[0090] As Figure 8 and Figure 9 shown, the reliability of the light-emitting element 2 under the over-electrical stress (EOS) test is better than that of the conventional light-emitting element 3. In an embodiment of the present invention, through the design of the surrounding insulating portion 201b of the first insulating structure and the periphery 505b of the second insulating structure 50b, the light-emitting element 2 of the present invention can avoid current concentration at the corners. And, the area and position of the first contact region of the contact layer 60b can be adjusted to achieve an acceptable forward voltage. Thus, a forward voltage between 2.15 V and 2.4 V can be achieved, improving the current distribution of the light-emitting element 2 and enhancing the reliability of the light-emitting element 2.

[0091] Figure 10FIG. 0 is a schematic diagram of a light-emitting device 30 according to an embodiment of the present invention. The light-emitting element 2 in the foregoing embodiment is mounted on the first pad 511 and the second pad 512 of the packaging substrate 51 in a flip-chip form. Electrical insulation is provided between the first pad 511 and the second pad 512 by an insulating portion 53 including an insulating material. The flip-chip is mounted with the growth substrate 11b side facing the pads facing up, so that the growth substrate side is the main light extraction surface. To increase the light extraction efficiency of the light-emitting device 30, a reflective structure 54 may be provided around the light-emitting element 2.

[0092] Figure 11 FIG. 4 is a schematic diagram of a light-emitting device 4 according to an embodiment of the present invention. The light-emitting device 4 is a bulb lamp and includes a lamp cover 602, a reflector 604, a light-emitting module 610, a lamp base 612, a heat sink 614, a connecting portion 616, and an electrical connection element 618. The light-emitting module 610 includes a carrying portion 606, and a plurality of light-emitting units 608 are located on the carrying portion 606, where the plurality of light-emitting units 608 may be the light-emitting element 2 or the light-emitting device 30 in the foregoing embodiment.

[0093] The embodiments listed in the present invention are only used to illustrate the present invention, and are not intended to limit the scope of the present invention. Any obvious modification or change made by anyone to the present invention does not depart from the spirit and scope of the present invention.

Claims

1. A light-emitting element, characterized in that, comprising: a semiconductor structure including a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; a surrounding portion including a first surface of the first semiconductor layer not covered by the second semiconductor layer and the active layer, located at the periphery of the semiconductor structure; a first insulating structure located on the semiconductor structure, in a top view of the light-emitting element, including a plurality of first protrusions covering a plurality of portions of the first surface of the first semiconductor layer, and a plurality of first depressions to expose other portions of the first surface of the first semiconductor layer not covered by the plurality of protrusions; and a second insulating structure located on the first insulating structure, in a top view of the light-emitting element, including a plurality of second protrusions and a plurality of second depressions.

2. The light-emitting element according to claim 1, further comprising a first contact portion formed on the surrounding portion and discontinuously contacting the first surface of the first semiconductor layer through the plurality of first depressions.

3. The light-emitting element according to claim 1 or 2, wherein positions of the plurality of first protrusions correspond to positions of the plurality of second protrusions, and positions of the plurality of first depressions correspond to positions of the plurality of second depressions.

4. The light-emitting element according to claim 3, wherein an area of the second protrusion is smaller than an area of the first protrusion.

5. The light-emitting element according to claim 2, further comprising one or more through holes passing through the second semiconductor layer and the active layer to expose the first semiconductor layer, and the first contact portion contacts the first semiconductor layer through the one or more through holes.

6. The light-emitting element according to claim 1 or 2, wherein the first insulating structure covers a plurality of corners of the first surface of the first semiconductor layer.

7. The light-emitting element according to claim 1 or 2, further comprising a transparent conductive layer formed on the second semiconductor layer, and a reflective structure formed on the transparent conductive layer, wherein the transparent conductive layer and the reflective structure extend onto the first insulating structure.

8. The light-emitting element according to claim 1 or 2, wherein the plurality of second protrusions and the plurality of second depressions are located on the first surface.

9. The light-emitting element according to claim 1 or 2, wherein the first insulating structure includes a distributed Bragg reflector (DBR).

10. The light-emitting element according to claim 1 or 2, wherein in a top view of the light-emitting element, a shape of one of the plurality of first protrusions or the plurality of second protrusions includes a triangle, a rectangle, a semi-circle, a circle, or a polygon.

11. The light-emitting element according to claim 7, wherein the second insulating structure is located on the reflective structure.

12. The light-emitting element according to claim 1 or 2, further comprising a third insulating structure located on the semiconductor structure and covering the first insulating structure and the second insulating structure.

13. The light-emitting element according to claim 1 or 2, wherein the first insulating structure and / or the second insulating structure includes alumina.

14. The light-emitting element according to claim 2 further includes a third contact portion located on the second semiconductor layer, wherein the third contact portion is electrically connected to the second semiconductor layer, and the first contact portion is electrically connected to the first semiconductor layer.

15. The light-emitting element according to claim 13, wherein the third contact portion is surrounded by the first contact portion.

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