A BCM interleaved parallel PFC circuit, control device and control method

Abstract

This application provides a BCM interleaved parallel PFC circuit, control device, and control method. The BCM interleaved parallel PFC circuit includes a sampling circuit, a trough detection circuit, a digital processor, a drive circuit, and a main circuit. The main circuit includes a first diode, a second diode, and a first boost circuit and a second boost circuit connected in parallel. This scheme is implemented using a digital processor, offering advantages such as ease of operation, accurate phase difference acquisition via register settings, and interleaved phase shifting controlled by adjusting the on-time. It is also easy to modify, eliminating the need for querying input signals or handling multiple interrupts before controlling the output drive signal. Phase shift value calculation is simple and accurate, and it is less susceptible to external interference and additional digital technology functions.

Description

Technical Field

[0001] This application relates to the field of switching power supply technology, and in particular to a BCM interleaved parallel PFC circuit, control device and control method. Background Technology

[0002] Interleaved parallel critical power factor correction (PFC) combines the advantages of low input / output current ripple current of continuous conduction mode (CCM) PFC with the zero-current switching capability of boundary conduction mode (BCM) PFC, allowing for the use of low-cost devices. Therefore, it is widely used in low-cost, compact PFC applications. Traditional interleaved parallel critical PFC is mostly constructed using analog chips, but this method suffers from drawbacks such as difficulty in modification, susceptibility to interference, and lack of communication capabilities. Using microcontrollers or other processors for program configuration and calculation results in high memory consumption, large phase shift deviations, and the inability to achieve satisfactory critical interleaving effects. Summary of the Invention

[0003] To solve the aforementioned counting problem, this application provides a BCM interleaved parallel PFC circuit, a control device, and a control method, the specific solution of which is as follows:

[0004] In a first aspect, embodiments of this application provide a BCM interleaved parallel PFC circuit, the circuit including a sampling circuit, a valley detection circuit, a digital processor, a driving circuit and a main circuit, the main circuit including a first diode, a second diode and a first boost circuit and a second boost circuit connected in parallel;

[0005] The first boost circuit includes a first inductor and a first switching transistor connected via a first node. The second boost circuit includes a second inductor and a second switching transistor connected via a second node. The anode of the first diode is connected to the first node, and the cathode of the first diode is connected to the power supply voltage of the main circuit through a third node. The anode of the second diode is connected to the second node, and the cathode of the second diode is connected to the power supply voltage of the main circuit through the third node.

[0006] The input terminal of the sampling circuit is connected to the input terminal of the main circuit and the third node, respectively, and the output terminal of the sampling circuit is connected to the input terminal of the digital processor. The sampling circuit is used to sample the input voltage and output voltage of the main circuit.

[0007] The trough detection circuit is connected to the voltage input terminal of the main circuit and the first node, the second node, and the input terminal of the digital processor. The digital processor is connected to the output terminal of the trough detection circuit, the output terminal of the sampling circuit, and the input terminal of the driving circuit. When the trough detection circuit detects that the voltage of the first inductor or the second inductor is less than the input voltage of the main circuit, it outputs a first high level or a second high level. When the digital processor receives the first high level or the second high level, it triggers a first zero current detection signal or a second zero current detection signal. The digital processor calculates the phase difference between the first boost circuit and the second boost circuit based on the first zero current detection signal or the second zero current detection signal. The digital processor performs phase adjustment based on the phase difference and outputs a first high level or a second high level and a first low level or a second low level signal.

[0008] The driving circuit is connected to the control terminals of the first switch transistor, the second switch transistor, and the signal output terminal of the digital processor, respectively. The driving circuit converts the received first high level or first low level into a driving signal for the first switch transistor, and the second high level or second low level into a driving signal for the second switch transistor.

[0009] According to a specific embodiment disclosed in this application, the digital processor includes an EPWM1A module, an EPWM2 module, and an EPWM3A module. The EPWM1A module, EPWM2 module, and EPWM3A module are all equipped with a counter, and their clock synchronization is all achieved by an upward counting method.

[0010] The EPWM1A module is connected to the first switching transistor through the driving circuit, the EPWM3A is connected to the second switching transistor through the driving circuit, the EPWM2 module is configured as an internal counter of the digital processor, and an internal capture function register is configured.

[0011] Secondly, embodiments of this application provide a switch control device, the control device including the BCM interleaved parallel PFC circuit described in the embodiments of the first aspect.

[0012] Thirdly, embodiments of this application provide a control method for a BCM interleaved parallel PFC circuit, the control method being applied to the control device described in the second aspect, the method comprising:

[0013] The sampling circuit samples the input voltage and output voltage of the main circuit;

[0014] When the trough detection circuit detects that the voltage of the first inductor or the second inductor is less than the input voltage of the main circuit, it outputs a first high level or a second high level.

[0015] When the digital processor receives the first high level or the second high level, it triggers the first zero current detection signal or the second zero current detection signal. The digital processor calculates the phase difference between the first boost circuit and the second boost circuit based on the first zero current detection signal or the second zero current detection signal. The digital processor performs phase adjustment based on the phase difference and outputs the first high level or the second high level and the first low level or the second low level.

[0016] The driving circuit converts the received first high level or first low level into a driving signal for the first switching transistor, and the second high level or second low level into a driving signal for the second switching transistor.

[0017] According to a specific embodiment disclosed in this application, when the digital processor receives the first high level or the second high level, it triggers a first zero current detection signal or a second zero current detection signal. The digital processor calculates the phase difference between the first boost circuit and the second boost circuit based on the first zero current detection signal or the second zero current detection signal. The digital processor performs phase adjustment based on the phase difference and outputs a first high level or a second high level and a first low level or a second low level signal, including:

[0018] When the digital processor acquires the first zero-current detection signal or the second zero-current detection signal, it resets the internal counter of the EPWM1A module or the EPWM3A module to zero and outputs the first high level or the second high level. When the internal counter of the EPWM1A module or the EPWM3A module is equal to the first adjustment value, it outputs the first low level or the second low level.

[0019] According to a specific embodiment disclosed in this application, the digital processor includes an EPWM1A module, an EPWM2 module, and an EPWM3A module;

[0020] The step of the digital processor performing phase adjustment based on the detected first zero-current detection signal and second zero-current detection signal includes:

[0021] After receiving the first zero current detection signal, the EPWM1A module resets the counter to zero.

[0022] After receiving the first zero current detection signal, the EPWM2 module interrupts the first boost circuit and reads the counter value as the period value of the first boost circuit. After receiving the second zero current detection signal, it generates a capture function and reads the counter value as the DCCAP value.

[0023] After receiving the second zero current detection signal, the EPWM3A module resets the counter to zero;

[0024] The digital processor compares half of the period value of the first boost circuit with the DCCAP value to determine the phase difference between the first boost circuit and the second boost circuit.

[0025] The first adjustment value of the EPWM3A module is adjusted to the second adjustment value, while the first adjustment value of the EPWM1A module remains unchanged.

[0026] According to a specific embodiment disclosed in this application, the phase difference between the first boost circuit and the second boost circuit is half the period value of the first boost circuit minus the DCCAP value.

[0027] According to a specific embodiment disclosed in this application, before the step of adjusting the first adjustment value of the EPWM3A module to the second adjustment value through the phase difference, the method further includes:

[0028] The first regulation value of the EPWM1A module and the first regulation value of the EPWM3A module are calculated using the PID voltage loop of the output voltage of the main circuit.

[0029] According to a specific embodiment disclosed in this application, the calculation step of the second adjustment value of the EPWM3A module includes:

[0030] The second adjustment value of the EPWM3A module is calculated using the formula CMP1 = CMP ± KΔT, where CMP1 is the second adjustment value of the EPWM3A module, CMP is the first adjustment value of the EPWM3A module, K is a preset value, and ΔT is the phase difference.

[0031] According to a specific embodiment disclosed in this application, the step of calculating the second adjustment value of the EPWM3A module using the formula CMP1=CMP±K△T includes:

[0032] If half of the period value of the first boost circuit is greater than the DCCAP value, then the second adjustment value of the EPWM3A module is calculated by CMP1 = CMP + KΔT;

[0033] If half of the period value of the first boost circuit is less than the DCCAP value, then the second adjustment value of the EPWM3A module is calculated by CMP1 = CMP - KΔT.

[0034] Compared with the prior art, this application has the following beneficial effects:

[0035] The BCM interleaved parallel PFC circuit provided in this application includes a sampling circuit, a trough detection circuit, a digital processor, a driving circuit, and a main circuit. The main circuit includes a first diode, a second diode, and a first boost circuit and a second boost circuit connected in parallel. The sampling circuit samples the input and output voltages of the main circuit. When the trough detection circuit detects that the current of the first or second inductor is less than the input voltage, it outputs a first high level or a second high level. When the digital processor receives the first high level or the second high level, it triggers a first zero-current detection signal or a second zero-current detection signal. The digital processor calculates the phase difference between the first boost circuit and the second boost circuit based on the first zero-current detection signal or the second zero-current detection signal. The digital processor performs phase adjustment based on the phase difference and outputs a first high level or a second high level and a first low level or a second low level signal. The driving circuit converts the received first high level or first low level into a driving signal for the first switch transistor, and the second high level or second low level into a driving signal for the second switch transistor. The turn-on time of the second boost circuit is controlled by adjusting the DSP so that the switching devices of the two boost circuits switch alternately with a 180° phase shift. This scheme, implemented using a digital processor, offers advantages such as ease of operation (directly setting adjustment values ​​through registers to control the turn-on cycle, easy modification, no need to query input signals or handle multiple interrupts before controlling the output drive signal in the program, simple and accurate calculation of phase shift values, resistance to external interference, and additional digital functionality. Attached Figure Description

[0036] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope of protection of the present invention. In the various drawings, similar components are numbered similarly.

[0037] Figure 1 A schematic diagram of a BCM interleaved parallel PFC circuit provided in an embodiment of this application;

[0038] Figure 2 A flowchart illustrating a control method for a BCM interleaved parallel PFC circuit provided in an embodiment of this application;

[0039] Figure 3 A schematic diagram of the driving waveform generation method involved in the BCM interleaved parallel PFC circuit provided in the embodiments of this application;

[0040] Figure 4 A schematic diagram illustrating the phase shift principle of the second boost circuit included in the BCM interleaved parallel PFC circuit provided in this application embodiment. Detailed Implementation

[0041] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0042] The components of the embodiments of the invention described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0043] In the following, the terms “comprising,” “having,” and their cognates, which may be used in various embodiments of the invention, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as excluding, firstly, the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more features, numbers, steps, operations, elements, components, or combinations thereof.

[0044] Furthermore, the terms "first," "second," and "third" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0045] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the invention pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be interpreted as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of the invention.

[0046] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0047] See also Figure 1 , Figure 1 This is a schematic diagram of a BCM interleaved parallel PFC circuit provided in an embodiment of this application. In this embodiment, the BCM interleaved parallel PFC circuit includes a sampling circuit, a valley detection circuit, a DSP, a driving circuit, and a main circuit. The main circuit includes a first diode D1, a second diode D2, and a first boost circuit and a second boost circuit connected in parallel.

[0048] The first boost circuit includes a first inductor L1 and a first switch G1 connected via a first node A. The second boost circuit includes a second inductor L2 and a second switch G2 connected via a second node B. The anode of the first diode D1 is connected to the first node A, and the cathode of the first diode D1 is connected to the power supply voltage of the main circuit via a third node C. The anode of the second diode D2 is connected to the second node B, and the cathode of the second diode D2 is connected to the power supply voltage of the main circuit via a third node C.

[0049] The sampling circuit samples the input voltage Vin and output voltage Vo of the main circuit, and then sends them to the DSP for AD conversion to calculate the actual value.

[0050] When Vds1 and Vds2 in the trough detection circuit detect that the voltage of the first inductor or the second inductor is less than Vin, they output a first high level or a second high level. When the DSP receives the first high level or the second high level, it triggers the first zero current detection signal ZCD1 or the second zero current detection signal ZCD2. The DSP calculates the phase difference between the first boost circuit and the second boost circuit based on ZCD1 or ZCD2. The DSP performs phase adjustment based on the phase difference and outputs the first high level or the second high level and the first low level or the second low level signal.

[0051] The driving circuit converts the received first high level or first low level into a driving signal for the first switching transistor G1, and the second high level or second low level into a driving signal for the second switching transistor G2.

[0052] The output of the valley detection circuit is connected to the TZ pin of the DSP. After the first high level or the second high level output by the valley detection circuit enters the TZ pin of the DSP, the TZ pin triggers ZCD1 or ZCD2.

[0053] After processing, ZCD1 or ZCD2 outputs a first high level or a second high level and a first low level or a second low level via the PWM pin of the DSP.

[0054] The zero-current detection signal is a signal triggered by the DSP when the inductor voltage is less than the main circuit input voltage, indicating that the input inductor current has dropped to zero.

[0055] For details, see Figure 1 This is a schematic diagram of a BCM interleaved parallel PFC circuit provided in an embodiment of this application. The DSP includes an EPWM1A module, an EPWM2 module, and an EPWM3A module. Each of the EPWM1A, EPWM2, and EPWM3A modules has a built-in counter, and their clock synchronization all adopts an upward counting method.

[0056] The EPWM1A module is connected to the control terminal of the first switching transistor G1 through a drive circuit, the EPWM3A module is connected to the control terminal of the second switching transistor G2 through a drive circuit, and the EPWM2 module is configured as the internal counter and internal capture function register of the DSP.

[0057] The built-in counters of the EPWM1A, EPWM2, and EPWM3A modules are set to reset to zero upon receiving either ZCD1 or ZDC2.

[0058] The EPWM1A, EPWM2, and EPWM3A modules each have internal registers for storing the first adjustment value of the EPWM1A module, the counter value of the EPWM2 module, and the first adjustment value of the EPWM3A module.

[0059] The EPWM2 internal capture function register stores the captured value in the register for subsequent use without software intervention.

[0060] The BCM interleaved parallel PFC circuit provided in this application uses a DSP to adjust the second adjustment value of the EPWM3A module based on the calculated phase difference to regulate the on / off time of the second boost circuit, so that the switching devices of the two boost circuits switch alternately with a 180° phase shift. By employing a DSP to implement this scheme, the counter accurately times the circuit without software interrupts or polling. Using the internal counter of the EPWM2 module, ZCD1 and ZCD2 are set as trigger signals to accurately capture the period value and phase difference of the first boost circuit. Once configured, no software intervention is required, offering simple operation. The adjustment value can be directly set through the register to control the on-cycle, and it is also easy to modify. The calculation of the phase shift value is simple, accurate, and not easily affected by external interference, and includes other digital technology functions.

[0061] This application also provides a switch control device, which includes the BCM interleaved parallel PFC circuit described in any of the above embodiments.

[0062] See also Figure 2 This is a flowchart illustrating a control method for a BCM interleaved parallel PFC circuit provided in an embodiment of this application. The method includes:

[0063] Step S201: The sampling circuit samples the input voltage and output voltage of the main circuit.

[0064] In step S202, when the trough detection circuit detects that the voltage of the first inductor L1 or the second inductor L2 is less than the input voltage of the main circuit, it outputs a first high level or a second high level.

[0065] In step S203, when the DSP receives the first high level or the second high level, it triggers ZCD1 or ZCD2. The DSP calculates the phase difference between the first boost circuit and the second boost circuit based on ZCD1 or ZCD2. The DSP adjusts the phase based on the phase difference and outputs the first high level or the second high level and the first low level or the second low level signal.

[0066] When the DSP detects that the second high level is not at half the time of the entire cycle of the first boost circuit, it determines whether the second boost circuit is ahead or behind by calculating the phase difference.

[0067] According to the method described in step S203, when the DSP receives the first high level or the second high level, it triggers ZCD1 or ZCD2, and the DSP calculates the phase difference between the first boost circuit and the second boost circuit based on ZCD1 or ZCD2. (See also...) Figure 3 , Figure 3 The schematic diagram of the driving and waveform generation method of the BCM interleaved parallel PFC circuit provided in the embodiments of this application shows the steps of the DSP adjusting the phase according to the phase difference and outputting a first high level or a second high level and a first low level or a second low level signal, including:

[0068] When the DSP acquires ZCD1 or ZCD2, it resets the internal counter of the EPWM1A module or EPWM3A module to zero and outputs a first high level or a second high level. When the internal counter of the EPWM1A module or EPWM3A module is equal to the first adjustment value, it outputs a first low level or a second low level.

[0069] Specifically, the digital processor includes an EPWM1A module, an EPWM2 module, and an EPWM3A module;

[0070] The step of the DSP performing phase adjustment based on the detected ZCD1 and ZCD2 includes:

[0071] After receiving the first zero current detection signal, the EPWM1A module resets the counter to zero and outputs a high level.

[0072] After receiving ZCD1, the EPWM2 module interrupts the first boost circuit and reads the counter value as the cycle value of the first boost circuit. After receiving ZCD2, it generates a capture function and reads the counter value as the DCCAP value.

[0073] After receiving the ZCD2, the EPWM3A module resets the counter to zero and outputs a high level.

[0074] The EPWM2 module compares half of the period value of the first boost circuit with the DCCAP value to determine the phase difference between the first boost circuit and the second boost circuit.

[0075] The first adjustment value of the EPWM3A module is adjusted to the second adjustment value, while the first adjustment value of the EPWM1A module remains unchanged.

[0076] In specific implementation, the phase difference between the first boost circuit and the second boost circuit is half the period value of the first boost circuit minus the DCCAP value.

[0077] Specifically, before the step of adjusting the first adjustment value of the EPWM3A module to the second adjustment value through the phase difference, the method further includes:

[0078] The first regulation value of the EPWM1A module and the first regulation value of the EPWM3A module are calculated using the PID voltage loop of the output voltage of the main circuit.

[0079] In specific implementation, the calculation steps for the second adjustment value of the EPWM3A module include:

[0080] The second adjustment value of the EPWM3A module is calculated using the formula CMP1 = CMP ± KΔT, where CMP1 is the second adjustment value of the EPWM3A module, CMP is the first adjustment value of the EPWM3A module, K is a preset value, and ΔT is the phase difference.

[0081] The preset value K coefficient is reasonably selected based on the actual situation, and the value range is from 1 / 8 to 1 / 32.

[0082] The step of calculating the second adjustment value of the EPWM3A module using the formula CMP1=CMP±K△T includes:

[0083] If half of the period value of the first boost circuit is greater than the DCCAP value, then the second adjustment value of the EPWM3A module is calculated by CMP1 = CMP + KΔT;

[0084] If half of the period value of the first boost circuit is less than the DCCAP value, then the second adjustment value of the EPWM3A module is calculated by CMP1 = CMP - KΔT.

[0085] See Figure 4 , Figure 4This is a schematic diagram illustrating the phase shift principle of the second boost circuit included in the BCM interleaved parallel PFC circuit provided in this application embodiment. By reducing the second adjustment value of the EPWM3A module, the duty cycle of the second boost circuit is reduced, thereby controlling the turn-on time of the second switching transistor. As a result, the peak input current decreases, and the time when it reaches zero is advanced. The first boost circuit does not require adjustment, and when it is turned on again, it achieves a 180° phase shift relative to the first boost circuit.

[0086] In step S204, the driving circuit converts the received first high level or first low level into a driving signal for the first switching transistor, and the second high level or second low level into a driving signal for the second switching transistor.

[0087] The BCM interleaved parallel PFC circuit provided in this application uses a DSP to adjust the second adjustment value of the EPWM3A module based on the calculated phase difference to regulate the on / off time of the second boost circuit, so that the switching devices of the two boost circuits switch alternately with a 180° phase shift. By employing a DSP to implement this scheme, the counter accurately times the circuit without software interrupts or polling. Using the internal counter of the EPWM2 module, and setting ZCD1 as the trigger signal, it accurately captures the period value and phase difference of the first boost circuit. Once configured, no software intervention is required, offering simple operation. The adjustment value can be directly set through the register to control the on-cycle, and it is also easy to modify. The method is simple, with low software overhead and minimal DSP memory usage during implementation, allowing the controller to handle more other tasks and facilitating the implementation of larger systems.

[0088] In the several embodiments provided in this application, it should be understood that the disclosed circuits and methods can also be implemented in other ways. The circuit embodiments described above are merely illustrative; for example, the flowcharts and circuit diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of the circuits and methods according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that, as an alternative implementation, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0089] In addition, the functional modules or units in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0090] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A BCM interleaved parallel PFC circuit, characterized in that, The BCM interleaved parallel PFC circuit includes a sampling circuit, a trough detection circuit, a digital processor, a driving circuit, and a main circuit. The main circuit includes a first diode, a second diode, and a first boost circuit and a second boost circuit connected in parallel. The first boost circuit includes a first inductor and a first switching transistor connected via a first node. The second boost circuit includes a second inductor and a second switching transistor connected via a second node. The anode of the first diode is connected to the first node, and the cathode of the first diode is connected to the power supply voltage of the main circuit through a third node. The anode of the second diode is connected to the second node, and the cathode of the second diode is connected to the power supply voltage of the main circuit through the third node. The input terminal of the sampling circuit is connected to the input terminal of the main circuit and the third node, respectively, and the output terminal of the sampling circuit is connected to the input terminal of the digital processor. The sampling circuit is used to sample the input voltage and output voltage of the main circuit. The trough detection circuit is connected to the voltage input terminal of the main circuit and the first node, the second node, and the input terminal of the digital processor. The digital processor is connected to the output terminal of the trough detection circuit, the output terminal of the sampling circuit, and the input terminal of the driving circuit. When the trough detection circuit detects that the voltage of the first inductor or the second inductor is less than the input voltage of the main circuit, it outputs a first high level or a second high level. When the digital processor receives the first high level or the second high level, it triggers a first zero current detection signal or a second zero current detection signal. The digital processor calculates the phase difference between the first boost circuit and the second boost circuit based on the first zero current detection signal or the second zero current detection signal. The digital processor performs phase adjustment based on the phase difference and outputs a first high level or a second high level and a first low level or a second low level signal. The driving circuit is connected to the control terminals of the first switch transistor, the second switch transistor, and the signal output terminal of the digital processor, respectively. The driving circuit converts the received first high level or first low level into a driving signal for the first switch transistor, and the second high level or second low level into a driving signal for the second switch transistor. The digital processor includes an EPWM1A module, an EPWM2 module, and an EPWM3A module. Each of the EPWM1A, EPWM2, and EPWM3A modules has a built-in counter, and their clock synchronization all uses an upward counting method. The EPWM1A module is connected to the first switching transistor through the driving circuit, the EPWM3A is connected to the second switching transistor through the driving circuit, the EPWM2 module is configured as an internal counter of the digital processor, and an internal capture function register is configured. After receiving the first zero current detection signal, the EPWM1A module resets the counter to zero. After receiving the first zero current detection signal, the EPWM2 module interrupts the first boost circuit and reads the counter value as the cycle value of the first boost circuit. After receiving the second zero current detection signal, it generates a capture function and reads the counter value as the DCCAP value. After receiving the second zero current detection signal, the EPWM3A module resets the counter to zero; The EPWM2 module compares half of the period value of the first boost circuit with the DCCAP value to determine the phase difference between the first boost circuit and the second boost circuit. The first adjustment value of the EPWM3A module is adjusted to the second adjustment value, while the first adjustment value of the EPWM1A module remains unchanged.

2. A switch control device, characterized in that, Includes the BCM interleaved parallel PFC circuit as described in claim 1.

3. A control method for a BCM interleaved parallel PFC circuit, characterized in that, The method, applied to the switch control device of claim 2, comprises: The sampling circuit samples the input voltage and output voltage of the main circuit; When the trough detection circuit detects that the voltage of the first inductor or the second inductor is less than the input voltage of the main circuit, it outputs a first high level or a second high level. When the digital processor receives the first high level or the second high level, it triggers the first zero current detection signal or the second zero current detection signal. The digital processor calculates the phase difference between the first boost circuit and the second boost circuit based on the first zero current detection signal or the second zero current detection signal. The digital processor performs phase adjustment based on the phase difference and outputs the first high level or the second high level and the first low level or the second low level. The driving circuit converts the received first high level or first low level into a driving signal for the first switching transistor, and the second high level or second low level into a driving signal for the second switching transistor.

4. The method according to claim 3, characterized in that, The steps of triggering a first zero-current detection signal or a second zero-current detection signal when the digital processor receives the first high level or the second high level, calculating the phase difference between the first boost circuit and the second boost circuit based on the first zero-current detection signal or the second zero-current detection signal, and performing phase adjustment based on the phase difference and outputting a first high level or a second high level and a first low level or a second low level signal include: When the digital processor acquires the first zero-current detection signal or the second zero-current detection signal, it resets the internal counter of the EPWM1A module or the EPWM3A module to zero and outputs a first high level or a second high level. When the internal counter of the EPWM1A module or the EPWM3A module is equal to the first adjustment value, it outputs a first low level or a second low level.

5. The method according to claim 3, characterized in that, The digital processor includes an EPWM1A module, an EPWM2 module, and an EPWM3A module; The step of the digital processor performing phase adjustment based on the detected first zero-current detection signal and the second zero-current detection signal includes: After receiving the first zero current detection signal, the EPWM1A module resets the counter to zero. After receiving the first zero current detection signal, the EPWM2 module interrupts the first boost circuit and reads the counter value as the cycle value of the first boost circuit. After receiving the second zero current detection signal, it generates a capture function and reads the counter value as the DCCAP value. After receiving the second zero current detection signal, the EPWM3A module resets the counter to zero; The EPWM2 module compares half of the period value of the first boost circuit with the DCCAP value to determine the phase difference between the first boost circuit and the second boost circuit. The first adjustment value of the EPWM3A module is adjusted to the second adjustment value, while the first adjustment value of the EPWM1A module remains unchanged.

6. The method according to claim 5, characterized in that, The phase difference between the first boost circuit and the second boost circuit is half the period value of the first boost circuit minus the DCCAP value.

7. The method according to claim 5, characterized in that, Before the step of adjusting the first adjustment value of the EPWM3A module to the second adjustment value through the phase difference, the method further includes: The first regulation value of the EPWM1A module and the first regulation value of the EPWM3A module are calculated using the PID voltage loop of the output voltage of the main circuit.

8. The method according to claim 5, characterized in that, The calculation steps for the second adjustment value of the EPWM3A module include: The second adjustment value of the EPWM3A module is calculated using the formula CMP1=CMP±K△T, where CMP1 is the second adjustment value of the EPWM3A module, CMP is the first adjustment value of the EPWM3A module, K is a preset value, and △T is the phase difference.

9. The method according to claim 8, characterized in that, The step of calculating the second adjustment value of the EPWM3A module using the formula CMP1=CMP±K△T includes: If half of the period value of the first boost circuit is greater than the DCCAP value, then the second adjustment value of the EPWM3A module is calculated by CMP1=CMP+K△T; If half of the period value of the first boost circuit is less than the DCCAP value, then the second adjustment value of the EPWM3A module is calculated by CMP1=CMP-K△T.

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